Integrated chip and preparation method thereof

Abstract

The present invention relates to the field of chip technology, and discloses an integrated chip and a preparation method thereof, the integrated chip comprising: a wafer layer, the wafer layer comprising a first single crystal silicon layer, a second single crystal silicon layer and a silicon dioxide dielectric layer in between, the first single crystal silicon layer forming a first chip; further comprising a first dielectric layer and a first metal part sequentially formed on the first single crystal silicon layer, the first metal part being electrically connected to the corresponding electrical connection part of the first chip through a via hole; further comprising a second chip device layer, a second dielectric layer, and a second metal part sequentially formed on the second single crystal silicon layer, the second chip device layer forming a second chip, the second metal part being electrically connected to the corresponding electrical connection part of the second chip through a via hole; the second metal part being electrically connected to the corresponding first metal part through a via hole. The integrated chip integrates multiple identical or different chips on both sides of the wafer, simplifies the connection between chips and is small in size.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to an integrated chip and a preparation method thereof. Background Art

[0002] With the rapid development of equipment, manufacturing processes and device physics of wide bandgap semiconductor materials (i.e., third-generation semiconductor materials) represented by SiC and GaN, SiC and GaN-based power electronic devices have gradually become an important development direction of power semiconductor devices and have gradually entered the market application, among which GaN Schottky Barrier Diode (Schottky Barrier Diode, SBD), GaN High Electron Mobility Transistor (High Electron Mobility Transistor, HEMT), Silicon Carbide Junction Barrier Diode JBS, Silicon Carbide Field Effect Transistor MOSFET and other devices are the main ones. Because the third-generation semiconductor power devices have the characteristics of high breakdown electric field, high saturation electron velocity, high thermal conductivity, high electron density, high mobility, low power loss, etc., they are widely used in power electronics, new energy and other fields.

[0003] At present, the power chips and devices used in intelligent power modules (IPMs) are still mainly silicon devices, with a few being silicon devices mixed with GaN devices or SiC devices. The module packaging design is still based on the structure of traditional silicon-based devices, and the devices are connected to the circuit by wire bonding, which makes the intelligent power module (IPM) large in size, with many package leads, and cannot effectively play the advantages of the third-generation semiconductor power devices. Summary of the invention

[0004] The present invention provides an integrated chip and a preparation method thereof. The integrated chip integrates a plurality of chips on both sides of a wafer, simplifies the connection between the chips and has a small volume.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] An integrated chip, comprising:

[0007] A wafer layer, wherein the wafer layer includes a first single crystal silicon layer, a second single crystal silicon layer, and a silicon dioxide dielectric layer disposed between the first single crystal silicon layer and the second single crystal silicon layer, wherein the first single crystal silicon layer includes a groove region, wherein the groove region separates the first single crystal silicon layer into a middle region and an edge region, and a first chip is formed at a portion of the first single crystal silicon layer located in the middle region;

[0008] A first dielectric layer formed on a side of the first single crystal silicon layer facing away from the second single crystal silicon layer;

[0009] A first metal portion is formed on the first dielectric layer away from the first single crystal silicon layer, the first metal portion being electrically connected to a corresponding electrical connection portion of the first chip through a via;

[0010] A second chip device layer is formed on a side of the second single crystal silicon layer away from the first single crystal silicon layer, the second chip device layer forming a second chip;

[0011] a second dielectric layer formed on a side of the second chip device layer away from the second single crystal silicon layer;

[0012] A second metal portion is formed on the side of the second dielectric layer facing away from the second chip device layer, and the second metal portion is electrically connected to the corresponding electrical connection portion of the second chip through a via; the second metal portion is electrically connected to the corresponding first metal portion through a via that penetrates the second dielectric layer, the second chip device layer, the wafer layer, and the first dielectric layer.

[0013] The above-mentioned integrated chip includes a wafer layer, the wafer layer includes a first single crystal silicon layer, a second single crystal silicon layer and a silicon dioxide dielectric layer arranged between the first single crystal silicon layer and the second single crystal silicon layer, the first single crystal silicon layer includes a groove area, the groove area separates the first single crystal silicon layer into a middle area and an edge area, the first chip is formed at the position of the first single crystal silicon layer located in the middle area, the groove area is located in the peripheral area of ​​the first chip, and the electrical isolation of the first chip is realized; the above-mentioned integrated chip also includes a first dielectric layer formed on the side of the first single crystal silicon layer away from the second single crystal silicon layer, the first dielectric layer realizes the electrical isolation of the first chip, and also includes a first metal part formed on the first dielectric layer away from the first single crystal silicon layer, the first metal part is electrically connected to the corresponding electrical connection part of the first chip through a via, and the first chip is electrically connected to other components through the via and the first metal part; the above-mentioned integrated chip also includes a first dielectric layer formed on the side of the first single crystal silicon layer away from the second single crystal silicon layer, the first dielectric layer realizes the electrical isolation of the first chip, and also includes a first metal part formed on the first dielectric layer away from the first single crystal silicon layer, the first metal part is electrically connected to the corresponding electrical connection part of the first chip through a via, and the first chip is electrically connected to other components through the first metal part through the via; A second chip device layer formed on a side of the second single crystal silicon layer away from the first single crystal silicon layer, a second dielectric layer formed on a side of the second chip device layer away from the second single crystal silicon layer, and a second metal part formed on a side of the second dielectric layer away from the second chip device layer, wherein the second chip device layer forms a second chip, and the second metal part is electrically connected to the electrical connection part of the corresponding second chip through a via, that is, each second chip is electrically connected to other components through the via and the second metal part; the second metal part is electrically connected to the corresponding first metal part through the via that penetrates the second dielectric layer, the second chip device layer, the wafer layer, and the first dielectric layer, thereby realizing the electrical connection between the second chip electrically connected to the second chip and the first chip electrically connected to the first metal part; the above-mentioned integrated chip realizes the integration of different chips into the wafer layer and electrically connecting them, which is conducive to reducing the volume of the chip and simplifying the electrical connection between different chips.

[0014] Preferably, the device further comprises a first protective layer formed on a side of the first metal portion away from the first single crystal silicon layer and a second protective layer formed on a side of the second metal portion away from the second single crystal silicon layer.

[0015] Preferably, a lead terminal is provided on a surface of the first protective layer on a side facing away from the first single crystal silicon layer, and the lead terminal is electrically connected to the first metal portion through a via hole penetrating the first protective layer.

[0016] Preferably, the device further comprises a buffer layer formed between the second chip device layer and the second single crystal silicon layer.

[0017] Preferably, the device further comprises an isolation structure formed in the second chip device layer for isolating adjacent second chips.

[0018] Preferably, the first chip is a driver chip, and the second chip is a gallium nitride high electron mobility transistor.

[0019] Preferably, it also includes an insulating layer arranged on the side walls of the via holes penetrating the second dielectric layer, the second chip device layer, the wafer layer, and the first dielectric layer.

[0020] Preferably, the insulating layer is a silicon dioxide layer.

[0021] The present invention also provides a method for preparing an integrated chip, comprising:

[0022] Providing a wafer layer, the wafer layer comprising a first single crystal silicon layer, a second single crystal silicon layer, and a silicon dioxide dielectric layer disposed between the first single crystal silicon layer and the second single crystal silicon layer;

[0023] forming a groove region on the first single crystal silicon layer to separate the first single crystal silicon layer into a middle region and an edge region;

[0024] forming a first chip in a middle region of the first single crystal silicon layer;

[0025] forming a first dielectric layer on a side of the first single crystal silicon layer facing away from the second single crystal silicon layer;

[0026] forming a second chip device layer on a side of the second single crystal silicon layer away from the first single crystal silicon layer, wherein the second chip device layer forms a second chip;

[0027] forming a second dielectric layer on a side of the second chip device layer away from the second single crystal silicon layer;

[0028] forming a via hole in a portion of the second dielectric layer opposite to the electrical connection portion of the second chip, and forming a via hole in a portion of the first dielectric layer opposite to the electrical connection portion of the first chip;

[0029] Forming a via hole penetrating the second dielectric layer, the second chip device layer, the wafer layer, and the first dielectric layer in a portion opposite to the edge region of the first single crystal silicon;

[0030] A first metal portion is formed on a side of the first dielectric layer away from the first single crystal silicon layer, and the first metal portion is electrically connected to the corresponding electrical connection portion of the first chip through a via; a second metal portion is formed on a side of the second dielectric layer away from the second chip device layer, and the second metal portion is electrically connected to the corresponding electrical connection portion of the second chip through a via; the second metal portion is electrically connected to the corresponding first metal portion through a via that penetrates the second dielectric layer, the second chip device layer, the wafer layer, and the first dielectric layer.

[0031] Preferably, the method further comprises forming a buffer layer on a side of the second single crystal silicon layer away from the first single crystal silicon layer by using a vapor deposition method.

[0032] Preferably, the method further comprises forming an isolation structure between every two adjacent second chips in the second chip device layer by using an ion implantation process.

[0033] Preferably, the method further comprises forming an insulating layer on the sidewalls of the via hole penetrating the second dielectric layer, the second chip device layer, the wafer layer and the first dielectric layer by using a chemical vapor deposition method.

[0034] Preferably, the method further comprises forming a first protective layer on a side of the first metal portion away from the first single crystal silicon layer, and forming a second protective layer on a side of the second metal portion away from the second single crystal silicon layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figures 1 to 8 A schematic diagram of film layer changes during the preparation of an integrated chip provided by the present invention.

[0036] icon:

[0037] 1-first single crystal silicon layer; 2-groove area; 3-middle area; 4-edge area; 5-second single crystal silicon layer; 6-silicon dioxide dielectric layer; 7-first dielectric layer; 8-first metal part; 9-first protective layer; 10-second chip device layer; 11-second dielectric layer; 12-second metal part; 13-second protective layer; 14-buffer layer; 15-isolation structure; 16-lead end; 17-insulating layer; 18-via. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] Please refer to Figure 1 The present invention provides an integrated chip, comprising:

[0040] The wafer layer includes a first single crystal silicon layer 1, a second single crystal silicon layer 5, and a silicon dioxide dielectric layer 6 disposed between the first single crystal silicon layer 1 and the second single crystal silicon layer 5, the first single crystal silicon layer 1 includes a groove region 2, the groove region 2 separates the first single crystal silicon layer 1 into a middle region 3 and an edge region 4, and a first chip is formed at a portion of the first single crystal silicon layer 1 located in the middle region 3;

[0041] A first dielectric layer 7 formed on a side of the first single crystal silicon layer 1 away from the second single crystal silicon layer 5;

[0042] A first metal portion 8 is formed on the first dielectric layer 7 away from the first single crystal silicon layer 1, and the first metal portion 8 is electrically connected to the corresponding electrical connection portion of the first chip through a via 18;

[0043] A second chip device layer 10 is formed on a side of the second single crystal silicon layer 5 away from the first single crystal silicon layer 1, and the second chip device layer 10 forms a second chip;

[0044] A second dielectric layer 11 formed on a side of the second chip device layer 10 away from the second single crystal silicon layer 5;

[0045] A second metal part 12 is formed on the side of the second dielectric layer 11 away from the second chip device layer 10, and the second metal part 12 is electrically connected to the corresponding electrical connection part of the second chip through a via 18; the second metal part 12 is electrically connected to the corresponding first metal part 8 through the via 18 that penetrates the second dielectric layer 11, the second chip device layer 10, the wafer layer, and the first dielectric layer 7.

[0046] The above-mentioned integrated chip includes a wafer layer, the wafer layer includes a first single crystal silicon layer 1, a second single crystal silicon layer 5 and a silicon dioxide dielectric layer 6 arranged between the first single crystal silicon layer 1 and the second single crystal silicon layer 5, the first single crystal silicon layer 1 includes a groove area 2, the groove area 2 separates the first single crystal silicon layer 1 into a middle area 3 and an edge area 4, the first single crystal silicon layer 1 is located in the middle area 3 to form a first chip, the groove area 2 is located in the peripheral area of ​​the first chip, and the electrical isolation of the first chip is achieved; the above-mentioned integrated chip also includes a first dielectric layer 7 formed on the side of the first single crystal silicon layer 1 away from the second single crystal silicon layer 5, the first dielectric layer 7 achieves electrical isolation of the first chip, and also includes a first metal part 8 formed on the first dielectric layer 7 away from the first single crystal silicon layer 1, the first metal part 8 is electrically connected to the corresponding electrical connection part of the first chip through a via 18, and the first chip is electrically connected to other components through the first metal part 8 through the via 18; the above-mentioned integrated chip also includes a first dielectric layer 7 formed on the second single crystal silicon layer 1 The second chip device layer 10 of the first single crystal silicon layer 1 is formed on the side of the second chip device layer 10 away from the second single crystal silicon layer 5, the second dielectric layer 11 is formed on the side of the second chip device layer 10 away from the second single crystal silicon layer 5, and the second metal part 12 is formed on the side of the second dielectric layer 11 away from the second chip device layer 10, wherein the second chip device layer 10 forms a second chip, and the second metal part 12 is electrically connected to the electrical connection part of the corresponding second chip through the via 18, that is, each second chip is electrically connected to other components through the via 18 and the second metal part 12; the second metal part 12 is electrically connected to the corresponding first metal part 8 through the via 18 penetrating the second dielectric layer 11, the second chip device layer 10, the wafer layer, and the first dielectric layer 7, thereby realizing the electrical connection between the second chip electrically connected to the second chip and the first chip electrically connected to the first metal part 8; the above-mentioned integrated chip realizes the integration of different chips into the wafer layer and the electrical connection, which is conducive to reducing the volume of the chip and simplifying the electrical connection between different chips.

[0047] The trench region may be filled with insulating material, such as silicon dioxide, to achieve electrical isolation of the periphery of the first chip.

[0048] Specifically, it also includes a first protective layer 9 formed on a side of the first metal portion 8 away from the first single crystal silicon layer 1 and a second protective layer 13 formed on a side of the second metal portion 12 away from the second single crystal silicon layer 5 .

[0049] The above-mentioned integrated chip also includes a first protective layer 9 and a second protective layer 13 formed on the surfaces of both sides of the chip, namely, the side of the first metal part 8 away from the first single crystal silicon layer 1 and the side of the second metal part 12 away from the second single crystal silicon layer 5, which helps to protect the internal structure of the chip, improve the service life of the integrated chip, and make the integrated chip more beautiful.

[0050] Specifically, a lead terminal 16 is provided on a surface of the first protective layer 9 facing away from the first single crystal silicon layer 1 , and the lead terminal 16 is electrically connected to the first metal portion 8 through a via hole 18 penetrating the first protective layer 9 .

[0051] A lead terminal 16 is provided on the surface of the first protective layer 9 facing away from the first single crystal silicon layer 1 , one end of the lead terminal 16 is electrically connected to the first metal part 8 through a via 18 penetrating the first protective layer 9 , and the other end is used for connection with other devices during use.

[0052] Specifically, it also includes a buffer layer 14 formed between the second chip device layer 10 and the second single crystal silicon layer 5 .

[0053] A buffer layer 14 is disposed between the second chip device layer 10 and the second single crystal silicon layer 5 , so as to realize a transition between the second single crystal silicon layer 5 and the second chip device layer 10 .

[0054] Specifically, it also includes an isolation structure 15 formed in the second chip device layer 10 for isolating adjacent second chips.

[0055] When the second chip device layer 10 is formed with a plurality of second chips, an isolation structure 15 is provided between adjacent second chips to achieve electrical isolation between adjacent second chips and prevent interference between adjacent second chips from affecting the performance of the second chips.

[0056] Specifically, in one embodiment, the first chip is a driver chip, and the second chip is a gallium nitride high electron mobility transistor. The integrated chip realizes the integration of the driver chip and the gallium nitride high electron mobility transistor. In another embodiment, the first chip and the second chip can be two parts of a large-area chip. The integrated chip realizes the decomposition of the large-area chip to both sides of the wafer layer, thereby reducing the chip area and realizing the miniaturized packaging of the device.

[0057] Specifically, it also includes an insulating layer 17 arranged on the side wall of the via 18 penetrating the second dielectric layer 11, the second chip device layer 10, the wafer layer, and the first dielectric layer 7. The insulating layer 17 is arranged on the side wall of the via 18 penetrating the second dielectric layer 11, the second chip device layer 10, the wafer layer, and the first dielectric layer 7 to help achieve electrical isolation between the first chip and the second chip to prevent affecting the performance of the chip. The insulating layer 17 is a silicon dioxide layer or other material layer with insulating properties.

[0058] The present invention also provides a method for preparing an integrated chip, comprising:

[0059] First, if Figure 1As shown, a groove is prepared in the wafer layer to form a groove area 2, the wafer layer includes a first single crystal silicon layer 1, a second single crystal silicon layer 5, and a silicon dioxide dielectric layer 6 disposed between the first single crystal silicon layer 1 and the second single crystal silicon layer 5, and the groove area 2 is formed in the first single crystal silicon layer 1 to separate the first single crystal silicon layer 1 into a middle area 3 and an edge area 4;

[0060] Then, a first chip is formed in the middle region 3 of the first single crystal silicon layer 1;

[0061] Then, if Figure 1 As shown, a first dielectric layer 7 is formed on a side of the first single crystal silicon layer 1 away from the second single crystal silicon layer 5;

[0062] Then, if Figure 2 As shown, a buffer layer 14 is formed on the side of the second single crystal silicon layer 5 facing away from the first single crystal silicon layer 1;

[0063] Then, if Figure 2 As shown, a second chip device layer 10 is formed on the side of the buffer layer 14 away from the first single crystal silicon layer 1, and the second chip device layer 10 forms a second chip;

[0064] Then, if Figure 3 As shown, a second dielectric layer 11 is formed on a side of the second chip device layer 10 away from the second single crystal silicon layer 5;

[0065] Then, if Figure 4 As shown, a via hole 18 is formed in the second dielectric layer 11 at a position opposite to the electrical connection portion of the second chip, and a via hole 18 is formed in the first dielectric layer 7 at a position opposite to the electrical connection portion of the first chip;

[0066] Then, if Figure 5 As shown, a via hole 18 penetrating the second dielectric layer 11, the second chip device layer 10, the wafer layer, and the first dielectric layer 7 is formed in a portion opposite to the edge region 4 in the first single crystal silicon;

[0067] Then, if Figure 6 As shown, an insulating layer 17 is formed on the side wall of the via hole 18 penetrating the second dielectric layer 11, the second chip device layer 10, the wafer layer, and the first dielectric layer 7;

[0068] Then, if Figure 7As shown, a first metal portion 8 is formed on a side of the first dielectric layer 7 away from the first single crystal silicon layer 1, and the first metal portion 8 is electrically connected to the electrical connection portion of the corresponding first chip through a via 18; a second metal portion 12 is formed on a side of the second dielectric layer 11 away from the second chip device layer 10, and the second metal portion 12 is electrically connected to the electrical connection portion of the corresponding second chip through the via 18; the second metal portion 12 is electrically connected to the corresponding first metal portion 8 through the via 18 that penetrates the second dielectric layer 11, the second chip device layer 10, the wafer layer, and the first dielectric layer 7;

[0069] Then, if Figure 8 As shown, a first protective layer 9 is formed on a side of the first metal portion 8 facing away from the first single crystal silicon layer 1 , and a second protective layer 13 is formed on a side of the second metal portion 12 facing away from the second single crystal silicon layer 5 .

[0070] In the above-mentioned integrated chip preparation method, the first chip is prepared in the central area of ​​the first single crystal silicon of the wafer layer, and the second chip is prepared on the side of the second single crystal silicon layer 5 of the wafer layer away from the first single crystal silicon layer 1, thereby realizing the integration of the first chip and the second chip and achieving the effect of reducing the chip weight. A first metal part 8 electrically connected to the electrical connection part of the first chip is prepared on the side of the first chip away from the wafer layer, and a second metal part 12 electrically connected to the electrical connection part of the second chip is prepared on the side of the second chip away from the wafer layer, and the first metal part 8 and the second metal part 12 are electrically connected through a via 18 that penetrates the wafer layer, thereby simplifying the electrical connection between the first chip and the second chip.

[0071] Specifically, in the above-mentioned preparation method, a buffer layer 14 is formed on the side of the second single crystal silicon layer 5 away from the first single crystal silicon layer 1 by a vapor deposition method; Figure 3 As shown, an isolation structure 15 is formed between every two adjacent second chips in the second chip device layer 10 by an ion implantation process, and an insulating layer 17 is formed on the side wall of a via hole 18 penetrating the second dielectric layer 11, the second chip device layer 10, the wafer layer, and the first dielectric layer 7 by a chemical vapor deposition method. The insulating layer 17 is formed on the side wall of the via hole 18 by a chemical vapor deposition method. The formation method is simple and the effect is good.

[0072] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. An integrated chip, characterized in that: include: A wafer layer, wherein the wafer layer includes a first single crystal silicon layer, a second single crystal silicon layer, and a silicon dioxide dielectric layer disposed between the first single crystal silicon layer and the second single crystal silicon layer, wherein the first single crystal silicon layer includes a groove region, wherein the groove region separates the first single crystal silicon layer into a middle region and an edge region, and a first chip is formed at a portion of the first single crystal silicon layer located in the middle region; A first dielectric layer formed on a side of the first single crystal silicon layer facing away from the second single crystal silicon layer; A first metal portion is formed on the first dielectric layer away from the first single crystal silicon layer, the first metal portion being electrically connected to a corresponding electrical connection portion of the first chip through a via; A second chip device layer is formed on a side of the second single crystal silicon layer away from the first single crystal silicon layer, the second chip device layer forming a second chip; a second dielectric layer formed on a side of the second chip device layer away from the second single crystal silicon layer; A second metal portion is formed on the side of the second dielectric layer away from the second chip device layer, the second metal portion is electrically connected to the corresponding electrical connection portion of the second chip through a via hole; the second metal portion is electrically connected to the corresponding first metal portion through a via hole penetrating the second dielectric layer, the second chip device layer, the wafer layer, and the first dielectric layer; The first chip and the second chip are integrated into the integrated chip through a wafer process.

2. The integrated chip according to claim 1, characterized in that: The invention also includes a first protective layer formed on a side of the first metal portion away from the first single crystal silicon layer and a second protective layer formed on a side of the second metal portion away from the second single crystal silicon layer.

3. The integrated chip according to claim 2, characterized in that: A lead terminal is disposed on a surface of the first protective layer on a side facing away from the first single crystal silicon layer. The lead terminal is electrically connected to the first metal portion through a via hole penetrating the first protective layer.

4. The integrated chip according to claim 1, characterized in that: The invention also includes a buffer layer formed between the second chip device layer and the second single crystal silicon layer.

5. The integrated chip according to claim 1, characterized in that: It also includes an isolation structure formed in the second chip device layer for isolating adjacent second chips.

6. The integrated chip according to claim 1, characterized in that: The first chip is a driver chip.

7. The integrated chip according to claim 1, characterized in that: The second chip is a gallium nitride high electron mobility transistor.

8. The integrated chip according to claim 1, characterized in that: It also includes an insulating layer arranged on the side wall of the via hole that penetrates the second dielectric layer, the second chip device layer, the wafer layer, and the first dielectric layer.

9. The integrated chip according to claim 8, characterized in that: The insulating layer is a silicon dioxide layer.

10. A method for preparing an integrated chip, characterized in that: include: Providing a wafer layer, the wafer layer comprising a first single crystal silicon layer, a second single crystal silicon layer, and a silicon dioxide dielectric layer disposed between the first single crystal silicon layer and the second single crystal silicon layer; forming a groove region on the first single crystal silicon layer to separate the first single crystal silicon layer into a middle region and an edge region; forming a first chip in a middle region of the first single crystal silicon layer; forming a first dielectric layer on a side of the first single crystal silicon layer facing away from the second single crystal silicon layer; forming a second chip device layer on a side of the second single crystal silicon layer away from the first single crystal silicon layer, wherein the second chip device layer forms a second chip; forming a second dielectric layer on a side of the second chip device layer away from the second single crystal silicon layer; forming a via hole in a portion of the second dielectric layer opposite to the electrical connection portion of the second chip, and forming a via hole in a portion of the first dielectric layer opposite to the electrical connection portion of the first chip; Forming a via hole penetrating the second dielectric layer, the second chip device layer, the wafer layer, and the first dielectric layer in a portion opposite to the edge region of the first single crystal silicon; forming a first metal portion on a side of the first dielectric layer away from the first single crystal silicon layer, wherein the first metal portion is electrically connected to a corresponding electrical connection portion of the first chip through a via; A second metal part is formed on the side of the second dielectric layer facing away from the second chip device layer, and the second metal part is electrically connected to the corresponding electrical connection part of the second chip through a via; the second metal part is electrically connected to the corresponding first metal part through a via that penetrates the second dielectric layer, the second chip device layer, the wafer layer, and the first dielectric layer.

11. The preparation method according to claim 10, characterized in that: The method also includes forming a buffer layer on a side of the second single crystal silicon layer away from the first single crystal silicon layer by using a vapor deposition method.

12. The preparation method according to claim 10, characterized in that: The method also includes forming an isolation structure between every two adjacent second chips in the second chip device layer by using an ion implantation process.

13. The preparation method according to claim 10, characterized in that: The method also includes forming an insulating layer on the sidewall of the via hole that passes through the second dielectric layer, the second chip device layer, the wafer layer, and the first dielectric layer by using a chemical vapor deposition method.

14. The preparation method according to claim 10, characterized in that: The method also includes forming a first protective layer on a side of the first metal portion away from the first single crystal silicon layer, and forming a second protective layer on a side of the second metal portion away from the second single crystal silicon layer.

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