A low-cost and high-performance IGBT driving circuit and method

Abstract

The present invention discloses a low-cost, high-performance IGBT driving circuit and method, wherein the driving circuit comprises: a signal input module for inputting a first PWM control signal and a second PWM control signal; a driving module for controlling the working state of a MOS upper tube according to the first PWM control signal and controlling the working state of a MOS lower tube according to the second PWM control signal; a discharge module, comprising an upper tube discharge unit and a lower tube discharge unit, wherein the upper tube discharge unit is used to release the electricity on the gate of the MOS upper tube after the MOS upper tube is turned off; and the lower tube discharge unit is used to release the electricity on the gate of the MOS lower tube after the MOS lower tube is turned off. The present invention provides a novel low-cost, high-performance, small and medium-power IGBT driving application circuit, which is simple, has the advantages of low cost and high reliability, has good economic and social application value, and can be widely used in the field of power electronics application technology.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics applications, and in particular to a low-cost and high-performance IGBT driving circuit and method. Background Art

[0002] The existing patents with patent numbers CN202020365413.0 and CN202010500180.5 have detailed the small and medium power IGBT driving technology. The former uses the driver chip acpl-333j+ to assist the periphery to realize IGBT driving and protection, which increases the chip cost and is unfavorable to the cost of small and medium-sized enterprises; although the latter does not rely on the driver chip, it uses optocoupler drive isolation, which cannot be used in occasions with high requirements for speed dynamic performance.

[0003] Terminology explanation:

[0004] IGBT: Insulated Gate Bipolar Transistor, is a composite fully controlled voltage-driven power semiconductor device composed of BJT (bipolar junction transistor) and MOS (insulated gate field effect transistor), which has the advantages of both high input impedance of MOSFET and low on-state voltage drop of GTR. Summary of the invention

[0005] In order to solve one of the technical problems existing in the prior art to at least a certain extent, an object of the present invention is to provide a low-cost and high-performance IGBT driving circuit and method.

[0006] The technical solution adopted by the present invention is:

[0007] A low-cost and high-performance IGBT driving circuit, comprising:

[0008] A signal input module, used for inputting a first PWM control signal and a second PWM control signal;

[0009] A driving module, used to control the working state of the MOS upper tube according to the first PWM control signal, and control the working state of the MOS lower tube according to the second PWM control signal;

[0010] The discharge module comprises an upper tube discharge unit and a lower tube discharge unit. The upper tube discharge unit is used to release the electricity on the grid of the MOS upper tube after the MOS upper tube is turned off; the lower tube discharge unit is used to release the electricity on the grid of the MOS lower tube after the MOS lower tube is turned off.

[0011] Further, the signal input module includes a first input module and a second input module;

[0012] The first input module includes a twenty-fifth resistor, a twenty-sixth resistor and a ninth transistor;

[0013] One end of the 25th resistor is connected to the first bias voltage, the other end of the 25th resistor is connected to the base of the 9th transistor, the emitter of the 9th transistor is connected to one end of the 26th resistor, the other end of the 26th resistor inputs the first PWM control signal, and the collector of the 9th transistor is connected to the driving module;

[0014] The second input module includes a thirty-first resistor and a thirteenth transistor;

[0015] The base of the thirteenth transistor is connected to the first bias voltage, the emitter of the thirteenth transistor is connected to one end of the thirty-first resistor, the other end of the thirty-first resistor inputs the second PWM control signal, and the collector of the thirteenth transistor is connected to the driving module.

[0016] Further, the driving module includes an upper tube driving unit and a lower tube driving unit;

[0017] The upper tube driving unit is used to control the working state of the MOS upper tube, and the lower tube driving unit is used to control the working state of the MOS lower tube.

[0018] Further, the upper tube driving unit includes a tenth transistor, an eighth diode, a twenty-third resistor, a ninety-ninth resistor and a hundredth resistor;

[0019] The base of the tenth transistor is connected to the collector of the ninth transistor, the emitter of the tenth transistor is connected to the second bias voltage, the collector of the tenth transistor is connected to the anode of the eighth diode, the cathode of the eighth diode is connected to one end of the twenty-third resistor, the other end of the twenty-third resistor is respectively connected to one end of the ninety-ninth resistor and one end of the one hundredth resistor, the other end of the ninety-ninth resistor is connected to the gate of the fifth MOS tube, and the other end of the one hundredth resistor is connected to the gate of the sixth MOS tube;

[0020] The fifth MOS tube and the sixth MOS tube are both MOS upper tubes.

[0021] Further, the lower tube driving unit includes an eleventh transistor, a nineteenth diode, a twenty-eighth resistor, a twenty-ninth resistor, a thirtieth resistor and a sixty-seventh resistor;

[0022] The base of the eleventh transistor is connected to the collector of the thirteenth transistor, the emitter of the eleventh transistor is connected to the second bias voltage, the collector of the eleventh transistor is connected to the anode of the nineteenth diode, the cathode of the nineteenth diode is connected to one end of the twenty-eighth resistor, and the other end of the twenty-eighth resistor is respectively connected to one end of the twenty-ninth resistor, one end of the thirtieth resistor and one end of the sixty-seventh resistor;

[0023] The other end of the 29th resistor is connected to the gate of the seventh MOS tube, the other end of the 30th resistor is connected to the gate of the eighth MOS tube, and the other end of the 67th resistor is connected to the gate of the fourteenth MOS tube;

[0024] The seventh MOS tube, the eighth MOS tube and the fourteenth MOS tube are all MOS lower tubes.

[0025] Further, the upper tube discharge unit includes a sixth transistor, a forty-ninth resistor, a fifty-third resistor, a nineteenth resistor and a twenty-first capacitor;

[0026] The base of the sixth transistor is connected to the collector of the tenth transistor, the emitter of the sixth transistor is connected to the other end of the twenty-third resistor, the collector of the sixth transistor is grounded via the fifty-third resistor and the nineteenth resistor in sequence, and the forty-ninth resistor is connected in series between the base and the collector of the sixth transistor;

[0027] One end of the twenty-first capacitor is connected to one end of the first hundred resistor, and the other end of the twenty-first capacitor is connected to the collector of the sixth transistor.

[0028] Further, the lower tube discharge unit includes a fourteenth transistor and a nineteenth resistor;

[0029] The base of the fourteenth transistor is connected to the collector of the eleventh transistor, the emitter of the fourteenth transistor is connected to the other end of the twenty-eighth resistor, and the collector of the fourteenth transistor is grounded through the nineteenth resistor.

[0030] Further, the lower tube driving unit includes an overcurrent protection circuit, and the overcurrent protection circuit includes a seventy-sixth capacitor and a thirty-third resistor;

[0031] One end of the seventy-sixth capacitor is connected to one end of the nineteenth resistor, the other end of the seventy-sixth capacitor is connected to one end of the thirty-third resistor, and the other end of the thirty-third resistor is connected to the base of the eleventh transistor.

[0032] Furthermore, the lower tube driving unit further includes a thirtieth diode, an anode of the thirtieth diode is connected to the second bias voltage, and a cathode of the thirtieth diode is connected to the emitter of the eleventh transistor.

[0033] Another technical solution adopted by the present invention is:

[0034] A control method, applied to a low-cost and high-performance IGBT drive circuit as described above, comprises the following steps:

[0035] Using the first PWM control signal to control the on and off of the MOS upper tube;

[0036] The second PWM control signal is used to control the on and off of the MOS lower tube;

[0037] When the MOS lower tube is turned on, the MOS upper tube is also turned on.

[0038] The beneficial effects of the present invention are as follows: the present invention provides a novel low-cost, high-performance, small and medium-power IGBT drive application circuit, the drive circuit is simple, has the advantages of low cost and high reliability, and has good economic and social application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the embodiments of the present invention or the drawings of related technical solutions in the prior art are introduced below. It should be understood that the drawings introduced below are only for the convenience of clearly describing some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 is an electronic circuit diagram of a low-cost, high-performance IGBT drive circuit in an embodiment of the present invention;

[0041] Figure 2 It is a simulation circuit diagram of a low-cost and high-performance IGBT drive circuit in an embodiment of the present invention;

[0042] Figure 3 It is a schematic diagram of simulation results of a low-cost and high-performance IGBT drive circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and are not to be construed as limitations of the present invention. For the step numbers in the following embodiments, they are only provided for the convenience of explanation, and the order between the steps is not limited in any way, and the execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0044] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0045] In the description of the present invention, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed" etc. are understood as not including the number itself, and "above", "below", "within" etc. are understood as including the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing the technical features, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0046] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0047] like Figure 1 As shown, this embodiment provides a low-cost and high-performance IGBT driving circuit, including:

[0048] A signal input module, used for inputting a first PWM control signal and a second PWM control signal;

[0049] A driving module, used to control the working state of the MOS upper tube according to the first PWM control signal, and control the working state of the MOS lower tube according to the second PWM control signal;

[0050] The discharge module comprises an upper tube discharge unit and a lower tube discharge unit. The upper tube discharge unit is used to release the electricity on the grid of the MOS upper tube after the MOS upper tube is turned off; the lower tube discharge unit is used to release the electricity on the grid of the MOS lower tube after the MOS lower tube is turned off.

[0051] Further as an optional implementation, the signal input module includes a first input module and a second input module;

[0052] The first input module includes a twenty-fifth resistor R25, a twenty-fifth resistor R26 and a ninth transistor Q9;

[0053] One end of the 25th resistor R25 is connected to the first bias voltage, the other end of the 25th resistor R25 is connected to the base of the ninth transistor Q9, the emitter of the ninth transistor Q9 is connected to one end of the 25th resistor R26, the other end of the 25th resistor R26 inputs the first PWM control signal, and the collector of the ninth transistor Q9 is connected to the driving module;

[0054] The second input module includes a thirty-first resistor R31 and a thirteenth transistor Q13;

[0055] The base of the thirteenth transistor Q13 is connected to the first bias voltage, the emitter of the thirteenth transistor Q13 is connected to one end of the thirty-first resistor R31, the other end of the thirty-first resistor R31 inputs the second PWM control signal, and the collector of the thirteenth transistor Q13 is connected to the driving module.

[0056] Further as an optional implementation, the driving module includes an upper tube driving unit and a lower tube driving unit;

[0057] The upper tube driving unit is used to control the working state of the MOS upper tube, and the lower tube driving unit is used to control the working state of the MOS lower tube.

[0058] Further as an optional implementation, the upper tube driving unit includes a tenth transistor Q10, an eighth diode D8, a twenty-third resistor R23, a ninety-ninth resistor R99 and a hundredth resistor R100;

[0059] The base of the tenth transistor Q10 is connected to the collector of the ninth transistor Q9, the emitter of the tenth transistor Q10 is connected to the second bias voltage, the collector of the tenth transistor Q10 is connected to the anode of the eighth diode D8, the cathode of the eighth diode D8 is connected to one end of the twenty-third resistor R23, the other end of the twenty-third resistor R23 is respectively connected to one end of the ninety-ninth resistor R99 and one end of the one-hundredth resistor R100, the other end of the ninety-ninth resistor R99 is connected to the gate of the fifth MOS tube, and the other end of the one-hundredth resistor R100 is connected to the gate of the sixth MOS tube;

[0060] The fifth MOS tube and the sixth MOS tube are both MOS upper tubes.

[0061] Further as an optional implementation, the lower tube driving unit includes an eleventh transistor Q11, a nineteenth diode D19, a twenty-eighth resistor R28, a twenty-ninth resistor R29, a thirtieth resistor R30 and a sixty-seventh resistor R67;

[0062] The base of the eleventh transistor Q11 is connected to the collector of the thirteenth transistor Q13, the emitter of the eleventh transistor Q11 is connected to the second bias voltage, the collector of the eleventh transistor Q11 is connected to the anode of the nineteenth diode D19, the cathode of the nineteenth diode D19 is connected to one end of the twenty-eighth resistor R28, and the other end of the twenty-eighth resistor R28 is respectively connected to one end of the twenty-ninth resistor R29, one end of the thirtieth resistor R30 and one end of the sixty-seventh resistor R67;

[0063] The other end of the 29th resistor R29 is connected to the gate of the seventh MOS tube, the other end of the 30th resistor R30 is connected to the gate of the eighth MOS tube, and the other end of the 67th resistor R67 is connected to the gate of the fourteenth MOS tube;

[0064] The seventh MOS tube, the eighth MOS tube and the fourteenth MOS tube are all MOS lower tubes.

[0065] As a further optional implementation, the upper tube discharge unit includes a sixth transistor Q6, a forty-ninth resistor R49, a fifty-third resistor R53, a nineteenth resistor R19 and a twenty-first capacitor C21;

[0066] The base of the sixth transistor Q6 is connected to the collector of the tenth transistor Q10, the emitter of the sixth transistor Q6 is connected to the other end of the twenty-third resistor R23, the collector of the sixth transistor Q6 is grounded via the fifty-third resistor R53 and the nineteenth resistor R19 in sequence, and the forty-ninth resistor R49 is connected in series between the base and the collector of the sixth transistor Q6;

[0067] One end of the twenty-first capacitor C21 is connected to one end of the first-hundredth resistor R100 , and the other end of the twenty-first capacitor C21 is connected to the collector of the sixth transistor Q6 .

[0068] As a further optional implementation, the lower tube discharge unit includes a fourteenth transistor Q14 and a nineteenth resistor R19;

[0069] The base of the fourteenth transistor Q14 is connected to the collector of the eleventh transistor Q11, the emitter of the fourteenth transistor Q14 is connected to the other end of the twenty-eighth resistor, and the collector of the fourteenth transistor Q14 is grounded through the nineteenth resistor R19.

[0070] Further as an optional implementation, the lower tube driving unit includes an overcurrent protection circuit, and the overcurrent protection circuit includes a seventy-sixth capacitor C76 and a thirty-third resistor R33;

[0071] One end of the seventy-sixth capacitor C76 is connected to one end of the nineteenth resistor R19, the other end of the seventy-sixth capacitor C76 is connected to one end of the thirty-third resistor R33, and the other end of the thirty-third resistor R33 is connected to the base of the eleventh transistor Q11.

[0072] As a further optional implementation, the lower tube driving unit further includes a 30th diode D30, an anode of the 30th diode D30 is connected to the second bias voltage, and a cathode of the 30th diode D30 is connected to the emitter of the eleventh transistor Q11.

[0073] The following combination Figure 1-Figure 3 The above circuit is explained in detail.

[0074] The principle of normal driving and shutting down of MOS upper tube is as follows:

[0075] When the input signal IO1 is at a low level, the first bias voltage 3.3V is amplified through the resistor R25, the transistor Q9, and the resistor R26 to form a loop, so that the transistor Q9 is turned on. After the transistor Q9 is turned on, the second bias voltage 15V forms a loop through the diode D9, the resistor R17, the transistor Q9, and the resistor R26. At this time, the transistor Q10 is also turned on. At this time, the transistor Q6 is turned off. The second bias voltage 15V is pumped up and charged through the diode D9, the resistor R49, and the capacitor C22 bootstrap circuit. At the same time, the second bias voltage 15V is normally driven by the transistor Q10, the diode D8, the resistor R23, the resistor R99, and the resistor R100. At this time, MOS5 and MOS6 are turned on.

[0076] When the input signal IO1 is at a high level, transistors Q9 and Q10 are turned off, and transistor Q6 is turned on. MOS5 is discharged through resistor R99, and MOS6 is discharged through resistors R100 and C21, and then through transistor Q6, resistor R49 and resistor R131. At this time, the corresponding MOS5 and MOS6 are turned off.

[0077] The principle of normal driving and shutting down of the lower tube is as follows:

[0078] When the input signal IO2 is at a low level, the first bias voltage 3.3V is amplified through the transistor Q13 and the resistor R31 to form a loop, so that the transistor Q11 is turned on. After the transistor Q11 is turned on, the second bias voltage 15V forms a loop through the diode D30, the transistor Q11, the transistor Q13, and the resistor R31. At this time, the transistor Q11 is also turned on, and the transistor Q14 is turned off. The second bias voltage 15V is directly pushed and pulled through the diode D30, the transistor Q11, the diode D19, the resistor R28, the resistor R29, and the resistor R30 to drive MOS7, MOS8, and MOS14. At the same time, the second bias voltage 15V is normally driven through Q10, D8, R23, R99, and R100 to drive MOS5 and MOS6.

[0079] When the input signal IO2 is at a high level, the transistors Q11 and Q13 are turned off, while the transistor Q14 is turned on. MOS7, MOS8 and MOS14 are discharged through the resistors R29, R130, capacitors C23 and R67, and then through Q14, R32 and R19. At this time, the corresponding MOS7, MOS8 and MOS14 are turned off.

[0080] When the system is powered on, the upper tube needs to be charged by turning on the lower tubes MOS7, MOS8, and MOS14. The specific working process is as follows:

[0081] Input IO1 is set high and IO2 is set low, that is, the lower tube is turned on and the upper tube is turned off (this specific working process has been described in detail above and will not be repeated here);

[0082] When IO2 is low and the lower tube is turned on, 15V charges the electrolytic capacitor C22 to 15V through the diode D9 and the resistor R131;

[0083] When the input detects that the input IO1 is low and IO2 is high, that is, when the upper tube is turned on and the lower tube is turned off, the upper tubes MOS5 and MOS6 are powered by bootstrap to increase the voltage at the gate of the upper tubes MOS5 and MOS6 to 15V higher than the voltage at point U (the voltage across the electrolytic capacitor C22 cannot change suddenly).

[0084] The IGBT overcurrent protection principle is as follows:

[0085] When an overcurrent occurs in the IGBT, a high level is detected at the SENSOR terminal. At this time, the base of the transistor Q11 that the SENSOR enters through the capacitor C76 and the resistor R30 is at a high level. Therefore, the transistor Q11 is cut off, resulting in blocking the path of the second bias voltage 15V to MOS7, MOS8 and MOS14, thereby effectively protecting the IGBT from overcurrent damage.

[0086] The principle of IGBT turn-on and turn-off timing control is as follows:

[0087] When the upper tube of the IGBT is turned on, the gate charging circuit of MOS5 is: 15V→D8→R23→R99 to drive MOS5; the gate charging circuit of MOS6 is: 15V→D8→R23→R100 to drive MOS6.

[0088] When the upper tube of the IGBT is turned off, the gate discharge circuit of MOS5 is: MOS5→R99→Q6→R49→R53→R19→ground for discharge; the gate discharge circuit of MOS6 is: MOS6→R100→C21→R53→R19→ground for discharge.

[0089] When the lower tube of IGBT is turned on, the gate charging circuit of MOS7 is: 15V→D19→R28→R29 drives MOS7; the gate charging circuit of MOS8 is: 15V→D19→R28→R30→ drives MOS8; the gate charging circuit of MOS14 is: 15V→D19→R28→R167→ drives MOS8.

[0090] When the lower tube of the IGBT is turned off, the gate discharge circuit of MOS7 is: MOS7→R29→Q14→R19→ground for discharge; the gate discharge circuit of MOS8 is: MOS8→R30→Q14→R19→ground for discharge; the gate discharge circuit of MOS14 is: MOS14→R67→Q14→R19→ground for discharge.

[0091] Figure 2 is a simulation circuit diagram of the IGBT driving circuit of this embodiment, Figure 3 The driving voltage waveforms of the MOS upper tube and the MOS lower tube obtained by simulation.

[0092] In summary, the IGBT driving circuit of this embodiment has the following beneficial effects compared with the prior art:

[0093] (1) This embodiment provides a novel low-cost, high-performance, small and medium-power IGBT drive application circuit, which has a simple drive circuit, a small on-board volume, low cost, high reliability, and good economic and social application value.

[0094] (2) The IGBT small and medium drive application circuit of this embodiment does not require any auxiliary power supply, simplifies the circuit, and naturally reduces the common coupling links that cause circuit parasitic oscillations. The circuit design of this embodiment is simple, the components are small, and few external components are required, which simplifies the circuit and saves the main circuit board area.

[0095] (3) The small power IGBT drive application circuit in this embodiment is suitable for single tube, half-bridge and full-bridge driving, and is also suitable for series and parallel driving of small and medium power IGBTs, which greatly expands its application scope and has a wide economic and social value.

[0096] In some selectable embodiments, the function / operation mentioned in the block diagram may not occur in the order mentioned in the operation diagram. For example, depending on the function / operation involved, the two boxes shown in succession can actually be executed substantially simultaneously or the boxes can sometimes be executed in reverse order. In addition, the embodiment presented and described in the flow chart of the present invention is provided by way of example, for the purpose of providing a more comprehensive understanding of technology. The disclosed method is not limited to the operation and logic flow presented herein. Selectable embodiments are expected, wherein the order of various operations is changed and the sub-operation of a part for which is described as a larger operation is performed independently.

[0097] In addition, although the present invention is described in the context of functional modules, it should be understood that, unless otherwise specified, one or more of the functions and / or features described may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in separate physical devices or software modules. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding the present invention. More specifically, in view of the properties, functions, and internal relationships of the various functional modules in the device disclosed herein, the actual implementation of the module will be understood within the conventional skills of the engineer. Therefore, those skilled in the art can implement the present invention set forth in the claims without excessive experimentation using ordinary techniques. It is also understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present invention, which is determined by the full scope of the appended claims and their equivalents.

[0098] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc., which can store program codes.

[0099] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in conjunction with such instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in conjunction with such instruction execution systems, devices or apparatuses.

[0100] More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk case (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be a paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering or, if necessary, processing in another suitable manner, and then stored in a computer memory.

[0101] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0102] In the above description of this specification, the description with reference to the terms "one embodiment / example", "another embodiment / example" or "certain embodiments / examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0103] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

[0104] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the above embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A low-cost, high-performance IGBT drive circuit, characterized in that: include: A signal input module, used for inputting a first PWM control signal and a second PWM control signal; A driving module, used to control the working state of the MOS upper tube according to the first PWM control signal, and control the working state of the MOS lower tube according to the second PWM control signal; The discharge module includes an upper tube discharge unit and a lower tube discharge unit, wherein the upper tube discharge unit is used to release the electricity on the gate of the MOS upper tube after the MOS upper tube is turned off; and the lower tube discharge unit is used to release the electricity on the gate of the MOS lower tube after the MOS lower tube is turned off; The signal input module includes a first input module and a second input module; The first input module includes a twenty-fifth resistor, a twenty-sixth resistor and a ninth transistor; One end of the 25th resistor is connected to the first bias voltage, the other end of the 25th resistor is connected to the base of the 9th transistor, the emitter of the 9th transistor is connected to one end of the 26th resistor, the other end of the 26th resistor inputs the first PWM control signal, and the collector of the 9th transistor is connected to the driving module; The second input module includes a thirty-first resistor and a thirteenth transistor; The base of the thirteenth transistor is connected to the first bias voltage, the emitter of the thirteenth transistor is connected to one end of the thirty-first resistor, the other end of the thirty-first resistor inputs the second PWM control signal, and the collector of the thirteenth transistor is connected to the driving module; The driving module includes an upper tube driving unit and a lower tube driving unit; The upper tube driving unit is used to control the working state of the MOS upper tube, and the lower tube driving unit is used to control the working state of the MOS lower tube; The upper tube driving unit includes a tenth transistor, an eighth diode, a twenty-third resistor, a ninety-ninth resistor and a hundredth resistor; The base of the tenth transistor is connected to the collector of the ninth transistor, the emitter of the tenth transistor is connected to the second bias voltage, the collector of the tenth transistor is connected to the anode of the eighth diode, the cathode of the eighth diode is connected to one end of the twenty-third resistor, the other end of the twenty-third resistor is respectively connected to one end of the ninety-ninth resistor and one end of the one hundredth resistor, the other end of the ninety-ninth resistor is connected to the gate of the fifth MOS tube, and the other end of the one hundredth resistor is connected to the gate of the sixth MOS tube; The fifth MOS tube and the sixth MOS tube are both MOS upper tubes; The lower tube driving unit includes an eleventh transistor, a nineteenth diode, a twenty-eighth resistor, a twenty-ninth resistor, a thirtieth resistor and a sixty-seventh resistor; The base of the eleventh transistor is connected to the collector of the thirteenth transistor, the emitter of the eleventh transistor is connected to the second bias voltage, the collector of the eleventh transistor is connected to the anode of the nineteenth diode, the cathode of the nineteenth diode is connected to one end of the twenty-eighth resistor, and the other end of the twenty-eighth resistor is respectively connected to one end of the twenty-ninth resistor, one end of the thirtieth resistor and one end of the sixty-seventh resistor; The other end of the 29th resistor is connected to the gate of the seventh MOS tube, the other end of the 30th resistor is connected to the gate of the eighth MOS tube, and the other end of the 67th resistor is connected to the gate of the fourteenth MOS tube; The seventh MOS tube, the eighth MOS tube and the fourteenth MOS tube are all MOS lower tubes.

2. A low-cost, high-performance IGBT drive circuit according to claim 1, characterized in that: The upper tube discharge unit includes a sixth transistor, a forty-ninth resistor, a fifty-third resistor, a nineteenth resistor and a twenty-first capacitor; The base of the sixth transistor is connected to the collector of the tenth transistor, the emitter of the sixth transistor is connected to the other end of the twenty-third resistor, the collector of the sixth transistor is grounded through the fifty-third resistor and the nineteenth resistor in sequence, and the forty-ninth resistor is connected in series between the base and the collector of the sixth transistor; One end of the twenty-first capacitor is connected to one end of the first hundred resistor, and the other end of the twenty-first capacitor is connected to the collector of the sixth transistor.

3. A low-cost, high-performance IGBT drive circuit according to claim 1, characterized in that: The lower tube discharge unit includes a fourteenth transistor and a nineteenth resistor; The base of the fourteenth transistor is connected to the collector of the eleventh transistor, the emitter of the fourteenth transistor is connected to the other end of the twenty-eighth resistor, and the collector of the fourteenth transistor is grounded through the nineteenth resistor.

4. A low-cost, high-performance IGBT drive circuit according to claim 3, characterized in that: The lower tube driving unit includes an overcurrent protection circuit, and the overcurrent protection circuit includes a seventy-sixth capacitor and a thirty-third resistor; One end of the seventy-sixth capacitor is connected to one end of the nineteenth resistor, the other end of the seventy-sixth capacitor is connected to one end of the thirty-third resistor, and the other end of the thirty-third resistor is connected to the base of the eleventh transistor.

5. The low-cost, high-performance IGBT drive circuit according to claim 1, characterized in that: The lower tube driving unit further includes a 30th diode, an anode of the 30th diode is connected to the second bias voltage, and a cathode of the 30th diode is connected to the emitter of the 11th transistor.

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