Analog-to-digital converter, image sensor, and method for operating the same

Abstract

An analog-to-digital converter, an image sensor including the analog-to-digital converter, and a method for operating the analog-to-digital converter are provided. The analog-to-digital converter is used to convert a pixel signal generated from sensed light into a digital signal, and the analog-to-digital converter includes: a comparator configured to compare the pixel signal with a ramp signal having a constant slope to generate a comparison signal; a delay circuit configured to generate a first signal corresponding to the comparison signal, the delay circuit including a plurality of delay elements configured to generate a second signal by delaying the first signal by a first time period; and a compensator circuit configured to measure a period of the comparison signal and output a delay selection signal to the delay circuit based on the measured period, the delay selection signal being used to delay the first signal by a first time period, wherein the first time period is obtained by dividing the period of the comparison signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0130811 filed on October 21, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present inventive concept relates to an analog-to-digital converter (ADC), and more particularly, to an ADC including a digital correlated double sampling (CDS) circuit, an image sensor including the ADC, and a method of operating the ADC. Background Art

[0004] An image sensor is a device that detects and transmits information used to create an image. Two main types of image sensors include charge-coupled device (CCD) image sensors and complementary metal oxide semiconductor (CMOS) image sensors. Cameras integrated into small consumer products (e.g., smartphones) often include CMOS image sensors for capturing images. CMOS image sensors can be arranged as an array of pixels (e.g., a pixel array).

[0005] The analog pixel signals output from the pixel array may include variations due to differences in the inherent characteristics of the pixels (e.g., fixed pattern noise (FPN)). Furthermore, the digital pixel signals generated from the analog pixel signals may include variations due to differences in the characteristics of the analog-to-digital conversion elements arranged in the columns of the pixel array. A CDS circuit including a counter can be used to compensate for such variations. However, using a CDS circuit to perform this compensation may require the counter to run at a very high speed, which increases power consumption. Summary of the Invention

[0006] At least one embodiment of the inventive concept provides an analog-to-digital converter (ADC) that improves an operating speed of an image sensor without increasing a clock speed of the image sensor, an image sensor including the ADC, and a method of operating the ADC.

[0007] According to an exemplary embodiment of the present invention, an ADC is provided for converting a pixel signal (e.g., an analog signal) generated from sensed light into a digital signal. The ADC includes: a comparator configured to compare the pixel signal with a ramp signal having a constant slope to generate a comparison signal; a delay circuit configured to generate a first signal corresponding to the comparison signal, the delay circuit including a plurality of delay elements configured to delay the first signal by a first time period to generate a second signal; and a compensator circuit configured to measure a period of the comparison signal and output a delay selection signal to the delay circuit based on the measured period, the delay selection signal being used to delay the first signal by the first time period, wherein the first time period is obtained by dividing the period of the comparison signal.

[0008] According to an exemplary embodiment of the present inventive concept, there is provided an image sensor, comprising: a pixel array including a plurality of pixels arranged in a matrix, each of the plurality of pixels being configured to generate a pixel signal; a ramp generator being configured to generate a ramp signal in response to a ramp enable signal, the ramp signal having a constant slope; a comparator being configured to compare the pixel signal with the ramp signal to generate a comparison signal; a plurality of delay circuits each including a plurality of delay elements configured to delay the comparison signal, each of the plurality of delay circuits being configured to generate a first signal corresponding to the comparison signal and generate a second signal by delaying the first signal by a first time period; a compensator circuit configured to measure a period of the comparison signal and output a delay selection signal to the multiple delay circuits based on the measured period, the delay selection signal being used to delay the first signal by the first time period; a phase generator configured to generate a plurality of phase-shifted codes based on a clock signal; a timing generator configured to generate the clock signal and the ramp enable signal; a latch circuit configured to latch the plurality of phase-shifted codes based on the first signal and the second signal; and a column counter configured to generate a binary code based on a digital code output from the latch circuit and output the binary code sequentially bit by bit, wherein the first time period is obtained by dividing the period of the comparison signal.

[0009] According to an exemplary embodiment of the present inventive concept, a method for operating an ADC is provided. The method includes: comparing a pixel signal with a ramp signal to generate a comparison signal; inverting the comparison signal to generate a first signal; measuring a period of the first signal; determining a first time period based on the measured period; generating a delay selection signal for delaying the first signal by the first time period; and outputting a second signal by delaying the first signal by the first time period based on the delay selection signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The embodiments of the present invention will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram of an image processing system according to an exemplary embodiment of the present inventive concept, the image processing system including an image sensor having an analog-to-digital converter (ADC);

[0012] Figure 2 is a block diagram of an ADC according to an exemplary embodiment of the present inventive concept;

[0013] Figure 3A is a block diagram of a delay circuit according to an exemplary embodiment of the present inventive concept, Figure 3B is a circuit diagram of a delay circuit according to an exemplary embodiment of the present inventive concept;

[0014] Figure 4A is a block diagram of a compensator according to an exemplary embodiment of the present inventive concept, Figure 4B and Figure 4C is a circuit diagram of a compensator according to an exemplary embodiment of the present inventive concept;

[0015] Figure 5 is a circuit diagram of a latch circuit and a counter according to an exemplary embodiment of the present inventive concept;

[0016] Figure 6 is a timing diagram illustrating a clock signal and signals generated from the clock signal according to an exemplary embodiment of the inventive concept;

[0017] 7A to 7C is a block diagram of an image sensor including a delay circuit and a compensator according to an exemplary embodiment of the present inventive concept;

[0018] Figure 8 and Figure 9 is a flowchart of a method of operating an ADC according to an exemplary embodiment of the present inventive concept; and

[0019] Figure 10 is a block diagram of an electronic device including an image sensor according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0020] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0021] Figure 1 is a block diagram of an image processing system 1 according to an exemplary embodiment of the present inventive concept, the image processing system 1 including an image sensor 10 having an analog-to-digital converter (ADC) 200. Figure 1, the image processing system 1 includes an image sensor 10 , an image processor 30 , and a display block 50 (eg, a display device).

[0022] Image sensor 10 includes a pixel array 110, a row driver 120 (e.g., a driving circuit), a ramp generator 130 (e.g., a voltage generator), a phase generator 140 (e.g., a signal generator), a timing generator 150 (e.g., a signal generator), an ADC 200, and an output buffer 160. Image sensor 10 may also include additional components for improving image sensing capabilities.

[0023] Image sensor 10 can be mounted on electronic devices capable of sensing images or light. For example, image sensor 10 can be mounted on electronic devices such as cameras, smartphones, wearable devices, Internet of Things (IoT) devices, tablet personal computers (PCs), personal digital assistants (PDAs), portable multimedia players (PMPs), navigation devices, drones, and advanced driver assistance systems (ADAS). Image sensor 10 can also be mounted on electronic devices used as components in vehicles, furniture, manufacturing facilities, doors, or various measurement devices. Image sensor 10 can be controlled by image processor 30 to sense objects captured by a lens (not shown).

[0024] The pixel array 110 includes a plurality of row lines, a plurality of column lines, and a plurality of pixels arranged in a matrix, wherein each pixel is connected to one row line and one column line. The row line may include a plurality of lines to transmit row selection signals and pixel control signals to the pixels connected thereto.

[0025] In an exemplary embodiment, each pixel includes a photosensitive device that senses light and converts the sensed light into a pixel signal PS (e.g., an analog electrical signal). For example, the photosensitive device may include a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), or a combination thereof. In an exemplary embodiment, the photosensitive device has a four-transistor structure comprising a photodiode, a transfer transistor, a reset transistor, an amplifier transistor, and a select transistor. Depending on the embodiment, the photosensitive device may have a one-transistor structure, a three-transistor structure, a five-transistor structure, or a structure in which some transistors are shared among multiple pixels.

[0026] The row driver 120 drives the pixel array 110 row by row. The row driver 120 can decode the row control signal ROW_CTRL (e.g., an address signal) received from the timing generator 150 and select at least one row of the pixel array 110 in response to the decoded row control signal. For example, the row driver 120 can generate a row select signal. The row select signal and a pixel control signal for controlling the selected pixel can be provided to the pixel via a row line.

[0027] Pixel signals PS are output from a row of pixels selected by a row select signal provided by row driver 120. Pixel signal PS may include a reset signal and an image signal. The voltage difference between the reset signal and the image signal may include information about the amount of light received by each pixel. For example, when the pixel does not receive light, the reset signal is the same as the image signal. When the pixel receives light, the voltage of the reset signal may be different from the voltage of the image signal.

[0028] The ramp generator 130 may generate a ramp signal RAMP. The ramp generator 130 may operate based on a ramp control signal from the timing generator 150. The ramp control signal may include a ramp enable signal RAMP_en. When the ramp enable signal RAMP_en is activated, the ramp generator 130 may generate a ramp signal RAMP having a constant slope. The ramp signal RAMP may increase or decrease at a constant slope.

[0029] The phase generator 140 generates an input phase-shift code IPSC based on the clock signal CLK. The input phase-shift code IPSC may include a plurality of phase-shift signals having the same period and partially overlapping phases. For example, the input phase-shift code IPSC may include first to second phase-shift signals. n Phase-shifted signal, where "n" is a natural number greater than or equal to 2.

[0030] The ADC 200 receives analog signals (eg, pixel signals PS) output from pixels of a selected row and converts the pixel signals PS into digital signals. The digital signals may be referred to as digital pixel values DP. The digital pixel values DP generated by the ADC 200 are output to the output buffer 160.

[0031] In an exemplary embodiment, ADC 200 uses correlated double sampling (CDS) technology to convert the pixel voltage levels into digital codes. CDS technology can be used to remove fixed pattern noise (FPN) that can be observed in the signals output from the image sensor's pixels and can be used to detect desired signal components. The use of CDS technology can significantly reduce the inherent FPN of the pixels and noise caused by differences in pixel characteristics. CDS technology utilizes the difference between a reset signal maintained at a constant voltage level and the image signal corresponding to the light signal sensed by each pixel.

[0032] ADC 200 includes a delay circuit 220 and a compensator 230 (eg, a circuit). Figures 2 to 4C The delay circuit 220 and the compensator 230 are described.

[0033] The timing generator 150 may provide a control signal and / or a clock signal CLK to each component of the image sensor 10 (e.g., the row driver 120, the ramp generator 130, the phase generator 140, and the ADC 200). The row driver 120, the ramp generator 130, and the ADC 200 may each operate according to the timing set therefor based on the control signal and / or clock signal CLK provided by the timing generator 150. For example, a counter included in the ADC 200 may receive a count signal and a clock signal CLK from the timing generator 150. For example, the timing generator 150 may generate and output a row control signal ROW_CTRL to the row driver 120, may generate and output a ramp enable signal RAMP_en to the ramp generator 130, and may generate and output a clock signal CLK to the phase generator 140.

[0034] Output buffer 160 can temporarily store the plurality of digital pixel values DP output from ADC 200, then amplify and output the digital pixel values DP. Output buffer 160 may include a plurality of memories (not shown) and readout amplifiers (not shown). Each memory can temporarily store the digital pixel values DP output from ADC 200, and then sequentially or selectively output the digital pixel values DP to the readout amplifiers. The readout amplifiers can sense and amplify the digital pixel values DP. The readout amplifiers can output the amplified digital pixel values as image data IDATA.

[0035] The image processor 30 may process the image data IDATA that has been sensed and output by the image sensor 10, and may output the processed image data to the display block 50. The image processor 30 includes an image signal processor (ISP) 310, a camera controller 320 (e.g., a control circuit), and a PC interface (I / F) 330 (e.g., an interface circuit). For example, the camera controller 320 may use an inter-integrated circuit (I 2 C) to control the image sensor 10. However, embodiments of the inventive concept are not limited thereto, and various interfaces may be used between the camera controller 320 and the image sensor 10.

[0036] The ISP 310 may receive image data IDATA (e.g., an output signal of the output buffer 160), process the image data IDATA to generate an image that can be viewed by humans, and output the processed image to the display block 50. Alternatively, the ISP 310 may receive a control signal from an external host through the PC I / F 330 and provide the processed image to the external host. Figure 1 The ISP 310 is located in the image processor 30 , but embodiments of the inventive concept are not limited thereto. For example, the ISP 310 may be located in the image sensor 10 .

[0037] The display block 50 includes any device that can output an image. For example, the display block 50 may include a computer, a cellular phone, or other image output terminals.

[0038] The image sensor 10 includes a delay circuit 220 that generates a digital pixel value DP, and the delay circuit 220 can generate at least one signal delayed based on the delay selection signal received from the compensator 230. Additional bits can be ensured by generating pixel data in the digital domain using the at least one signal. Figures 2 to 10 Describe this.

[0039] Figure 2 2 is a block diagram of an ADC 200 according to an exemplary embodiment of the present inventive concept. Figure 2 , the ADC 200 includes a comparator 210 (eg, a comparison circuit, an operational amplifier, etc.), a delay circuit 220 , a compensator 230 , a latch circuit 240 , and a counter 250 (eg, a counter circuit).

[0040] The comparator 210 can receive a plurality of pixel signals PS from each column of the pixel array 110 via a column line. The comparator 210 can compare the ramp signal RAMP from the ramp generator 130 with each pixel signal PS to generate a comparison result, and output the comparison result as a logic low or a logic high. The comparator 210 can generate the comparison result as a comparison signal COMP using a CDS.

[0041] The multiple pixel signals PS outputted from the multiple pixels may have differences due to inherent pixel characteristics (e.g., FPN) and / or differences due to differences in the characteristics of the logic elements (e.g., transistors that output photocharges stored in the pixel's photoelectric conversion element) that each outputs the pixel signal PS. To compensate for these differences in the multiple pixel signals PS outputted via the multiple column lines, the following process is performed: a reset signal (or reset component) and a unit signal (or unit component) are obtained for each pixel signal PS, and the difference (e.g., voltage difference) between the reset signal and the unit signal is extracted as a valid signal component. This process may be referred to as CDS. The comparator 210 may use CDS to output a comparison signal COMP corresponding to the comparison result.

[0042] The delay circuit 220 can output a first signal SIG1 having a phase that is the same as or opposite to the phase of the comparison signal COMP applied from the comparator 210. The delay circuit 220 can also output a second signal SIG2 by delaying the comparison signal COMP for a specific period of time. According to an exemplary embodiment, the delay circuit 220 includes a plurality of delay elements. Each delay element can delay an input signal for a specific period of time and output the signal to a subsequent delay element. Therefore, the delay circuit 220 can output a signal whose phase lags behind the phase of the input signal by a period corresponding to the number of delay elements. In other words, the delay circuit 220 can output the comparison signal COMP or a signal having a phase opposite to the comparison signal COMP as the first signal SIG1, while outputting the second signal SIG2 by delaying the comparison signal COMP for a specific period of time.

[0043] The delay circuit 220 may select and output a first delayed signal from among the delay signals outputted from the plurality of delay elements, respectively, in response to the delay selection signal Delay_SEL outputted from the compensator 230. In other words, the delay selection signal Delay_SEL may select a delay element from among the plurality of delay elements of the delay circuit 220 that outputs a delayed signal that lags behind the input signal by a first period of time, and the delay selection signal Delay_SEL may output the first delayed signal outputted by the selected delay element as the second signal SIG2.

[0044] According to an exemplary embodiment, the first time period corresponds to 0.5 least significant bit (LSB). Here, LSB may refer to the bit information located at the lowest position among the binary bits. In other words, the first time period may refer to the time period of the pulse signal corresponding to the lowest bit. According to an exemplary embodiment, the first time period corresponds to 0.25 LSB. In the current specification, 0.5 LSB or 0.25 LSB is recommended as the first time period, but the embodiments of the present inventive concept are not limited thereto. In addition to 0.5 LSB and 0.25 LSB, the first time period may correspond to any of various time periods obtained by dividing the LSB time period into a specific ratio. Reference will be made to Figures 3A to 4C A configuration of outputting the first delayed signal in response to the delay selection signal Delay_SEL is described in detail.

[0045] Compensator 230 may output a delay selection signal, Delay_SEL, to delay circuit 220 to reduce power-voltage-temperature (PVT) noise in delay circuit 220. Compensator 230 may include multiple compensating delay elements. Compensator 230 may also include a ripple counter that measures the period of an input signal. The ripple counter may count the ripple corresponding to the measured period of the input signal. Compensator 230 may measure the period of the input signal (i.e., comparison signal COMP) and, based on the measured period of comparison signal COMP, generate a delay selection signal, Delay_SEL, indicating the index of a compensating delay element. In other words, the ripple counter may count the ripple corresponding to the measured period of the signal to generate a count result, and generate a delay selection signal, Delay_SEL, based on the count result. According to an exemplary embodiment, delay selection signal Delay_SEL may correspond to the index of a compensating delay element among the multiple compensating delay elements that outputs a first delay selection signal that lags behind by a first period of time.

[0046] Compensator 230 can measure the period of comparison signal COMP and, based on the measured period of comparison signal COMP, identify a compensating delay element from among a plurality of compensating delay elements to output a delay selection signal for delaying the signal by a first time period (e.g., a time period corresponding to 0.5 LSB). In an exemplary embodiment, the first time period is obtained by dividing the period of the comparison signal. Compensator 230 can generate a first delay selection signal indicating an index of the compensating delay element and output the first delay selection signal to delay circuit 220. Therefore, even if PVT noise varies, delay circuit 220 can adapt to the PVT noise variation and generate a signal that is delayed by a time period close to the first time period.

[0047] The compensator 230 may have a similar path as the delay circuit 220. According to an exemplary embodiment, the compensator 230 includes the same number of delay elements as the delay circuit 220. For example, the compensator 230 may include the same number of inverters, NAND gates, and multiplexers as the delay circuit 220. In other words, the compensator 230 may be configured to have a PVT noise trend similar to that of the delay circuit 220. However, embodiments of the present inventive concept are not limited to a configuration in which the compensator 230 includes the same number of elements as the delay circuit 220. The compensator 230 and the delay circuit 220 may include various numbers of elements that exhibit similar PVT noise distributions. For ease of description, it is assumed that the delay circuit 220 and the compensator 230 include the same number of elements.

[0048] In an exemplary embodiment, the compensator 230 is implemented as a time-to-digital converter (TDC). The TDC may be classified into various types, for example, a Vernier type or a ring oscillator type.

[0049] The compensator 230 can be turned on or off in response to the compensation enable signal CMPN_en. According to an exemplary embodiment, the ADC 200 generates a delay signal corresponding to the PVT difference by turning the compensator 230 on or off when necessary, or generates a delay signal that is not related to the PVT difference. Figures 4A to 4C The configuration of the compensator 230 generating the delay selection signal Delay_SEL is described in detail.

[0050] The latch circuit 240 can latch the input phase shift code IPSC and sequentially store a phase shift code representing a reset component and a phase shift code representing an image component. In an exemplary embodiment, the reset component and the image component (or signal component) are included in the analog pixel signal PS output from the pixel array 110 of the image sensor 10.

[0051] According to an exemplary embodiment, the input phase shift code IPSC includes a plurality of phase shift signals having the same period and having partially overlapping phases. For example, the input phase shift code IPSC may include first to second n phase-shifted signals, where "n" is a natural number greater than or equal to 2.

[0052] The latch circuit 240 may latch the input phase shift code IPSC based on a first signal SIG1 corresponding to the comparison signal COMP output from the comparator 210 and a second signal SIG2 obtained by delaying the comparison signal COMP. After being latched, the input phase shift code IPSC may be output to the counter 250.

[0053] The counter 250 can count the input phase shift code IPSC output from the latch circuit 240. The counter 250 can receive the input phase shift code IPSC from the timing generator 300 ( Figure 1 ) receives the clock signal CLK ( Figure 1 The counter 250 can count the input phase-shift code IPSC output from the latch circuit 240 based on the clock signal CLK during a time period when the count signal is activated (for example, during a logic-high time period of the clock signal CLK). The counter 250 can count the logic-high or logic-low comparison results of the input phase-shift code IPSC output from the latch circuit 240 based on the clock signal CLK during a reset transition time period when the reset signal is sensed and a signal transition time period when the pixel signal PS is sensed to generate a counting result, and can output a digital pixel value DP based on the counting result.

[0054] The counter 250 can generate a gray code based on the input phase shift code IPSC output from the latch circuit 240, and can generate a binary code based on the gray code. The binary code can be referred to as a digital pixel value DP. The binary code or the digital pixel value DP can be sequentially output to the output buffer 160. Figure 5 The Gray code and the binary code generated by the counter 250 are described in detail.

[0055] Figure 3A is a block diagram of a delay circuit 220 according to an exemplary embodiment of the inventive concept. Figure 3A The delay circuit 220 includes an input block 221 (eg, an input circuit), a switch block 222 (eg, a switch circuit), a delay block 223 (eg, logic for introducing a signal delay), and a selection block 224 (eg, a selection circuit such as a multiplexer).

[0056] The input block 221 may output a signal having a phase that is the same as or opposite to that of the comparison signal COMP output from the pixel array 110 to the latch circuit 240. The signal output to the latch circuit 240 may be referred to as a first signal SIG1. When the comparison signal COMP is not directly output to the latch circuit 240, the comparison signal COMP may pass through another path. According to an exemplary embodiment, the comparison signal COMP applied to the input block 221 may be output to the switch block 222 as is or after its phase is inverted.

[0057] The switch block 222 may turn on or off the delay circuit 220. In other words, the switch block 222 may determine whether to operate the delay circuit 220, thereby determining whether to generate a signal delayed by a first period of time.

[0058] The delay block 223 delays an input signal having the same or opposite phase as the comparison signal COMP by a specific period of time. The delay block 223 may include a plurality of delay elements (eg, a logic circuit for delaying a signal).

[0059] The selection block 224 may select a delay element that outputs a first delayed signal from among the delay elements. The first delayed signal may be output as the second signal SIG2. In other words, the selection block 224 may generate the second signal SIG2 obtained by delaying the comparison signal COMP.

[0060] Figure 3B is a circuit diagram of a delay circuit 220_1 according to an exemplary embodiment of the inventive concept. Figure 3B A detailed circuit diagram of the delay circuit 220_1 is shown. The delay circuit 220_1 can be used to implement one of the delay elements.

[0061] The input block 221_1 may include an inverter or a buffer. The input block 221_1 receives the comparison signal COMP and outputs the comparison signal COMP to the latch circuit 240 as is or after inverting the phase of the comparison signal COMP. The comparison signal COMP applied to the input block 221_1 may also be output to the switch block 222_1 as is or after inverting its phase.

[0062] The switch block 222_1 includes a NAND gate (NAND gate). The switch block 222_1 determines whether to operate the delay circuit 220_1 in response to the delay enable signal Delay_en applied to the NAND gate. Accordingly, it determines whether to generate a signal delayed by the first time period. Figure 3B A NAND gate is shown in FIG, but embodiments of the inventive concept are not limited thereto. Various logic elements or switches that determine whether to operate the delay circuit 220_1 may be used.

[0063] The delay block 223_1 may delay the comparison signal COMP for a specific period of time, or delay a signal obtained by inverting the phase of the comparison signal COMP for a specific period of time. As described above, the delay block 223_1 may include a plurality of delay elements.

[0064] Each delay element can delay the input signal for the second time period. In other words, when the delay block 223_1 includes N delay elements, the delay block 223_1 can generate a total of N delayed signals Delay_[1]: Delay_[N], including: the delayed signal Delay_[1] delayed by the second time period, the delayed signal Delay_[2] delayed by twice the second time period (2×[second time period]), ..., and the delayed signal Delay_[N] delayed by N times the second time period (N×[second time period]). Although Figure 3B Inverters are illustrated as delay elements in FIG. 1 , but embodiments of the inventive concept are not limited thereto, and various logic elements that delay a signal may be used.

[0065] Selection block 224_1 selects one of the N delayed signals Delay_[1]:Delay_[N] generated by delay block 223_1. Selection block 224_1 may be implemented by a multiplexer. According to an exemplary embodiment, selection block 224_1 selects a first delayed signal delayed by a first time period from among the N delayed signals Delay_[1]:Delay_[N] in response to the delay selection signal Delay_SEL output from compensator 230. In other words, selection block 224_1 may select a delay element that outputs the first delayed signal from among the delay elements. The first delayed signal may be output as a second signal SIG2. In other words, selection block 224_1 may generate a second signal SIG2 obtained by delaying comparison signal COMP.

[0066] Reference Figure 3B , the selection block 224_1 may include a multiplexer MUX. According to an embodiment, the multiplexer MUX may select a first delayed signal from a plurality of delayed signals in response to a delay selection signal Delay_SEL applied from the compensator 230 and output the first delayed signal as the second signal SIG2. The delay element may be located at Figure 3B Each node shown is connected so that each next input to the multiplexer is a signal that has been delayed by an increasing number of delay elements. Figure 3B , but the embodiment is not limited thereto, and various logic elements that generate a single output with respect to a plurality of inputs may be used.

[0067] Figure 4A is a block diagram of the compensator 230 according to an exemplary embodiment of the present inventive concept. Figure 4A The compensator 230 includes a compensation input block 231 (eg, a circuit), a compensation switch block 232 (eg, a circuit), a compensation delay block 233 (eg, a circuit), and a compensation determination block 234 (eg, a circuit).

[0068] As described above, the compensator 230 may measure a period of an input signal; based on the measured period of the input signal, identify a compensating delay element among a plurality of compensating delay elements that outputs a delay selection signal Delay_SEL, the delay selection signal Delay_SEL being used to delay the signal for a first period of time (e.g., a period corresponding to 0.5 LSB); and generate a first delay selection signal indicating an index indicating the compensating delay element.

[0069] The compensation input block 231 may output the voltage from the power source as it is or after the phase of the voltage is inverted.The voltage applied to the compensation input block 231 may be output to the compensation switching block 232 as it is or after its phase is inverted.

[0070] The compensation switching block 232 may turn on or off the compensator 230. In other words, the compensation switching block 232 may determine whether to operate the compensator 230.

[0071] The compensation delay block 233 may delay the input voltage by a specific period of time, or delay a signal having an opposite phase to the input voltage by a specific period of time. The compensation delay block 233 may include a plurality of compensation delay elements.

[0072] The compensation determination block 234 can measure the period of the input signal and, based on the measured period of the input signal, generate a delay selection signal Delay_SEL indicating the index of the compensating delay element among the compensating delay elements that outputs a first delay selection signal delayed by a first time period of the delay circuit 220. For example, the first time period can correspond to 0.5 LSB. In other words, the compensation determination block 234 can determine the amount of signal delay.

[0073] Figure 4B is a circuit diagram of the compensator 230_1 according to an exemplary embodiment of the inventive concept. Figure 4B The compensator 230_1 is Figure 4A An example of a compensator 230 is shown. Figure 4B An example is shown in which the compensator 230 is configured as a ring oscillator type. Figure 4B , the compensator 230_1 includes a compensation input block 231_1 , a compensation switch block 232_1 , a compensation delay block 233_1 , and a compensation determination block 234_1 .

[0074] The voltage applied to the compensation input block 231_1 may be output to the compensation switching block 232_1 as is or after its phase is inverted. The compensation input block 231_1 may include an inverter or a buffer. The compensation input block 231_1 receives the comparison signal COMP.

[0075] The compensation switch block 232_1 includes a NAND gate. The compensation switch block 232_1 can determine whether to operate the compensator 230_1 in response to the compensation enable signal CMPN_en applied to the NAND gate. Figure 4B , but embodiments of the inventive concept are not limited thereto, and various logic elements or switches that determine whether to operate the compensator 230_1 may be used. For example, in addition to the NAND gate, a two-stage NAND gate or a NOR gate (not-or gate) having three inputs may be used.

[0076] The compensation delay block 233_1 may delay a voltage or an inverse voltage for a specific period of time. As described above, the compensation delay block 233_1 may include a plurality of compensation delay elements.

[0077] Each compensation delay element can delay the signal for the second time period. In other words, when the compensation delay block 233_1 includes N compensation delay elements, the compensation delay block 233_1 can generate a total of N compensation delay signals C_Delay_[1]:C_Delay_[N], including: the compensation delay signal C_Delay_[1] delayed by the second time period, the compensation delay signal C_Delay_[2] delayed by twice the second time period (2×[second time period]), ..., and the compensation delay signal C_Delay_[N] delayed by N times the second time period (N×[second time period]). Although in Figure 4B An inverter is shown as the compensating delay element in FIG, but embodiments of the inventive concept are not limited thereto, and various logic elements that delay a signal may be used.

[0078] The compensation determination block 234_1 selects one of the N compensation delay signals C_Delay_[1]:C_Delay_[N] generated by the compensation delay block 233_1. The compensation determination block 234_1 can measure the period of the input signal and, based on the measured period of the input signal, generate a delay selection signal Delay_SEL indicating the index of the following compensation delay element among the compensation delay elements: the compensation delay element that outputs the first delay selection signal delayed by a first time period. The first time period can correspond to 0.5 LSB. In some cases, the first time period can correspond to 0.25 LSB. In addition to 0.5 LSB and 0.25 LSB, the first time period can also include various delay times required by the ADC.

[0079] The compensation determination block 234_1 includes a ripple counter Ripple CNT. The ripple counter Ripple CNT can count the ripples within the measured period of the compensation signal COMP to generate a count result, and generate the delay selection signal Delay_SEL based on the count result. In other words, the ripple counter Ripple CNT can determine the period of the input signal.

[0080] The compensation determination block 234_1 includes a multiplexer MUX. In this case, the compensator 230_1 is considered to be a ring oscillator type TDC. Although Figure 4B A multiplexer MUX is shown in FIG. 1 , but embodiments of the inventive concept are not limited thereto, and various logic elements that generate a single output with respect to a plurality of inputs may be used.

[0081] Figure 4C is a circuit diagram of the compensator 230_2 according to an exemplary embodiment of the inventive concept. Figure 4C The compensator 230_2 is Figure 4A The example of the compensator 230 will be omitted. Figure 4BRedundant description given. Figure 4C An example is shown in which the compensator 230 is configured as a fine-tuning type.

[0082] Reference Figure 4C , the compensator 230_2 includes a compensation input block 231_2, a compensation switch block 232_2, a compensation delay block 233_2 and a compensation determination block 234_2.

[0083] The voltage applied to the compensation input block 231_2 may be output to the compensation switch block 232_2 as is or after its phase is inverted. The compensation input block 231_2 may include an inverter or a buffer. The compensation input block 231_2 receives the comparison signal COMP. The compensation input block 231_2 also receives the comparison signal COMP. Figure 1 The reference signal Ref is generated by the timing generator 150 in .

[0084] The compensation switch block 232_2 may determine whether to operate the compensator 230_2 using a switch. In an embodiment, the compensation switch block 232_2 determines whether to operate the compensator 230_2 in response to the compensation enable signal CMPN_en. Figure 4C , the compensation switch block 232_2 is shown as a switch, but embodiments of the inventive concept are not limited thereto, and various logic elements that determine whether to operate the compensator 230_2 may be used. For example, a NAND gate with three inputs, a two-stage NAND gate, or a NOR gate may be used.

[0085] The compensation delay block 233_2 may delay the voltage or the inverse voltage for a specific period of time. As described above, the compensation delay block 233_2 may include a plurality of compensation delay elements.

[0086] Each compensation delay element can delay a signal for a specific time period. In other words, when the compensation delay block 233_2 includes N compensation delay elements, the compensation delay block 233_2 can generate a total of N compensation delay signals C_Delay_[1]: C_Delay_[N], including: a compensation delay signal C_Delay_[1] delayed for a first time period, a compensation delay signal C_Delay_[2] delayed for a second time period, ..., and a compensation delay signal C_Delay_[N] delayed for an Nth time period. Although Figure 4C Buffers and D flip-flops (eg, DFFs) are illustrated as compensating delay elements in FIG. 1 , but embodiments of the inventive concept are not limited thereto, and various logic elements that delay a signal may be used.

[0087] The compensation determination block 234_2 can select one of the N compensation delay signals C_Delay_[1]:C_Delay_[N] generated by the compensation delay block 233_2. The compensation determination block 234_2 can measure the period of the input signal and, based on the measured period of the input signal, generate a delay selection signal Delay_SEL indicating the index of the following compensation delay element among the compensation delay elements: the compensation delay element that outputs a first delay selection signal delayed by a first time period. For example, the first time period can correspond to 0.5 LSB. In some cases, the first time period can correspond to 0.25 LSB. In addition to 0.5 LSB and 0.25 LSB, the first time period can also include various delay times required by the ADC.

[0088] Reference Figure 4C , the compensation determination block 234_2 may include a decoder. In this case, the compensator 230_2 may be a fine-tuning TDC. Figure 4B Compared to the ring oscillator type shown in , the fine-tuning TDC uses a D flip-flop instead of multiple connections of NAND gates and inverters. However, when an inverter is added to the front end of the D flip-flop, the effect of the D flip-flop is eliminated, so Figure 4C The fine-tuning type compensator 230_2 can compensate for PVT noise similarly to the ring oscillator type compensator 230_1.

[0089] Reference Figure 4C , the fine-tuning compensator 230_2 outputs a delay selection signal Delay_SEL by performing a logic operation on the comparison signal COMP and the reference signal Ref. Figure 4C A decoder is shown in , but embodiments of the inventive concept are not limited thereto, and various logic elements that generate a single output with respect to a plurality of inputs may be used.

[0090] Reference Figures 3A to 4CADC 200, including delay circuit 220 and compensator 230, can generate second signal SIG2 by delaying comparison signal COMP by a first period (e.g., a time corresponding to 0.5 LSB). Compensator 230 has a similar path as delay circuit 220 and is therefore affected by PVT noise with a similar PVT noise distribution to that of delay circuit 220. Therefore, compensator 230 can measure the period of the signal containing PVT noise and generate a delay selection signal Delay_SEL indicating the index of the compensating delay element that outputs the first delay selection signal delayed by the first period. In other words, because compensator 230 generates delay selection signal Delay_SEL while taking PVT noise into account and outputs it to delay circuit 220, delay circuit 220 can generate second signal SIG2 that is more accurately delayed by the first period based on delay selection signal Delay_SEL.

[0091] The second signal SIG2 delayed by the first time period can be processed by the latch circuit 240 and the counter 250 of the ADC 200 so that an additional bit of information can be generated in addition to the original bit information. The additional bit generated can be the LSB and can refer to the information of the lowest bit (e.g., the rightmost bit) in the binary data. Figure 5 and Figure 6 Describes the extra bits generated in detail.

[0092] According to an exemplary embodiment, the ADC 200 generates one additional bit without increasing the clock signal CLK, thereby increasing its operating speed. The ADC 200 having the increased operating speed may have an increased digital resolution.

[0093] Additionally, the ADC 200 can generate one additional bit without increasing the clock signal CLK, and thus increase the number of effective bits, thereby reducing power used to maintain operating speed.

[0094] Figure 5 2 is a circuit diagram of a latch circuit and counter 600 according to an exemplary embodiment of the present inventive concept. For example, the latch circuit and counter 600 may be used to implement the latch circuit 240 and the counter 250.

[0095] Reference Figure 5 ADC 200 includes a first block 610 that generates an LSB and a second block 630 that generates another bit other than the LSB (eg, the most significant bit (MSB)). ADC 200 also includes a full adder 650 and a flip-flop 670.

[0096] The first block 610 and the second block 630 may include a plurality of latches and a plurality of logic elements (e.g., XOR gates). The first block 610 and the second block 630 may latch the phase-shifted signals P[0], P[1], P[2], and P[3] and perform logic conversion on the latched signals to sequentially generate binary signals.

[0097] In other words, the latch circuit and the counter 600 may generate a binary code SIG related to the image component and a binary code RST related to the reset component based on the input phase shift code IPSC.

[0098] The latch circuit and counter 600 can generate a binary signal based on four phase-shifted signals P[0], P[1], P[2], and P[3] having the same period and partially overlapping phases. The four phase-shifted signals P[0], P[1], P[2], and P[3] can be generated by the phase generator 140. In other words, the input phase-shifted code IPSC can be an orthogonal phase-shifted code.

[0099] The second block 630 may generate a two-bit Gray code based on an input phase-shift code IPSC including three phase-shift signals P[0], P[1], and P[2] among four phase-shift signals P[0], P[1], P[2], and P[3].

[0100] The second block 630 includes XOR gates 641, 642, and 643 and latches 631, 632, 633, 634, and 635 (eg, LAT4, LAT5, LATG1, LATB1, and LATB2). Depending on the embodiment, at least one latch and at least one XOR gate may be required to generate a two-bit Gray code.

[0101] The phase shift bit corresponding to phase-shift signal P[1] can be stored in latch 633 and then output as the first bit of the Gray code. The phase shift bits corresponding to phase-shift signals P[0] and P[2] can be stored in latches 631 and 632, respectively, and then subjected to an XOR operation in XOR gate 641 to output the second bit of the Gray code from XOR gate 641. XOR gate 643 can perform an XOR operation on the first bit of the Gray code and sign decision bit SDB to generate the first bit of the binary code. XOR gate 642 can perform an XOR operation on the first bit of the binary code and the second bit of the Gray code output from XOR gate 641 to generate the second bit of the binary code. Latch 635 can latch the first bit of the binary code output from XOR gate 643. Latch 634 can latch the second bit of the binary code output from XOR gate 642. The number of latches (e.g., latches 634 and 635) can be substantially the same as the number of bits in the binary code or Gray code.

[0102] Since the first block 610 has a similar structure to the second block 630, the description will focus on the differences between them. The first block 610 can also use the phase shift signal P[3] among the phase shift signals P[0] to P[3] of the input phase shift code IPSC in addition to the phase shift signals P[0], P[1], and P[2] used in the second block 630. In other words, the ADC 200 can use the phase generator 140 to additionally generate the phase shift signal P[3].

[0103] The phase shift bits corresponding to phase-shifted signals P[0] and P[1], respectively, can be stored in latches 611 and 612 (e.g., LAT0 and LAT1), and then subjected to an XOR operation in XOR gate 621, so that the third bit of the Gray code can be output from XOR gate 621. The phase shift bits corresponding to phase-shifted signals P[2] and P[3], respectively, can be stored in latches 613 and 614 (e.g., LAT2 and LAT3), and then subjected to an XOR operation in XOR gate 622, so that the fourth bit of the Gray code can be output from XOR gate 622. XOR gate 623 can perform an XOR operation on the third and fourth bits of the Gray code, thereby generating the fifth bit of the Gray code. XOR gate 624 can perform an XOR operation on the fifth bit of the Gray code output from XOR gate 623 and the first bit of the binary code, thereby generating the third bit of the binary code as the least significant bit (LSB). The third bit of the binary code can be the least significant bit of the binary signal and can be a binary bit related to the image signal. The latch 615 (eg, LATB0) may latch the third bit of the binary code output from the XOR gate 624. The bit stored in the latch 615 may be a binary code RST related to a reset signal.

[0104] The full adder 650 may sequentially output binary signals based on the binary code RST for the reset component and the binary code SIG for the image component and the processing of the flip-flop 670. The output signal may correspond to a digital pixel value DP.

[0105] The full adder 650 can perform bitwise processing and may include a first input terminal for receiving a binary code SIG related to the image signal, a second input terminal for receiving a binary code RST related to the reset signal, a third input terminal for receiving the output of the flip-flop 670, a first output terminal for outputting the binary code bit by bit, and a second output terminal for outputting a carry. According to an exemplary embodiment, the binary code RST related to the reset signal represents the negative value of the first bit of the Gray code, and the full adder 650 adds the binary code RST related to the reset signal and the binary code SIG related to the image signal bit by bit, thereby outputting a binary code. The binary code output by the full adder 650 may be referred to as a digital pixel value DP.

[0106] Although Figure 5XOR gates 621 to 624 and 641 to 643 are shown as the counter 250 in FIG. 2 , but this is merely an example, and various logic elements that generate corresponding outputs may be used.

[0107] Reference Figures 2 to 5 , the second signal SIG2, delayed by the first time period, can additionally generate information about one bit. For example, a signal delayed by a time period corresponding to 0.5 LSB can be applied to the latch circuit and counter 600, thereby additionally generating information about the LSB of the binary code. According to an exemplary embodiment, the LSB can refer to the bit located at the first decimal place. Although 0.5 LSB is used as an example, this is only for ease of description. When the signal is delayed by a time period corresponding to 0.25 LSB, the additional information generated can be about the bit located at the second decimal place.

[0108] Figure 6 1 is a timing diagram illustrating a clock signal CLK and signals generated from the clock signal CLK according to an exemplary embodiment of the present inventive concept. It can be assumed that the clock speed or frequency of the clock signal is A GHz. Figure 6 , phase shift signal P <0> 、P <1> 、P <2> and P <3> It can be used to generate Gray and binary codes related to two bits and extra bits of information.

[0109] Reference Figure 6 , when a constant (eg, periodic) clock signal CLK is provided, the phase shift signal P <0> and P <1> The Gray signal G in the Gray code has the same period and has phases that partially overlap with each other. <1> , G <2> and G <3> Gray code can have different periods. Unlike typical binary codes, Gray code is configured so that two consecutive values differ by only one bit. Gray code can reduce data errors and is therefore useful as an input / output code. However, as operating speed increases, Gray code may lead to increased frequency and power consumption.

[0110] Reference Figure 6 , Gray signal G <1> and phase shift signal P <1> has substantially the same waveform, so the phase-shifted signal P can be used as is. <1> The corresponding phase shift is used to generate the first bit of the Gray code. <2> and phase shift signal P <0> When performing XOR operation, Gray signal G is generated <1> , phase shift signal P <2> The phase of the phase shift signal P <1> The phase of the phase shift signal P <0> The phase lags behind the phase shift signal P <1> Therefore, the image sensor according to the exemplary embodiment can <0> and P <2> The corresponding phase-shifted codes are XORed to generate the second bit of the Gray code.

[0111] Reference Figures 2 to 6, using the phase shift signal P <0> 、P <1> and P <2> Generates Gray signal G <1> , G <2> and G <3> Gray code and generates a 4-bit binary signal (eg, 0101.x). According to an exemplary embodiment, ADC 200 generates a phase shift signal P which is not normally used. <3> To obtain an additional bit of information, and thus generate a binary signal with a fractional bit (eg, 0101.1) from a 4-bit binary signal (eg, 0101.x). In other words, according to an exemplary embodiment of the present inventive concept, the ADC is based on the phase shift signal P that has been generated. <0> and P <1> , to generate a phase-shifted signal P that provides an additional bit of information LSB [0]、P LSB [1] P LSB [2] and P LSB [3], and by additionally using the phase-shifted signal P <3> Generate a phase shift signal P by combining <0> and P <1> The obtained Gray code (including Gray signal G <1> and G <2> ).

[0112] By obtaining an extra bit of information, the digital resolution of the ADC 200 or the image sensor 10 can be improved without increasing the frequency of the clock signal CLK. In other words, the power consumption can be reduced for the same resolution.

[0113] 7A to 7C is a block diagram of an image sensor including a delay circuit and a compensator according to an exemplary embodiment of the present inventive concept. 7A to 7C , the image sensor 10 includes a comparator 210, delay circuits 220 (a, b, c), compensators 230 (a, b, c), a latch circuit 240, a counter 250, and an output buffer 160. Redundant descriptions will be omitted.

[0114] Reference Figure 7A , the four delay circuits 220a of the image sensor 10a are electrically connected to one compensator 230a. According to an exemplary embodiment, each delay circuit 220a outputs the second signal SIG2 in response to the delay selection signal Delay_SEL from the compensator 230a. Figure 7A In FIG. 2 , the compensator 230a is located before a row of delay circuits 220a, but the compensator 230a may be located after a series of delay circuits 220a. Figure 7AFour delay circuits 220a are shown in FIG. 1 , but this is for ease of description only, and additional delay circuits 220a may be included in the image sensor. For example, the image sensor may include N delay circuits 220a corresponding to the number of columns in the pixel array, where N is the number of columns in an M×N pixel array. For example, the comparator 210 may receive multiple pixel signals PS (e.g., one pixel signal PS for each column of the pixel array 110) and output multiple comparison signals based on comparisons of the pixel signals with the ramp signal RAMP.

[0115] Reference Figure 7B In the example, four delay circuits 220b of the image sensor 10b are electrically connected to one compensator 230b, and the compensator 230b is located between the four delay circuits 220b. For example, the compensator 230b can be located between pairs of delay circuits 220b. Because the compensator 230b is located in the middle of a row of delay circuits 220b, the difference in PVT noise distribution relative to the distance between the compensator 230b and the delay circuit 220b can be relatively small.

[0116] Reference Figure 7C , the four delay circuits 220c of the image sensor 10c are electrically connected to four compensators 230c, respectively. In other words, the compensators 230c and the delay circuits 220c can be arranged in a one-to-one correspondence. Each compensator 230c outputs a delay selection signal Delay_SEL that takes into account PVT noise to the delay circuit 220c corresponding thereto. When there are a greater number of compensators 230c, the second signal SIG2 delayed by the delay circuit 220c for the first time period can be more accurate. According to an exemplary embodiment, in order to generate the second signal SIG2 that is most accurately delayed for the first time period, the image sensor 10 includes as many compensators 230c as the number of delay circuits 220c. However, four delay circuits 220c and four compensators 230c are shown only for the convenience of description. A plurality of compensators 230c and a plurality of delay circuits 220c can be included in the image sensor 10c in a one-to-one correspondence. Although in Figure 7C , one compensator is shown connected to one delay circuit, but embodiments of the inventive concept are not limited thereto, and the image sensor may include a plurality of compensators connected to a plurality of delay circuits. Figure 8 is a flowchart of a method of operating an ADC according to an exemplary embodiment of the inventive concept.

[0117] Reference Figure 1 、 Figure 2 and Figure 8 In operation S110 , the comparator 210 of the ADC 200 compares the pixel signal PS output from the pixel array 110 with the ramp signal RAMP output from the ramp generator 130 and generates a comparison signal COMP.

[0118] In operation S120, the delay circuit 220 of the ADC 200 generates the first signal SIG1 by inverting the comparison signal COMP. In an alternative embodiment, the first signal SIG1 may be obtained by outputting the comparison signal COMP as it is (eg, without inversion).

[0119] In operation S130, the compensator 230 of the ADC 200 measures the period of the first signal SIG1 based on the comparison signal COMP. The measurement of the period of the first signal SIG1 can be performed by a ripple counter Ripple CNT (see Figure 4B ) to execute.

[0120] In operation S140, the compensator 230 determines a first time period based on a period of the first signal SIG1. The first time period may correspond to 0.5 LSB. In some cases, the first time period may correspond to 0.25 LSB.

[0121] In operation S150 , the compensator 230 generates a delay selection signal Delay_SEL that delays the first signal SIG1 by a first period of time.

[0122] In operation S160 , the delay circuit 220 outputs the second signal SIG2 to the latch circuit 240 by delaying the first signal SIG1 by a first period of time.

[0123] Figure 9 is a flow chart of a method of operating an ADC according to an exemplary embodiment of the present invention. In an exemplary embodiment, Figure 9 yes Figure 8 Detailed flowchart of operation S150 in .

[0124] Reference Figure 9 In operation S151, the compensator 230 searches for a compensating delay element that outputs a compensated delayed signal corresponding to a delayed signal delayed by a first time period. For example, the compensator 230 may search for a delayed signal corresponding to a signal delayed by a first time period.

[0125] In operation S152, the compensator 230 outputs a signal indicating the found compensation delay element as the delay selection signal Delay_SEL. In operation S160, the delay circuit 220 may output the second signal SIG2 to the latch circuit 240 by delaying the first signal SIG1 by a first time period. For example, the compensator 230 may determine the found delay signal as the delay selection signal Delay_SEL.

[0126] Figure 10is a block diagram of an electronic device including the image sensor 10 according to an exemplary embodiment of the inventive concept. Figure 10 FIG. 1 is a hierarchical diagram of an electronic device including an image sensor 10 including an ADC 200 having a delay circuit 220 and a compensator 230. Figure 10 The electronic device includes an image sensor 10 , a processor 2000 , a memory device 3000 , an input / output (I / O) device 4000 , a power supply 5000 , and a storage device 6000 .

[0127] Reference Figure 1 and Figure 10 The processor 2000 can perform specific calculations or tasks required for the operation of the image processing system 1, and the storage device 3000 and the storage device 6000 can store data required for the operation of the image processing system 1. For example, the processor 2000 may include a microprocessor, a central processing unit (CPU), or an application processor (AP). The storage device 3000 may include volatile memory and / or non-volatile memory. The storage device 6000 may include a solid-state drive (SSD), a hard disk drive (HDD), or a CD-ROM. The I / O device 4000 may include an input unit such as a keyboard, a keypad, or a mouse, and an output unit such as a printer or a display. The power supply 5000 may provide the operating voltage required for the operation of the image processing system 1.

[0128] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept.

Claims

1. An analog-to-digital converter for converting a pixel signal generated from sensed light into a digital signal, the analog-to-digital converter comprising: a comparator configured to compare the pixel signal with a ramp signal having a constant slope to generate a comparison signal; a delay circuit configured to generate a first signal corresponding to the comparison signal and to generate a second signal by delaying the first signal for a first time period, wherein the delay circuit comprises a plurality of delay elements, each of the plurality of delay elements being configured to delay an input signal for a second time period to generate a delayed signal; and a compensator circuit configured to measure a period of the comparison signal to output a delay selection signal to the delay circuit based on the measured period, the delay selection signal being used to select a first delayed signal, which is a signal obtained by delaying the first signal by the first time period, as the second signal from among a plurality of delayed signals generated by the plurality of delay elements; The first time period is obtained by dividing the period of the comparison signal.

2. The analog-to-digital converter according to claim 1, wherein The delay circuit further includes a multiplexer, Each of the plurality of delay elements is configured to delay a signal input to the delay element by the second time period, and output a delayed signal to a subsequent delay element and / or the multiplexer so that the multiplexer receives the plurality of delayed signals respectively output from the plurality of delay elements, and The multiplexer is configured to select the first delayed signal from among the plurality of delayed signals based on the delay selection signal and output the first delayed signal as the second signal.

3. The analog-to-digital converter according to claim 1, wherein The compensator circuit includes a plurality of compensation delay elements configured to delay the comparison signal, and The compensator circuit is configured to select a compensating delay element among the plurality of compensating delay elements based on the cycle of the comparison signal, the selected compensating delay element outputting a signal corresponding to the first time period, and is configured to output a first delay selection signal as the delay selection signal to the delay circuit, the first delay selection signal indicating an index of the selected compensating delay element.

4. The analog-to-digital converter according to claim 3, wherein: The first time period is 1 / 2 of the period of the comparison signal.

5. The analog-to-digital converter according to claim 3, wherein The first time period is 1 / 4 of the period of the comparison signal.

6. The analog-to-digital converter according to claim 3, wherein: A plurality of comparison signals including the comparison signal are output from columns of a pixel array of an image sensor, and The compensator circuit includes a plurality of compensators, each of the compensators being configured to measure a period of a corresponding comparison signal among the plurality of comparison signals.

7. The analog-to-digital converter according to claim 3, wherein: The compensator circuit further includes: a multiplexer configured to receive a plurality of compensation delay signals respectively output from the plurality of compensation delay elements; and a ripple counter configured to count the ripples within the period of the comparison signal to output a counting result, and generate the delay selection signal based on the counting result.

8. The analog-to-digital converter according to claim 3, wherein: The plurality of compensating delay elements includes at least one D flip-flop.

9. An image sensor comprising: a pixel array comprising a plurality of pixels arranged in a matrix, each pixel of the plurality of pixels being configured to generate a pixel signal; a ramp generator configured to generate a ramp signal in response to a ramp enable signal, wherein the ramp signal has a constant slope; a comparator configured to compare the pixel signal with the ramp signal to generate a comparison signal; a plurality of delay circuits, each comprising a plurality of delay elements configured to delay the comparison signal, each of the plurality of delay circuits being configured to generate a first signal corresponding to the comparison signal and to generate a second signal by delaying the first signal for a first time period, each of the plurality of delay elements of each of the delay circuits being configured to delay an input signal for a second time period to generate a delayed signal; a compensator circuit configured to measure a period of the comparison signal and output a delay selection signal to the plurality of delay circuits based on the measured period, the delay selection signal being used to select a first delayed signal, which is a signal obtained by delaying the first signal by the first time period, as the second signal from among a plurality of delayed signals generated by a plurality of delay elements of each of the delay circuits; a phase generator configured to generate a plurality of phase-shifted codes based on a clock signal; a timing generator configured to generate the clock signal and the ramp enable signal; a latch circuit configured to latch the plurality of phase-shifted codes based on the first signal and the second signal; as well as a column counter configured to generate a binary code based on the digital code output from the latch circuit and sequentially output the binary code bit by bit, The first time period is obtained by dividing the period of the comparison signal.

10. The image sensor according to claim 9, wherein Each of the delay circuits further comprises a multiplexer, Each of the plurality of delay elements is configured to delay a signal input to the delay element by the second time period, and output a delayed signal to a subsequent delay element and / or the multiplexer so that the multiplexer receives a plurality of delayed signals respectively output from the plurality of delay elements, and The multiplexer is configured to select the first delayed signal from the plurality of delayed signals based on the delay selection signal and output the first delayed signal as the second signal.

11. The image sensor according to claim 9, wherein: The compensator circuit includes a plurality of compensation delay elements configured to delay the comparison signal, and The compensator circuit is configured to select a compensating delay element among the plurality of compensating delay elements based on the cycle of the comparison signal, the selected compensating delay element outputting a signal corresponding to the first time period, and is configured to output a first delay selection signal as the delay selection signal to the plurality of delay circuits, the first delay selection signal indicating an index of the selected compensating delay element.

12. The image sensor according to claim 11, wherein The first time period is 1 / 2 of the period of the comparison signal.

13. The image sensor according to claim 11, wherein: The plurality of phase-shift codes include a first phase-shift code, a second phase-shift code, and a third phase-shift code; and The phase generator also generates a fourth phase-shifted code.

14. The image sensor according to claim 13, wherein: The latch circuit latches the first to fourth phase-shifted codes based on the first signal and the second signal.

15. The image sensor according to claim 14, wherein: The column counter is further configured to obtain additional bit information based on the digital code.

16. The image sensor according to claim 15, wherein The column counter is further configured to generate a Gray code by converting the digital code, and to generate the binary code by converting the Gray code.

17. The image sensor according to claim 9, wherein: The timing generator is further configured to generate a compensator enable signal, and The compensator circuit is turned on or off in response to the compensator enable signal.

18. A method of operating an analog-to-digital converter, the method comprising: comparing the pixel signal with the ramp signal to generate a comparison signal; inverting the comparison signal to generate a first signal; measuring a period of the first signal; determining a first time period based on the measured period; generating a delay selection signal for delaying the first signal by the first time period; as well as outputting a second signal by delaying the first signal by the first time period based on the delay selection signal, Wherein, generating the delay selection signal includes: searching a plurality of compensated delayed signals to find a compensated delayed signal that is delayed by the first time period; and The found compensation delay signal is determined as the delay selection signal.

19. The method according to claim 18, wherein The first time period is 1 / 2 of the period of the first signal.

20. The method according to claim 19, wherein Determining the first time period includes counting a time period corresponding to 1 / 2 of the cycle of the first signal.

Images