Frequency detection circuit and frequency detection method

Abstract

The present invention discloses a frequency detection circuit and a frequency detection method, comprising a reference oscillator, a counter, a timer, a register and a comparator. The register in the present invention stores a reference digital signal, which represents a reference frequency. The comparator can obtain different second digital signals, each of which represents the product of the frequency of an input signal in a second time period and a coefficient. In this way, by comparing the reference digital signal with different second digital signals, the change in the frequency of the input signal can be obtained, that is, the comparison threshold is transferred to the input signal, thereby indirectly generating the change in the base frequency. The frequency detection circuit in the present invention has the advantages of high detection accuracy, simple structure, high operating speed, etc.

Description

Technical Field

[0001] The present invention relates to frequency detection technology, in particular to a frequency detection circuit and a frequency detection method, and belongs to the technical field of integrated circuits. Background Art

[0002] Frequency detection technology is widely used. It is generally used to process external analog signals of the chip, that is, first convert the external analog signal into a digital signal containing frequency information, and then perform data processing on the digital signal. Frequency detection technology can also detect small changes in external analog signals and amplify them to achieve certain operations. For example, in electronic cigarettes, if the change in capacitance is used to indicate the size and direction of the puffing and inhaling airflow, the capacitance can be converted into a digital signal carrying frequency information, and then the digital signal can be processed to obtain the capacitance and its change, thereby obtaining the size and direction of the puffing and inhaling current.

[0003] In order to reduce the impact of changes in environment, temperature, etc. on frequency detection, a basic frequency can be set, which will not change drastically when affected by environment, temperature, etc., thereby increasing the reliability of the system. However, when a certain condition causes the basic frequency to change drastically, additional data is required to indicate the degree of change, so that the frequency state can be fully and accurately expressed. In the prior art, operation circuits such as multipliers and dividers are generally used to obtain the change in the basic frequency. Figure 1 As shown, the frequency detection circuit includes a threshold operation device and a plurality of operation comparators. The threshold operation device is used to realize the function of multiplying or dividing the signal of the register unit by a coefficient.

[0004] The existing frequency detection circuit includes an operation circuit, which greatly increases the complexity of the circuit and reduces the operation speed of the circuit. Summary of the invention

[0005] The present invention provides a frequency detection circuit and a frequency detection method, which can reduce the complexity of the frequency detection circuit and improve the operation speed of the circuit, thereby solving the technical problems of high complexity and slow operation speed of the frequency detection circuit in the related art.

[0006] The present invention specifically adopts the following technical solutions to solve the above technical problems:

[0007] A frequency detection circuit, comprising: a reference oscillator, a counter, a timer, a register and a comparator;

[0008] The first input end of the counter is the input end of the frequency detection circuit, the second input end of the counter is connected to the third output end of the timer, and the output end of the counter is respectively connected to the first input end of the register and the first input end of the comparator;

[0009] The output terminal of the reference oscillator is connected to the first input terminal of the timer;

[0010] The second input terminal of the timer is connected to the output terminal of the comparator, the first output terminal of the timer is connected to the second input terminal of the register, and the second output terminal of the timer is connected to the second input terminal of the comparator;

[0011] The output end of the register is connected to the third input end of the comparator, and the output end of the register is the output end of the frequency detection circuit;

[0012] The frequency detection circuit is used to determine the change in the frequency of the input signal.

[0013] A frequency detection method, used in the frequency detection circuit as described above, the method comprising:

[0014] The timer performs timing according to the clock provided by the reference oscillator;

[0015] The timer outputs the generated reset signal to the counter;

[0016] The counter performs a clearing operation according to the clearing signal, counts the number of pulses of the input signal, and obtains a first digital signal and M second digital signals, wherein the first digital signal represents the frequency of the input signal in a first time period, and the second digital signal represents the product of the frequency of the input signal in a second time period and a coefficient, and different second digital signals correspond to different second time periods and coefficients, and M is greater than or equal to 2;

[0017] The counter sequentially outputs the M second digital signals to the comparator, and the timer sequentially outputs the generated M control signals to the comparator;

[0018] The comparator compares a second digital signal with a reference digital signal in the register each time a control signal is received, and outputs a comparison result, wherein the reference digital signal represents a reference frequency;

[0019] The change amount of the frequency of the input signal is determined according to the M comparison results output by the comparator.

[0020] In a possible implementation manner, M / 2 second time periods are set to be shorter than the first time period, and M / 2 second time periods are set to be longer than the first time period, and M is an even number.

[0021] In a possible implementation, the size of the coefficient is positively correlated with the length of the corresponding second time period.

[0022] In a possible implementation manner, determining the change amount of the frequency of the input signal according to the M comparison results output by the comparator includes:

[0023] If the M comparison results indicate that M / 2 second digital signals are greater than the first digital signal, and M / 2 second digital signals are less than the first digital signal, it is determined that the change in the frequency of the input signal is less than a predetermined threshold; otherwise, it is determined that the change in the frequency of the input signal is greater than the predetermined threshold.

[0024] In a possible implementation, the method further includes:

[0025] If it is determined that the change in the frequency of the input signal is greater than a predetermined threshold, continue to detect the change in the frequency of the input signal;

[0026] If within a predetermined period, the frequency change of the input signal continues to be greater than a predetermined threshold, the timer outputs the generated refresh signal to the register, the counter outputs the currently counted first digital signal to the register, and the register updates the reference digital signal to the first digital signal.

[0027] In a possible implementation, the method further includes:

[0028] When the frequency detection circuit is started, the timer outputs the generated refresh signal to the register, the counter outputs the first digital signal to the register, and the register determines the first digital signal as the reference digital signal.

[0029] In a possible implementation manner, the reference digital signal has the same number of bits as the first digital signal, and the reference digital signal has the same number of bits as each second digital signal.

[0030] Compared with the prior art, the technical solution adopted by the present invention has the following advantages and significant effects:

[0031] (1) The accuracy of conventional frequency detection is limited by the number of digits of the coefficient. The higher the number of digits of the coefficient, the higher the accuracy. However, the frequency detection accuracy of the present invention is not affected by the number of digits of the coefficient.

[0032] (2) The structure is simpler, thus reducing circuit complexity and area;

[0033] (3) There are no complex multipliers or dividers, and the circuit operates at a higher speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is the structure of the frequency detection circuit in the prior art;

[0035] Figure 2 This is a structure of a frequency detection circuit proposed by the present invention;

[0036] Figure 3 This is a process of a frequency detection method proposed by the present invention;

[0037] Figure 4 It is a working state diagram of the frequency detection circuit proposed by the present invention;

[0038] Figure 5 It is a working waveform diagram of the frequency detection circuit provided by the present invention. DETAILED DESCRIPTION

[0039] like Figure 2 A frequency detection circuit shown in the figure includes a reference oscillator 210, a counter 220, a timer 230, a register 240 and a comparator 250. The first input end of the counter 220 is the input end of the frequency detection circuit, the second input end of the counter 220 is connected to the third output end of the timer 230, and the output end of the counter 220 is respectively connected to the first input end of the register 240 and the first input end of the comparator 250; the output end of the reference oscillator 210 is connected to the first input end of the timer 230; the second input end of the timer 230 is connected to the output end of the comparator 250, the first output end of the timer 230 is connected to the second input end of the register 240, and the second output end of the timer 230 is connected to the second input end of the comparator 250; the output end of the register 240 is connected to the third input end of the comparator 250, and the output end of the register 240 is the output end of the frequency detection circuit; wherein the frequency detection circuit is used to determine the change in the frequency of the input signal.

[0040] Please refer to Figure 3 , which shows a frequency detection method proposed by the present invention, applied to Figure 2 The frequency detection circuit shown in the figure, the frequency detection method may include the following steps:

[0041] Step 301: A timer counts according to a clock provided by a reference oscillator.

[0042] Step 302: The timer outputs the generated reset signal to the counter.

[0043] The reset signal is a signal periodically outputted from the third output terminal of the timer.

[0044] In this embodiment, the clear signal is represented as a Pclr signal, and the generation period of the clear signal is Tclr, and the generation frequency of the clear signal is 1 / Tclr.

[0045] In step 303, the counter performs a reset operation according to the reset signal, counts the number of pulses of the input signal, and obtains a first digital signal and M second digital signals. The first digital signal represents the frequency of the input signal in the first time period, and the second digital signal represents the product of the frequency of the input signal in the second time period and the coefficient. Different second digital signals correspond to different second time periods and coefficients, and M is greater than or equal to 2.

[0046] The digital signal A in the counter increases gradually, and at the beginning or end of each cycle, a reset signal is used to reset the digital signal A. After the reset operation is completed, the counter starts to count the number of pulses of the input signal and generates a new digital signal A. The digital signal A includes a first digital signal and M second digital signals.

[0047] In this embodiment, M second time periods may be preset. Specifically, M / 2 second time periods are set to be shorter than the first time period, and M / 2 second time periods are set to be longer than the first time period, where M is an even number.

[0048] Assuming that the first time period is recorded as TA, and the second time periods are recorded as T1, T2, T3, etc., half of the second time periods are shorter than TA, and the other half are longer than TA.

[0049] Please refer to Figure 4 and 5 , f A It represents the frequency of the input signal (IN), f0 represents the reference frequency, or it can be said that the reference frequency is f A The average value over a period of time, f1-f4 represents the multiple of the frequency of the input signal, that is, f1 = f A *x1,f2=f A *x2,f3=f A *x3,f4=f A *x4. The first digital signal is based on f A The digital signal generated is a digital signal generated according to f1 or f2 or f3 or f4. The reference digital signal has the same number of bits as the first digital signal, and the reference digital signal has the same number of bits as each of the second digital signals.

[0050] In this embodiment, a coefficient may be preset, and the size of the coefficient is positively correlated with the length of the corresponding second time period. Figure 4 It can be seen that f1 and f A The coefficient x1 is TA / T1, f2 and f A The coefficient x2 is TA / T2, f3 and f A The coefficient x3 is TA / T3, f4 and f A The coefficient x4 is TA / T4.

[0051] In step 304, the counter sequentially outputs the M second digital signals to the comparator, and the timer sequentially outputs the generated M control signals to the comparator.

[0052] After each second digital signal is generated, the counter outputs the second digital signal to the comparator.

[0053] The second output terminal of the timer can periodically generate a control signal and output the control signal to the comparator.

[0054] Step 305: The comparator compares a second digital signal with a reference digital signal in the register each time it receives a control signal, and outputs a comparison result, wherein the reference digital signal represents a reference frequency.

[0055] The number of comparisons performed by the comparator is equal to the number of control signals output by the timer. That is, if the timer outputs only one control signal in one cycle, the comparator only needs to perform one comparison; if the timer outputs multiple control signals in one cycle, the comparator needs to perform multiple comparisons.

[0056] After receiving each control signal, the comparator works under the control of the control signal to compare the reference digital signal in the register with a second digital signal output by the counter to obtain a comparison result, which is used to indicate the size of the reference digital signal and the second digital signal.

[0057] Assuming that the second digital signal generated according to f1 is A1, the second digital signal generated according to f2 is A2, the second digital signal generated according to f3 is A3, the second digital signal generated according to f4 is A4, and the reference digital signal is F, then when the comparator receives the control signal for the first time, it compares F with A1 to obtain a comparison result; when it receives the control signal for the second time, it compares F with A2 to obtain a comparison result; when it receives the control signal for the third time, it compares F with A3 to obtain a comparison result; when it receives the control signal for the fourth time, it compares F with A4 to obtain a comparison result, and finally obtains 4 comparison results.

[0058] It should be noted that when the frequency detection circuit is started, the timer outputs the generated refresh signal to the register, the counter outputs the first digital signal to the register, and the register determines the first digital signal as the reference digital signal. Subsequently, the reference digital signal can be updated according to the frequency of the input signal, as described below.

[0059] Step 306: Determine the change in the frequency of the input signal according to the M comparison results output by the comparator.

[0060] Specifically, if M comparison results indicate that M / 2 second digital signals are greater than the first digital signal, and M / 2 second digital signals are less than the first digital signal, it is determined that the change in the frequency of the input signal is less than a predetermined threshold; otherwise, it is determined that the change in the frequency of the input signal is greater than the predetermined threshold.

[0061] In this embodiment, if it is determined that the change in the frequency of the input signal is greater than a predetermined threshold, the change in the frequency of the input signal continues to be detected; if within a predetermined period, the change in the frequency of the input signal continues to be greater than the predetermined threshold, the timer outputs the generated refresh signal to the register, the counter outputs the currently counted first digital signal to the register, and the register updates the reference digital signal to the first digital signal.

[0062] like Figure 4 As shown, the predetermined period may be Tfre, and if the frequency variation of the input signal within Tfre is continuously greater than a predetermined threshold, it is determined that the reference frequency has changed, and the reference frequency may be updated. Specifically, the first output end of the timer may output the generated refresh signal (Pfre signal) to the register, the timer outputs the first digital signal to the register, and the register updates the reference digital signal in the register using the first digital signal.

[0063] The above description is only a preferred embodiment of the present invention and is not limited to the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A frequency detection circuit, characterized in that: The frequency detection circuit includes: a reference oscillator, a counter, a timer, a register and a comparator; The first input end of the counter is the input end of the frequency detection circuit, the second input end of the counter is connected to the third output end of the timer, and the output end of the counter is respectively connected to the first input end of the register and the first input end of the comparator; The output terminal of the reference oscillator is connected to the first input terminal of the timer; The second input terminal of the timer is connected to the output terminal of the comparator, the first output terminal of the timer is connected to the second input terminal of the register, and the second output terminal of the timer is connected to the second input terminal of the comparator; The output end of the register is connected to the third input end of the comparator, and the output end of the register is the output end of the frequency detection circuit; The frequency detection circuit is used to determine the change in the frequency of the input signal.

2. A frequency detection method, characterized in that: Used in the frequency detection circuit as claimed in claim 1, the method comprises: The timer performs timing according to the clock provided by the reference oscillator; The timer outputs the generated reset signal to the counter; The counter performs a clearing operation according to the clearing signal, counts the number of pulses of the input signal, and obtains a first digital signal and M second digital signals, wherein the first digital signal represents the frequency of the input signal in a first time period, and the second digital signal represents the product of the frequency of the input signal in a second time period and a coefficient, and different second digital signals correspond to different second time periods and coefficients, and M is greater than or equal to 2; The counter sequentially outputs the M second digital signals to the comparator, and the timer sequentially outputs the generated M control signals to the comparator; The comparator compares a second digital signal with a reference digital signal in the register each time a control signal is received, and outputs a comparison result, wherein the reference digital signal represents a reference frequency; The change amount of the frequency of the input signal is determined according to the M comparison results output by the comparator.

3. The method according to claim 2, characterized in that It is set that M / 2 second time periods are shorter than the first time period, and M / 2 second time periods are longer than the first time period, and M is an even number.

4. The method according to claim 3, characterized in that The magnitude of the coefficient is positively correlated with the length of the corresponding second time period.

5. The method according to claim 4, characterized in that Determining the change in the frequency of the input signal according to the M comparison results output by the comparator includes: If the M comparison results indicate that M / 2 second digital signals are greater than the first digital signal, and M / 2 second digital signals are less than the first digital signal, it is determined that the change in the frequency of the input signal is less than a predetermined threshold; otherwise, it is determined that the change in the frequency of the input signal is greater than the predetermined threshold.

6. The method according to claim 5, characterized in that The method further comprises: If it is determined that the change in the frequency of the input signal is greater than a predetermined threshold, continue to detect the change in the frequency of the input signal; If within a predetermined period, the frequency change of the input signal continues to be greater than a predetermined threshold, the timer outputs the generated refresh signal to the register, the counter outputs the currently counted first digital signal to the register, and the register updates the reference digital signal to the first digital signal.

7. The method according to claim 2, characterized in that The method further comprises: When the frequency detection circuit is started, the timer outputs the generated refresh signal to the register, the counter outputs the first digital signal to the register, and the register determines the first digital signal as the reference digital signal.

8. The method according to claim 2, characterized in that: The reference digital signal has the same number of bits as the first digital signal, and the reference digital signal has the same number of bits as each of the second digital signals.

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