Code sharing system and code sharing method

Abstract

The present invention provides a system for sharing codes and a code sharing method. The system includes a memory and multiple processors. The memory further includes a shared segment and a non-shared segment. The multiple processors include at least a first processor and a second processor, and the first processor and the second processor have read-only access rights to the shared segment of the memory. The first processor and the second processor respectively execute the shared code stored in the shared segment of the memory, and respectively execute the non-shared code stored in the first sub-segment and the second sub-segment of the non-shared segment. The first processor and the second processor respectively execute the shared code according to the first scheduler and the second scheduler. The first scheduler works independently of the second scheduler. The system for sharing codes and the code sharing method provided by the present invention can save costs.

Description

Technical Field

[0001] The present invention relates generally to system processing and, more particularly, to a multiprocessor computing system having shared access to at least a portion of a memory subsystem. Background Art

[0002] Modern computing systems typically have multiple processors, each with its own dedicated memory. Mobile device systems (e.g., smartphones) typically provide limited memory capacity to their users due to limited form factors. As the storage requirements for multimedia content grow, there is also an increasing demand for memory capacity. Increased memory capacity results in increased power consumption due to leakage currents, and also increased cost due to higher gate counts. Therefore, effectively utilizing existing memory capacity without adding more memory to the system can significantly improve system performance and cost.

[0003] Several approaches have been proposed for efficient memory usage. However, design strategies are needed, especially for memory-constrained multiprocessor systems. Summary of the invention

[0004] In an embodiment, a system for sharing code is provided. The system includes a memory and a plurality of processors. The memory further includes a shared section and a non-shared section. The plurality of processors include at least a first processor and a second processor, and the first processor and the second processor have read-only access rights to the shared section of the memory. The first processor and the second processor respectively execute the shared code stored in the shared section of the memory, and respectively execute the non-shared code stored in the first subsection and the second subsection of the non-shared section. The first processor and the second processor respectively execute the shared code according to the first scheduler and the second scheduler. The first scheduler works independently of the second scheduler.

[0005] In another embodiment, a method for sharing code in multiple processors is provided. The method includes: storing shared code in a shared section of a memory and storing non-shared code in a non-shared section of the memory; executing the shared code in the shared section by a first processor according to a first scheduler; and executing the shared code in the shared section by a second processor according to a second scheduler. The first processor and the second processor have read-only access rights to the shared section, and the second scheduler operates independently of the first scheduler.

[0006] The code sharing system and code sharing method provided by the present invention can save costs.

[0007] Other embodiments and advantages are described in the detailed description that follows. This summary is not intended to limit the invention. The invention is defined by the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] BRIEF DESCRIPTION OF THE DRAWINGS The present invention is described by way of example and not limitation, wherein like reference numerals identify similar components. It should be noted that different references to one embodiment in the present invention are not necessarily to the same embodiment, and such references mean at least one. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is claimed that a person skilled in the art would be aware of the feature, structure, or characteristic in conjunction with other embodiments.

[0009] Figure 1 A system is described in which embodiments of the present invention may work.

[0010] Figure 2 is a schematic diagram describing address mapping or redirection according to an embodiment.

[0011] Figure 3 is a flowchart describing a code sharing method according to an embodiment.

[0012] Figure 4 An example mobile device is described according to the embodiments. DETAILED DESCRIPTION

[0013] Detailed embodiments of the present invention are disclosed herein. However, it is to be understood that this embodiment is only for the purpose of describing various forms of the present invention. However, the present invention can be presented in various different forms and is not necessarily limited to the embodiments described in the present invention. These embodiments are provided to make the description of the present invention more thorough and complete, and to fully express the scope of the present invention to those skilled in the art. In the following description, known features and technologies will be ignored to avoid unnecessary interference with the description of the embodiments of the present invention.

[0014] Embodiments of the present invention provide a system and method for sharing executable code in a memory accessed by multiple processors. Read-only data in the memory can also be shared between processors. The processors execute instructions according to their respective independent schedulers. The processors execute the shared code without copying the shared code into the respective non-shared subsections of the processors in the memory. Therefore, the amount of memory occupied by the shared code and data can be significantly reduced, and the memory capacity requirements in the device are thereby reduced. The amount of memory in a device is directly proportional to the number of gates, leakage current and cost of the device. Similarly, the code and data sharing described herein can increase the effective utilization of the memory, and thus can improve the performance and cost of the device containing the memory.

[0015] Figure 11 is a block diagram of a system 100 according to an embodiment. The system 100 includes two or more processors, for example, a first processor 110 and a second processor 120. In many embodiments, the processors may be referred to as processor cores, microprocessors, cores, multi-core processors, computing units, execution units, processing circuits, etc. The following description uses two processors as an example; however, it is understood that the description applies to more than two processors that share access to the same memory.

[0016] The first processor 110 and the second processor 120 may have the same or compatible instruction set architecture (ISA), which enables the processors to execute instructions from the same or compatible instruction set. In many embodiments, in the same or compatible ISA implementation, the processors 110 and 120 may have different micro-architectures. Examples of compatible ISAs may include the same processor architecture sequence (e.g., sequence, sequence, sequence or other processor architecture sequence) ISA.

[0017] In an embodiment, the first processor 110 and the second processor 120 execute instructions according to tasks scheduled by the schedulers 115 and 125, respectively. A task includes a set of instructions. The schedulers 115 and 125 operate independently of each other; for example, the schedulers 115 and 125 can schedule different tasks to each processor to execute at a given time. When the instructions are ready to be executed, the scheduled instructions can be issued. The first processor 110 and the second processor 120 also include respective issuing circuits (i.e., first issuing circuit 117 and second issuing circuit 127). The first issuing circuit 117 and the second issuing circuit 127 also operate independently of each other. In addition, the processors 110 and 120 operate independently; more specifically, by receiving tasks and instructions from each scheduler 115 and 125 and each issuing circuit 117 and 127. The processors 110 and 120 do not receive tasks or instructions from a centralized task scheduler and / or centralized instruction issuing circuit. In other words, the processors 110 and 120 can execute instructions (e.g., user and operating system instructions) independently of each other.

[0018] Each of the first processor 110 and the second processor 120 is coupled to a cache set (aset of cache memory), for example, an instruction cache (I cache 111 or 121) and a data cache (D cache 113 or 123). The cache can be used to store pre-fetched instructions and frequently used data to reduce the latency of accessing the memory 140. In an embodiment, the I caches 111 and 121 can store instructions that are expected to be repeatedly executed, for example, instructions in a while-loop. In an embodiment, the first processor 110, the second processor 120 and their respective caches can be part of a system on chip (SoC) platform. In an embodiment, the SoC platform can be part of a mobile computing and / or communication device, a desktop computing system, a server computing system, a cloud computing system, etc.

[0019] In an embodiment, the first processor 110 and the second processor 120 share access to a memory 140. The memory 140 may be a system memory or a main memory of the system 100. The memory 140 may include a random access memory (RAM) device, such as a dynamic random access memory (DRAM) device, a flash memory device, and / or other volatile or non-volatile memory devices. The memory 140 may also include a read-only memory (ROM) for storing read-only data or read-only code (e.g., shared code). The first processor 110 and the second processor 120 may access the memory 140 via the local bus 130 or another type of connection.

[0020] In an embodiment, the memory 140 includes a shared segment and a non-shared segment. For example, the shared segment may include a general code area 141 and a general read-only (RO) data area 142. The shared segment is write-protected (e.g., read-only) to ensure data integrity. The non-shared segment may be divided into a plurality of sub-segments, wherein each sub-segment is assigned to a processor. For example, a first sub-segment is assigned to the first processor 110, and the first sub-segment includes a first code area 143 and a first read-write (RW) data area 144. A second sub-segment is assigned to the second processor 120, and the second sub-segment includes a second code area 145 and a second RW data area 146.

[0021] The general code area 141 stores programs shared by two or more processors. For example, multiple processors can share a program for measuring execution time. The first processor 110 and the second processor 120 execute the shared code in the general code area 141 independently of each other. Without the need to save a copy of the shared program in each non-shared sub-segment, using the general code area 141 to store the shared program can significantly save the storage space of the memory 140. Similarly, the general RO data area 142 stores read-only data shared by two or more processors. For example, the shared data can include input parameters used by the shared program stored in the general code area 141. Other shared read-only data can also be stored in the general RO data area 142. The use of the general RO data area 142 can also significantly save the storage space of the memory 140.

[0022] In an embodiment, processors 110 and 120 may read the shared section of memory 140 at the same time or at different times during program execution, and may write the execution results to their respective non-shared sub-sections.

[0023] The general code area 141 stores machine executable instructions that can be executed by the processors 110 and 120. The machine executable instructions may specify source operands (e.g., input data) and / or target operands (e.g., execution results). For example, the source operand may be loaded from a given memory address in a shared segment of the memory 140. In many cases, the source operand and / or the target operand may be located in a non-shared segment of the memory 140. In an embodiment, when the instructions in the general code area 410 are executed, the same memory address or pointer may be provided to the first processor 110 and the second processor 120. The memory address or pointer may point to a memory location at the first RW data area 144 that only the first processor 110 accesses. At runtime, the memory address or pointer may be mapped or redirected to another memory location at the second RW data area 146 that only the second processor 120 accesses. Software or hardware may perform the mapping or redirection step, refer to the following. Figure 2 Provide technical details.

[0024] Figure 21 is a schematic diagram describing memory operations (e.g., load or store) performed by processors 110 and 120 according to an embodiment. When executing instructions stored in the general code area 141, processors 110 and 120 may read data from memory 140 and may generate execution results written back to memory 140. In an embodiment, both processors 110 and 120 may simultaneously or non-simultaneously execute read / write (e.g., load / store) instructions with operands at a first address in the first RW data area 144. The first processor 110 may read or write at the first address, and the second processor 120 may read or write at a second address mapped to the first address. In an embodiment, the second processor 120 may execute an address mapping method indicated by the memory management system software at runtime. In another embodiment, an offset value is configured for a hardware circuit 250 coupled to the memory 140 and / or the second processor 120. When the second processor 120 executes a read / write instruction with an operand at the first address, the hardware circuit 250 adds the offset value to the first address to generate a second address at the second sub-segment and redirects the read / write operation of the second processor 120 from the first address to the second address.

[0025] In systems that include additional processors (eg, greater than two), hardware circuitry 250 may be configured with a different offset value for each additional processor so that read / write accesses by these additional processors may also be redirected to respective non-shared subsegments of memory 140 .

[0026] Figure 3 A method 300 of code sharing is described according to an embodiment. Figure 1 System 100 and / or Figure 4 The mobile device 400 or another computing and / or communication device may perform the method 300. In an embodiment, the device performing the method 300 includes a circuit (e.g., processing hardware) and a computer-readable medium (e.g., memory) storing instructions, wherein when the instructions are executed, the device will perform the method 300.

[0027] refer to Figure 3 In an embodiment, method 300 begins at step 310, storing shared code in a shared section of a memory, and storing non-shared code in a non-shared section of the memory. At step 320, a first processor executes the shared code in the shared section according to a first scheduler. At step 330, a second processor executes the shared code in the shared section according to a second scheduler. The first processor and the second processor have read-only access to the shared section. The second scheduler operates independently of the first scheduler.

[0028] In an embodiment, the device 100 and / or the mobile device 400 may include two or more processors that share executable code in a shared memory segment without copying the shared code to their respective non-shared sub-segments. In an embodiment based on shared code, a first processor and a second processor may execute a read / write instruction with an operand at a first address in a first sub-segment, and at runtime, the second processor may map the first address to a second address in a second sub-segment according to an address mapping method. In another embodiment, at runtime, a hardware circuit may redirect a read / write operation performed by the second processor from a first address in a first sub-segment to a second address in a second sub-segment. In an embodiment, the first processor and the second processor may also share read-only data stored in a shared memory segment.

[0029] Figure 4 An example of a mobile device 400 is described according to an embodiment. The mobile device 400 may be Figure 1 An example of a device 100 that provides a platform for the above-mentioned video recording. The mobile device 400 includes a processing circuit 410, which further includes a processor 415 (e.g., a central processing unit), a graphics processing unit (GPU), a digital processing unit (DSP), a multimedia processor, other general and / or special processing circuits. In many systems, the processor 415 may be the same as a "core" or "processor core", and in many other systems, the processor may include multiple cores. Each processor 415 may include an arithmetic logic unit (ALU), control circuits, caches, and other hardware circuits. In an embodiment, the processing circuit 410 operates to execute software (including the aforementioned memory management system software) and applications running on the mobile device 400. In an embodiment, the mobile device 400 operates to execute Figure 3 Method 300.

[0030] The mobile device 400 further includes a memory 420 coupled to the processing circuit 410. The memory 420 includes partitions such as a shared segment 422 and a non-shared segment 423. The memory 420 may include a memory device, such as a dynamic RAM device, a ROM device, a flash memory, and / or other volatile or non-volatile memory devices. The memory 420 may further include a storage device, such as any type of solid-state or magnetic storage device. In an embodiment, the memory 420 may be a main memory or a system memory of the mobile device 400.

[0031] The mobile device 400 may also include I / O circuitry 430 to receive input and display output. The I / O circuitry 430 may further include wireless communication circuitry 450, such as an antenna, a digital and / or logic radio frequency (RF) transceiver, and RF circuitry. The mobile device 400 may further include a battery 490 to power the hardware components of the mobile device 400.

[0032] It is understandable that for descriptive purposes, the Figure 3 Additional hardware components may be added, and the Figure 4 Many of the components shown.

[0033] Although the mobile device 400 is used as an example in the present invention, it is understood that the method of the present invention can be applied to any computing and / or communication device including multiple processors. Non-limiting examples of the mobile device 400 include smartphones, smart watches, wearable devices, tablets, network connection devices, gaming devices, navigation devices, Internet of Things (IoT) devices, image processing devices, infotainment devices, reader devices, and other portable and / or wearable electronic devices.

[0034] Already referenced Figure 1 and Figure 4 The embodiment describes Figure 3 However, it should be understood that, unlike Figure 1 and Figure 4 Other embodiments of the invention discussed above may be implemented Figure 3 The flowchart operation, and Figure 1 and Figure 4 The embodiments discussed may perform steps different from those discussed in the flowcharts. Figure 3 The flowcharts show a specific order in which operations are performed by a specific embodiment of the present invention, but it should be understood that this order is exemplary (for example, alternative embodiments may perform operations in a different order, combine specific operations, overlap specific operations, etc.).

[0035] Various functional elements or blocks have been described above. It will be appreciated by those skilled in the art that the above functional modules may be implemented by circuits (special purpose circuits or general purpose circuits operating under the control of one or more processors and code instructions), which generally include transistors, which may be configured in the above manner to operate according to the above functional and operational control circuits.

[0036] Although the present invention has been described by way of example and in accordance with preferred embodiments, it is to be understood that the present invention is not limited thereto. Those skilled in the art will still be able to make various changes and modifications without departing from the scope and spirit of the present invention. Therefore, the scope of the present invention should be limited and protected by the appended claims and their equivalents.

Claims

1. A code sharing system, comprising: A memory including a shared segment and a non-shared segment; and A plurality of processors, including at least a first processor and a second processor, wherein the first processor and the second processor have read-only access rights to the shared segment of the memory, wherein: The first processor and the second processor perform the following steps: executing the shared code stored in the shared section of the memory according to the first scheduler and the second scheduler respectively, wherein the first scheduler operates independently of the second scheduler, executing the non-shared codes stored in the first sub-segment and the second sub-segment of the non-shared segment respectively; and The first processor and the second processor are configured to execute a read or write instruction having an operand at a first address in the first sub-segment according to the shared code, and for accessing the operand, at runtime, the second processor maps the first address to a second address in the second sub-segment according to an address mapping method.

2. The code sharing system according to claim 1, characterized in that: The first processor and the second processor are further configured to write respective results of executing the shared code into the first sub-segment and the second sub-segment respectively.

3. The code sharing system according to claim 1, characterized in that: The system further includes a hardware circuit, wherein, when running, the hardware circuit redirects a read or write operation performed by the second processor from a first address in the first sub-segment to a second address in the second sub-segment.

4. The code sharing system according to claim 1, characterized in that: The first processor and the second processor are further configured to access the shared segment of the memory simultaneously.

5. The code sharing system according to claim 1, characterized in that: The first processor and the second processor are configured to share read-only data stored in the shared section of the memory.

6. The code sharing system according to claim 1, characterized in that: The first processor and the second processor execute the shared code independently of each other.

7. The code sharing system according to claim 1, characterized in that: The first processor and the second processor have the same or compatible instruction set architecture.

8. The code sharing system according to claim 1, characterized in that: The first processor and the second processor are configured to execute the shared code stored in the shared section without requiring a copy of the shared code in the non-shared section.

9. The code sharing system according to claim 1, characterized in that: The memory and the plurality of processors are packaged in a mobile device.

10. A code sharing method, comprising: storing the shared code in a shared section of a memory and storing the non-shared code in a non-shared section of the memory, wherein the non-shared section includes a first sub-section and a second sub-section; executing, by a first processor according to a first scheduler, the shared code in the shared section and the non-shared code in the first subsection of the non-shared section; executing, by a second processor according to a second scheduler, the shared code in the shared section and the non-shared code in the second sub-section of the non-shared section; as well as executing, by the first processor and the second processor according to the shared code, a read or write instruction having an operand at a first address in the first subsection, and During operation, the second processor maps the first address to a second address in the second sub-segment and accesses the operand according to the address mapping method. The first processor and the second processor have read-only access rights to the shared segment, and the second scheduler works independently of the first scheduler.

11. The code sharing method according to claim 10, characterized in that: Further including: Writing, by the first processor, a first result of executing the shared code into a first subsection of the non-shared section; and The second processor writes a second result of executing the shared code into a second sub-segment of the non-shared segment.

12. The code sharing method according to claim 10, characterized in that: The method further includes: redirecting, by a hardware circuit, a read or write operation executed by the second processor from a first address in a first sub-segment of the non-shared segment to a second address in a second sub-segment of the non-shared segment.

13. The code sharing method according to claim 10, characterized in that: Further including: The shared section of the memory is accessed simultaneously by the first processor and the second processor.

14. The code sharing method according to claim 10, characterized in that: Further including: The read-only data stored in the shared section of the memory is shared by the first processor and the second processor.

15. The code sharing method according to claim 10, characterized in that: The first processor and the second processor execute the shared code independently of each other.

16. The code sharing method according to claim 10, characterized in that: The first processor and the second processor have the same or compatible instruction set architecture.

17. The code sharing method according to claim 10, characterized in that: The method further includes executing the shared code in the shared section without copying the shared code into the non-shared section.

18. The code sharing method according to claim 10, characterized in that: The first processor and the second processor are packaged in a mobile device.

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