Apparatus and method for input receiver circuit and receiver mask for the input receiver circuit

Abstract

Apparatus and methods for input receiver circuits and receiver masks for electronic memories are disclosed. Embodiments of the present disclosure include memory receiver masks having shapes other than rectangular shapes. For example, receiver masks according to some embodiments of the present disclosure may have a hexagonal shape. Receiver masks of other shapes may also be included in other embodiments of the present disclosure. Circuits, timing, and operating parameters for implementing non-rectangular and various shapes of receiver masks are described.

Description

Background Art

[0001] Semiconductor memories are used in many electronic systems to store data that can be retrieved at a later time. As electronic systems are increasingly required to be faster, have greater data capacity, and consume less power, semiconductor memories that are faster to access, store more data, and use less power are constantly being developed to meet the changing needs. Part of this development involves creating new specifications for controlling and accessing semiconductor memories, and the changes in specifications from one generation to the next involve improving the performance of memories in electronic systems.

[0002] Semiconductor memory is typically controlled by providing command signals, memory address signals, and clocks to the memory. For example, various command and address signals and clocks may be provided by a memory controller. The command signals may control the semiconductor memory to perform various memory operations, such as read operations for retrieving data from the memory and write operations for storing data to the memory. Data signals may be provided between the controller and the memory at a known timing relative to receipt of an associated command by the memory.

[0003] In the case of a newly developed memory, the memory may be provided with, for example, a system clock for timing commands and addresses and further provided with a data clock for timing read data provided by the memory and for timing write data provided to the memory. The memory may also provide a clock to the controller for timing the provision of data provided to the controller.

[0004] The external clock provided to the memory is used to provide an internal clock, which controls the timing of various internal circuits during the operation of the memory. For example, the internal clock can be used to clock the input circuit to receive various signals provided to the memory, such as command signals and address signals, as well as data signals. The input receiver of the input circuit receives the input signal and captures the valid input signal when the signal meets the specification of the defined characteristics such as voltage and / or timing characteristics. Input signals that do not meet the specifications cannot be guaranteed to be successfully captured by the input receiver. In addition, as the system frequency and data clock increase, the timing margin for capturing the valid input signal by the input receiver decreases, making the correct operation of the memory more challenging. Summary of the invention

[0005] Devices and methods for input receiver circuits and receiver masks are described herein. In one aspect of the disclosure, a device includes an input receiver configured to capture an input signal having at least one time-varying voltage characteristic based at least in part on a predefined receiver mask. The receiver mask has a first timing parameter associated with a first voltage level and further has a second timing parameter associated with a second voltage level. The second timing parameter is greater than the first timing parameter.

[0006] In another aspect of the present disclosure, a device includes an input circuit configured to receive an input signal. The input circuit includes an input receiver configured to capture a valid input signal when the input signal does not have a region defined by a receiver mask. The receiver mask is defined as a hexagonal mask shape.

[0007] In another aspect of the disclosure, a method includes providing a clock to a memory device and providing an input signal to the memory device. The input signal is not defined as a receiver mask in a hexagonal mask shape.

[0008] In another aspect of the disclosure, a method includes receiving an input signal at an input receiver and further includes capturing, at the input receiver, the input signal having a time-varying voltage characteristic based at least in part on a receiver mask. The receiver mask is in the shape of a hexagonal mask.

[0009] In another aspect of the present disclosure, an apparatus includes a memory, the memory including an input receiver, a command / address bus, a data bus, and a clock bus. The apparatus further includes a memory controller, the memory controller being coupled to the memory via the command / address bus, the data bus, and the clock bus. The memory controller is configured to provide a clock to a memory device on the clock bus and to provide an input signal to the memory device. The input signal does not encroach on a receiver mask of the input receiver, and the receiver mask is defined as a hexagonal mask shape.

[0010] In another aspect of the present disclosure, a device includes a command / address bus, a data bus, a clock bus, and a controller, the controller being configured to provide a clock on the clock bus and to provide an input signal. The device further includes a memory, the memory being coupled to the controller via the command / address bus, the data bus, and the clock bus. The memory includes an input receiver and is configured to receive the input signal at the input receiver. The memory is further configured to capture the input signal at the input receiver when the input signal remains outside a region defined by a receiver mask having a hexagonal mask shape. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a block diagram of a system according to an embodiment of the present disclosure.

[0012] Figure 2 is a block diagram of a device according to an embodiment of the present disclosure.

[0013] Figure 3 is a block diagram of an input circuit according to an embodiment of the present disclosure.

[0014] Figure 4 is a diagram of a receiver mask for an input signal according to an embodiment of the present disclosure.

[0015] Figure 5A and 5B is a diagram of the definition of a pulse of an input signal according to some embodiments of the present disclosure.

[0016] Figure 6 is a diagram of a receiver mask for an input signal according to an embodiment of the present disclosure.

[0017] Figure 7 is a diagram of a definition of a pulse of an input signal according to an embodiment of the present disclosure.

[0018] Fig. 8A and 8B is a diagram of the timing of input signals at external terminals according to an embodiment of the present disclosure.

[0019] Fig. 9 is a diagram of a receiver mask for an input signal according to an embodiment of the present disclosure.

[0020] Fig.10 is a diagram of a definition of a pulse of an input signal according to an embodiment of the present disclosure.

[0021] Fig.11 is a diagram showing the timing of input signals at external terminals of a semiconductor device according to an embodiment of the present disclosure.

[0022] Fig.12 is a diagram of a receiver mask for an input signal according to an embodiment of the present disclosure.

[0023] Fig.13 is a diagram of a definition of a pulse of an input signal according to an embodiment of the present disclosure.

[0024] Fig.14A and 14B is a diagram showing the timing of input signals at external terminals of a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] Devices and methods for implementing non-rectangular and various shapes of receiver masks in memory systems are described, and the devices and methods include circuits, timing and operating parameters. As explained herein, a typical receiver mask may have a rectangular shape. However, the rectangular shape may have a limited timing margin for the input receiver to successfully capture the input signal. Therefore, embodiments of the present disclosure include memory receiver masks having shapes other than rectangular shapes. For example, the receiver mask according to some embodiments of the present disclosure may have a hexagonal shape. Receiver masks of other shapes may also be included in other embodiments of the present disclosure.

[0026] Figure 1 1 is a block diagram of a system 100 according to an embodiment of the present disclosure. The system 100 includes a controller 10 and a memory system 105. The memory system 105 includes memories 110(0)-110(p) (e.g., "device 0" to "device p"), ​​where p is the number of memories. The memory 110 may be a dynamic random access memory (DRAM). In some embodiments of the present disclosure, the memory 110 may be a low power double data rate (LPDDR) DRAM. The memories 110(0)-110(p) are each coupled to a command / address, data, and clock bus. The controller 10 and the memory system 105 communicate via several buses. Commands and addresses are received by the memory system 105 on a command / address bus 115, and data is provided between the controller 10 and the memory system 105 via a data bus 125. Various clocks may be provided between the controller and the memory system 105 via a clock bus 130. The clock bus 130 may include signal lines for providing the controller 10 with system clocks CK_t and CK_c received by the memory system 105, data clocks WCK_t and WCK_c received by the memory system 105, and access data clocks RDQS_t and RDQS_c provided by the memory system 105. Each of the buses may include one or more signal lines on which signals are provided.

[0027] The CK_t and CK_c clocks provided by the controller 10 to the memory system 105 are used to time the provision and receipt of commands and addresses. The WCK_t and WCK_c clocks and the RDQS_t and RDQS_c clocks are used to time the provision of data. The CK_t and CK_c clocks are complementary, the WCK_t and WCK_c clocks are complementary, and the RDQS_t and RDQS_c clocks are complementary. The clocks are complementary when the rising edge of the first clock occurs simultaneously with the falling edge of the second clock, and when the rising edge of the second clock occurs simultaneously with the falling edge of the first clock.

[0028] The controller 10 provides commands to the memory system 105 to perform memory operations. Examples of memory commands include timing commands for controlling the timing of various operations, access commands for accessing the memory such as read commands for performing read operations and write commands for performing write operations, mode register write and read commands for performing mode register write and read operations, and other commands and operations. The command signal provided by the controller 10 to the memory system 105 further includes a selection signal (e.g., chip select CS signals CS0, CS1, CSp). When all memories 110 are provided with commands, addresses, data, and clocks, the selection signals provided on the corresponding selection signal lines are used to select which memory in the memory 110 will respond to the command and perform the corresponding operation. In some embodiments of the present disclosure, a corresponding selection signal is provided to each memory 110 of the memory system 105. The controller 10 provides an active selection signal to select the corresponding memory 110. When the corresponding selection signal is active, the corresponding memory 100 is selected to receive the command and address provided on the command / address bus 115.

[0029] In operation, when a read command and an associated address are provided to the memory system 105 by the controller 10, the memory 110 selected by the selection signal receives the read command and the associated address and performs a read operation to provide the controller 10 with read data from a memory location corresponding to the associated address. The read data is provided to the controller 10 by the selected memory 110 according to the timing relative to receiving the read command. For example, the timing may be based on a read latency (RL) value, which indicates the number of clock cycles of the CK_t and CK_c clocks after the read command when the read data is provided to the controller 10 by the selected memory 110 (the clock cycles of the CK_t and CK_c clocks are referred to as tCK). The RL value is programmed in the memory 110 by the controller 10. For example, the RL value may be programmed in a corresponding mode register of the memory 110. As is known, the mode register in each memory included in the memory 110 may be programmed with information for setting various operating modes and / or may be programmed to select features for the operation of the memory. One of the settings may be for the RL value.

[0030] When preparing to make the selected memory 110 provide read data to the controller 10, the controller provides active WCK_t and WCK_c clocks to the memory system 105. The WCK_t and WCK_c clocks can be used by the selected memory 110 to generate access data clocks RDQS_t and RDQS_c. When the clock periodically switches between a low clock level and a high clock level, the clock is active. On the contrary, when the clock maintains a constant clock level and does not periodically switch, the clock is inactive. The RDQS_t and RDQS_c clocks are provided to the controller 10 by the memory 110 performing the read operation for timing the read data provided to the controller 10. The controller 10 can use the RDQS_t and RDQS_c clocks for receiving read data.

[0031] In operation, when a write command and an associated address are provided to the memory system 105 by the controller 10, the memory 110 selected by the selection signal receives the write command and the associated address and performs a write operation to write data from the controller 10 to a memory location corresponding to the associated address. The write data is provided to the selected memory 110 by the controller 10 according to the timing relative to receiving the write command. For example, the timing may be based on a write latency (WL) value indicating the number of clock cycles of the CK_t and CK_c clocks after the write command when the write data is provided by the controller 10 to the selected memory 110. The WL value is programmed in the memory 110 by the controller 10. For example, the WL value may be programmed in a corresponding mode register of the memory 110.

[0032] In preparation for the selected memory 110 to receive write data from the controller 10, the controller provides active WCK_t and WCK_c clocks to the memory system 105. The WCK_t and WCK_c clocks can be used by the selected memory 110 to generate an internal clock for timing the operation of the circuit for receiving the write data. The data is provided by the controller 10, and the selected memory 110 receives the write data according to the WCK_t and WCK_c clocks, and the write data is written to the memory corresponding to the memory address.

[0033] Figure 2 2 is a block diagram of an apparatus according to an embodiment of the present disclosure. The apparatus may be a semiconductor device 200 and will be referred to as such. The semiconductor device 200 may include, but is not limited to, a DRAM device. In some embodiments of the present disclosure, the semiconductor device 200 may be a low power DDR (LPDDR) memory integrated into a single semiconductor chip.

[0034] The semiconductor device 200 includes a memory array 250. The memory array 250 is shown to include a plurality of memory banks. Figure 2In the embodiment of FIG. 1 , the memory array 250 is shown to include eight memory banks BANK0-BANK7. Each memory bank includes a plurality of word lines WL, a plurality of bit lines BL and / BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL and / BL. The selection of the word lines WL may be performed by the row decoder 240, and the selection of the bit lines BL and / BL may be performed by the column decoder 245. Figure 2 In the embodiment of the present invention, the row decoder 240 includes a corresponding row decoder for each memory bank, and the column decoder 245 includes a corresponding column decoder for each memory bank. The bit lines BL and / BL are coupled to corresponding sense amplifiers (SAMPs). The read data from the bit lines BL or / BL is amplified by the sense amplifier SAMP and transmitted to the read / write amplifier 255 through the complementary local data line (LIOT / B), the transmission gate (TG) and the complementary main data line (MIOT / B). Conversely, the write data output from the read / write amplifier 255 is transmitted to the sense amplifier SAMP through the complementary main data line MIOT / B, the transmission gate TG and the complementary local data line LIOT / B and written into the memory cell MC coupled to the bit lines BL or / BL.

[0035] The semiconductor device 200 may employ a plurality of external terminals including a command and address and chip select (CA / CS) terminal coupled to a command and address bus to receive a command and address and a CS signal. The external terminals may further include a clock terminal for receiving clocks CK_t and CK_c and data clocks WCK_t and WCK_c and providing access data clocks RDQS_t and RDQS_c, data terminals DQ and DM, and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0036] The clock terminal is supplied with external clocks CK_t and CK_c provided to the input buffer 220. The external clocks may be complementary. The input buffer 220 generates an internal clock ICLK based on the CK_t and CK_c clocks. The ICLK clock is provided to the command decoder 215 and the internal clock generator 222. The internal clock generator 222 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used to time the operation of various internal circuits. Data clocks WCK_t and WCK_c are also provided to the external clock terminal. The WCK_t and WCK_c clocks are provided to the data clock circuit 275, which generates an internal data clock based on the WCK_t and WCK_c clocks. The internal data clock is provided to the input / output circuit 260 to time the operation of the circuit contained in the input / output circuit 260, for example, to the input receiver circuit (also referred to as the input receiver) to time the reception of the write data.

[0037] The CA / CS terminal may be supplied with a memory address. The memory address supplied to the CA / CS terminal is transmitted to the address decoder 212 through the command / address input circuit 205. The address decoder 212 receives the address and supplies the decoded row address XADD to the row decoder 240 and supplies the decoded column address YADD to the column decoder 245. The CA / CS terminal may be supplied with a command. Examples of commands include access commands for accessing the memory such as a read command for performing a read operation and a write command for performing a write operation, a mode register write and read command for performing a mode register write and read operation, and other commands and operations.

[0038] The command may be provided as an internal command signal to the command decoder 215 through the command / address input circuit 205. The command decoder 215 includes circuits for decoding the internal command signal to generate various internal signals and commands for performing operations. For example, the command decoder 215 may provide a row command signal ACT for selecting a word line and a column command signal R / W for selecting a bit line.

[0039] The power supply terminals are supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 270. The internal voltage generator circuit 270 generates various internal potentials VPP, VOD, VARY, VTARGET, VPERI, etc. based on the power supply potentials VDD and VSS supplied to the power supply terminals. The internal potential VPP is mainly used in the row decoder 240, the internal potentials VOD and VARY are mainly used in the sense amplifier SAMP included in the memory array 250, VTARGET may be a target voltage of the internal potential VARY, and the internal potential VPERI is used in many peripheral circuit blocks.

[0040] The power supply terminals may also be supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 260. In an embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be the same potentials as the power supply potentials VDD and VSS supplied to the power supply terminals. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminals. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals are used for the input / output circuit 260 so that the power supply noise generated by the input / output circuit 260 does not propagate to other circuit blocks.

[0041] When a read command is received and the read command is supplied in time for the row address and the column address, read data is read from the memory cell corresponding to the row address and the column address in the memory array 250. The read command is received by the command decoder 215, which provides an internal command so that the read data from the memory array 250 is provided to the read / write amplifier 255. The read data is output to the outside from the data terminal DQ through the input / output circuit 260. RDQS_t and RDQS_c clocks are provided from the clock terminal to the outside for timing the read data provided by the input / output circuit 260. The external terminal DQ includes a plurality of separate terminals, each of which provides a data bit synchronized with the clock edge of the RDQS_t and RDQS_c clocks.

[0042] When a write command is received and the write command is supplied for the row address and the column address in time, the write data supplied to the data terminal DQ is written to the memory cell corresponding to the row address and the column address in the memory array 250. A data mask can be provided to the data terminal DM so as to mask the parts of the data when writing to the memory. The write command is received by the command decoder 215, which provides an internal command so that the write data is received by the input receiver in the input / output circuit 260. WCK_t and WCK_c clocks can also be provided to the external clock terminal for timing the reception of the write data by the input receiver of the input / output circuit 260. The write data is supplied to the read / write amplifier 255 through the input / output circuit 260 and supplied to the memory array 250 by the read / write amplifier 255 to be written into the memory cell MC. As previously described, the external terminal DQ includes several separate terminals. With reference to the write operation, each external terminal DQ simultaneously receives a data bit synchronized with the clock edge of the WCK_t and WCK_c clocks.

[0043] Various circuits in the previously described circuits may include input receiver circuits for receiving input signals. For example, an input receiver may be included in the command / address input circuit 205 to receive command and address signals and receive a selection signal. In another example, an input receiver may be included in the input / output circuit 260 to receive a data signal and / or a signal related to the data signal (e.g., a data mask signal DM, an error correction code signal including a parity signal, a data bus inversion signal, etc.). The input receiver may receive an input signal such as that timed by a clock. In some embodiments of the present disclosure, the clock may be, for example, a CK_t and CK_c clock (or a clock based on the CK_t and CK_c clocks) of an input receiver for receiving command and address signals and / or an input receiver for receiving a selection signal. In some embodiments of the present disclosure, the clock may be, for example, a WCK_t and WCK_c clock (or a clock based on the WCK_t and WCK_c clocks) of an input receiver for receiving a data signal (or related to a data signal). As previously mentioned, an input receiver can capture a valid input signal when the input signal meets specifications that define characteristics of the input signal (e.g., voltage and / or timing characteristics). As an example, the input signal can include time-varying voltage characteristics based at least in part on predefined characteristics. An input signal that does not meet the specifications is not guaranteed to be successfully captured by the input receiver.

[0044] Figure 3 3 is a block diagram of an input circuit 300 according to an embodiment of the present disclosure. The input circuit 300 may be included in an input / output circuit. In some embodiments of the present disclosure, the input circuit 300 is included in Figure 2 The input / output circuit 260 of the semiconductor device 200 of FIG. The input circuit 300 may be provided with input signals IN0-INn from external terminals, where n is the number of external terminals. The input circuit 300 may be further provided with clocks CLK_t and CLK_c. The CLK_t and CLK_c clocks may be complementary. The CLK_t and CLK_c clocks may enable the input circuit 300 to capture the IN0-INn signals, thereby controlling the timing of the input circuit 300.

[0045] The input circuit 300 includes an input receiver circuit 310, which receives a corresponding IN signal from an external terminal. Each input receiver in the input receiver 310 is driven by the CLK_t and CLK_c clocks to capture the corresponding IN signal. The input receiver 310 further receives a reference voltage VREF. The input receiver 310 compares the voltage of the corresponding IN signal with the VREF signal to determine the logic level of the corresponding IN signal and provides a corresponding output signal OUT whose voltage corresponds to the logic level based on the comparison. For example, an input signal whose voltage is greater than the VREF voltage when captured by the input receiver is determined to be a 1 logic level, and conversely, an input signal whose voltage is less than the VREF voltage when captured by the input receiver is determined to be a 0 logic level. The voltage of the resulting corresponding output signal OUT provided by the input receiver corresponds to a logic level based on the logic level of the corresponding input signal. The OUT signal can be provided to the internal circuit for further operation. The input receiver 310 of the input circuit 300 can be implemented by a conventional input receiver known now or developed later.

[0046] In various embodiments of the present disclosure, the input signal may be, for example, a command and address signal, a selection signal, an input signal, and / or a data signal. In various embodiments of the present disclosure, the CLK_t and CLK_c clocks may be, for example, system clocks CK_t and CK_c, data clocks WCK_t and WCK_c, and / or clocks based on the system clock, data clock, etc.

[0047] As previously described, the input receiver circuit receives an input signal when clocked by a clock. The input signal should meet specifications that define the characteristics of the input signal in order for the input receiver to capture the input signal (e.g., accurately capture the data of the input signal). An input signal that does not meet the specifications is not guaranteed to be successfully captured by the input receiver.

[0048] For example, the specification for the input signal may include defining a pulse of the input signal and defining a receiver mask for the input signal. The receiver mask defines an area that the input signal must not encroach on for the input receiver to capture the input signal. As an example, when the input signal does not have an area defined by the receiver mask (such as the input signal does not cross into the area of ​​the receiver mask, the input signal remains outside the area of ​​the receiver mask, etc.), the input receiver captures the input signal. The receiver mask may be defined by a timing parameter and a voltage parameter. The timing parameter may represent a mask width of the receiver mask, and the voltage parameter may represent a mask height of the receiver mask. As an example, the input receiver may capture an input signal that includes a time-varying voltage characteristic based at least in part on a predefined receiver mask.

[0049] A typical receiver mask may have a rectangular shape. However, a rectangular shape may have a limited timing margin for the input receiver to successfully capture the input signal. In the case where a high frequency clock is used to time the operation of the input receiver, increasing the margin for successfully capturing the input signal may be desirable. Embodiments of the present disclosure include receiver masks having shapes other than a rectangular shape. Receiver masks according to some embodiments of the present disclosure may have a hexagonal shape.

[0050] Other embodiments of the present disclosure may include receiver masks of other shapes, such as receiver masks of polygonal shapes with five or more straight sides and receiver masks of curved shapes such as circles, ellipses, etc. Embodiments of the present disclosure may also include receiver masks of shapes that cannot be mirrored across an axis, such as irregular polygonal shapes and curved shapes.

[0051] Figure 4 is a diagram of a receiver mask for an input signal according to an embodiment of the present disclosure. Figure 5A and 5B is a diagram of the definition of pulses of an input signal according to some embodiments of the present disclosure. As previously described, a receiver mask defines an area that an input signal must not encroach upon in order for an input receiver to capture the input signal. Such an input receiver may be included in Figure 2 In different input circuits of the semiconductor device 200, such as the command / address input circuit 205, the input / output circuit 260, etc. In some embodiments of the present disclosure, such input receivers may be included in Figure 3 The input circuit 300 is input to the input receiver 310 .

[0052] refer to Figure 4 , the receiver mask 400 can be defined as a "hexagonal mask" shape. Figure 4 Also shown in FIG. 4 are several example input signals relative to receiver mask 400 . Figure 4 The input signals shown in FIG. 4 may be displaced in time or voltage relative to each other. However, none of the example input signals encroach upon the area of ​​the receiver mask 400. Thus, the input receivers (e.g., Figure 3 The input receiver 310) can capture the input signal.

[0053] The receiver mask 400 can be defined by timing parameters and voltage parameters. For example, Figure 4The receiver mask 400 is shown as having timing parameters tIVW1 and tIVW2 and a voltage parameter vIVW. The tIVW1 parameter is defined as the length of time between points A and D. Points A and D of the receiver mask 400 correspond to times T0 and T3. Points A and D are relative to each other and represent the vertices of the hexagonal mask. The tIVW2 parameter is defined as the length of time between points B and C and / or points F and E. Points B and C are located at both ends of edge BC, and points F and E are located at both ends of edge FE. Points B and C and / or points F and E correspond to times T1 and T2. The vIVW parameter is defined as the voltage difference between the voltage of edge BC (e.g., a high voltage) and the voltage of edge FE (e.g., a low voltage). The tIVW1 and tIVW2 parameters can represent the mask width of the receiver mask 400, and the vIVW parameter can represent the mask height of the receiver mask 400.

[0054] Compared to the typical rectangular shape of the receiver mask, the reference Figure 4 The receiver mask described can provide greater timing margin. For example, Figure 4 The non-rectangular shape of a receiver mask can better allow signals provided to an input receiver to transition from a low logic level voltage to a high logic level voltage, and vice versa. The rate at which a signal changes from a low logic level voltage to a high logic level voltage, and vice versa, can be such that a rectangular receiver mask is encroached upon at the corners of the mask, particularly when receiving signals at high clock speeds. A rectangular receiver mask is typically defined by a mask width. Reference Figure 4 , the mask width of a typical rectangular receiver mask will be equal to the timing parameter tCSIVW2. However, Figure 4 The non-rectangular receiver mask has a second timing parameter tCSIVW1 that is greater than the tCSIVW2 parameter and is also greater than the mask width of a typical rectangular receiver mask. Figure 4 The wider mask width (eg, the second timing parameter) of the receiver mask provides additional timing margin for the input receiver to capture the input signal. Figure 1 Compared to the system 100 of the present invention, the system using input receivers and receiver masks according to the embodiments of the present disclosure may be able to operate at a faster clock speed. Therefore, compared to conventional systems, the embodiments of the present disclosure may improve overall system performance.

[0055] Figure 5A and 5B An example of a pulse of an input signal having a rising voltage (e.g., data "1") and a pulse of an input signal having a falling voltage (e.g., data "0") is shown. The pulse of the input signal is defined by a timing parameter and a voltage parameter. For example, Figure 5AThe input signal pulse of is shown as having timing parameter tIPW and voltage parameters vIHL_AC, vIVW and VREF, and Figure 5B The pulses of the input signal are shown with timing parameters tIPW and tIHL and voltage parameters vIHL_AC, vIVW and VREF.

[0056] The tIPW parameter is defined as the length of time between the intersection of the pulse and the reference voltage VREF. The VREF voltage may represent a voltage used to determine the logic level of the input signal. The voltage difference between the high voltage and the low voltage is defined as a voltage vIVW. The vIVW voltage is centered around the VREF voltage. In some embodiments of the present disclosure, the vIVW voltage may correspond to a parameter used to define a receiver mask. For example, the vIVW parameter is a previously referenced Figure 4 Specific reference is made to the receiver mask 400 shown in FIG. Figure 5B , the tIHL parameter is defined as the length of time between the intersection of a pulse and a high voltage (eg, for an input signal that increases in voltage) or a low voltage (eg, for an input signal that decreases in voltage).

[0057] The vIHL_AC parameter is defined as the peak-to-peak voltage between the high voltage peak and the low voltage peak of the example rising input signal and the falling input signal. The vIHL_AC parameter is centered around the VREF voltage such that vIHL_AC / 2 is met both above and below the VREF voltage. The input signal should meet or exceed vIHL_AC at any time within the entire unit interval of the input signal. The high voltage peak is greater than the high voltage of the vIVW parameter, and the low voltage peak is less than the low voltage of the vIVW parameter.

[0058] The tIPW parameter can represent the pulse width of the input signal, and the tIHL parameter ( Figure 5B ) can represent the pulse width of the input signal above / below the high / low voltage of vIVW. The vIHL_AC parameter can represent the pulse amplitude of the input signal.

[0059] Figure 6 is a diagram of a receiver mask for an input signal according to an embodiment of the present disclosure. Figure 7 is a diagram of the definition of a pulse of an input signal according to an embodiment of the present disclosure. In some embodiments of the present disclosure, Figure 6 The receiver mask and Figure 7 The definition of the input signal pulse can be for an input receiver that receives command and / or address signals. Such an input receiver can be included in Figure 2 In some embodiments of the present disclosure, such an input receiver may be included in the command / address input circuit 205 of the semiconductor device 200. Figure 3 The input circuit 300 is input to the input receiver 310 .

[0060] refer to Figure 6 , the receiver mask 600 is defined as a hexagonal mask shape. In embodiments where the input signal is a command and / or address signal, the command and address signals apply the same compliance mask and operate in double data rate mode (e.g., captured at both the rising and falling edges of the clock). As previously described, the receiver mask defines an area that the input signal does not encroach on for the input receiver to capture a valid input signal.

[0061] Figure 6 The receiver mask 600 is shown as having timing parameters tCIVW1 and tCIVW2 and a voltage parameter vCIVW. The tCIVW1 parameter is defined as the length of time between points A and D. Points A and D of the receiver mask 600 correspond to times T0 and T3. Points A and D are opposite to each other and represent the vertices of the hexagonal mask. The tCIVW2 parameter is defined as the length of time between points B and C and / or points F and E. Points B and C are located at both ends of edge BC, and points F and E are located at both ends of edge FE. Points B and C and / or points F and E correspond to times T1 and T2. The vCIVW parameter is defined as the voltage difference between the voltage of edge BC (e.g., a high voltage) and the voltage of edge FE (e.g., a low voltage).

[0062] The tCIVW1 parameter may represent the mask width of the receiver mask 600 at the reference voltage VREFCA, and the tCIVW2 parameter may represent the mask width of the receiver mask 600 at vCIVW. The vCIVW parameter may represent the mask height of the receiver mask 600.

[0063] Figure 7 An example of a pulse of an input signal having a rising voltage (eg, data “1”) and a falling voltage (eg, data “0”) is shown. Figure 7 The pulse of the input signal has a timing parameter tCIPW and voltage parameters vCIHL_AC, vCIVW and VREFCA. The tCIPW parameter is defined as the length of time between the intersection of the pulse and the reference voltage VREFCA. The VREFCA voltage can represent a voltage used to determine the logic level of the input signal. The voltage difference between the high voltage and the low voltage is defined as a voltage vCIVW. The vCIVW voltage is centered around the VREFCA voltage. In some embodiments of the present disclosure, the vCIVW voltage can correspond to a parameter used to define a receiver mask. For example, the vCIVW parameter is a parameter previously referenced Figure 6 Receiver mask 600 is shown in FIG.

[0064] The vCIHL_AC parameter is the peak-to-peak voltage between the high voltage peak and the low voltage peak for the example rising and falling input signals. The vCIHL_AC parameter is centered around the VREFCA voltage such that vCIHL_AC / 2 is met both above and below the VREFCA voltage. The input signal should meet or exceed vCIHL_AC at any time within the entire unit interval of the input signal. The high voltage peak is greater than the high voltage of the vCIVW parameter, and the low voltage peak is less than the low voltage of the vCIVW parameter. However, vCIHL_AC does not have to be met when a transition is not occurring.

[0065] The tCIPW parameter can represent the pulse width of the input signal. The vCIHL_AC parameter can represent the pulse amplitude of the input signal.

[0066] Fig. 8A and 8B is a diagram of the timing of input signals at external terminals according to an embodiment of the present disclosure. The external terminals may be semiconductor devices such as Figure 2 In some embodiments of the present disclosure, Fig. 8A and 8B The timing of the input signal at the external terminal can be related to Figure 6 Used with receiver mask 600.

[0067] Fig. 8A The timing of the input signal at the rising clock edge of the system clock CK_t (and at the falling clock edge of the clock CK_c, which is complementary to the CK_t clock) is shown. Figure 8B The timing of the input signal at the falling clock edge of the clock CK_t (and at the rising clock edge of the CK_c clock) is shown. Fig. 8A and 8B An example receiver mask is shown in FIG. In some embodiments of the present disclosure, the receiver mask may be Figure 6 For example, a receiver mask 600 having timing parameters tCIVW1 and tCIVW2 and a voltage parameter vCIVW is shown. The input signal does not encroach on the receiver mask area.

[0068] The input signal timing terms at the external pins are measured from CK_t / CK_c (differential mode) / CK (single-ended mode) to the center (midpoint) of the tCIVW1 and tCIVW2 windows taken at midpoint and vCIVW voltage levels. The receiver mask window is centered around the CK_t / CK_c crossing point (differential mode) / CK (single-ended mode).

[0069] Fig. 9 is a diagram of a receiver mask for an input signal according to an embodiment of the present disclosure. Fig.10is a diagram of the definition of a pulse of an input signal according to an embodiment of the present disclosure. In some embodiments of the present disclosure, Fig. 9 The receiver mask and Fig.10 The definition of the pulse of the input signal can be used for an input receiver that receives a selection signal (e.g., a chip selection signal). Such an input receiver can be included in Figure 2 In some embodiments of the present disclosure, such an input receiver may be included in the command / address input circuit 205 of the semiconductor device 200. Figure 3 The input circuit 300 is input to the input receiver 310 .

[0070] refer to Fig. 9 , the receiver mask 900 is defined as a hexagonal mask shape. In embodiments where the input signal is a select signal, the select signal applies the same compliance mask and operates in a single data rate mode (e.g., captured at the rising edge of the system clock). As previously described, the receiver mask defines an area that the input signal does not encroach on for the input receiver to capture a valid input signal.

[0071] Fig. 9 The receiver mask 900 is shown as having timing parameters tCSIVW1 and tCSIVW2 and a voltage parameter vCSIVW. The tCSIVW1 parameter is defined as the length of time between points A and D. Points A and D of the receiver mask 900 correspond to times T0 and T3. Points A and D are opposite to each other and represent vertices of the hexagonal mask. The tCSIVW2 parameter is defined as the length of time between points B and C and / or points F and E. Points B and C are located at both ends of edge BC, and points F and E are located at both ends of edge FE. Points B and C and / or points F and E correspond to times T1 and T2. The vCSIVW parameter is defined as the voltage difference between the voltage of edge BC (e.g., a high voltage) and the voltage of edge FE (e.g., a low voltage).

[0072] The tCSIVW1 parameter may represent the mask width of the receiver mask 900 at the reference voltage VREFCS, and the tCSIVW2 parameter may represent the mask width of the receiver mask 900 at vCSIVW. The vCSIVW parameter may represent the mask height of the receiver mask 900.

[0073] Fig.10 An example of a pulse of an input signal having a rising voltage (eg, data “1”) and a falling voltage (eg, data “0”) is shown. Fig.10The pulse of the input signal has a timing parameter tCSIPW and voltage parameters vCSIHL_AC, vCSIVW and VREFCS. The tCSIPW parameter is defined as the length of time between the intersection of the pulse and the reference voltage VREFCS. The VREFCS voltage can represent a voltage used to determine the logic level of the input signal. The voltage difference between the high voltage and the low voltage is defined as a voltage vCSIVW. The vCSIVW voltage is centered around the VREFCS voltage. In some embodiments of the present disclosure, the vCSIVW voltage can correspond to a parameter used to define a receiver mask. For example, the vCSIVW parameter is a previously referenced Fig. 9 Receiver mask 900 is shown as described above.

[0074] The vCSIHL_AC parameter is the peak-to-peak voltage between the high voltage peak and the low voltage peak for the example rising and falling input signals. The vCSIHL_AC parameter is centered around the VREFCS voltage such that vCSIHL_AC / 2 is met both above and below the VREFCS voltage. The input signal should meet or exceed vCSIHL_AC at any time within the entire unit interval of the input signal. The high voltage peak is greater than the high voltage of the vCSIVW parameter, and the low voltage peak is less than the low voltage of the vCSIVW parameter. However, vCSIHL_AC does not have to be met when a transition is not occurring.

[0075] The tCSIPW parameter may represent the pulse width of the input signal. The vCSIHL_AC parameter may represent the pulse amplitude of the input signal.

[0076] Fig.11 is a diagram showing the timing of input signals at external terminals of a semiconductor device according to an embodiment of the present disclosure. In some embodiments of the present disclosure, Fig.11 The timing of the input signal at the external terminal can be related to Fig. 9 Used with receiver mask 900.

[0077] Fig.11 The timing of the input signal at the rising clock edge of clock CK_t (and at the falling clock edge of clock CK_c, which is complementary to the CK_t clock) is shown. Fig.11 An example receiver mask is shown in FIG. In some embodiments of the present disclosure, the receiver mask may be Fig. 9 Receiver mask 900 with timing parameters tCSIVW1 and tCSIVW2 and voltage parameter vCSIVW is shown. The example input signal does not encroach on the receiver mask area.

[0078] The input signal timing terms at the external pins are measured from CK_t / CK_c (differential mode) / CK (single-ended mode) to the center (midpoint) of the tCSIVW1 and tCSIVW2 windows taken at midpoint and vCSIVW voltage levels. The receiver mask window is centered around the CK_t / CK_c crossing point (differential mode) / CK (single-ended mode).

[0079] Fig.12 is a diagram of a receiver mask for an input signal according to an embodiment of the present disclosure. Fig.13 is a diagram of the definition of a pulse of an input signal according to an embodiment of the present disclosure. In some embodiments of the present disclosure, Fig.12 The receiver mask and Fig.13 The definition of the pulse of the input signal can be for an input receiver that receives a data signal and / or a signal related to the data signal, such as a data mask signal, a data inversion signal, an error correction signal, etc. Such an input receiver can be included in Figure 2 In some embodiments of the present disclosure, such an input receiver may be included in the input / output circuit 260 of the semiconductor device 200. Figure 3 The input circuit 300 is input to the input receiver 310 .

[0080] refer to Fig.12 , the receiver mask 1200 is defined as a hexagonal mask shape. As previously described, the receiver mask defines the area that the input signal does not encroach on for the input receiver to capture a valid input signal. Fig.12 The receiver mask 1200 is shown as having timing parameters tDIVW1 and tDIVW2 and a voltage parameter vDIVW. The tDIVW1 parameter is defined as the length of time between points A and D. Points A and D of the receiver mask 1200 correspond to times T0 and T3. Points A and D are opposite to each other and represent the vertices of the hexagonal mask. The tDIVW2 parameter is defined as the length of time between points B and C and / or points F and E. Points B and C are located at both ends of edge BC, and points F and E are located at both ends of edge FE. Points B and C and / or points F and E correspond to times T1 and T2. The vDIVW parameter is defined as the voltage difference between the voltage of edge BC (e.g., a high voltage) and the voltage of edge FE (e.g., a low voltage). The tDIVW1 parameter can represent the mask width of the receiver mask 1200 under the reference voltage VREFDQ, and the tDIVW2 parameter can represent the mask width of the receiver mask 1200 under vDIVW. The vDIVW parameter may represent the mask height of the receiver mask 1200 .

[0081] Fig.13 An example of a pulse of an input signal having a rising voltage (eg, data “1”) and a falling voltage (eg, data “0”) is shown. Fig.13The pulse of the input signal is shown as having timing parameters tDIPW and tDIHL and voltage parameters vDIHL_AC, vDIVW, and VREFDQ. The tDIPW parameter is defined as the length of time between the intersection of the pulse and the reference voltage VREFDQ. The VREFDQ voltage can represent a voltage used to determine the logic level of the input signal. The tDIHL parameter is defined as the length of time between the intersection of the pulse and the high voltage of vDIVW or the low voltage of vDIVW. The voltage difference between the high voltage and the low voltage is defined as the voltage vDIVW. The vDIVW voltage is centered around the VREFDQ voltage. In some embodiments of the present disclosure, the vDIVW voltage may correspond to a parameter used to define a receiver mask. For example, the vDIVW parameter is a previously referenced Fig.12 The receiver mask 1200 shown in FIG.

[0082] The vDIHL_AC parameter is the peak-to-peak voltage between the high voltage peak and the low voltage peak of the example rising input signal and the falling input signal. The vDIHL_AC parameter is centered around the VREFDQ voltage so that vDIHL_AC / 2 is met both above and below the VREFDQ voltage. The input signal should meet or exceed vDIHL_AC at any time throughout the unit interval of the input signal. The high voltage peak is greater than the high voltage of the vDIVW parameter, and the low voltage peak is less than the low voltage of the vDIVW parameter.

[0083] The tDIPW parameter may represent the pulse width of the input signal at the VREFDQ voltage, and tDIHL may represent the pulse width of the input signal above / below the high / low voltage of vDIVW. The vDIHL_AC parameter may represent the pulse amplitude of the input signal.

[0084] Fig.14A and 14B is a diagram showing the timing of an input signal at an external terminal of a semiconductor device according to an embodiment of the present disclosure. The timing of the input signal may refer to an internal latch circuit. In some embodiments of the present disclosure, Fig.14A and 14B The timing of the input signal at the external terminal can be related to Fig.12 Used with a receiver mask of 1200.

[0085] Fig.14A The timing of the input signal at the internal latch circuit for the rising clock edge of the internal data clock WCKm is shown. The "data eye" of the input signal is center aligned with the WCKm clock. The input signal is center aligned with the strobe at the internal latch circuit. Fig. 14BThe timing of the input signal at the rising clock edge of the data clock WCK_t (and at the falling clock edge of the WCK_c clock, which is complementary to the WCK_t clock) is shown. Fig. 14B 2DQIy after the rising clock edge of the WCK_t clock. The tWCK2DQI time represents the minimum tWCK2DQI time. The third example is for an input signal in which the example receiver mask is centered at a time tWCK2DQIx after the rising clock edge of the WCK_t clock. The tWCK2DQIy time represents the minimum tWCK2DQI time. The third example is for an input signal in which the example receiver mask is centered at a time tWCK2DQIz after the rising clock edge of the WCK_t clock. The tWCK2DQIz time represents the maximum tWCK2DQI time.

[0086] In some embodiments of the present disclosure, Fig. 14B The receiver mask can be Fig.12 For example, a receiver mask 1200 having timing parameters tDIPW and TDIHL and voltage parameter vDIVW. The input signal does not encroach on the receiver mask area.

[0087] Based on the foregoing, it should be understood that although specific embodiments of the present disclosure have been described for illustrative purposes, various modifications may be made without departing from the spirit or scope of the present disclosure. For example, although the specific example of the receiver mask previously described is a hexagonal shape, the embodiments of the present disclosure are not intended to be limited to receiver masks of hexagonal shapes. As previously described, receiver masks of other shapes may be included in the embodiments of the present disclosure. Therefore, the scope of the present disclosure should not be limited to any specific embodiment described herein.

[0088] Certain details are set forth herein to provide a full understanding of the examples of the present disclosure. However, it will be clear to those skilled in the art that the examples of the present disclosure can be practiced without these specific details. In addition, the specific examples of the present disclosure described herein should not be interpreted as limiting the scope of the present disclosure to these specific examples. In other cases, well-known circuits, control signals, timing schemes and software operations are not shown in detail to avoid unnecessarily obscuring the present disclosure. In addition, terms such as "coupling (couples and coupled)" mean that two components can be electrically coupled directly or indirectly. Indirect coupling can imply that two components are coupled through one or more intermediate components.

Claims

1. A semiconductor device comprising: An input receiver configured to capture an input signal having at least one time-varying voltage characteristic based on a predefined receiver mask, wherein the receiver mask has a first timing parameter associated with a first voltage level and further has a second timing parameter associated with a second voltage level, wherein the second timing parameter is greater than the first timing parameter, wherein a receiver mask window is centered around a crossing point of a complementary system clock signal, and wherein when the input signal is a command and / or address signal, the command and / or address signal is captured at a rising edge and a falling edge of one of the complementary system clock signals. 2 . The semiconductor device of claim 1 , wherein the first voltage level comprises a high voltage or a low voltage of a voltage parameter of the receiver mask. 3 . The semiconductor device according to claim 1 , wherein the second voltage level is a reference voltage. 4 . The semiconductor device of claim 1 , wherein the receiver mask is centered around the second voltage level. 5 . The semiconductor device according to claim 1 , wherein the first voltage level is greater than the second voltage level. 6 . The semiconductor device of claim 1 , wherein the receiver mask further has a third timing parameter associated with a third voltage level that is less than the second voltage level. 7 . The semiconductor device according to claim 6 , wherein the third timing parameter is equal to the first timing parameter. 8 . The semiconductor device according to claim 6 , wherein a first voltage difference between the first voltage level and the second voltage level is equal to a second voltage difference between the second voltage level and the third voltage level.

9. The semiconductor device of claim 6 , wherein the first timing parameter extends from a first start time to a first end time, the second timing parameter extends from a second start time to a second end time, and the third timing parameter extends from a third start time to a third end time, and wherein the first start time, the second start time, and the third start time and the first end time, the second end time, and the third end time correspond to vertices of a hexagonal shape. 10 . The semiconductor device according to claim 1 , wherein the input signal comprises at least one of a data signal, a command signal, an address signal, or a selection signal, or any combination thereof.

11. A semiconductor device comprising: an input circuit configured to receive an input signal, the input circuit comprising an input receiver configured to capture a valid input signal when the input signal is outside a region defined by a receiver mask, wherein the receiver mask is defined as a hexagonal mask shape; as well as A clock input buffer configured to receive a first external clock and a second external clock, the second external clock being complementary to the first external clock, wherein a center of the receiver mask is aligned with an intersection of the first external clock and the second external clock, and wherein when the input signal is a command and / or address signal, the command and / or address signal is captured at a rising edge and a falling edge of one of the first external clock and the second external clock. 12 . The semiconductor device according to claim 11 , wherein the input signal comprises a command signal, an address signal, a selection signal, or a combination thereof. 13 . The semiconductor device of claim 11 , further comprising a data clock circuit configured to receive a data clock, and wherein the receiver mask is center-aligned at a time after a rising clock edge of the data clock. 14 . The semiconductor device of claim 13 , wherein the input signal comprises a data signal, a signal related to a data signal, or a combination thereof. 15 . The semiconductor device of claim 11 , wherein the input circuit is further configured to receive a reference voltage, and wherein the voltage parameter of the receiver mask is centered around the reference voltage. 16 . The semiconductor device of claim 15 , wherein the voltage parameter represents a mask height of the receiver mask. 17 . The semiconductor device of claim 11 , wherein the receiver mask comprises a first mask width at a reference voltage and further comprises a second mask width at a receiver mask height.

18. A method for providing a signal to a memory device, comprising: providing a complementary system clock signal to the memory device; as well as An input signal is provided to the memory device, wherein the input signal is outside a receiver mask defined as a hexagonal mask shape, wherein a receiver mask window is centered around intersections of the complementary system clock signals, and wherein when the input signal is a command and / or address signal, the command and / or address signal is captured at rising and falling edges of one of the complementary system clock signals.

19. The method of claim 18, wherein the input signal comprises a command signal, an address signal, a selection signal, or a combination thereof.

20. The method of claim 18, further comprising providing a data clock, and wherein the input signal comprises a data signal, a signal related to a data signal, or a combination thereof.

21. The method of claim 18, wherein the pulses of the input signal are defined by pulse width or pulse amplitude or both, wherein the pulse amplitude is centered about a reference voltage.

22. A method for processing a signal, comprising: receiving an input signal and a complementary system clock signal at an input receiver; as well as An input signal having a time-varying voltage characteristic based on a receiver mask is captured at the input receiver, wherein the receiver mask is in the shape of a hexagonal mask, wherein a receiver mask window center surrounds an intersection of the complementary system clock signal, and wherein when the input signal is a command and / or address signal, the command and / or address signal is captured at a rising edge and a falling edge of one of the complementary system clock signals.

23. The method of claim 22, wherein capturing the input signal at the input receiver is responsive to a clock signal.

24. The method of claim 22, wherein the definition of the receiver mask comprises a first timing parameter at a first voltage and a second timing parameter at a second voltage, wherein the first timing parameter is longer than the second timing parameter.

25. The method of claim 24, wherein the first timing parameter represents a mask width at the first voltage and the second timing parameter represents a mask width at the second voltage.

26. The method of claim 24, wherein the definition of the receiver mask further comprises a voltage parameter, the voltage parameter being defined as a voltage difference between the first voltage and the second voltage.

27. The method of claim 22, wherein the input signal comprises a command signal, an address signal, a selection signal, a data signal, a signal related to a data signal, or a combination thereof.

28. A semiconductor device comprising: a memory, the memory comprising an input receiver; Command / address bus; Data bus; Clock bus; as well as a memory controller coupled to the memory via the command / address bus, the data bus, and the clock bus, the memory controller being configured to provide a complementary system clock signal to the memory device on the clock bus and to provide an input signal to the memory device, wherein the input signal does not encroach on a receiver mask of the input receiver, the receiver mask being defined as a hexagonal mask shape wherein a receiver mask window center surrounds an intersection of the complementary system clock signal, and wherein when the input signal is a command and / or address signal, the command and / or address signal is captured at a rising edge and a falling edge of one of the complementary system clock signals.

29. The apparatus of claim 28, wherein the input signal comprises a command signal, an address signal, or a select signal provided to the memory on the command / address bus.

30. The apparatus of claim 28, wherein the input signal comprises a data signal or a signal related to a data signal provided to the memory on the data bus.

31. A semiconductor device comprising: Command / address bus; Data bus; Clock bus; a controller configured to provide a complementary system clock signal on the clock bus and to provide an input signal; as well as A memory, the memory being coupled to the controller via the command / address bus, the data bus and the clock bus, the memory comprising an input receiver, and the memory being configured to receive the input signal at the input receiver and being further configured to capture the input signal at the input receiver when the input signal remains outside a region defined by a receiver mask having a hexagonal mask shape, wherein the receiver mask window center surrounds the intersection of the complementary system clock signal, and wherein when the input signal is a command and / or address signal, the command and / or address signal is captured at a rising edge and a falling edge of one of the complementary system clock signals.

32. The apparatus of claim 31, wherein the input signal received by the memory is provided by the controller to the memory on the command / address bus.

33. The apparatus of claim 31, wherein the input signal received by the memory is provided by the controller to the memory on the data bus.

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