Substrate Structure for Power Module

Abstract

The present invention provides a substrate structure for a power module. The substrate includes: an element region on which a plurality of semiconductor elements are provided; a central region that defines a space between the element regions; an input terminal region on which an input terminal for applying current to the substrate is provided; and one or more slit insulating portions defined on one side of the element region in the element region adjacent to the input terminal region. The slit insulating portions extend toward the central region so that the current applied through the input terminal region flows into the central region.

Description

Technical Field

[0001] The present disclosure relates to a substrate structure for a power module having a slit insulating portion that changes a path of current applied to a substrate. Background Art

[0002] In recent years, significant progress has been made in the technological development of power conversion devices (e.g., inverters), which are not only one of the core components of hybrid vehicles and electric vehicles but also a main component of environmentally friendly vehicles. The research and development of power modules is a core technology in the field of environmentally friendly vehicles. Power modules are the core components of power conversion devices and account for a large proportion of the cost of power conversion devices.

[0003] A plurality of semiconductor elements are mounted in a power module. When current is applied to the power module, the current is applied to the plurality of semiconductor elements, and the plurality of semiconductor elements convert the applied current. Therefore, when the current applied to each semiconductor element mounted in the power module has the same density, the function of the power module can be maximized.

[0004] In the prior art, in order to reduce the size of the power module, an integrated power module having a double-sided cooling deformed structure is manufactured. In a power module for power conversion in the conventional manner, when a plurality of semiconductor elements are used to configure the module, the current applied to each semiconductor element has a different density. In other words, when the power module is configured with a plurality of semiconductor elements, there is a problem that the current cannot be uniformly applied to the semiconductor elements. Summary of the Invention

[0005] An object of the present disclosure is to provide a substrate structure capable of changing a path of current applied to a substrate, thereby enabling the current applied to a plurality of semiconductor elements to maintain the same density.

[0006] According to an aspect of the present disclosure, there is provided a substrate structure for a power module. The substrate includes: an element region on which a plurality of semiconductor elements are disposed; a central region defining a space between the element regions; an input terminal region on which an input terminal for applying current to the substrate is disposed; and one or more slit insulating portions defined on one side of the element region adjacent to the input terminal region in the element region. The slit insulating portion extends toward the central region so that the current applied through the input terminal region flows into the central region.

[0007] In the structure according to this aspect, the element regions may sequentially include a first element region, a second element region, a third element region, and a fourth element region in the counterclockwise direction. The first element region and the fourth element region may be adjacent to the input terminal region. The slit insulating portion may include a first slit insulating portion defined between the first element region and the input terminal region and a second slit insulating portion defined between the fourth element region and the input terminal region.

[0008] In the structure according to this aspect, the first slit insulating portion and the second slit insulating portion may extend from the side of the substrate that defines the input terminal region toward the other side of the substrate opposite to the one side of the substrate.

[0009] In the structure according to this aspect, the first slit insulating portion may extend in a manner closer to the other side of the substrate than the second slit insulating portion.

[0010] In the structure according to this aspect, the first slit insulating portion and the second slit insulating portion may be provided between the first element region and the fourth element region.

[0011] In the structure according to this aspect, the first slit insulating portion may include: a first main slit insulating portion defined between the input terminal region and the first element region; and a first sub-slit insulating portion defined on one side of the first element region. The second slit insulating portion may include: a second main slit insulating portion defined between the input terminal region and the fourth element region; and a second sub-slit insulating portion defined on one side of the fourth element region.

[0012] In the structure according to this aspect, the first sub-slit insulating portion may extend in the direction from the first element region toward the second element region, and the second sub-slit insulating portion may extend in the direction from the fourth element region toward the third element region.

[0013] In the structure according to this aspect, the first sub-slit insulating portion may not protrude beyond the end of the first element region in the direction from the first element region toward the second element region. The second sub-slit insulating portion may not protrude beyond the end of the fourth element region in the direction from the fourth element region toward the third element region.

[0014] In the structure according to this aspect, the central region may refer to a region covering a predetermined range based on a center point equidistant from the element regions, and the current applied through the input terminal region may be applied to the element regions through the central region.

[0015] In the structure according to this aspect, the substrate may include: a source signal electrode portion that transmits a source signal to a semiconductor element; and a gate signal electrode portion that transmits a gate signal to the semiconductor element, and the source signal electrode portion and the gate signal electrode portion may be connected to the semiconductor element through a wire.

[0016] The structure according to this aspect may further include: a first electrode insulating portion and a second electrode insulating portion, wherein the source signal electrode portion is disposed between the second electrode insulating portion and the edge of the substrate, and the gate signal electrode portion is disposed between the first electrode insulating portion and the second electrode insulating portion.

[0017] According to another aspect of the present disclosure, there is provided a substrate structure for a power module, the substrate having a first region and a second region. Each of the first region and the second region includes: an element region on which a plurality of semiconductor elements are disposed; a central region that defines a space between the element regions; an input terminal region on which an input terminal for applying current to the substrate is disposed; and one or more slit insulating portions defined on one side of the element region adjacent to the input terminal region in the element region. The slit insulating portion extends toward the central region to allow the current applied through the input terminal region to flow into the central region.

[0018] In the structure according to this aspect, the input terminal region may include: a first input terminal region disposed on the first region, and current is applied to the first input terminal region from the outside; and a second input terminal region that applies the current transmitted from each semiconductor element disposed on the first region to the second region.

[0019] In the structure according to this aspect, the element region adjacent to the first input terminal region in the element region defined on the first region may be defined as a first lower element region. The element region adjacent to the second input terminal region in the element region defined on the second region may be defined as a second lower element region. The slit insulating portion may be disposed on one side of each first lower element region and one side of each second lower element region. The slit insulating portion may be disposed between the first lower element regions and between the second lower element regions.

[0020] In the structure according to this aspect, the slit insulating portion may include: a first slit insulating portion and a second slit insulating portion that extend from one side of the first region defining the first input terminal region toward the other side of the first region opposite to one side of the first region; and a third slit insulating portion and a fourth slit insulating portion that extend from one side of the second region defining the second input terminal region toward the other side of the second region opposite to one side of the second region.

[0021] In the structure according to this aspect, the first slit insulating portion and the second slit insulating portion may be defined on one side of their respective first lower element regions, and the first slit insulating portion and the second slit insulating portion may not respectively protrude beyond the ends of the first lower element regions adjacent to the first slit insulating portion and the second slit insulating portion.

[0022] In the structure according to this aspect, the third slit insulating portion and the fourth slit insulating portion are provided in plurality and are defined on one side of their respective second lower element regions, and the third slit insulating portion and the fourth slit insulating portion may not respectively protrude beyond the ends of the second lower element regions adjacent to the third slit insulating portion and the fourth slit insulating portion.

[0023] The slit insulating portion according to an embodiment of the present disclosure can change the path of the current applied through the input terminal so that the current applied to each semiconductor element can maintain a uniform density.

[0024] The slit insulating portion according to an embodiment of the present disclosure prevents the current from being directly transmitted to the semiconductor element adjacent to the input terminal, and thus enables the current applied to the semiconductor element not adjacent to the input terminal and the semiconductor element adjacent to the input terminal to have the same density. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a view showing a power module according to an embodiment of the present disclosure;

[0026] Figure 2 is a view showing a first region of a substrate according to an embodiment of the present disclosure;

[0027] Figure 3 is along Figure 2 a cross-sectional view taken along line A-A' in

[0028] Figure 4 is a view showing a second region of a substrate according to an embodiment of the present disclosure; and

[0029] Figure 5 is along Figure 4 a cross-sectional view taken along line B-B' in DETAILED DESCRIPTION

[0030] According to the embodiments of the accompanying drawings and the following detailed description, the advantages and features of the present disclosure and the methods for achieving these advantages and features should be apparent. However, the present disclosure is not limited to the embodiments disclosed below, and various different embodiments can be implemented. These embodiments are provided to fully disclose the present disclosure and enable those of ordinary skill in the art to which the present disclosure pertains to fully understand the scope of the present disclosure. The present disclosure is only defined by the scope of the claims. Throughout the specification, the same reference numerals denote the same or equivalent components.

[0031] As used throughout the specification, terms such as "section", "unit", "module", etc. refer to components that perform at least one function or operation, and can be implemented in hardware, software, or a combination of hardware and software. When a component, device, element, etc. of the present disclosure is described as having a purpose or performing an operation, function, etc., the component, device, or element should be regarded herein as "configured to" achieve the purpose or perform the operation or function. In addition, the controller described herein may include a processor programmed to perform the operations, functions, calculations, etc.

[0032] In addition, in order to distinguish between components having the same name, terms such as "first", "second", etc. are used throughout the specification. In the following description, the order is not limited thereto.

[0033] The present disclosure is described in detail in an illustrative manner. In addition, the above description is provided for embodiments of the present disclosure, and various different combinations and various modifications can be made to the present disclosure in various environments. Modifications or changes can be made to the present disclosure within the scope of the concept of the examples or embodiments disclosed herein, the scope of equivalent forms of the described disclosure, and / or the scope of the technology or knowledge in the art. The described embodiments are the optimal states for implementing the technical idea of the present disclosure. The present disclosure can be variously deformed according to the needs of specific application fields and uses. Therefore, the above detailed description related to the present disclosure is not intended to impose any limitation on the disclosed embodiments. In addition, the claims should also be construed to cover other embodiments.

[0034] Figure 1 is a diagram showing a power module according to an embodiment of the present disclosure.

[0035] Refer to Figure 1, the power module 1 includes a first switching unit SW1 and a second switching unit SW2. The first switching unit SW1 includes a plurality of constituent elements mounted on the first region of the substrate 100, and the second switching unit SW2 includes a plurality of constituent elements mounted on the second region of the substrate 100. The first switching unit SW1 and the second switching unit SW2 are electrically connected to each other. The first switching unit SW1 is a high-side switching unit and includes high-side semiconductor elements 200a, 200b, 200c, and 200d, a first input terminal 410, and an output terminal 450. The second switching unit SW2 is a low-side switching unit and may include low-side semiconductor elements 300a, 300b, 300c, and 300d, a second input terminal 510, and an alternating current terminal 430. For example, the semiconductor elements 200a, 200b, 200c, 200d, 300a, 300b, 300c, and 300d are metal-oxide semiconductor field effect transistors (MOSFETs) made of one of silicon carbide (SiC), silicon (Si), and gallium nitride (GaN). The current converted by the high-side semiconductor elements 200a, 200b, 200c, and 200d is applied to the second input terminal 510, and the current applied through the second input terminal 510 is applied to the low-side semiconductor elements 300a, 300b, 300c, and 300d and the alternating current terminal 430. The current converted by the low-side semiconductor elements 300a, 300b, 300c, and 300d is applied to the connection terminal 530. The current applied to the connection terminal 530 is output through the output terminal 450 electrically connected to the connection terminal 530. The second input terminal 510 serves as a connection terminal connecting the first switching unit SW1 and the second switching unit SW2 on the substrate 100. The second input terminal 510 also serves as an input terminal for applying current to the low-side semiconductor elements 300a, 300b, 300c, and 300d of the second switching unit SW2. The power module 1 according to an embodiment of the present disclosure is configured in a two-in-one structure in which the first switching unit SW1 and the second switching unit SW2 are formed on one substrate 100. Accordingly, there are two alternating current terminals 430.

[0036] The substrate 100 includes a conductive layer. A plurality of substrates 100 may be provided on the power module 1. For example, the power module 1 may include an upper substrate and a lower substrate. The upper substrate and the lower substrate respectively transmit the applied current to the semiconductor elements 200a, 200b, 200c, and 200d and the semiconductor elements 300a, 300b, 300c, and 300d, and are electrically connected to the plurality of terminals 410, 430, 450, 510, and 530. In other words, the substrate 100 provides an area for mounting the semiconductor elements 200a, 200b, 200c, 200d, 300a, 300b, 300c, and 300d and the plurality of terminals 410, 430, 450, 510, and 530, and electrically connects the semiconductor elements 200a, 200b, 200c, 200d, 300a, 300b, 300c, and 300d to the plurality of terminals 410, 430, 450, 510, and 530.

[0037] The substrate 100 is divided into a first region and a second region. The first region and the second region of the substrate 100 are electrically insulated from each other. The high-side semiconductor elements 200a, 200b, 200c, and 200d, the first input terminal 410, and the output terminal 450 are provided on the first region of the substrate 100. The low-side semiconductor elements 300a, 300b, 300c, and 300b, the second input terminal 510, and the alternating current terminal 430 are provided on the second region of the substrate 100. In order to electrically connect the first region and the second region of the substrate 100, the second input terminal 510 and the connection terminal 530 are provided on the substrate 100.

[0038] The high-side semiconductor elements 200a, 200b, 200c, and 200d are arranged counterclockwise. The high-side semiconductor elements 200a, 200b, 200c, and 200d include a first high-side semiconductor element 200a, a second high-side semiconductor element 200b, a third high-side semiconductor element 200c, and a fourth high-side semiconductor element 200d. The first high-side semiconductor element 200a and the fourth high-side semiconductor element 200d are arranged adjacent to the first input terminal 410. Specifically, the first high-side semiconductor element 200a is arranged adjacent to the first input terminal 410, and the fourth high-side semiconductor element 200d is arranged adjacent to the output terminal 450. However, the first high-side semiconductor element 200a and the fourth high-side semiconductor element 200d are electrically insulated from the output terminal 450 by a pattern formed on the substrate 100.

[0039] The slit insulating parts 120 and 140 are defined on the first region of the substrate 100. The slit insulating parts 120 and 140 refer to the spaces excluding the conductive layers constituting the substrate 100. The slit insulating parts 120 and 140 prevent the current applied through the first input terminal 410 from concentrating on the first high-side semiconductor element 200a and the fourth high-side semiconductor element 200d. Specifically, the slit insulating parts 120 and 140 are respectively defined between the first input terminal 410 and the first high-side semiconductor element 200a and between the first input terminal 410 and the fourth high-side semiconductor element 200d, and guide the current applied through the first input terminal 410 to be applied to the high-side semiconductor elements 200a, 200b, 200c, and 200d after being transmitted to the space between the high-side semiconductor elements 200a, 200b, 200c, and 200d. In other words, the slit insulating parts 120 and 140 change the path of the current flow to prevent the current applied through the first input terminal 410 from being directly transmitted to the first high-side semiconductor element 200a and the fourth high-side semiconductor element 200d.

[0040] The slit insulating parts 120 and 140 are defined on the sides of the high-side semiconductor elements 200a and 200d adjacent to the first input terminal 410 among the high-side semiconductor elements 200a, 200b, 200c, and 200d. Specifically, the slit insulating parts 120 and 140 include a first slit insulating part 120 defined on the side of the substrate 100 facing the first high-side semiconductor element 200a and a second slit insulating part 140 defined on the side of the substrate 100 facing the fourth high-side semiconductor element 200d. The first slit insulating part 120 and the second slit insulating part 140 extend in the direction from the side of the substrate 100 where the first input terminal 410 is provided toward the other side of the substrate 100 opposite to this side. In other words, the first slit insulating part 120 extends in the direction from the first high-side semiconductor element 200a toward the second high-side semiconductor element 200b, and the second slit insulating part 140 extends in the direction from the fourth high-side semiconductor element 200d toward the third high-side semiconductor element 200c. The first slit insulating part 120 extends in the direction from one side of the substrate 100 toward the other side of the substrate 100, but does not protrude beyond the end of the first high-side semiconductor element 200a. The second slit insulating part 140 extends in the direction from one side of the substrate 100 toward the other side of the substrate 100, but does not protrude beyond the end of the fourth high-side semiconductor element 200d. The first slit insulating part 120 extends closer to the other side than the second slit insulating part 140. The first slit insulating part 120 and the second slit insulating part 140 are defined in the space between the first high-side semiconductor element 200a and the fourth high-side semiconductor element 200d.

[0041] The low-side semiconductor elements 300a, 300b, 300c, and 300d are arranged counterclockwise. The low-side semiconductor elements 300a, 300b, 300c, and 300d include a first low-side semiconductor element 300a, a second low-side semiconductor element 300b, a third low-side semiconductor element 300c, and a fourth low-side semiconductor element 300d. The first low-side semiconductor element 300a and the fourth low-side semiconductor element 300d are arranged adjacent to the second input terminal 510. The first low-side semiconductor element 300a and the fourth low-side semiconductor element 300d are electrically insulated from the output terminal 450 by a pattern formed on the substrate 100.

[0042] The slit insulating portions 160 and 180 are defined in the second region of the substrate 100. The slit insulating portions 160 and 180 refer to the spaces excluding the conductive layers constituting the substrate 100. The slit insulating portions 160 and 180 prevent the current applied through the second input terminal 510 from concentrating on the first low-side semiconductor element 300a and the fourth low-side semiconductor element 300d, respectively. Specifically, the slit insulating portions 160 and 180 are defined between the second input terminal 510 and the first low-side semiconductor element 300a and between the second input terminal 510 and the fourth low-side semiconductor element 300d, respectively, and guide the current applied through the second input terminal 510 to be applied to the low-side semiconductor elements 300a, 300b, 300c, and 300d after being transmitted to the space between the low-side semiconductor elements 300a, 300b, 300c, and 300d. In other words, the slit insulating portions 160 and 180 change the path of the current flow to prevent the current applied through the second input terminal 510 from being directly transmitted to the first low-side semiconductor element 300a and the fourth low-side semiconductor element 300d.

[0043] The slit insulating portions 160 and 180 are defined on one side of the low-side semiconductor elements 300a and 300d among the low-side semiconductor elements 300a, 300b, 300c, and 300d adjacent to the second input terminal 510. Specifically, the slit insulating portions 160 and 180 include a third slit insulating portion 160 defined on one side of the substrate 100 facing the first low-side semiconductor element 300a and a fourth slit insulating portion 180 defined on one side of the substrate 100 facing the fourth low-side semiconductor element 300d. The third slit insulating portion 160 and the fourth slit insulating portion 180 extend in a direction from the side of the substrate 100 where the second input terminal 510 is provided toward the other side of the substrate 100 opposite to this side. In other words, the third slit insulating portion 160 extends in a direction from the first low-side semiconductor element 300a toward the second low-side semiconductor element 300b, and the fourth slit insulating portion 180 extends in a direction from the fourth low-side semiconductor element 300b toward the third low-side semiconductor element 300c. The third slit insulating portion 160 extends in a direction from one side of the substrate 100 toward the other side of the substrate 100, but does not protrude beyond the end of the first low-side semiconductor element 300a. The fourth slit insulating portion 180 extends in a direction from one side of the substrate 100 toward the other side of the substrate 100, but does not protrude beyond the end of the fourth low-side semiconductor element 300d. The third slit insulating portion 160 extends closer to the other side than the fourth slit insulating portion 180. The third slit insulating portion 160 and the fourth slit insulating portion 180 are defined in the space between the first low-side semiconductor element 300a and the fourth low-side semiconductor element 300d.

[0044] The frame portion 480 includes a plurality of frame terminals and is connected to an external controller (not shown) and the semiconductor elements 200a, 200b, 200c, 200d, 300a, 300b, 300c, and 300d through at least one frame terminal. The frame portion 480 transmits the control signals of the external controller to the semiconductor elements 200a, 200b, 200c, 200d, 300a, 300b, 300c, and 300d. For example, the frame portion 480 is electrically connected to the substrate 100 through a wire (not shown).

[0045] According to an embodiment of the present disclosure, the slit insulating parts 120 and 140 are used to uniformly transmit the current applied through the first input terminal 410 to the semiconductor elements 200a, 200b, 200c, and 200d, and the slit insulating parts 160 and 180 are used to uniformly transmit the current applied through the second input terminal 510 to the semiconductor elements 300a, 300b, 300c, and 300d. The slit insulating parts 120 and 140 prevent the current from directly transmitting to the semiconductor elements 200a, 200b, 200c, and 200d adjacent to the first input terminal 410. The slit insulating parts 160 and 180 prevent the current from directly transmitting to the semiconductor elements 300a, 300b, 300c, and 300d adjacent to the second input terminal 510. In other words, the slit insulating parts 120 and 140 change the path of the current applied through the first input terminal 410 to uniformly maintain the current transmitted to the semiconductor elements 200a, 200b, 200c, and 200d, and the slit insulating parts 160 and 180 change the path of the current applied through the second input terminal 510 to uniformly maintain the current transmitted to the semiconductor elements 300a, 300b, 300c, and 300d.

[0046] Figure 2 is a view showing a first region of a substrate according to an embodiment of the present disclosure.

[0047] Referring to Figure 1 and Figure 2 and, on the first region 100a of the substrate 100 on which the first switching unit SW1 is formed, element regions 205a, 205b, 205c, and 205d, a first central region 50a, a first input terminal region 415, an output terminal region 455, and slit insulating parts 120c, 120a, 140c, and 140a are defined.

[0048] The element regions 205a, 205b, 205c, and 205d refer to regions where the high-side semiconductor elements 200a, 200b, 200c, and 200d are provided. In other words, the first high-side semiconductor element 200a is provided on the first element region 205a, the second high-side semiconductor element 200b is provided on the second element region 205b, the third high-side semiconductor element 200c is provided on the third element region 205c, and the fourth high-side semiconductor element 200d is provided on the fourth element region 205d. The first element region 205a, the second element region 205b, the third element region 205c, and the fourth element region 205d are defined counterclockwise. Specifically, the first element region 205a and the fourth element region 205d are adjacent to the first input terminal region 415 where the first input terminal 410 is provided.

[0049] The first central region 50a refers to the space between the element regions 205a, 205b, 205c, and 205d or the space between the high-side semiconductor elements 200a, 200b, 200c, and 200d. Specifically, the first central region 50a refers to the region that covers a predetermined range based on the first center point 10, and the first center point 10 is located at a position equidistant from the element regions 205a, 205b, 205c, and 205d or the high-side semiconductor elements 200a, 200b, 200c, and 200d. The distance between the first center point 10 and the first element region 205a or the distance between the first center point 10 and the first high-side semiconductor element 200a is defined as the first distance d1. The distance between the first center point 10 and the second element region 205b or the distance between the first center point 10 and the second high-side semiconductor element 200b is defined as the second distance d2. The distance between the first center point 10 and the third element region 205c or the distance between the first center point 10 and the third high-side semiconductor element 200c is defined as the third distance d3. The distance between the first center point 10 and the fourth element region 205d or the distance between the first center point 10 and the fourth high-side semiconductor element 200d is defined as the fourth distance d4. In this embodiment, the first distance d1, the second distance d2, the third distance d3, and the fourth distance d4 are the same. The current applied through the first input terminal region 415 can be applied to the element regions 205a, 205b, 205c, and 205d through the first central region 50a. Therefore, the lengths of the paths through which the current transmitted to the first central region 50a is transmitted to each of the high-side semiconductor elements 200a, 200b, 200c, and 200d are the same. Therefore, the current transmitted to each of the high-side semiconductor elements 200a, 200b, 200c, and 200d has a uniform density.

[0050] The slit insulating portions 120c, 120a, 140c, and 140a guide the current applied through the first input terminal 410 to flow into the first central region 50a. In other words, the slit insulating portions 120c, 120a, 140c, and 140a change the path of the current flow. The slit insulating portions 120c, 120a, 140c, and 140a are defined as at least one and are defined on one side of the element regions 205a and 205d adjacent to the first input terminal region 415 in the element regions 205a, 205b, 205c, and 205d.

[0051] The slit insulating portions 120c, 120a, 140c, and 140a include: first slit insulating portions 120c and 120a, which are defined between the first element region 205a and the first input terminal region 415; and second slit insulating portions 140c and 140a, which are defined between the fourth element region 205d and the first input terminal region 415. The first slit insulating portions 120c and 120a include: a first main slit insulating portion 120c, which is defined between the first input terminal region 415 and the first element region 205a; and a first sub-slit insulating portion 120a, which is defined on one side of the first element region 205a. The second slit insulating portions 140c and 140a include: a second main slit insulating portion 140c, which is defined between the first input terminal region 415 and the fourth element region 205d; and a second sub-slit insulating portion 140a, which is defined on one side of the fourth element region 205d. The first sub-slit insulating portion 120a extends in a direction from the first element region 205a toward the second element region 205b, and the second sub-slit insulating portion 140a extends in a direction from the fourth element region 205d toward the third element region 205c. The first sub-slit insulating portion 120a does not protrude beyond the end of the first element region 205a in the direction from the first element region 205a toward the second element region 205b. In other words, in the case where the first sub-slit insulating portion 120a protrudes beyond the end of the first element region 205a, it will prevent current from flowing from the first central region 50a into the first high-side semiconductor element 200a. Therefore, the first sub-slit insulating portion 120a does not protrude beyond the end of the first element region 205a. The second sub-slit insulating portion 140a does not protrude beyond the end of the fourth element region 205d in the direction from the fourth element region 205d toward the third element region 205c. In other words, in the case where the second sub-slit insulating portion 140a protrudes beyond the end of the fourth element region 205d, it will prevent current from flowing from the first central region 50a into the fourth high-side semiconductor element 200d. Therefore, the second sub-slit insulating portion 140a does not protrude beyond the end of the fourth element region 205d.

[0052] On the substrate 100, a gate signal electrode portion 101 and a source signal electrode portion 103 are defined. The gate signal electrode portion 101 transmits a gate signal to the high-side semiconductor elements 200a, 200b, 200c, and 200d, and the source signal electrode portion 103 transmits a source signal to the high-side semiconductor elements 200a, 200b, 200c, and 200d. The gate signal electrode portion 101 and the source signal electrode portion 103 are electrically connected to the frame portion 480. The gate signal electrode portion 101 and the source signal electrode portion 103 are not directly connected to the high-side semiconductor elements 200a, 200b, 200c, and 200d due to the first electrode insulating portion 115 and the second electrode insulating portion 117, respectively. Specifically, the source signal electrode portion 103 is disposed between the second electrode insulating portion 117 and the edge of the substrate 100, and the gate signal electrode portion 101 is disposed between the first electrode insulating portion 115 and the second electrode insulating portion 117. According to an embodiment of the present disclosure, one end portion of the first electrode insulating portion 115 and one end portion of the second electrode insulating portion 117 are connected to the first main slit insulating portion 120c. One end portion of the first electrode insulating portion 115 and one end portion of the second electrode insulating portion 117 refer to the portions adjacent to the first high-side semiconductor element 200a. The first electrode insulating portion 115 and the second electrode insulating portion 117 are connected to each other at the portion adjacent to the fourth high-side semiconductor element 200d.

[0053] The gate signal electrode portion 101 and the source signal electrode portion 103 are connected to the high-side semiconductor elements 200a, 200b, 200c, and 200d through high-side wires 510a, 510b, 510c, and 510d and high-side wires 530a, 530b, 530c, and 530d, respectively. The high-side wires 510a, 510b, 510c, 510d, 530a, 530b, 530c, and 530d include first high-side wires 510a, 510b, 510c, and 510d that connect the high-side semiconductor elements 200a, 200b, 200c, and 200d to the gate electrodes, respectively, and second high-side wires 530a, 530b, 530c, and 530d that connect the high-side semiconductor elements 200a, 200b, 200c, and 200d to the source electrodes, respectively. In other words, the high-side semiconductor elements 200a, 200b, 200c, and 200d are not directly connected to the substrate 100 due to the first electrode insulating portion 115 and the second electrode insulating portion 117. However, the control signal applied through the frame portion 480 can be applied to the high-side semiconductor elements 200a, 200b, 200c, and 200d through the high-side wires 510a, 510b, 510c, 510d, 530a, 530b, 530c, and 530d.

[0054] According to an embodiment of the present disclosure, the slit insulating portions 120c, 120a, 140c, and 140a guide the current applied through the first input terminal 410 to flow into the first central region 50a. The slit insulating portions 120c and 120a and the slit insulating portions 140c and 140a respectively prevent the current applied through the first input terminal 410 from being directly transmitted to the first high-side element region 205a and the fourth high-side element region 205d which are the first lower element regions. Therefore, the current flowing through the slit insulating portions 120c, 120a, 140c, and 140a flows into the first central region 50a, and is applied from the first central region 50a to the element regions 205a, 205b, 205c, and 205d.

[0055] Figure 3 is a cross-sectional view taken along Figure 2 line A-A' in

[0056] Referring to Figures 1 to 3 , the substrate 100a includes a lower substrate 104 and an upper substrate 102. The lower substrate 104 includes an upper conductive layer 104a, an insulating layer 104b, and a lower conductive layer 104c. The upper substrate 102 includes an upper conductive layer 102c, an insulating layer 102b, and a lower conductive layer 102a. According to an embodiment of the present disclosure, the high-side semiconductor elements 200a, 200b, 200c, and 200d, the first input terminal 410, and the output terminal 450 are described as being disposed on the lower substrate 104. Therefore, the current applied through the first input terminal 410 flows into the high-side semiconductor elements 200a, 200b, 200c, and 200d through the upper conductive layer 104a of the lower substrate 104. The current converted by the high-side semiconductor elements 200a and 200b and the high-side semiconductor elements 200c and 200d respectively flows into the lower conductive layer 102a of the upper substrate 102 through the isolators 210a and 210d. The current is transmitted to the second input terminal 510 of the second switching unit SW2 through the lower conductive layer 102a on the upper substrate 102.

[0057] The slit insulating portions 120a, 120b, 140a, and 140b are formed in one or both of the lower substrate 104 and the upper substrate 102. In one embodiment, the slit insulating portions 120a, 120b, 140a, and 140b are formed in the lower substrate 104 which is the substrate for mounting the high-side semiconductor elements 200a, 200b, 200c, and 200d. In another embodiment, the slit insulating portions 120a, 120b, 140a, and 140b may also be formed in the upper substrate 102.

[0058] The slit insulating portions 120a and 140a refer to the portions where a part of the upper conductive layer 104a is removed from the lower substrate 104 respectively. The slit insulating portions 120b and 140b refer to the portions where a part of the lower conductive layer 102a is removed from the upper substrate 102 respectively. By removing a part of the upper conductive layer 104a and the lower conductive layer 102a respectively, patterns are formed in the upper conductive layer 104a of the lower substrate 104 and the lower conductive layer 102a of the upper substrate 102. The path of the current is determined by the patterns. Therefore, by using the slit insulating portions 120a, 120b, 140a and 140b, the current applied through the first input terminal 410 flows into the first central region 50a.

[0059] For the sake of brief description, a structure in which semiconductor elements are disposed between two substrates, i.e., substrates 104 and 102, is adopted. However, the slit insulating portions 120a, 120b, 140a and 140b can be applied to a double-sided power module in which semiconductor elements are disposed on the upper surface and the lower surface of a single substrate respectively. Specifically, the slit insulating portions 120a, 120b, 140a and 140b can be applied to a double-sided power module in which semiconductor elements are also disposed on the lower conductive layer 104c of the lower substrate 104.

[0060] Figure 4 It is a view showing a second region of a substrate according to an embodiment of the present disclosure.

[0061] Referring to Figure 1 and Figure 4 In, element regions 305a, 305b, 305c and 305d, a second central region 50b, a second input terminal region 515, an alternating current terminal region 435 and slit insulating portions 160c, 160a, 180c and 180a are defined on a second region 100b of a substrate 100 to which a second switching unit SW2 is applied.

[0062] The element regions 305a, 305b, 305c and 305d refer to the regions where low-side semiconductor elements 300a, 300b, 300c and 300d are disposed respectively. In other words, the first low-side semiconductor element 300a is disposed on the first element region 305a, the second low-side semiconductor element 300b is disposed on the second element region 305b, the third low-side semiconductor element 300c is disposed on the third element region 305c, and the fourth low-side semiconductor element 300d is disposed on the fourth element region 305d. The first element region 305a, the second element region 305b, the third element region 305c and the fourth element region 305d are defined counterclockwise. Specifically, the first element region 305a and the fourth element region 305d are adjacent to the second input terminal region 515 where the second input terminal 510 is disposed.

[0063] The second central region 50b refers to the space between the component regions 305a, 305b, 305c, and 305d or the space between the low-side semiconductor components 300a, 300b, 300c, and 300d. Specifically, the second central region 50b refers to the region that covers a predetermined range with respect to the second center point 20, which is located at an equal distance from the component regions 305a, 305b, 305c, and 305d or the low-side semiconductor components 300a, 300b, 300c, and 300d. The distance between the second center point 20 and the first component region 305a or the distance between the second center point 20 and the first low-side semiconductor component 300a is defined as the fifth distance d5. The distance between the second center point 20 and the second component region 305b or the distance between the second center point 20 and the second low-side semiconductor component 300b is defined as the sixth distance d6. The distance between the second center point 20 and the third component region 305c or the distance between the second center point 20 and the third low-side semiconductor component 300c is defined as the seventh distance d7. The distance between the second center point 20 and the fourth component region 305d or the distance between the second center point 20 and the fourth low-side semiconductor component 300d is defined as the eighth distance d8. In this embodiment, the fifth distance d5, the sixth distance d6, the seventh distance d7, and the eighth distance d8 are the same. The current applied through the second input terminal region 515 can be applied to the component regions 305a, 305b, 305c, and 305d through the second central region 50b. Therefore, the lengths of the paths through which the current transmitted to the second central region 50b is transmitted to each of the low-side semiconductor components 300a, 300b, 300c, and 300d are the same. Therefore, the current transmitted to each of the low-side semiconductor components 300a, 300b, 300c, and 300d has a uniform density.

[0064] The slit insulating parts 160c, 160a, 180c, and 180a guide the current applied through the second input terminal 510 to flow into the second central region 50b. In other words, the slit insulating parts 160c, 160a, 180c, and 180a change the path of the current flow. The slit insulating parts 160c, 160a, 180c, and 180a are defined as at least one and are defined on one side of the component regions 305a and 305d adjacent to the second input terminal region 515 in the component regions 305a, 305b, 305c, and 305d.

[0065] The slit insulating portions 160c, 160a, 180c, and 180a include: third slit insulating portions 160c and 160a defined between the first element region 305a and the second input terminal region 515; and fourth slit insulating portions 180c and 180a defined between the fourth element region 305d and the second input terminal region 515. The third slit insulating portions 160c and 160a include: a third main slit insulating portion 160c defined between the second input terminal region 515 and the first element region 305a; and a third sub-slit insulating portion 160a defined on one side of the first element region 305a. The fourth slit insulating portions 180c and 180a include: a fourth main slit insulating portion 180c defined between the second input terminal region 515 and the fourth element region 305d; and a fourth sub-slit insulating portion 180a defined on one side of the fourth element region 305d. The third sub-slit insulating portion 160a extends in a direction from the first element region 305a toward the second element region 305b, and the fourth sub-slit insulating portion 180a extends in a direction from the fourth element region 305d toward the third element region 305c. The third sub-slit insulating portion 160a does not protrude beyond the end of the first element region 305a in the direction from the first element region 305a toward the second element region 305b. In other words, when the third sub-slit insulating portion 160a protrudes beyond the end of the first element region 305a, it will prevent current from flowing from the second central region 50b into the first low-side semiconductor element 300a. Therefore, the third sub-slit insulating portion 160a does not protrude beyond the end of the first element region 305a. The fourth sub-slit insulating portion 180a does not protrude beyond the end of the fourth element region 305d in the direction from the fourth element region 305d toward the third element region 305c. In other words, when the fourth sub-slit insulating portion 180a protrudes beyond the end of the fourth element region 305d, it will prevent current from flowing from the second central region 50b into the fourth low-side semiconductor element 300d. Therefore, the fourth sub-slit insulating portion 180a does not protrude beyond the end of the fourth element region 305d.

[0066] The gate signal electrode portion 105 and the source signal electrode portion 107 are defined on the substrate 100. The gate signal electrode portion 105 transmits the gate signal to the low-side semiconductor elements 300a, 300b, 300c, and 300d, and the source signal electrode portion 107 transmits the source signal to the low-side semiconductor elements 300a, 300b, 300c, and 300d. The gate signal electrode portion 105 and the source signal electrode portion 107 are electrically connected to the frame portion 480. The gate signal electrode portion 105 and the source signal electrode portion 107 are not directly connected to the low-side semiconductor elements 300a, 300b, 300c, and 300d due to the third electrode insulating portion 155 and the fourth electrode insulating portion 157, respectively. Specifically, the source signal electrode portion 107 is disposed between the fourth electrode insulating portion 157 and the edge of the substrate 100, and the gate signal electrode portion 105 is disposed between the third electrode insulating portion 155 and the fourth electrode insulating portion 157. According to an embodiment of the present disclosure, one end portion of the third electrode insulating portion 155 and one end portion of the fourth electrode insulating portion 157 are connected to the fourth main slit insulating portion 180c. One end portion of the third electrode insulating portion 155 and one end portion of the fourth electrode insulating portion 157 refer to the portions adjacent to the fourth low-side semiconductor element 300d. The third electrode insulating portion 155 and the fourth electrode insulating portion 157 are connected to each other at the portion adjacent to the first low-side semiconductor element 300a.

[0067] The gate signal electrode portion 105 and the source signal electrode portion 107 are connected to the low-side semiconductor elements 300a, 300b, 300c, and 300d through the low-side wires 550a, 550b, 550c, and 550d and the low-side wires 570a, 570b, 570c, and 570d, respectively. The low-side wires 550a, 550b, 550c, 550d, 570a, 570b, 570c, and 570d include the first low-side wires 550a, 550b, 550c, and 550d respectively connected to the gate electrodes of the low-side semiconductor elements 300a, 300b, 300c, and 300d and the second low-side wires 570a, 570b, 570c, and 570d respectively connected to the source electrodes of the low-side semiconductor elements 300a, 300b, 300c, and 300d. In other words, the low-side semiconductor elements 300a, 300b, 300c, and 300d are not directly connected to the substrate 100 due to the third electrode insulating portion 155 and the fourth electrode insulating portion 157. However, the control signal applied through the frame portion 480 can be applied to the low-side semiconductor elements 300a, 300b, 300c, and 300d through the low-side wires 550a, 550b, 550c, 550d, 570a, 570b, 570c, and 570d.

[0068] According to an embodiment of the present disclosure, the slit insulating portions 160c, 160a, 180c, and 180a guide the current applied through the second input terminal 510 to flow into the second central region 50b. The slit insulating portions 160c and 160a and the slit insulating portions 180c and 180a respectively prevent the current applied through the second input terminal 510 from being directly transmitted to the first low-side element region 305a and the fourth low-side element region 305d, which are the second lower element regions. Therefore, the current flowing through the slit insulating portions 160c, 160a, 180c, and 180a flows into the second central region 50b and is applied from the second central region 50b to the element regions 305a, 305b, 305c, and 305d.

[0069] Figure 5 is a cross-sectional view taken along Figure 4 line B-B' in

[0070] Referring to Figure 4 and Figure 5 , the substrate 100b includes a lower substrate 104 and an upper substrate 102. The lower substrate 104 includes an upper conductive layer 104a, an insulating layer 104b, and a lower conductive layer 104c. The upper substrate 102 includes an upper conductive layer 102c, an insulating layer 102b, and a lower conductive layer 102a. According to an embodiment of the present disclosure, the low-side semiconductor elements 300a, 300b, 300c, and 300d, the second input terminal 510, and the alternating current terminal 430 are described as being disposed on the lower substrate 104. Therefore, the current applied through the second input terminal 510 can flow into the low-side semiconductor elements 300a, 300b, 300c, and 300d through the upper conductive layer 104a of the lower substrate 104. The current converted by the low-side semiconductor elements 300a, 300b, 300c, and 300d flows into the lower conductive layer 102a of the upper substrate 102 through the isolators 310a and 310d. The current is transmitted to the connection terminal 530 through the lower conductive layer 102a of the upper substrate 102.

[0071] The slit insulating portions 160a, 160b, 180a, and 180b are formed in one or both of the lower substrate 104 and the upper substrate 102. In one embodiment, the slit insulating portions 160a, 160b, 180a, and 180b are formed in the lower substrate 104, which is the substrate on which the low-side semiconductor elements 300a, 300b, 300c, and 300d are mounted. In another embodiment, the slit insulating portions 160a, 160b, 180a, and 180b can also be formed in the upper substrate 102.

[0072] The slit insulating portions 160a and 180a refer to the portions where a part of the upper conductive layer 104a is removed from the lower substrate 104. The slit insulating portions 160b and 180b refer to the portions where a part of the lower conductive layer 102a is removed from the upper substrate 102. By removing a part of the upper conductive layer 104a and the lower conductive layer 102a respectively, patterns are formed in the upper conductive layer 104a of the lower substrate 104 and the lower conductive layer 102a of the upper substrate 102. The path of the current is determined by the patterns. Therefore, the current applied through the second input terminal 510 is caused to flow into the second central region 50b by using the slit insulating portions 160a, 160b, 180a, and 180b.

[0073] The embodiments of the present disclosure have been described above with reference to the drawings, and it should be apparent to those of ordinary skill in the art to which the present disclosure pertains that the present disclosure can be implemented in other specific forms without modifying the technical idea and essential features of the present disclosure. Therefore, it should be understood that the above embodiments are exemplary in every aspect and not restrictive.

Claims

1. A substrate structure for a power module, wherein the substrate comprises: An element region on which a plurality of semiconductor elements are disposed; A central region that defines a space between the element regions; An input terminal region on which an input terminal for applying current to the substrate is disposed; And One or more slit insulation portions defined on one side of the element region adjacent to the input terminal region in the element region, The slit insulation portion extends toward the central region so that the current applied through the input terminal region flows into the central region.

2. The structure according to claim 1, Wherein, The element region sequentially includes a first element region, a second element region, a third element region, and a fourth element region in the counterclockwise direction, The first element region and the fourth element region are adjacent to the input terminal region, and The slit insulation portion includes a first slit insulation portion defined between the first element region and the input terminal region and a second slit insulation portion defined between the fourth element region and the input terminal region.

3. The structure according to claim 2, Wherein, The first slit insulation portion and the second slit insulation portion extend from one side of the substrate that defines the input terminal region toward the other side of the substrate opposite to the one side of the substrate.

4. The structure according to claim 3, Wherein, The first slit insulation portion extends in a manner closer to the other side of the substrate than the second slit insulation portion.

5. The structure according to claim 2, Wherein, The first slit insulation portion and the second slit insulation portion are disposed between the first element region and the fourth element region.

6. The structure according to claim 2, Wherein, The first slit insulation portion includes: a first main slit insulation portion defined between the input terminal region and the first element region; and a first sub-slit insulation portion defined on one side of the first element region, and The second slit insulation portion includes: a second main slit insulation portion defined between the input terminal region and the fourth element region; and a second sub-slit insulation portion defined on one side of the fourth element region.

7. The structure according to claim 6, Wherein, The first sub-slit insulation portion extends in the direction from the first element region toward the second element region, and The second sub-slit insulation portion extends in the direction from the fourth element region toward the third element region.

8. The structure according to claim 7, Wherein, The first sub-slit insulation portion does not protrude beyond the end of the first element region in the direction from the first element region toward the second element region, and The second sub-slit insulation portion does not protrude beyond the end of the fourth element region in the direction from the fourth element region toward the third element region.

9. The structure according to claim 1, Wherein, The central region refers to a region that covers a predetermined range based on a center point at an equal distance from the element region, and The current applied through the input terminal region is applied to the element region through the central region.

10. The structure according to claim 1, wherein, the substrate includes: a source signal electrode portion for transmitting a source signal to the semiconductor element; and a gate signal electrode portion for transmitting a gate signal to the semiconductor element, wherein the source signal electrode portion and the gate signal electrode portion are connected to the semiconductor element through a wire.

11. The structure according to claim 10, further including: a first electrode insulating portion and a second electrode insulating portion, wherein the source signal electrode portion is disposed between the second electrode insulating portion and the edge of the substrate, and the gate signal electrode portion is disposed between the first electrode insulating portion and the second electrode insulating portion.

12. A substrate structure for a power module, the substrate having a first region and a second region, wherein each of the first region and the second region includes: an element region on which a plurality of semiconductor elements are disposed; a central region defining a space between the element regions; an input terminal region on which an input terminal for applying current to the substrate is disposed; and one or more slit insulating portions defined on one side of the element region adjacent to the input terminal region in the element region, wherein the slit insulating portion extends toward the central region to allow the current applied through the input terminal region to flow into the central region.

13. The structure according to claim 12, wherein, the input terminal region includes: a first input terminal region disposed on the first region, to which current is applied from the outside; and a second input terminal region for applying the current transmitted from each of the semiconductor elements disposed on the first region to the second region.

14. The structure according to claim 13, wherein, the element region defined on the first region adjacent to the first input terminal region is defined as a first lower element region, the element region defined on the second region adjacent to the second input terminal region is defined as a second lower element region, the slit insulating portion is disposed on one side of each of the first lower element regions and on one side of each of the second lower element regions, and the slit insulating portion is disposed between the first lower element regions and between the second lower element regions.

15. The structure according to claim 14, wherein, the slit insulating portion includes: a first slit insulating portion and a second slit insulating portion extending from one side of the first region defining the first input terminal region toward the other side of the first region opposite to the one side of the first region; and a third slit insulating portion and a fourth slit insulating portion extending from one side of the second region defining the second input terminal region toward the other side of the second region opposite to the one side of the second region.

16. The structure according to claim 15, wherein, The first slit insulating part and the second slit insulating part are defined at one side of their respective first lower element regions, and the first slit insulating part and the second slit insulating part do not respectively protrude beyond the ends of the first lower element regions adjacent to the first slit insulating part and the second slit insulating part.

17. The structure according to claim 15, wherein, the third slit insulating part and the fourth slit insulating part are provided in plural and are defined at one side of their respective second lower element regions, and the third slit insulating part and the fourth slit insulating part do not respectively protrude beyond the ends of the second lower element regions adjacent to the third slit insulating part and the fourth slit insulating part.

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