Input circuit of the inter-IC system

Abstract

The present application relates to an input circuit for an inter-integrated circuit system. An inter-integrated circuit input circuit includes a pull-up current circuit and an input circuit (400). The input circuit (400) includes an output inverter (407), an input inverter (405) and a pull-up circuit (411). The pull-up circuit (411) is coupled to an input (412G) of the input inverter (405) and includes a pull-up transistor (404) and a cascode transistor (402). The pull-up transistor (404) is coupled to the input (412G) of the input inverter (405). The cascode transistor (402) is coupled to the pull-up current circuit and the pull-up transistor (404) and is configured to isolate the pull-up transistor (404) from the capacitance of a conductor coupled to the pull-up current circuit and the input circuit (400).

Description

Technical Field

[0001] The present disclosure relates to an integrated circuit, and more particularly to an input circuit for an inter-integrated circuit system. Background Art

[0002] Various serial communication buses have been developed to reduce the cost and complexity associated with communications using parallel buses. 2 C) bus is such a serial bus. 2 The C-bus uses two conductors (assuming a common ground) to provide communication between electronic devices (e.g., communication between a microcontroller and one or more peripheral devices). The first conductor connects the clock output terminal of the master device to the clock input terminal of one or more slave devices. The second conductor connects the data input terminal / data output terminal of the interconnected devices. Summary of the invention

[0003] This article discloses an integrated circuit (I 2 C) Input circuitry that reduces timing variations caused by parasitic capacitance on the pull-up current routing. In one example, I 2 The C input circuit includes a pull-up current circuit and an input circuit. The input circuit includes a signal input terminal, a signal output terminal, an output transistor, a first transistor, a second transistor, and a cascode transistor. The output transistor includes a first terminal coupled to the signal output terminal and a second terminal coupled to a power rail. The first transistor includes a first terminal coupled to the input terminal and a second terminal coupled to a first bias voltage source. The second transistor includes a first terminal coupled to a third terminal of the first transistor and a second terminal coupled to the third terminal of the output transistor. The cascode transistor includes a first terminal coupled to the third terminal of the second transistor, a second terminal coupled to the second bias voltage source, and a third terminal coupled to the output terminal of the pull-up current circuit.

[0004] In another example, I 2 The C input circuit includes a pull-up current circuit and an input circuit. The input circuit includes an output inverter, an input inverter, and a pull-up circuit. The pull-up circuit is coupled to the input of the input inverter and includes a pull-up transistor and a cascode transistor. The pull-up transistor is coupled to the input of the input inverter. The cascode transistor is coupled to the pull-up current circuit and the pull-up transistor and is configured to isolate the pull-up transistor from the capacitance of a conductor coupled to the pull-up current circuit and the input circuit.

[0005] In another example, an integrated circuit includes a pull-up current circuit, a first input circuit, and a second input circuit. The first input circuit includes a pull-up input terminal coupled to a first output terminal of the pull-up current circuit. The second input circuit includes a pull-up input terminal, a signal input terminal, a signal output terminal, an output transistor, a first transistor, a second transistor, and a cascode transistor. The pull-up input terminal is coupled to the second output terminal of the pull-up current circuit. The output transistor includes a first terminal coupled to the signal output terminal and a second terminal coupled to a power rail. The first transistor includes a first terminal coupled to the input terminal and a second terminal coupled to a first bias voltage source. The second transistor includes a first terminal coupled to a third terminal of the first transistor and a second terminal coupled to a third terminal of the output transistor. The cascode transistor includes a first terminal coupled to a third terminal of the second transistor, a second terminal coupled to a second bias voltage source, and a third terminal coupled to an output terminal of the pull-up current circuit. The first input circuit is disposed at a first distance from the pull-up circuit, and the second input circuit is disposed at a second distance from the pull-up circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] For a detailed description of various embodiments, reference will now be made to the accompanying drawings, in which:

[0007] Figure 1 An example of an integrated circuit (I 2 C) Block diagram of the input circuit;

[0008] Figure 2 shows an integrated circuit according to the present description. 2 Example arrangement of C input circuit;

[0009] Figure 3 Example I according to the present description is shown 2 C pull-up current circuit;

[0010] Figure 4 Example I according to the present description is shown 2 C input circuit; and

[0011] Figure 5 The use of I according to the present description is shown 2 C input circuit receives the example signal. DETAILED DESCRIPTION

[0012] Certain terms are used throughout the specification and claims to refer to specific system components. As will be appreciated by those skilled in the art, different parties may refer to components by different names. This document is not intended to distinguish between components that have different names but the same function. In the present disclosure and claims, the terms "include" and "comprise" are used in an open manner and should therefore be interpreted as meaning "including, but not limited to..." In addition, the term "coupled" means an indirect or direct connection. Thus, if a first device is coupled to a second device, the connection may be achieved by a direct connection or by an indirect connection via other devices and connectors. The expression "based on" means "based at least in part on". Thus, if X is based on Y, then X may be a function of Y and any number of other factors.

[0013] The integrated circuit (I 2 C) The input circuit uses a pull-up current circuit to provide a pull-up current to multiple input circuits. In some integrated circuits, the conductors connecting each input circuit to the pull-up current circuit are very long, and the long conductors accumulate large parasitic capacitance. The parasitic capacitance affects the propagation delay of the associated input circuits and, in some embodiments, causes excessive propagation delay in the input circuits.

[0014] I open here 2 The C input circuit isolates the parasitic capacitance of the conductor connecting the pull-up current circuit and the input circuit from the pull-up circuit of the input circuit. Isolation is provided by adding a cascode transistor in each input circuit. The cascode transistor passes the pull-up current to the pull-up circuit of the input circuit. The isolation provided by the cascode transistor eliminates the timing dependency associated with routing parasitic capacitance and improves the timing performance of the input circuit. The cascode transistor is not placed at the pull-up current circuit, but is placed at the input circuit or a portion of the input circuit, and in some embodiments, the cascode transistor is biased by the voltage generated by the pull-up current circuit.

[0015] Figure 1 An example integrated circuit (I 2 C) Block diagram of a portion of input circuit 100. 2 C input circuit 100 includes pull-up current circuit 102, input circuit 104, input circuit 106, and input circuit 108. Input circuit 106 and input circuit 108 are similar or identical to input circuit 104. 2 C input circuit 100 is shown as including input circuit 104, input circuit 106, and input circuit 108, but I 2An embodiment of C input circuit 100 includes one or more input circuits. Pull-up current circuit 102 provides a pull-up current to each of input circuit 104, input circuit 106, and input circuit 108. Pull-up current circuit 102 includes an output terminal 102A coupled to pull-up input terminal 104E of input circuit 104 via conductor 110. Similarly, pull-up current circuit 102 includes an output terminal 102D coupled to pull-up input terminal 106E of input circuit 106 via conductor 112, and includes an output terminal 102E coupled to pull-up input terminal 108E of input circuit 108 via conductor 114. Each of input circuit 104, input circuit 106, and input circuit 108 includes a cascode transistor that isolates the pull-up circuit from parasitic capacitance of conductors 110, conductors 112, and conductors 114.

[0016] The pull-up current circuit 102 also generates bias voltages for the operation of the input circuits 104, 106, and 108. The pull-up current circuit 102 includes a bias voltage source 120 coupled to the output terminal 102B, which is in turn coupled to the input terminal 104C of the input circuit 104, for providing a bias voltage 116 to the input circuit 104. The pull-up current circuit 102 also includes a bias voltage source 122 coupled to the output terminal 102C, which is in turn coupled to the input terminal 104D of the input circuit 104, for providing a bias voltage 118 to the input circuit 104. The bias voltage 116 and the bias voltage 118 are also provided to the input circuits 106 and 108.

[0017] The input circuit 104 includes a signal input terminal 104A for receiving an input signal (eg, a clock signal or a data signal) and a signal output terminal 104B for providing the received signal to an external circuit.

[0018] Figure 2 shows an integrated circuit 200 according to the present description. 2 1. The integrated circuit 200 includes a pull-up current circuit 102, an input circuit 104, an input circuit 106, and an input circuit 108. The input circuit 104, the input circuit 106, and the input circuit 108 are separated from the pull-up current circuit 102 by a certain distance and are coupled via conductors 110, 112, and 114, respectively. For example, the pull-up current circuit 102 is disposed on one side of the integrated circuit 200, and the input circuit 104 is disposed on the opposite side of the integrated circuit 200 and is connected to the pull-up current circuit 102 via the conductor 110 passing through the integrated circuit 200. In some embodiments of the integrated circuit 200, the input circuit 104 is disposed at a first distance from the pull-up current circuit 102, and the input circuit 106 is disposed at a second distance from the pull-up current circuit 102.

[0019] Figure 3 Example I according to the present description is shown 2 C pull-up current circuit 300. I 2 The pull-up current circuit 300 is an implementation of the pull-up current circuit 102. 2 C pull-up current circuit 300 includes a pull-up current circuit 302 and a bias voltage circuit 304. Pull-up current circuit 302 includes a current mirror circuit formed by a diode-connected transistor 306 and output transistors 308, 310, and 312. Each of output transistors 308, 310, and 312 provides a pull-up current used by one of input circuits 104, 106, or 108. For example, transistor 308 is coupled to output terminal 102A, transistor 310 is coupled to output terminal 102D, and transistor 312 is coupled to output terminal 102E.

[0020] Bias voltage circuit 304 is an implementation of bias voltage source 120 and generates bias voltage 116 for bias circuits of input circuits 104, 106, and 108. 2 In some embodiments of the C pull-up current circuit 300, the bias voltage circuit 304 further includes a bias voltage source 122 and generates a bias voltage 118, or I 2 C pull-up current circuit 300 includes circuitry similar to bias voltage circuit 304 to implement bias voltage source 122 and generate bias voltage 118 .

[0021] Figure 4 Example I according to the present description is shown 2 C input circuit 400. I 2 C input circuit 400 is an implementation of input circuit 104, input circuit 106, or input circuit 108. 2 C input circuit 400 includes input inverter 405, output inverter 407, feedback circuit 409, transistor 406 and pull-up circuit 411. Input inverter 405 includes a high-side circuit including transistor 412 and transistor 414, and includes a low-side circuit including transistor 408 and transistor 410. 2 In some implementations of C-input circuit 400, transistors 412 and 414 are P-channel metal oxide semiconductor field effect transistors (MOSFETs), and transistors 408 and 410 are N-channel field effect transistors.

[0022] The gate terminal 408G of transistor 408 and the gate terminal 410G of transistor 410 are coupled to the signal input terminal 104A for receiving the input signal 426. The source terminal 408S of transistor 408 is coupled to the ground rail 403. The drain terminal 408D of transistor 408 is coupled to the source terminal 410S of transistor 410.

[0023] A gate terminal 412G of transistor 412 and a gate terminal 414G of transistor 414 are coupled to signal input terminal 104A via transistor 406 for receiving an input signal. A drain terminal 412D of transistor 412 is coupled to drain terminal 410G of transistor 410. A drain terminal 414D of transistor 414 is coupled to source terminal 412S of transistor 412. A source terminal 414S of transistor 414 is coupled to power rail 401.

[0024] Transistor 406 passes the input signal to transistors 412 and 414. Transistor 406 includes a gate terminal 406G coupled to input terminal 104C for biasing, a source terminal 406S coupled to signal input terminal 104A for receiving the input signal, and a drain terminal 406D coupled to gate terminal 412G of transistor 412 and gate terminal 414G of transistor 414. 2 In some implementations of C-input circuit 400, transistor 406 is an N-channel field effect transistor.

[0025] The pull-up circuit 411 includes a pull-up transistor 404 and a cascode transistor 402. The pull-up transistor 404 provides a pull-up current at a drain terminal 406D of the transistor 406. The pull-up transistor 404 includes a gate terminal 404G coupled to the drain terminal 410D of the transistor 410 and the drain terminal 412D of the transistor 412, a drain terminal 404D coupled to the drain terminal 406D of the transistor 406, and a source terminal 404S coupled to the pull-up input terminal 104E via the cascode transistor 402. The pull-up transistor 404 operates as a switch that is turned on or off by a signal provided at the drain terminal 410D of the transistor 410. At I 2 In some implementations of C-input circuit 400, pull-up transistor 404 and cascode transistor 402 are P-channel field effect transistors.

[0026] Cascode transistor 402 isolates pull-up transistor 404 from the parasitic capacitance of conductor 110. Gate terminal 402G of cascode transistor 402 is coupled to input terminal 104D for biasing. Source terminal 402S of cascode transistor 402 is coupled to pull-up input terminal 104E for receiving pull-up current. Drain terminal 402D of cascode transistor 402 is coupled to source terminal 404S of pull-up transistor 404 via conductor 430. Conductor 110 is longer than conductor 430. The voltage at source terminal 402S of cascode transistor 402 is isolated from the voltage at drain terminal 402D. As a result, when the input signal pulls down the voltage at drain terminal 402D, the voltage at source terminal 402S is not pulled down.

[0027] Output inverter 407 includes a high-side transistor 422 and a low-side transistor 424. Gate terminal 422G of high-side transistor 422 and gate terminal 424G of low-side transistor 424 are coupled to drain terminal 410D of transistor 410, drain terminal 412D of transistor 412, and gate terminal 404G of pull-up transistor 404. Source terminal 422S of high-side transistor 422 is coupled to power rail 401. Drain terminal 422D of high-side transistor 422 is coupled to signal output terminal 104B and drain terminal 424D of transistor 424. Source terminal 424S of low-side transistor 424 is coupled to ground rail 403. 2 In some implementations of C-input circuit 400, high-side transistor 422 is a P-channel field effect transistor and low-side transistor 424 is an N-channel field effect transistor.

[0028] Feedback circuit 409 provides feedback to input inverter 405 based on a signal at an input of output inverter 407 (e.g., gate terminal 422G of transistor 422), and includes transistor 416, transistor 418, and transistor 420. The feedback provided by feedback circuit 409 causes input inverter 405 to operate as a Schmitt trigger. Transistor 416 includes a gate terminal 416G coupled to gate terminal 422G of high-side transistor 422 to provide feedback to transistor 412 and transistor 414 based on a signal at the input of output inverter 407. A source terminal 416S of transistor 416 is coupled to a drain terminal 414D of transistor 414 and a source terminal 412S of transistor 412. A drain terminal 416D of transistor 416 is coupled to ground rail 403. 2 C In some embodiments of input circuit 400, transistor 416 is a P-channel field effect transistor.

[0029] Transistor 420 includes a gate terminal 420G coupled to a gate terminal 422G of a high-side transistor 422 to provide feedback to transistor 408 and transistor 410 based on a signal at the input of output inverter 407. A source terminal 420S of transistor 420 is coupled to a drain terminal 408D of transistor 408 and a source terminal 410S of transistor 410. A drain terminal 420D of transistor 420 is coupled to power rail 401 via transistor 418. A gate terminal 418G of transistor 418 is coupled to input terminal 104C for biasing. A source terminal 418S of transistor 418 is coupled to a drain terminal 420D of transistor 420, and a drain terminal 418D of transistor 418 is coupled to power rail 401. At I 2 In some implementations of C-input circuit 400, transistors 418 and 420 are N-channel field effect transistors.

[0030] Figure 5 The use of I according to the present description is shown 2 C input circuit 400 receives an example signal. Input signal 426 is represented by I 2 C input circuit 400 receives, and output signal 428 shows the 2 C input circuit 400 generates a propagation delay 502 range. For example, I 2 C input circuit 400 produces a maximum propagation delay of less than 10 nanoseconds. Signal 504 is generated by the missing I 2 The C input circuit generates and produces a propagation delay 506 in the range of about 185 nanoseconds.

[0031] The above discussion is intended to illustrate the principles and various embodiments of the present invention. Once the above disclosure is fully understood, many changes and modifications will become apparent to those skilled in the art. The following claims are intended to be interpreted as including all such changes and modifications.

Claims

1. An inter-IC input circuit, comprising: Pull-up current circuit; as well as An input circuit comprising: Output inverter; an input inverter; and a pull-up circuit coupled to an input of the input inverter and comprising: a pull-up transistor having a gate, a drain, and a source; and a cascode transistor having a gate, a drain, and a source and configured to decouple the pull-up transistor from capacitance directly coupled to the source of the pull-up current circuit and a conductor of the input circuit; Wherein the source of the pull-up transistor is directly coupled to the drain of the cascode transistor.

2. The inter-IC input circuit according to claim 1, wherein the input circuit comprises: Input terminal; as well as A first transistor is coupled to the input terminal and the input of the input inverter.

3. The inter-IC input circuit according to claim 2, further comprising: a first bias voltage source coupled to the cascode transistor; as well as A second bias voltage source is coupled to the first transistor.

4. The inter-IC input circuit of claim 2, wherein the input inverter comprises a second input coupled to the input terminal.

5. The inter-IC input circuit according to claim 1, wherein: The input inverter includes a high-side circuit; and The input circuit includes a feedback circuit configured to provide a feedback signal to the high-side circuit based on a signal at an input of the output inverter.

6. The inter-IC input circuit according to claim 1, wherein: The input inverter includes a low-side circuit; and The input circuit includes a feedback circuit configured to provide a feedback signal to the low-side circuit based on a signal at an input of the output inverter.

7. An integrated circuit comprising: Pull-up current circuit; A first input circuit comprising: a pull-up transistor having a gate, a drain, and a source; and a cascode transistor having a gate, a drain, and a source and configured to decouple the pull-up transistor from a capacitance directly coupled to the source of the pull-up current circuit and a conductor of the first input circuit; The second input circuit comprises: a pull-up input terminal coupled to the second output terminal of the pull-up current circuit; Signal input terminal; Signal output terminal; An output transistor comprising: a first terminal coupled to the signal output terminal; a second terminal coupled to a power source; A first transistor comprising: a first terminal coupled to the signal input terminal; a second terminal coupled to a first bias voltage source; A second transistor comprising: a first terminal coupled to a third terminal of the first transistor; a second terminal coupled to the third terminal of the output transistor; A cascode transistor comprising: a first terminal coupled to a third terminal of the second transistor; a second terminal coupled to a second bias voltage source; and a third terminal coupled to the second output terminal of the pull-up current circuit; The first input circuit is arranged at a first distance from the pull-up current circuit, and the second input circuit is arranged at a second distance from the pull-up current circuit.

8. The integrated circuit of claim 7, wherein: The output transistor is a first output transistor; and The second input circuit comprises: A second output transistor comprising: a first terminal coupled to the signal output terminal; a second terminal coupled to ground; and A third terminal coupled to the third terminal of the first output transistor.

9. The integrated circuit of claim 7, wherein the second input circuit comprises: A third transistor comprising: a first terminal coupled to the power source; a second terminal coupled to the second terminal of the first transistor; a fourth transistor comprising: a first terminal coupled to a third terminal of the third transistor; and a second terminal coupled to the third terminal of the output transistor; and a fifth transistor comprising: a first terminal coupled to the third terminal of the fourth transistor; and The second terminal is coupled to ground.

10. An inter-IC input circuit, comprising: Pull-up current circuit; as well as An input circuit comprising: Signal input terminal; Signal output terminal; An output transistor comprising: a first terminal coupled to the signal output terminal; and a second terminal coupled to a power source; A first transistor comprising: a first terminal coupled to the signal input terminal; and a second terminal coupled to a first bias voltage source; A second transistor comprising: a first terminal coupled to a third terminal of the first transistor; and a second terminal coupled to the third terminal of the output transistor; and A cascode transistor comprising: a first terminal coupled to a third terminal of the second transistor; a second terminal coupled to a second bias voltage source; and A third terminal is coupled to the output terminal of the pull-up current circuit.

11. The inter-IC input circuit according to claim 10, further comprising: a first conductor disposed between the output terminal of the pull-up current circuit and the third terminal of the cascode transistor; as well as a second conductor disposed between the second terminal of the second transistor and the first terminal of the cascode transistor; The first conductor is longer than the second conductor.

12. The inter-IC input circuit according to claim 10, wherein: The output transistor is a first output transistor; and The input circuit comprises: A second output transistor comprising: a first terminal coupled to the signal output terminal; a second terminal coupled to ground; and A third terminal coupled to the third terminal of the first output transistor.

13. The inter-IC input circuit according to claim 10, wherein the input circuit comprises: A third transistor comprising: a first terminal coupled to the power source; a second terminal coupled to the third terminal of the first transistor; a fourth transistor comprising: a first terminal coupled to a third terminal of the third transistor; a second terminal coupled to the second terminal of the third transistor; and A third terminal coupled to the third terminal of the output transistor.

14. The inter-IC input circuit according to claim 13, wherein the input circuit comprises: a fifth transistor comprising: a first terminal coupled to the first terminal of the fourth transistor; a second terminal coupled to the third terminal of the fourth transistor; and The third terminal is coupled to ground.

15. The inter-IC input circuit according to claim 10, wherein the input circuit comprises: A third transistor comprising: a first terminal coupled to the third terminal of the output transistor; a second terminal coupled to the signal input terminal; a fourth transistor comprising: a first terminal coupled to a third terminal of the third transistor; a second terminal coupled to the second terminal of the third transistor; and The third terminal is coupled to ground.

16. The inter-IC input circuit according to claim 15, wherein the input circuit comprises: a fifth transistor comprising: a first terminal coupled to the first terminal of the fourth transistor; a second terminal coupled to the third terminal of the output transistor; a sixth transistor comprising: a first terminal coupled to the third terminal of the fifth transistor; a second terminal coupled to the second terminal of the first transistor; and A third terminal is coupled to the power source.

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