In-memory arithmetic unit

Abstract

The present invention discloses an in-memory operator, comprising a plurality of storage cell arrays and a plurality of sensing amplifiers. The storage cell arrays receive a plurality of input signals respectively. The input signals are divided into a plurality of groups. The groups respectively have at least a portion of the input signals. Some of the input signals in each group have the same value. The number of the partial input signals in the groups is a geometric progression with a common ratio of 2. The storage cell arrays respectively provide a plurality of weight values, and perform multiplication and addition operations according to the received input signals and the respectively provided weight values ​​to generate a plurality of operation results. The sensing amplifiers respectively generate a plurality of sensing results according to the operation results.

Description

Technical Field

[0001] The present invention relates to an in-memory operator, and more particularly to an in-memory operator capable of improving accuracy. Background Art

[0002] As artificial intelligence is advancing, providing chips with high-efficiency multiplication and addition capabilities in integrated circuits has become an important issue. In today's technology, setting up an in-memory operator to perform multiplication and addition operations has become a mainstream.

[0003] In known in-memory operators, the memory is often divided into a plurality of storage unit blocks, and the multiplication and addition results performed on the plurality of storage unit blocks are quantized and normalized, and then summed up through a plurality of digital shift circuits and accumulator circuits to obtain the final result. Such an approach, under the condition of having a large number of input signals, will greatly increase the number of digital shift circuits and accumulator circuits, resulting in an increase in circuit complexity. In addition, the known in-memory operator requires multiple quantization operations based on the premise of digital processing operations. These quantization operations also cause errors in the operation results, reducing accuracy. Summary of the invention

[0004] The invention provides an in-memory operator, which can process a large amount of input signals and reduce the delay time generated by the calculation process.

[0005] The in-memory operator of the present invention includes a plurality of storage cell arrays and a plurality of sensing amplifiers. The storage cell arrays receive a plurality of input signals respectively. The input signals are divided into a plurality of groups. The groups respectively have at least a portion of the input signals. Some of the input signals in each group have the same numerical value. The number of some of the input signals in the groups is a geometric progression with a common ratio of 2. The sensing amplifiers are respectively coupled to the storage cell arrays. The storage cell arrays respectively provide a plurality of weight values, and perform multiplication and addition operations respectively based on the received input signals and the respectively provided weight values ​​to generate a plurality of operation results. The sensing amplifiers respectively generate a plurality of sensing results based on the operation results.

[0006] Based on the above, the present invention generates sensing results through pure analog multiplication and addition operations and current sensing operations. In this way, in applications with a large number of input signals, the necessary digital shifter circuits and digital accumulator circuits can be eliminated, effectively reducing the complexity of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A schematic diagram of an in-memory operator according to an embodiment of the present invention is shown.

[0008] Figure 2 A schematic diagram of an in-memory operator according to another embodiment of the present invention is shown.

[0009] Figure 3 A schematic diagram of an in-memory operator according to another embodiment of the present invention is shown.

[0010] Figure 4 A schematic diagram is shown of an implementation of a memory cell array according to an embodiment of the present invention.

[0011] Figure 5 FIG. 4 is a flowchart showing the operation of the in-memory operator according to an embodiment of the present invention.

[0012]

Explanation of symbols

[0013] 100, 200, 300: In-memory arithmetic unit

[0014] 111~11N, 211~21N, 311~31N, 400: memory cell array

[0015] 121~12N, 221~22N, 321~32N: Sense amplifier

[0016] 245: Current Multiplier

[0017] 240: Regularization Circuit

[0018] 241, 242, 231: Current source

[0019] 2431~243N: Current adder

[0020] 330: Controller

[0021] BL1~BL8: bit lines

[0022] COUT1~COUTN: operation result

[0023] COUT1'~COUTN': Calculation result after adjustment

[0024] IA, IB+, IB-: current

[0025] IREF: Reference current

[0026] IREF': Adjusted reference current

[0027] MC1~MC8:Memory unit

[0028] SL: Source Line

[0029] SOUT1~SOUTN: Sensing results

[0030] t1, t2: sub-time intervals

[0031] T1, T21, T22: time interval

[0032] WL: Word Line

[0033] X1~XN:Input signal DETAILED DESCRIPTION

[0034] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0035] Please refer to Figure 1 , Figure 1 A schematic diagram of an in-memory operator of an embodiment of the present invention is shown. The in-memory operator 100 includes a plurality of memory cell arrays 111-11N and a plurality of sense amplifiers (SA) 121-12N. The memory cell arrays 111-11N receive a plurality of input signals X1-XN respectively. The input signals X1-XN can be divided into a plurality of groups. Each group has one or more partial input signals among the plurality of input signals X1-XN. And the plurality of partial input signals in each group are the same. And the plurality of groups, according to the arrangement order, have a number of partial input signals which are sequentially a geometric progression with a common ratio of 2.

[0036] In detail, the input signals X1-XN include several input signal subsets Z1-ZH. The sum of an input signal subset = a0+a1×2 2 +a2×2 4 For example, the input signal subsets Z1~ZH can be set to seven partial input signals such as a0, a1, a1, a2, a2, a2, a2. The above seven partial input signals can be divided into three groups. Among them, the first group includes one partial input signal a0; the second group includes two partial input signals a1; and the third group includes four partial input signals a2. In an embodiment of the present invention, the seven partial input signals a0~a2 can be input to seven storage cell arrays respectively. The storage cell array performs multiplication and addition operations according to the corresponding partial input signals a0~a2 based on the provided weights to generate multiple operation results.

[0037] In this embodiment, the memory cell arrays 111-11N perform multiplication and addition operations to generate a plurality of operation results COUT1-COUTN. The sense amplifiers 121-12N receive the reference current IREF and perform sensing operations on the operation results COUT1-COUTN based on the reference current IREF to generate a plurality of sensing results SOUT1-SOUTN.

[0038] Please note that in the embodiment of the present invention, the multiplication and addition operations of the memory cell arrays 111 to 11N are processed based on signals in full analog format. In other words, the operation results COUT1 to COUTN are all signals in analog format. Under such conditions, the embodiment of the present invention can reduce the number of quantization operations that are unavoidable in the digital processing method, and effectively improve the accuracy of the operation.

[0039] The full analog format operation in this embodiment eliminates the need to set up a digital shift register circuit and an accumulation circuit in the memory operator 100, which can effectively reduce the complexity of the circuit.

[0040] Taking the example of processing an input signal of n bits and providing a weight of m bits, the embodiment of the present invention can utilize (2 n -1)×(2 m -1) storage unit to achieve.

[0041] In this embodiment, the memory cell array 111-11N can be a flash memory cell array composed of flash memory cells. The flash memory cells can provide different degrees of transconductance values ​​as weights through an erase operation or a program operation. The sense amplifiers 121-12N can be implemented by any sense amplifier circuit known to those skilled in the art without any limitation.

[0042] Please refer to the following Figure 2 , Figure 2 A schematic diagram of an in-memory operator according to another embodiment of the present invention is shown. The in-memory operator 200 includes a memory cell array 211-21N, a sense amplifier 221-22N, a reference current generator 230, and a normalization circuit 240. The memory cell arrays 211-21N receive a plurality of input signals X1-XN, respectively, and perform multiplication and addition operations based on a plurality of weights provided, and respectively generate a plurality of operation results COUT1-COUTN. The operation results COUT1-COUTN may be analog current signals.

[0043] The current IA generated by the reference current generator 230 is modulated by the reference current adjuster 244 and the reference current multiplier 245 and then transmitted to the sense amplifiers 221-22N. In this embodiment, the reference current generator 230 includes a current source 231. The current source 231 is used to provide the current IA.

[0044] The normalization circuit 240 is coupled to the memory cell arrays 211-21N and to the sense amplifiers 221-22N. The normalization circuit 240 includes a plurality of current adders 2431-243N, a reference current multiplier 245, a reference current adjuster 244, and current sources 241 and 242. The first input terminals of the current adders 2431-243N are respectively coupled to the memory cell arrays 211-21N and receive the operation results COUT1-COUTN. The second input terminals of the current adders 2431-243N receive the first current IB+ in common. The first current IB+ is provided by the current source 241. The current adders 2431-243N respectively add the operation results COUT1-COUTN and the first current IB+, and respectively generate a plurality of adjusted operation results COUT1'-COUTN'.

[0045] The reference current multiplier 245 receives the current IA and multiplies the current IA by a value to generate a reference current IREF by modulating the current value of the current IA. The first input terminal of the reference current adjuster 244 receives the reference current IREF, and the second input terminal of the reference current adjuster 244 receives the second current IB- provided by the current source 242. The reference current adjuster 244 adds the reference current IREF and the second current IB- to generate an adjusted reference current IREF'. In the present embodiment, the reference current adjuster 244 is a current adder.

[0046] In addition, in this embodiment, the adjusted reference current IREF' is provided to the sense amplifiers 221-22N, and the adjusted operation results COUT1'-COUTN' are provided to the sense amplifiers 221-22N respectively. The sense amplifiers 221-22N can sense the adjusted operation results COUT1'-COUTN' respectively according to the adjusted reference current IREF' to generate a plurality of sensing results SOUT1-SOUTN.

[0047] It is worth mentioning that, taking the reference current IREF as 1 / K times the current IA as an example, the normalization circuit 240 can perform a normalization operation based on the value K(yB), where y is the value of the sensing results SOUT1~SOUTN under the condition that K is 1 and B is 0, and B is the difference between the first current B+ and the second current B-. In the embodiment of the present invention, the first current B+ can be greater than the second current B-. The normalization circuit 240 performs an anti-normalization operation on the reference current IREF and the adjusted reference current IREF'. And the anti-normalization operation corresponding to the sensing results SOUT1~SOUTN is a normalization operation.

[0048] The above-mentioned normalization action, when applied to the calculation of the neural network-like, can realize the layer-wise normalization action (layer-wise normalization) of the neural network-like.

[0049] The current adders 2431-243N, the reference current adjuster 244 and the current multiplier 245 in this embodiment can all be implemented by using a current addition and multiplication operation circuit known to those skilled in the art, without any specific limitation. In addition, the current sources 241, 242 and 231 in this embodiment can be implemented by using a current source circuit known to those skilled in the art, also without any fixed limitation.

[0050] Please refer to the following Figure 3 , Figure 3 A schematic diagram of an in-memory operator according to another embodiment of the present invention is shown. The in-memory operator 300 includes a plurality of memory cell arrays 311-31N, a plurality of sense amplifiers (SA) 321-32N, and a controller 330. The controller 330 is coupled to the memory cell arrays 311-31N and the sense amplifiers (SA) 321-32N. The sense amplifiers (SA) 321-32N in this embodiment can perform a sensing operation according to the current IA.

[0051] The controller 330 is used to control the workflow of the in-memory computing unit 300 to perform computing actions.

[0052] Incidentally, in the embodiment of the present invention, the circuit in the dotted frame can also be used Figure 2 The circuit of the embodiment is implemented.

[0053] Please refer to it synchronously Figure 3 as well as Figure 4 ,in Figure 4 A schematic diagram of an implementation of a memory cell array according to an embodiment of the present invention is shown. The memory cell array 400 includes a plurality of flash memory cells MC1-MC8 coupled in parallel. The memory cells MC1-MC8 receive a word line WL in common, are coupled to bit lines BL1-BL8 respectively, and are coupled to a source line SL in common. The memory cells MC1-MC8 receive input signals through the bit lines BL1-BL8, and provide a plurality of weights according to a plurality of transconductance values ​​respectively. After the word line WL completes the setting action (the word line voltage on the word line WL is pulled high), the memory cells MC1-MC8 generate a calculation result COUT1 on the source line SL.

[0054] Please refer to the following Figure 3 as well as Figure 5 ,in Figure 5The flowchart of the operation of the arithmetic unit in the memory of the embodiment of the present invention is shown. In the first time interval T1, the controller 300 performs the setting operation of multiple word lines of the memory cell array 311~31N, and in the subsequent multiple second time intervals T21 and T22, the memory cell array 311~31N continuously performs multiple operation operations. In detail, in the operation operation, taking the second time interval T21 as an example, in the sub-time interval t1, the controller 330 can set the voltage of the bit line according to the input signal, so that the memory cell array 311~31N can perform multiplication and addition operations. Then, in the sub-time interval t2, the sense amplifier 221~22N can perform a current sensing operation on the operation results COUT1~COUTN generated by the memory cell array 311~31N.

[0055] Please note that in the operation of flash memory, the word line setting operation takes a relatively long time. In the embodiment of the present invention, multiple operation operations can be performed successively through a single word line setting operation. In this way, the time delay generated by the operation process can be effectively reduced, and the speed of executing the operation can be improved.

[0056] In summary, the present invention enables the storage cell array in the arithmetic unit in the memory to perform multiplication and addition operations under full analog conditions, thereby eliminating the need to set up digital shift circuits and accumulation circuits, effectively reducing the complexity of the circuit. In addition, the multiplication and addition operations performed under full analog conditions do not require quantization operations, effectively reducing the errors that may be caused by quantization operations and improving accuracy.

[0057] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An in-memory operator, wherein: include: A plurality of memory cell arrays, each receiving a plurality of input signals, wherein the input signals are divided into a plurality of groups, each of the groups having at least a portion of the input signals, the at least a portion of the input signals in each of the groups having the same value, and the number of the at least a portion of the input signals in the groups is a geometric progression with a common ratio of 2; as well as A plurality of sense amplifiers are respectively coupled to the memory cell arrays. Among them, these storage cell arrays respectively provide multiple weight values, and perform multiplication and addition operations based on the received input signals and the respectively provided weight values ​​to generate multiple operation results. The multiplication and addition operations of these storage cell arrays are processed based on signals in a full analog format, and these sensing amplifiers respectively generate multiple sensing results based on these operation results, and these operation results are signals in an analog format.

2. The in-memory operator according to claim 1, wherein: Each of the sensing amplifiers receives a reference current, and senses the operation results respectively according to the reference current to generate the sensing results.

3. The in-memory operator according to claim 2, wherein: Also includes: A reference current generator is coupled to the sense amplifiers to provide the reference current.

4. The in-memory operator according to claim 3, wherein: The reference current generator comprises: A current source generates a current.

5. The in-memory operator according to claim 4, wherein: Also includes: A normalized circuit, comprising: A plurality of current adders are respectively coupled between the coupling paths of the memory cell arrays and the sense amplifiers, and respectively add the operation results to a first current to respectively generate a plurality of adjusted operation results; a current multiplier receiving the current and generating the reference current by modulating the current value of the current; a reference current adjuster, receiving the reference current and adding the reference current to a second current to generate an adjusted reference current, The sensing amplifiers sense the adjusted operation results respectively according to the adjusted reference current to generate the sensing results. The normalization circuit performs a denormalization operation on the reference current and the adjusted reference current, wherein the denormalization operation corresponds to the normalization operation of the sensing results.

6. The in-memory operator according to claim 5, wherein: The regularization circuit also includes: a first current source, coupled to the current adders, for generating the first current; and A second current source is coupled to the reference current regulator and is used to generate the second current.

7. The in-memory operator according to claim 1, wherein: Also includes: A controller is coupled to the memory cell arrays to: In a first time interval, performing a setting operation of a plurality of word lines of the memory cell arrays; as well as In a plurality of second time intervals after the first time interval, a plurality of continuous computing actions are respectively performed.

8. The in-memory operator according to claim 7, wherein: In each of the calculation actions, the controller transmits the input signals to the storage cell arrays in a first sub-time interval, and the sense amplifiers perform a sensing action on the calculation results in a second sub-time interval.

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