Anti-fuse structure and preparation method thereof, and programmable memory

Abstract

The present application relates to an anti-fuse structure and a preparation method thereof, as well as an editable memory including the anti-fuse structure. The anti-fuse structure includes: a first doping region and a second doping region at least partially formed in the first doping region; an isolation layer formed on the first doping region and part of the second doping region, the isolation layer having a window exposing the second doping region; a gate structure including a stacked fuse dielectric layer and a gate conductive layer, the fuse dielectric layer contacting the second doping region through the window; a first electrode contacting the gate conductive layer; a second electrode sequentially penetrating the gate structure and the isolation layer and contacting the second doping region, the second electrode and the gate structure being electrically isolated by an isolation pad. By arranging the second doping region below the gate structure and allowing the second electrode to penetrate the gate structure to contact the second doping region, the area occupied by the anti-fuse structure can be reduced and the integration of the device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to an anti-fuse structure and a preparation method thereof, and a programmable memory. Background Art

[0002] OTP (One Time Programmable) memory is divided into fuse type and anti-fuse type, among which the programmable unit of anti-fuse type memory is an anti-fuse structure. The anti-fuse structure specifically includes a fuse dielectric layer and two electrodes connected to the two sides of the fuse dielectric layer respectively. When programming is not performed, the voltage applied to the fuse dielectric layer is small, the fuse dielectric layer is not broken down, and the anti-fuse structure is equivalent to a capacitor and is in a high-resistance state; when programming is performed, the voltage is increased to break down the fuse dielectric layer, and the anti-fuse structure is equivalent to a resistor and is in a low-resistance state.

[0003] At present, the gate dielectric layer in the transistor gate structure is usually used as the fuse dielectric layer, the gate is used as the first electrode, and the second electrode is drawn from the active area. Controlling the voltage difference between the first electrode and the second electrode can control whether the fuse dielectric layer breaks down. Among them, the gate structure and the active area need to occupy a certain area respectively, which makes the anti-fuse structure area larger, which is not conducive to the integration of devices. Summary of the invention

[0004] Based on this, the present application proposes an anti-fuse structure, a method for preparing the anti-fuse structure, and a programmable memory. The anti-fuse structure has a small area and can improve the device integration.

[0005] In order to solve the above technical problems, the first technical solution proposed in this application is:

[0006] An anti-fuse structure, comprising:

[0007] A first doped region having a first conductivity type and formed in the semiconductor substrate;

[0008] a second doped region having a second conductivity type and at least partially formed in the first doped region;

[0009] an isolation layer, formed on the first doping region and the second doping region, the isolation layer having a window exposing the second doping region;

[0010] A gate structure, comprising a fuse dielectric layer and a gate conductive layer stacked on the fuse dielectric layer, wherein the fuse dielectric layer contacts the second doped region through the window;

[0011] A first electrode in contact with the gate conductive layer; and

[0012] The second electrode sequentially penetrates the gate structure and the isolation layer and contacts the second doping region. The second electrode and the gate structure are electrically isolated from each other by an isolation pad.

[0013] In one embodiment, the second doped region includes a bottom arm formed in the first doped region and a protruding arm extending upward from the bottom arm, the isolation layer covers the first doped region and the bottom arm located on both sides of the protruding arm, the window exposes the protruding arm, and the fuse dielectric layer is in contact with the protruding arm.

[0014] In one embodiment, the side profile of the second doped region is L-shaped.

[0015] In one of the embodiments, isolation sidewalls are formed on both sides of the gate structure.

[0016] In one embodiment, it also includes:

[0017] A passivation layer covers the gate structure; the first electrode penetrates the passivation layer and contacts the gate conductive layer, and the second electrode sequentially penetrates the passivation layer, the gate structure and the isolation layer and contacts the second doped region.

[0018] In one embodiment, the isolation pad sequentially penetrates the passivation layer and the gate conductive layer, and the bottom of the isolation pad contacts the fuse dielectric layer.

[0019] In one of the embodiments, the isolation spacer penetrates the passivation layer and the gate structure in sequence and the bottom of the isolation spacer contacts the isolation layer.

[0020] In one embodiment, the fuse dielectric layer is an oxide layer.

[0021] In one of the embodiments, the gate conductive layer includes a polysilicon layer and a metal layer sequentially stacked on the fuse dielectric layer, and the bottom of the first electrode is in contact with the metal layer.

[0022] In order to solve the above technical problems, the second technical solution proposed in this application is:

[0023] A method for preparing an antifuse structure, comprising:

[0024] Step A: performing first conductivity type doping and second conductivity type doping on a semiconductor substrate respectively, forming a first doping region with the first conductivity type and a second doping region with the second conductivity type in the semiconductor substrate, and at least a portion of the second doping region is formed in the first doping region;

[0025] Step B: forming an isolation layer on the first doping region and the second doping region, wherein the isolation layer has a window exposing the second doping region;

[0026] Step C: forming a gate structure on the isolation layer, the gate structure comprising a fuse dielectric layer and a gate conductive layer stacked on the fuse dielectric layer, the fuse dielectric layer being in contact with the second doped region through the window; and

[0027] Step D: forming a first electrode in contact with the gate conductive layer and a second electrode penetrating the gate structure and the isolation layer in sequence and in contact with the second doping region, and forming an isolation pad for electrically isolating the second electrode from the gate structure.

[0028] In one embodiment, after step C and before step D, the method further includes:

[0029] forming a passivation layer on the gate structure;

[0030] The step D comprises:

[0031] A first trench penetrating the passivation layer and extending to the gate conductive layer, and a second trench penetrating the passivation layer, the gate structure and the isolation layer in sequence and extending to the second doping region are formed by etching processes, an isolation gasket covering the gate conductive layer is formed on at least part of the sidewall of the second trench, the first trench and the second trench are filled, and a first electrode and a second electrode are formed correspondingly.

[0032] In one embodiment, the forming of a second trench that sequentially penetrates the passivation layer, the gate structure, and the isolation layer and extends to the second doping region, and forming an isolation pad covering the gate conductive layer on at least a portion of the sidewall of the second trench, comprises:

[0033] Sequentially etching the passivation layer and the gate conductive layer to form a first opening exposing the fuse dielectric layer;

[0034] forming an isolation pad on a sidewall of the first opening;

[0035] The fuse dielectric layer and the isolation layer are continuously etched downward through the first opening to form a second opening exposing the second doped region, and the second trench includes the first opening and the second opening that are connected to each other.

[0036] In one embodiment, the second doped region includes a bottom arm formed in the first doped region and a protruding arm extending upward from the bottom arm;

[0037] The step of forming an isolation layer on the first doping region and a portion of the second doping region, wherein the isolation layer has a window exposing the second doping region, comprises:

[0038] Depositing an isolation layer on the first doping region and the second doping region;

[0039] The isolation layer is ground so that the upper surface of the isolation layer is flush with the upper surface of the protruding arm.

[0040] In order to solve the above technical problems, the third technical solution proposed in this application is:

[0041] A programmable memory comprises the anti-fuse structure described in any one of the above items.

[0042] The above-mentioned preparation method and structure use the gate as the first electrode and lead out the second electrode from the second doped region, wherein the second doped region is arranged at the bottom of the gate structure, the overlapping area of ​​the second doped region and the gate structure is increased, and the second electrode passes through the gate structure and is electrically connected to the second doped region at the bottom of the gate structure, thereby reducing the area occupied by the entire anti-fuse structure, which is beneficial to improving the integration of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1a is a side cross-sectional view of an anti-fuse structure in conventional technology;

[0044] Figure 1b For the corresponding Figure 1a A position relationship diagram of the second doping region and the gate structure;

[0045] Figure 2a is a side cross-sectional view of an anti-fuse structure in one embodiment of the present application;

[0046] Figure 2b For the corresponding Figure 2a A position relationship diagram of the second doping region and the gate structure;

[0047] Figure 3 is a side cross-sectional view of an anti-fuse structure in another embodiment of the present application;

[0048] Figure 4 A flowchart of the steps corresponding to the method for preparing an anti-fuse structure in an embodiment of the present application;

[0049] Figure 5a to Figure 5g A schematic diagram of a structure formed by related steps of a method for preparing an anti-fuse structure according to an embodiment of the present application.

[0050] Description of symbols

[0051] 100 first doped region; 110 second doped region; 111 bottom arm; 112 protruding arm; 200 isolation layer; 300 gate structure; 310 fuse dielectric layer; 320 gate conductive layer; 321 polysilicon layer; 322 metal layer; 400 passivation layer; 500 isolation pad; 601 first opening; 602 second opening; 610 first electrode; 620 second electrode; 700 isolation side wall; 710 first side wall; 720 second side wall; 730 third side wall; A breakdown region. DETAILED DESCRIPTION

[0052] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0054] like Figure 1a and 1b FIG. 1 shows an anti-fuse structure in conventional technology, wherein: Figure 1a is a side cross-sectional view of the antifuse structure. Figure 1b FIG. 4 is a diagram showing the position relationship between the second doped region and the gate structure.

[0055] like Figure 1a As shown, in the conventional technology, the second doping region 110' is formed in the first doping region 100', the gate dielectric layer in the gate structure 300' serves as the fuse dielectric layer 310', and the breakdown region A of the fuse dielectric layer 310' is defined by the isolation layer 200'. At the same time, one end of the second doping region 110' contacts the breakdown region A, and the other end extends outside the projection area of ​​the gate structure 300'. The first electrode 610' penetrates the passivation layer 400' and contacts the gate conductive layer 320', and the second electrode 620' is staggered from the gate structure 300' and contacts the second doping region 110' at a position different from the gate structure 300'. For the positional relationship between the second doping region 110' and the gate structure 300', see Figure 1b At this time, the length L' of the anti-fuse structure is relatively long, resulting in a larger area occupied by the anti-fuse structure.

[0056] To this end, the present application proposes a new anti-fuse structure.

[0057] like Figure 2a As shown, the anti-fuse structure includes at least the following structures:

[0058] The first doped region 100 has a first conductivity type and is formed in a semiconductor substrate. Specifically, the first doped region 100 may be a well region having a first conductivity type formed in the semiconductor substrate.

[0059] The second doping region 110 has a second conductivity type and is at least partially formed in the first doping region 100. The second doping region 110 is used to lead out the second electrode. The first conductivity type and the second conductivity type have opposite conductivity properties, wherein when the first conductivity type is N-type, the second conductivity type is P-type, and when the first conductivity type is P-type, the second conductivity type is N-type.

[0060] The isolation layer 200 is formed on the first doping region 100 and the second doping region 110 . The isolation layer 200 is provided with a window exposing the second doping region 110 .

[0061] The gate structure 300 is formed on the isolation layer 200, and includes a stacked gate dielectric layer and a gate conductive layer 320, wherein the gate dielectric layer forms the fuse dielectric layer 310 in the present application, and the fuse dielectric layer 310 contacts the second doped region 110 through the above-mentioned window. The above-mentioned window can be used to define the breakdown area A of the fuse dielectric layer 310, that is, the breakdown area A of the fuse dielectric layer 310 is the area where the fuse dielectric layer 310 contacts the second doped region 110 through the window.

[0062] A first electrode 610 and a second electrode 620, wherein the first electrode 610 contacts the gate conductive layer 320 to provide a voltage signal to one side of the fuse dielectric layer 310. The second electrode 620 sequentially penetrates the gate structure 300 and the isolation layer 200 and contacts the second doped region 110 to provide a voltage signal to the other side of the fuse dielectric layer 310. At the same time, the second electrode 620 is electrically isolated from the gate structure 300 by the isolation pad 500. Further, the above structure may also include a passivation layer 400 covering the gate structure 300, and the passivation layer 400 is used to protect the above structure. At this time, the first electrode 610 penetrates the passivation layer 400 and contacts the gate conductive layer 320, and the second electrode 620 sequentially penetrates the passivation layer 400, the gate structure 300 and the isolation layer 200 and contacts the second doped region 110.

[0063] In the anti-fuse structure, one side of the fuse dielectric layer 310 is electrically connected to the first electrode 610, and the other side is connected to the second electrode 620. By controlling the voltage difference between the two electrodes, the breakdown state of the fuse dielectric layer 310 can be controlled. Before programming, the fuse dielectric layer 310 is not broken down and is in a high-resistance state. When programming is required, the fuse dielectric layer 310 is broken down and is in a low-resistance state. At the same time, in the present application, combined with Figure 2bAs shown, the second doping region 110 is disposed below the gate structure 300, and the area of ​​the breakdown region A is limited by the isolation layer 200, and the second electrode 620 penetrates the gate structure 300 and the isolation layer 200 to contact the second doping region 110 directly below the gate structure 300, thereby increasing the overlapping area between the gate structure 300 and the second doping region 110, so that the area occupied by the anti-fuse structure is reduced. Figure 2b As shown, the length of the anti-fuse structure is L. Compared with the traditional anti-fuse structure, when the second doping region 110 and the gate structure 300 have the same morphology, the length L of the anti-fuse structure in the present application is less than the length L' of the traditional anti-fuse structure, that is, the area occupied by the anti-fuse structure in the present application is reduced, which is conducive to improving the integration of the device. At the same time, in the present application, the second doping region 110 is arranged below the gate structure 300, and the area of ​​the breakdown region A is limited by the isolation layer 200, which can increase the area of ​​the breakdown region A, so that the boundary of the breakdown region A becomes more obvious, thereby obtaining a significant boundary effect; accordingly, the second electrode 620 penetrates the gate structure 300 and contacts the second doping region 110, which can shorten the distance between the second electrode 620 and the breakdown region A, reduce the resistance between the second electrode 620 and the breakdown region A, and effectively improve the anti-fuse repair effect.

[0064] There are many ways for the above-mentioned fuse dielectric layer 310 to contact the second doping region 110 through the window, which are not limited here. For example, the second doping region 110 has a flat upper surface, and the lower surface of the fuse dielectric layer 310 has a protrusion matching the window, that is, the fuse dielectric layer 310 is deposited in the window to achieve contact with the second doping region 110. In this embodiment, the second doping region 110 includes a bottom arm 111 formed in the first doping region 100 and a protruding arm 112 extending upward from the bottom arm 110, and the upper surface of the protruding arm 112 is higher than the upper surface of the bottom arm 111 and the upper surface of the first doping region 100. The isolation layer 200 covers the first doping region 100 and the bottom arm 111 on both sides of the protruding arm 112, but does not cover the protruding arm 112, so as to form a window exposing the protruding arm 112 at the protruding arm 112, and at this time, the second doping region 110 is specifically in contact with the fuse dielectric layer 310 through the protruding arm 112. Furthermore, the upper surface of the protruding arm 112 is flush with the upper surface of the isolation layer 200, and the fuse dielectric layer 310 has a flat lower surface. Furthermore, when the second doped region 110 has the bottom arm 111 and the protruding arm 112, the bottom arm 111 and the protruding arm 112 are Figure 2a The side section shown is L-shaped, that is, the protruding arm 112 is extended upward from the end of the bottom arm 111.

[0065] In one embodiment, if Figure 2aAs shown, isolation sidewalls 700 are also formed on both sides of the gate structure 300. It can be understood that the isolation sidewalls 700 should contain insulating materials with an isolation effect. For example, the isolation sidewalls 700 can be made of one or more insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. When the isolation sidewalls 700 have a multi-layer structure, an air gap can be formed in the middle to further improve the isolation effect. In this embodiment, the isolation sidewalls 700 are composed of a first sidewall 710, a second sidewall 720, and a third sidewall 730 stacked together. The materials of the first sidewall 710, the second sidewall 720, and the third sidewall 730 are different. For example, the first sidewall 710 can be silicon nitride, the second sidewall 720 can be silicon oxide, and the third sidewall 730 can be silicon nitride.

[0066] Specifically, the isolation pad 500 can be disposed in a variety of ways, as long as it can electrically isolate the second electrode 620 from the gate structure 300, and is not limited here. Figure 2a As shown, the isolation pad 500 sequentially penetrates the passivation layer 400 and the gate conductive layer 320 and extends to the fuse dielectric layer 310, that is, the bottom of the isolation pad 500 contacts the fuse dielectric layer 310. In another embodiment, see Figure 3 As shown, the isolation pad 500 sequentially penetrates the passivation layer 400 and the gate structure 300 and extends to the isolation layer 200, that is, the bottom of the isolation pad 500 is in contact with the isolation layer 200. In other embodiments, the isolation pad 500 may also sequentially penetrate the passivation layer 400, the gate structure 300 and the isolation layer 200 and directly contact the second doping region 110. It can be understood that the isolation pad 500 should also include an insulating material with an isolation effect. For example, the isolation pad 500 can be made of one or more insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. When the isolation pad 500 has a multi-layer structure, an air gap can be formed in the middle to further improve the isolation effect.

[0067] Specifically, the fuse dielectric layer 310 may be an oxide layer, specifically a silicon oxide layer. The gate conductive layer 320 may be a polysilicon layer, or a metal layer, or a stacked polysilicon layer and a metal layer. In the present embodiment, the fuse dielectric layer 310 is a silicon oxide layer, the gate conductive layer 320 includes a polysilicon layer 321 and a metal layer 322 sequentially stacked on the fuse dielectric layer 310, and the first electrode 610 is specifically in contact with the metal layer 322. Furthermore, the metal layer 322 may be metal tungsten.

[0068] The present application also relates to a method for preparing an anti-fuse structure, by which the above-mentioned anti-fuse structure can be prepared.

[0069] like Figure 4 As shown, the method for preparing the anti-fuse structure includes at least the following steps:

[0070] Step S100: performing first conductivity type doping and second conductivity type doping on a semiconductor substrate respectively, forming a first doping region with the first conductivity type and a second doping region with the second conductivity type in the semiconductor substrate, and at least a portion of the second doping region is formed in the first doping region.

[0071] See also Figure 5a As shown, in this step, by doping the semiconductor substrate, a first doping region 100 and a second doping region 110 at least partially located in the first doping region 100 are formed in the semiconductor substrate.

[0072] In a specific embodiment, the second doping region 110 includes a bottom arm 111 formed in the first doping region 100 and a protruding arm 112 extending upward from the bottom arm 111 , and an upper surface of the protruding arm 112 is higher than upper surfaces of the first doping region 100 and the bottom arm 111 .

[0073] Correspondingly, the above-mentioned structure can be formed in a variety of ways. In one embodiment, step S100 can be decomposed into the following sub-steps:

[0074] Step S110: etching the semiconductor substrate so that the semiconductor substrate has an integrally formed bottom plate and a protrusion extending upward from the bottom plate.

[0075] Step S120: performing first conductivity type doping on the protrusion of the semiconductor substrate and the bottom plate around the protrusion to form an integrally formed first doping region.

[0076] Step S130: Continue to perform second conductivity type doping on the protrusion of the semiconductor substrate and part of the first doped region around the protrusion to form an integrally formed second doped region, wherein the second doped region includes a protruding arm formed at the protrusion and a bottom arm formed in the first doped region.

[0077] In addition to forming the second doped region 110 having the bottom arm 111 and the protruding arm 112 through the above steps S110 to S130, the above second doped region 110 may also be formed through other processes. In one embodiment, the semiconductor substrate may be first doped with the first conductivity type, and then the semiconductor substrate is etched to form the bottom plate and the protrusion, and finally the second doping type is doped to form the above structure. In another embodiment, the semiconductor substrate may be first doped with the first conductivity type and then doped with the second conductivity type, and then the semiconductor substrate is etched to form the above structure.

[0078] Step S200: forming an isolation layer on the first doping region and the second doping region, wherein the isolation layer has a window exposing the second doping region.

[0079] See also Figure 5bAs shown, an isolation layer 200 is formed on the first doping region 100 and the second doping region 110 , and the isolation layer 200 has a window exposing the second doping region 110 .

[0080] In one embodiment, the second doping region 110 has the bottom arm 111 and the protruding arm 112, and step S200 may include the following sub-steps:

[0081] Step S210: depositing an isolation layer on the first doping region and the second doping region.

[0082] Step S220: Grinding the isolation layer so that the upper surface of the isolation layer is flush with the upper surface of the protruding arm.

[0083] In the above sub-steps, an isolation layer is first deposited. At this time, the isolation layer covers the bottom arm 111 and the protruding arm 112 of the first doping region 110 and the second doping region 110. Then, the isolation layer is ground so that the upper surface of the isolation layer 200 is flush with the protruding arm 112. At this time, the isolation layer 200 forms a window exposing the protruding arm 112.

[0084] Step S300: forming a gate structure on the isolation layer, wherein the gate structure comprises a fuse dielectric layer and a gate conductive layer stacked on the fuse dielectric layer, and the fuse dielectric layer contacts the second doped region through the window.

[0085] See also Figure 5c As shown, after the isolation layer 200 is formed, a gate structure 300 is further formed on the isolation layer 200, and the gate structure 300 includes a fuse dielectric layer 310 and a gate conductive layer 320 stacked in sequence on the isolation layer 200, wherein the fuse dielectric layer 310 contacts the second doped region 110 through a window, and the area where the fuse dielectric layer 310 contacts the second doped region 110 through the window is the breakdown area A.

[0086] Specifically, the fuse dielectric layer 310 may be an oxide layer, specifically a silicon oxide layer, and the gate conductive layer 320 may include a polysilicon layer 321 and a metal layer 322 sequentially stacked on the fuse dielectric layer 310 .

[0087] Step S400: forming a first electrode in contact with the gate conductive layer and a second electrode penetrating the gate structure and the isolation layer in sequence and in contact with the second doping region, and forming an isolation pad for electrically isolating the second electrode from the gate structure.

[0088] Specifically, between step S300 and step S400, the following steps are also included:

[0089] A passivation layer is formed on the gate structure.

[0090] See also Figure 5c As shown, the passivation layer 400 covers the gate structure 300 to protect the gate structure 300 .

[0091] When the passivation layer 400 is formed, step S400 specifically includes:

[0092] A first trench penetrating the passivation layer and extending to the gate conductive layer, and a second trench penetrating the passivation layer, the gate structure and the isolation layer in sequence and extending to the second doping region are formed by etching processes, an isolation gasket covering the gate conductive layer is formed on at least part of the sidewall of the second trench, the first trench and the second trench are filled, and a first electrode and a second electrode are formed correspondingly.

[0093] Specifically, the above step S400 has multiple implementations. In one embodiment, step S400 can be decomposed into the following steps:

[0094] Step S410: etching the passivation layer to form a first trench exposing the gate conductive layer, and filling the first trench to form a first electrode in contact with the gate conductive layer.

[0095] like Figure 5c As shown, the passivation layer 400 is etched to form a first trench exposing the gate conductive layer 320 , and a conductive material is filled in the first trench to form a first electrode 610 in contact with the gate conductive layer 320 .

[0096] Step S420: Etch the passivation layer, the gate structure and the isolation layer in sequence to form a second trench exposing the second doped region, form an isolation pad covering the gate conductive layer on at least part of the sidewall of the second trench, fill the second trench, and form a second electrode in contact with the second doped region.

[0097] In the above steps S410 and S420, the first electrode is formed first and then the second electrode is formed. In another embodiment, the second electrode may be formed first and then the first electrode is formed, that is, the process in the above step S420 is performed first and then the process in step S410 is performed. In other embodiments, the first trench and the second trench may be opened first and an isolation gasket may be formed through the second trench, and then the first trench and the second trench may be filled synchronously to form the first electrode 610 and the second electrode 620 at the same time.

[0098] Furthermore, in step S400, a second trench is formed which sequentially penetrates the passivation layer, the gate structure and the isolation layer and extends to the second doping region, and an isolation pad covering the gate conductive layer is formed on at least a portion of the sidewall of the second trench, specifically comprising the following steps:

[0099] Step S421: etching the passivation layer and the gate conductive layer in sequence to form a first opening exposing the fuse dielectric layer.

[0100] like Figure 5d As shown, the passivation layer 400 and the gate conductive layer 320 are sequentially etched to form a first opening 601 exposing the fuse dielectric layer 310 .

[0101] Step S422: forming an isolation pad on the sidewall of the first opening.

[0102] like Figure 5e As shown, an isolation pad 500 is formed on the sidewall of the first opening 601. In a specific process, a layer of isolation material can be first deposited on the upper surface of the passivation layer 400, the bottom and sidewall of the first opening 601, and then etched back to remove the isolation material on the upper surface of the passivation layer 400 and the bottom of the first opening 601, and retain the isolation material on the sidewall of the first opening 601 to form the isolation pad 500.

[0103] Step S423: continue to etch downward the fuse dielectric layer and the isolation layer through the first opening to form a second opening exposing the second doped region, wherein the second trench includes the first opening and the second opening that are connected to each other.

[0104] like Figure 5f As shown, the fuse dielectric layer 310 and the isolation layer 200 are etched downward through the first opening 601 to form a second opening 602 exposing the second doped region 110 . The first opening 601 and the second opening 602 form a second trench.

[0105] After forming the second trench, the method further comprises:

[0106] Step S424: filling the second trench to form the second electrode.

[0107] like Figure 5g As shown, the second trench is filled with a conductive material to form a second electrode 620 in contact with the second doping region. In the above embodiment, when the second doping region 110 includes the bottom arm 111 and the protruding arm 112, the second electrode 620 is in contact with the bottom arm 111.

[0108] In this embodiment, the second electrode 620 is formed through the above steps S421 to S424, and the second electrode 620 is electrically isolated from the gate structure 300 through the isolation pad 500, wherein the bottom of the isolation pad 500 is in contact with the fuse dielectric layer 310. In other embodiments, the depth of the first opening may be deepened so that the first opening continues to penetrate the fuse dielectric layer 310 or continues to penetrate the fuse dielectric layer 310 and the isolation layer 200, and the bottom of the isolation pad 500 is in contact with the isolation layer 200 below the fuse dielectric layer 310 or directly in contact with the second doping region 110, which can also achieve electrical isolation of the second electrode 620 from the gate structure 300.

[0109] In one embodiment, an isolation spacer 700 is further formed on the sidewall of the gate structure 300. Specifically, the isolation spacer 700 may be formed after forming the first electrode 610 and the second electrode 620, or after forming the passivation layer 400 and before forming the first trench and the second trench. Specifically, the isolation spacer 700 is composed of a stacked first spacer 710, a second spacer 720, and a third spacer 730. The first spacer 710, the second spacer 720, and the third spacer 730 are made of different materials. For example, the first spacer 710 may be silicon nitride, the second spacer 720 may be silicon oxide, and the third spacer 730 may be silicon nitride.

[0110] The above-mentioned method for preparing the anti-fuse structure forms a second doped region 110 in the semiconductor substrate below the gate structure 300, and limits the area of ​​the breakdown region A through the isolation layer 200, and the second electrode 620 penetrates the gate structure 300 and the isolation layer 200 to contact the second doped region 110 directly below the gate structure 300, thereby increasing the overlapping area between the gate structure 300 and the second doped region 110, so that the area occupied by the anti-fuse structure is smaller, which is beneficial to improving the integration of the device.

[0111] The present application also relates to a programmable memory, which includes the anti-fuse structure, wherein the specific structure of the anti-fuse structure has been specifically introduced above and will not be repeated here. As mentioned above, the anti-fuse structure in the programmable memory occupies a small area, so the programmable memory has a high degree of integration.

[0112] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. An anti-fuse structure, characterized in that: include: A first doped region having a first conductivity type and formed in the semiconductor substrate; a second doped region having a second conductivity type and at least partially formed in the first doped region; an isolation layer, formed on the first doping region and the second doping region, the isolation layer having a window exposing the second doping region; A gate structure, comprising a fuse dielectric layer and a gate conductive layer stacked on the fuse dielectric layer, wherein the fuse dielectric layer contacts the second doped region through the window, and isolation sidewalls are formed on both sides of the gate structure, wherein the isolation sidewalls are composed of a first sidewall, a second sidewall and a third sidewall stacked together; A first electrode, contacting the gate conductive layer; as well as The second electrode sequentially penetrates the gate structure and the isolation layer and contacts the second doping region. The second electrode and the gate structure are electrically isolated from each other by an isolation pad.

2. The anti-fuse structure according to claim 1, wherein: The second doped region includes a bottom arm formed in the first doped region and a protruding arm extending upward from the bottom arm, the isolation layer covers the first doped region and the bottom arm located on both sides of the protruding arm, the window exposes the protruding arm, and the fuse medium layer contacts the protruding arm.

3. The anti-fuse structure according to claim 2, wherein: The side profile of the second doping region is L-shaped.

4. The anti-fuse structure according to claim 1, wherein: Also includes: A passivation layer covering the gate structure; The first electrode penetrates the passivation layer and contacts the gate conductive layer, and the second electrode sequentially penetrates the passivation layer, the gate structure and the isolation layer and contacts the second doping region.

5. The anti-fuse structure according to claim 4, wherein: The isolation pad sequentially penetrates the passivation layer and the gate conductive layer, and the bottom of the isolation pad contacts the fuse dielectric layer.

6. The anti-fuse structure according to claim 4, wherein: The isolation pad sequentially penetrates the passivation layer and the gate structure, and the bottom of the isolation pad contacts the isolation layer.

7. The anti-fuse structure according to any one of claims 1 to 6, wherein: The fuse dielectric layer is an oxide layer.

8. The anti-fuse structure according to claim 7, wherein: The gate conductive layer includes a polysilicon layer and a metal layer which are sequentially stacked on the fuse dielectric layer, and the bottom of the first electrode is in contact with the metal layer.

9. A method for preparing an anti-fuse structure, characterized in that: include: Step A: performing first conductivity type doping and second conductivity type doping on a semiconductor substrate respectively, forming a first doping region with the first conductivity type and a second doping region with the second conductivity type in the semiconductor substrate, and at least a portion of the second doping region is formed in the first doping region; Step B: forming an isolation layer on the first doping region and the second doping region, wherein the isolation layer has a window exposing the second doping region; Step C: forming a gate structure on the isolation layer, wherein the gate structure includes a fuse dielectric layer and a gate conductive layer stacked on the fuse dielectric layer, and the fuse dielectric layer is in contact with the second doped region through the window; as well as Step D: forming a first electrode in contact with the gate conductive layer and a second electrode penetrating the gate structure and the isolation layer in sequence and in contact with the second doping region, and forming an isolation pad for electrically isolating the second electrode from the gate structure.

10. The preparation method according to claim 9, characterized in that: After step C and before step D, the method further comprises: forming a passivation layer on the gate structure; The step D comprises: A first trench penetrating the passivation layer and extending to the gate conductive layer, and a second trench penetrating the passivation layer, the gate structure and the isolation layer in sequence and extending to the second doping region are formed by etching processes, an isolation gasket covering the gate conductive layer is formed on at least part of the sidewall of the second trench, the first trench and the second trench are filled, and a first electrode and a second electrode are formed correspondingly.

11. The preparation method according to claim 10, characterized in that: The forming of a second trench that sequentially penetrates the passivation layer, the gate structure, and the isolation layer and extends to the second doping region, and forming an isolation pad covering the gate conductive layer on at least a portion of the sidewall of the second trench, comprises: Sequentially etching the passivation layer and the gate conductive layer to form a first opening exposing the fuse dielectric layer; forming an isolation pad on a sidewall of the first opening; The fuse dielectric layer and the isolation layer are continuously etched downward through the first opening to form a second opening exposing the second doped region, and the second trench includes the first opening and the second opening that are connected to each other.

12. The preparation method according to any one of claims 9 to 11, characterized in that: The second doping region includes a bottom arm formed in the first doping region and a protruding arm extending upward from the bottom arm; The step of forming an isolation layer on the first doping region and a portion of the second doping region, wherein the isolation layer has a window exposing the second doping region, comprises: Depositing an isolation layer on the first doping region and the second doping region; The isolation layer is ground so that the upper surface of the isolation layer is flush with the upper surface of the protruding arm.

13. A programmable memory, characterized in that: The anti-fuse structure comprises the anti-fuse structure as described in any one of claims 1 to 8.

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