Power-on reset signal generator

Abstract

A power-on reset signal generating device includes a reference voltage generator, a signal driver, and a stabilizing circuit. The reference voltage generator generates a power-on reference voltage based on the voltage level of a power supply voltage. The signal driver drives the power-on reference voltage to generate a power-on reset signal. The stabilizing circuit receives the power-on reset signal and maintains the voltage level of the power-on reference voltage for a predetermined period of time.

Description

Technical Field

[0001] Various embodiments relate generally to semiconductor integrated circuit technology, and more particularly, to a power-on reset signal generating apparatus. Background Art

[0002] The semiconductor device operates by supplying a power supply voltage from an external power supply. When the semiconductor device is supplied with the power supply voltage, the semiconductor device performs a power-on operation. When the voltage level of the power supply voltage becomes stable, the semiconductor device enables a power-on reset signal. When the power-on reset signal is enabled, the semiconductor device initializes an internal circuit and prepares for normal operation. When the supply of the power supply voltage to the semiconductor device is interrupted, the semiconductor device performs a power-off operation. When the voltage level of the power supply voltage drops below a predetermined level or a lower level, the semiconductor device disables the power-on reset signal.

[0003] Semiconductor devices detect the level of the power supply voltage to generate a power-on reset signal. However, the power supply voltage provided from an external power supply is inevitably accompanied by noise. Therefore, during the power-on period or the power-off period, the voltage level of the power supply voltage stays near the target voltage level as a stable reference, and repeatedly fluctuates up and down relative to the target voltage level. Due to this noise of the power supply voltage, when the power supply voltage reaches near the target voltage level, the power-on reset signal becomes enabled and / or disabled, and then becomes disabled and / or enabled, which causes a glitch of the power-on reset signal. The glitch of the power-on reset signal causes semiconductor device failure. Summary of the invention

[0004] According to one embodiment, a power-on reset signal generating device may include a reference voltage generator, a signal driver, and a stabilization circuit. The reference voltage generator may detect a voltage level of a power supply voltage to generate a power-on reference voltage. The signal driver may drive the power-on reference voltage to generate a power-on reset signal. The stabilization circuit may keep the power-on reset signal enabled during a predetermined amount of time when the power-on reset signal is enabled, and may prevent the power-on reset signal from being enabled during a predetermined amount of time when the power-on reset signal is disabled.

[0005] According to one embodiment, a power-on reset signal generating device may include a reference voltage generator, a signal driver and a stabilization circuit. The reference voltage generator may generate a power-on reference voltage based on a voltage level of a power supply voltage. The signal driver may drive the power-on reference voltage to generate a power-on reset signal. The stabilization circuit may receive a fed-back power-on reset signal to continue to maintain the voltage level of the power-on reference voltage regardless of the voltage level fluctuation of the power supply voltage.

[0006] According to one embodiment, a power-on reset signal generating device may include a reference voltage generator, a signal driver, and a stabilization circuit. The reference voltage generator may detect a voltage level of a power supply voltage to generate a power-on reference voltage. The signal driver may drive the power-on reference voltage to generate a power-on reset signal that is enabled when the power supply voltage is equal to or greater than a target voltage level. The stabilization circuit may keep the power-on reset signal enabled for a predetermined amount of time after the power-on reset signal changes from a disabled state to an enabled state, even if the power supply voltage is less than the target voltage during a predetermined amount of time. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a diagram illustrating a configuration of a power-on reset signal generating device according to one embodiment;

[0008] Figure 2 It is an example Figure 1 A diagram showing the operation of a power-on reset signal generating device;

[0009] Figure 3 It is an example Figure 1 Another operation diagram of the power-on reset signal generating device shown;

[0010] Figure 4 is a diagram illustrating a configuration of a power-on reset signal generating device according to one embodiment;

[0011] Figure 5 It is an example Figure 4 A diagram of the configuration of the stabilization circuit shown;

[0012] Figure 6 is a diagram illustrating a configuration of a control signal generator according to one embodiment;

[0013] Figure 7 It is shown Figure 6 A timing diagram showing the operation of the control signal generator;

[0014] Figure 8 is a timing diagram illustrating the operation of a power-on reset signal generating device according to an embodiment during a power-on period;

[0015] Fig. 9 is a timing diagram illustrating the operation of a power-on reset signal generating device according to an embodiment during a power-off period; and

[0016] Fig.10 is an example of a power outage period Figure 5 A timing diagram of another operation of the stabilization circuit is shown. DETAILED DESCRIPTION

[0017] Figure 1is a diagram illustrating a configuration of a power-on reset signal generating device 100 according to one embodiment. Figure 1 , the power-on reset signal generating device 100 may receive the power supply voltage VCC, and may detect the voltage level of the power supply voltage VCC to generate the power-on reset signal POR. The power-on reset signal generating device 100 may detect the power-on state to enable the power-on reset signal POR, and may detect the power-off state to disable the power-on reset signal POR. In the power-on state, the power supply voltage VCC may be provided from an external power supply, and the voltage level of the power supply voltage VCC may be increased to reach a target voltage level or a higher voltage level. When the voltage level of the power supply voltage VCC increases to reach the target voltage level or a higher voltage level, the voltage level of the power supply voltage VCC may be determined to be stable. In the power-off state, the supply of the power supply voltage VCC from the external power supply may be interrupted, and the voltage level of the power supply voltage VCC may drop below the target voltage level. When the voltage level of the power supply voltage VCC increases to reach the target voltage level or a higher voltage level, the power-on reset signal generating device 100 may enable the power-on reset signal POR. When the voltage level of the power supply voltage VCC stays at the target voltage level or higher, the power-on reset signal generating device 100 can keep the power-on reset signal POR in the enabled state. When the voltage level of the power supply voltage VCC drops below the target voltage level, the power-on reset signal generating device 100 can disable the power-on reset signal POR to the disabled state.

[0018] The power-on reset signal generating device 100 may include a reference voltage generator 110 and a signal driver 120. The reference voltage generator 110 may detect the voltage level of the power supply voltage VCC to generate a power-on reference voltage PREF. When the voltage level of the power supply voltage VCC increases to reach a target voltage level or a higher voltage level, the reference voltage generator 110 may reduce the power-on reference voltage PREF so that the voltage level of the power-on reference voltage PREF may be determined as a logic low level. When the voltage level of the power supply voltage VCC stays at a target voltage level or a higher voltage level, the reference voltage generator 110 may maintain the power-on reference voltage PREF at a voltage level that can be determined as a logic low level of the power-on reference voltage PREF. When the voltage level of the power supply voltage VCC drops below the target voltage level, the reference voltage generator 110 may change the power-on reference voltage PREF so that the voltage level of the power-on reference voltage PREF may be determined as a logic high level. The reference voltage generator 110 may divide the power supply voltage VCC through a plurality of resistors to generate a detection voltage DREF from one or more divided voltages. When the voltage level of the detection voltage DREF becomes a target voltage level or more, the reference voltage generator 110 may drive the power-up reference voltage PREF through the ground voltage. When the voltage level of the detection voltage DREF becomes lower than the target voltage level, the reference voltage generator 110 may drive the power-up reference voltage PREF to the power supply voltage VCC.

[0019] The signal driver 120 may receive a power-on reference voltage PREF to generate a power-on reset signal POR. The signal driver 120 may drive the power-on reference voltage PREF to generate the power-on reset signal POR. In an embodiment, the signal driver 120 may non-inversion-drive the power-on reference voltage PREF to generate the power-on reset signal POR. For example, the signal driver 120 may include an even number of inverters, and may sequentially inverse-drive the power-on reference voltage PREF through an even number of inverters to generate the power-on reset signal POR. For example, Figure 1 As shown, the signal driver 120 may include a first inverter 121 and a second inverter 122. The first inverter 121 may receive a power-on reference voltage PREF, may invert the power-on reference voltage PREF, and may output the inverted power-on reference voltage PREF. The second inverter 122 may receive the output of the first inverter 121, may invert the output of the first inverter 121, and may output a power-on reset signal POR. In an embodiment, the signal driver 120 may include an odd number of inverters to invert the power-on reference voltage PREF to generate a power-on reset signal POR. In this case, the power-on reset signal POR output from the signal driver 120 may be enabled to another logic level.

[0020] The reference voltage generator 110 may include a first voltage divider 111, a second voltage divider 112, a diode transistor 113, and a trigger transistor 114. The first voltage divider 111 and the second voltage divider 112 may have the same configuration as each other. The first voltage divider 111 may include a plurality of resistors connected in series between a node provided with a power supply voltage VCC and a first node N1. The plurality of resistors may have the same resistance value as each other. The detection voltage DREF may be output from a node NR between any two resistors among the plurality of resistors connected in series with each other. The position between the two resistors for specifying the node NR may be arbitrarily selected to change the target voltage level. For example, as the two selected resistors are closer to the node provided with the power supply voltage VCC, the target voltage level may become higher. On the contrary, as the two selected resistors are closer to the first node N1, the target voltage level may become lower. The diode transistor 113 may be connected between the first node N1 and a node provided with a ground voltage VSS. For example, the diode transistor 113 may be an N-channel MOS transistor. The gate and drain of the diode transistor 113 may be coupled to the first node N1, and the source thereof may be coupled to a node supplied with the ground voltage VSS. The diode transistor 113 may allow a stable amount of current to flow from the first node N1 and the node supplied with the ground voltage VSS.

[0021] The second voltage divider 112 may include a plurality of resistors connected in series between a node provided with a power supply voltage VCC and a second node N2. The number of resistors included in the second voltage divider 112 may be the same as the number of resistors included in the first voltage divider 111. The resistance value of each resistor included in the second voltage divider 112 may be the same as the resistance value of each resistor included in the first voltage divider 111. A power-on reference voltage PREF may be output from the second node N2. The trigger transistor 114 may be connected between the second node N2 and a node provided with a ground voltage VSS. The trigger transistor 114 may receive a detection voltage DREF. For example, the trigger transistor 114 may be an N-channel MOS transistor. The gate of the trigger transistor 114 may receive the detection voltage DREF, the drain thereof may be connected to the second node N2, and the source thereof may be connected to a node provided with a ground voltage VSS. When the detection voltage DREF has a voltage level high enough to turn on the trigger transistor 114, the trigger transistor 114 may be turned on, and the power-on reference voltage PREF may be driven to the ground voltage VSS. When the detection voltage DREF has a voltage level too low to turn on the trigger transistor 114 , the trigger transistor 114 may be turned off, and the power-on reference voltage PREF may be driven by the power supply voltage VCC.

[0022] Figure 2 It is an example Figure 1 FIG. 1 is a diagram showing the operation of the power-on reset signal generating device 100. Figure 1 and Figure 2 Described will be the operation of the power-on reset signal generating device 100. When the power supply voltage VCC is provided from an external power supply, the voltage level of the power supply voltage VCC may gradually become higher. As the voltage level of the power supply voltage VCC gradually becomes higher, the voltage levels of the first node N1, the detection voltage DREF, and the power-on reference voltage PREF may increase. As the voltage level of the detection voltage DREF increases, the amount of current flowing through the trigger transistor 114 may become larger. As the voltage level of the power-on reference voltage PREF increases, the voltage level of the power-on reset signal POR may increase. When the trigger transistor 114 is fully turned on as the voltage level of the detection voltage DREF increases, the voltage level of the power-on reference voltage PREF may drop. When the voltage level of the power-on reference voltage PREF drops below the threshold voltage of the first inverter 121, the power-on reset signal POR may be enabled as a logic low level. When the voltage level of the power supply voltage VCC is maintained, the amount of current flowing through the trigger transistor 114 may be maintained, and therefore the voltage level of the power-on reference voltage PREF may be maintained and the power-on reset signal POR may remain enabled.

[0023] When the supply of the power supply voltage VCC from the external power supply is interrupted, the voltage level of the power supply voltage VCC may gradually decrease. As the voltage level of the power supply voltage VCC gradually decreases, the voltage level of the detection voltage DREF decreases and the amount of current flowing through the trigger transistor 114 may become smaller. Therefore, the voltage level of the power-on reference voltage PREF may increase. When the voltage level of the power-on reference voltage PREF increases as the voltage level of the detection voltage DREF decreases to reach the threshold voltage of the first inverter 121 or a voltage level greater, the power-on reset signal POR may be disabled as a logic high level. Then, as the voltage level of the power supply voltage VCC decreases, the voltage levels of the detection voltage DREF, the power-on reference voltage PREF, and the power-on reset signal POR may decrease. When the voltage level of the power supply voltage VCC increases to reach a target voltage level or a higher voltage level, the power-on reset signal generating device 100 may enable the power-on reset signal POR as a logic low level. When the voltage level of the power supply voltage VCC drops below the target voltage level, the power-on reset signal generating device 100 may disable the power-on reset signal POR as a logic high level.

[0024] Figure 3 It is schematically illustrated Figure 1. The voltage level of the power supply voltage VCC may change, and the power supply voltage VCC is accompanied by a considerable amount of noise. Specifically, when the power supply voltage VCC rises or falls near the target voltage level, the voltage level of the power supply voltage VCC may repeatedly become higher or lower than the target voltage level TL due to noise. When the voltage level of the power supply voltage VCC repeatedly becomes higher or lower than the target voltage level TL, the state of the power-on reset signal POR generated from the power-on reset signal generating device 100 may change. That is, even after the power-on reset signal POR becomes enabled, the power-on reset signal POR may repeatedly become enabled or disabled due to the noise of the power supply voltage VCC. In addition, even after the power-on reset signal POR becomes disabled, the power-on reset signal POR may repeatedly become enabled or disabled due to the noise of the power supply voltage VCC. The unstable state of the power-on reset signal POR and / or the burrs appearing in the power-on reset signal POR may cause reliability problems of semiconductor devices having the power-on reset signal generating device 100.

[0025] Figure 4 is a diagram illustrating a configuration of a power-on reset signal generating device 400 according to one embodiment. Figure 4 The power-on reset signal generating device 400 may include a reference voltage generator 410 and a signal driver 420, which is similar to Figure 1The power-on reset signal generating device 100 shown is the same, and the power-on reset signal generating device 400 may further include a stabilizing circuit 430. Among the elements configuring the power-on reset signal generating device 400, the elements identical to the elements included in the power-on reset signal generating device 100 may be represented by similar reference numerals, and the description of the identical elements will be omitted. The stabilizing circuit 430 may be connected between the input node and the output node of the signal driver 420. The stabilizing circuit 430 may receive the power-on reset signal POR to stabilize the state of the power-on reset signal POR. The power-on reset signal POR may be fed back to the stabilizing circuit 430, and the stabilizing circuit 430 may continue to maintain the voltage level of the power-on reference voltage PREF, thereby preventing the power-on reset signal POR from changing unstably. When the power-on reset signal POR is enabled, the stabilizing circuit 430 may keep the power-on reset signal POR enabled during a predetermined amount of time, regardless of the voltage level fluctuation of the power supply voltage VCC. The stabilization circuit 430 may continue to maintain the voltage level of the power-on reference voltage PREF during a predetermined amount of time to prevent the power-on reset signal POR from fluctuating and becoming disabled again. When the power-on reset signal POR becomes disabled, the stabilization circuit 430 may continue to keep the power-on reset signal POR disabled during a predetermined amount of time, regardless of the voltage level fluctuation of the power supply voltage VCC. The stabilization circuit 430 may continue to maintain the voltage level of the power-on reference voltage PREF during a predetermined amount of time to prevent the power-on reset signal POR from fluctuating and becoming enabled again. The word "predetermined" (such as a preset period) as used herein for a parameter refers to determining the value of the parameter before the parameter is used in a process or algorithm. For some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0026] When the power-on reset signal POR becomes enabled as a logic low level, the stabilization circuit 430 can drive the power-on reference voltage PREF to the level of the ground voltage VSS during a predetermined amount of time. Therefore, even when noise occurs in the voltage level of the power supply voltage VCC, the power-on reset signal POR can be prevented from fluctuating and becoming disabled again. When the power-on reset signal POR becomes disabled as a logic high level, the stabilization circuit 430 can drive the power-on reference voltage PREF to the level of the power supply voltage VCC during a predetermined amount of time. Therefore, even when noise occurs in the voltage level of the power supply voltage VCC, the power-on reset signal POR can be prevented from fluctuating and becoming enabled again.

[0027] Figure 5 It is an example Figure 4 The configuration of the stabilization circuit 430 is shown in FIG. Figure 5, the stabilization circuit 430 may include a discharge control signal generator 510, a charge control signal generator 520, and a voltage driver 530. The discharge control signal generator 510 may receive a power-on reset signal POR and may generate a discharge control signal DCCT based on the power-on reset signal POR. When the power-on reset signal POR is enabled, the discharge control signal generator 510 may enable the discharge control signal DCCT. The charge control signal generator 520 may receive the power-on reset signal POR and may generate a charge control signal CCT based on the power-on reset signal POR. When the power-on reset signal POR is disabled, the charge control signal generator 520 may enable the charge control signal CCT. The voltage driver 530 may change the voltage level of the power-on reference voltage PREF based on the discharge control signal DCCT and the charge control signal CCT. The voltage driver 530 may drive the power-on reference voltage PREF to the ground voltage VSS based on the discharge control signal DCCT. The voltage driver 530 may drive the power-on reference voltage PREF to the power supply voltage VCC based on the charge control signal CCT. When the discharge control signal DCCT is enabled, the voltage driver 530 may drive the power-on reference voltage PREF to the ground voltage VSS to reduce the voltage level of the power-on reference voltage PREF. When the charge control signal CCT is enabled, the voltage driver 530 may drive the power-on reference voltage PREF to the power supply voltage VCC to increase the voltage level of the power-on reference voltage PREF.

[0028] The discharge control signal generator 510 may include a first control signal generator 511. When the power-on reset signal POR is enabled, the first control signal generator 511 may generate a discharge control signal DCCT, which remains enabled during a predetermined amount of time. The discharge control signal DCCT may remain enabled as a logic high level during a predetermined amount of time. When the power-on reset signal POR is disabled, the charge control signal generator 520 may generate a charge control signal CCT, which remains enabled during a predetermined amount of time. The charge control signal CCT may remain enabled as a logic low level during a predetermined amount of time. The charge control signal generator 520 may include a first inverter 521, a second control signal generator 522, and a second inverter 523. The first inverter 521 may receive the power-on reset signal POR, and may invert the power-on reset signal POR to output a complementary signal PORB of the power-on reset signal POR. The second control signal generator 522 may be substantially the same in configuration as the first control signal generator 511, and may operate in substantially the same manner as the first control signal generator 511. When the power-on reset signal POR is disabled and the complementary signal PORB of the power-on reset signal POR is enabled as a logic low level, the second control signal generator 522 may generate a signal that remains enabled as a logic high level during a predetermined amount of time. The second inverter 523 may invert the signal generated by the second control signal generator 522 to output the charging control signal CCT.

[0029] The voltage driver 530 may include a discharge driver 531 and a charge driver 532. The discharge driver 531 may be connected between a node of a power-on reference voltage PREF and a node to which a ground voltage VSS is provided. The discharge driver 531 may receive a discharge control signal DCCT. When the discharge control signal DCCT is enabled, the discharge driver 531 may drive the node of the power-on reference voltage PREF to the ground voltage VSS. The charge driver 532 may be connected between a node to which a power supply voltage VCC is provided and a node of the power-on reference voltage PREF. The charge driver 532 may receive a charge control signal CCT. When the charge control signal CCT is enabled, the charge driver 532 may drive the node of the power-on reference voltage PREF to the power supply voltage VCC.

[0030] The discharge driver 531 may include a first transistor. The first transistor may be an N-channel MOS transistor. The drain of the first transistor may be connected to a node of a power-on reference voltage PREF, and its source may be connected to a node provided with a ground voltage VSS. The gate of the first transistor may receive a discharge control signal DCCT. The charge driver 532 may include a second transistor. The second transistor may be a P-channel MOS transistor. The source of the second transistor may be connected to a node provided with a power supply voltage VCC, and its drain may be connected to a node of a power-on reference voltage PREF. The gate of the second transistor may receive a charge control signal CCT.

[0031] Figure 6 is a diagram illustrating a configuration of a first control signal generator 511 included in the discharge control signal generator 510 according to one embodiment. Figure 6 , the first control signal generator 511 can receive the power-on reset signal POR, and when the power-on reset signal POR is enabled, a discharge control signal DCCT can be generated, which remains enabled during a predetermined amount of time. The first control signal generator 511 may include a delayer 610, a first gate circuit 620, a second gate circuit 630, a capacitor 640, and a discharger 650. The delayer 610 can delay the power-on reset signal POR to output a delay signal DLY. The delayer 610 may be a non-inverting delayer. For example, the delayer 610 may include four inverters and three capacitors, each capacitor being connected between adjacent inverters among the four inverters. The number of inverters and capacitors included in the delayer 610 will not be limited thereto. The number of inverters may be an even number, such as 2, 4 or more, and the number of capacitors may be increased or decreased according to the number of inverters. The delay amount of the delayer 610 may be determined by the appropriate number of inverters and capacitors included in the delayer 610.

[0032] The first gate circuit 620 can perform a gate operation on the power-on reset signal POR and the delay signal DLY to generate an enable signal EN. The first gate circuit 620 can perform an AND operation on the power-on reset signal POR and the delay signal DLY to generate an enable signal EN. When any one of the power-on reset signal POR and the delay signal DLY becomes a logic low level, the first gate circuit 620 can enable the enable signal EN to a logic low level. The first gate circuit 620 may include a first NAND gate 621 and an inverter 622. The first NAND gate 621 may receive the power-on reset signal POR and the delay signal DLY through its two input nodes, respectively. The inverter 622 may be connected to the output node of the first NAND gate 621. The inverter 622 may invert the output of the first NAND gate 621 to output the enable signal EN. The second gate circuit 630 may perform a gate operation on the power-on reset signal POR and the enable signal EN to generate a control signal CON. The second gate circuit 630 can perform a NAND operation on the power-on reset signal POR and the enable signal EN to generate a control signal CON. When any one of the power-on reset signal POR and the enable signal EN is enabled to a logic low level, the second gate circuit 630 can convert the control signal CON into a logic high level. The second gate circuit 630 may include a second NAND gate 631. The second NAND gate 631 may receive the power-on reset signal POR and the enable signal EN through its two input nodes, respectively. The second NAND gate 631 may output the control signal CON through its output node.

[0033] The capacitor 640 can enable the discharge control signal DCCT based on the control signal CON. When the control signal CON is enabled as a logic high level, the capacitor 640 can be charged and the discharge control signal DCCT can be enabled as a logic high level. The capacitor 640 can be connected to the output node of the second NAND gate 631 at one end, and can receive the control signal CON through this end. The capacitor 640 can be connected to the output node ON at the other end. The discharge control signal DCCT can be output through the output node ON. The discharger 650 can receive the bias voltage BIAS, and can change the voltage level of the discharge control signal DCCT based on the bias voltage BIAS. The discharger 650 can discharge the capacitor 640 to reduce the voltage level of the discharge control signal DCCT. The discharger 650 can include an N-channel MOS transistor 651. The drain of the N-channel MOS transistor 651 can be connected to the output node ON, and its source can be connected to a node provided with a ground voltage VSS. The gate of the N-channel MOS transistor 651 can receive the bias voltage BIAS. The capacitance of the capacitor 640, the size and / or current drivability of the N-channel MOS transistor 651, and the voltage level of the bias voltage BIAS may be changed in various ways to set the predetermined amount of time. The second control signal generator 522 may have the same configuration as the first control signal generator 511 except that the second control signal generator 522 may receive a complementary signal PORB of the power-on reset signal POR instead of the power-on reset signal POR.

[0034] Figure 7 It is an example Figure 5 and Figure 6 The timing diagram of the operation of the first control signal generator 511 is shown in FIG. Figures 5 to 7Described below will be the operation of the first control signal generator 511. When the power supply voltage VCC is provided, the voltage levels of the power-on reset signal POR and the bias voltage BIAS may increase. The voltage level of the power-on reset signal POR may also correspond to a logic low level. The control signal CON output from the second gate circuit 630 may have a logic high level. Even when the voltage level of the power-on reset signal POR increases, the delayer 610 may delay the power-on reset signal POR to generate a delay signal DLY. Therefore, during the delay time corresponding to the delay amount of the delayer 610, the voltage level of the delay signal DLY may not increase. When the delay time corresponding to the delay amount of the delayer 610 has passed, the voltage level of the enable signal EN output from the first gate circuit 620 may increase together with the voltage level of the power-on reset signal POR. When the voltage levels of the power-on reset signal POR and the enable signal EN increase to a logic high level, the second gate circuit 630 may convert the control signal CON to a logic low level. When the voltage level of the power-on reset signal POR continues to rise according to the voltage level of the power supply voltage VCC and the voltage level of the power supply voltage VCC reaches the target voltage level, the power-on reset signal POR can be converted to a logic low level. In addition, the enable signal EN can also be converted to a logic low level, and the second gate circuit 630 can convert the control signal CON to a logic high level. When the control signal CON is converted to a logic high level, the capacitor 640 can be charged and the discharge control signal DCCT can be enabled. When the discharger 650 discharges the capacitor 640 based on the bias voltage BIAS and the voltage level of the discharge control signal DCCT drops, the discharge control signal DCCT can therefore remain enabled during a predetermined amount of time.

[0035] Figure 8 is a timing diagram illustrating the operation of the power-on reset signal generating device 400 according to an embodiment during a power-on period. Fig. 9 1 is a timing diagram illustrating the operation of the power-on reset signal generating device 400 according to an embodiment during a power-off period. Figures 4 to 9 Described will be the operation of the power-on reset signal generating device 400 . Figure 8 and Fig. 91 is an enlarged diagram illustrating the time when the voltage level of the power supply voltage VCC has risen to the vicinity of the target voltage level. Therefore, the power supply voltage VCC looks like oscillating within a predetermined range. When the voltage level of the power supply voltage VCC rises during the power-on period to reach the target voltage level or a higher voltage level, the power-on reset signal generating device 400 can enable the power-on reset signal POR to a logic low level. When the power-on reset signal POR becomes enabled to a logic low level, the discharge control signal generator 510 can continue to enable the discharge control signal DCCT to a logic high level during a predetermined amount of time. When the discharge control signal DCCT is enabled, the voltage driver 530 can drive the power-on reference voltage PREF to the ground voltage VSS during a predetermined amount of time. Noise may occur in the power supply voltage VCC, so the voltage level of the power supply voltage VCC drops below the target voltage level, and noise may occur at the first node N1. According to the prior art, a glitch occurs in which the enabled power-on reset signal POR fluctuates and becomes disabled again. However, according to an embodiment of the present disclosure, the power-on reference voltage PREF can be driven to the ground voltage VSS, so that the power-on reset signal POR can be prevented from fluctuating and becoming disabled again. Therefore, when the power-on reset signal POR is enabled, the stabilization circuit 430 can keep the power-on reset signal POR enabled during a predetermined amount of time, regardless of the voltage level fluctuation of the power supply voltage VCC. When the predetermined amount of time has passed, the voltage level of the power supply voltage VCC rises to a voltage level sufficient to reach the target voltage level or greater, so even if noise occurs in the power supply voltage VCC, there is no chance of glitches in the power-on reset signal POR.

[0036] Reference Fig. 9 When the voltage level of the power supply voltage VCC drops below the target voltage level during the power-off period, the power-on reset signal generating device 400 may disable the power-on reset signal POR to a logic high level. The first inverter 521 of the charging control signal generator 520 may invert the power-on reset signal POR to output a complementary signal PORB of the power-on reset signal POR, and the second control signal generator 522 may generate a complementary signal having the same Figure 8The discharge control signal DCCT shown in the figure has substantially the same waveform as the discharge control signal DCCT. The second inverter 523 can invert the signal generated from the second control signal generator 522 to generate the charging control signal CCT. The charging control signal CCT can be enabled to a logic low level when the power-on reset signal POR is disabled, and can remain enabled during a predetermined amount of time. When the charging control signal CCT is enabled, the voltage driver 530 can drive the power-on reference voltage PREF to the power supply voltage VCC during a predetermined amount of time. Since the power-on reference voltage PREF is driven to the level of the power supply voltage VCC even when noise occurs in the power supply voltage VCC and the voltage level of the power supply voltage VCC is increased to reach the target voltage level or a higher voltage level, the power-on reference voltage PREF is also driven to the level of the power supply voltage VCC, so that the power-on reset signal POR can be prevented from fluctuating and becoming enabled again. Therefore, when the power-on reset signal POR is disabled, the stabilization circuit 430 can keep the power-on reset signal POR disabled during a predetermined amount of time, regardless of the voltage level fluctuation of the power supply voltage VCC. When a predetermined amount of time has elapsed, the voltage level of the power supply voltage VCC drops sufficiently below the target voltage level, so even if noise occurs in the power supply voltage VCC, there is no chance that a glitch will occur in the power-on reset signal POR.

[0037] Fig.10 is an example of a power outage period Figure 4 and Figure 5 FIG. 4 is a timing diagram of another operation of the stabilization circuit 430. Fig.10 , when the voltage level of the power supply voltage VCC drops below the target voltage level during the power-off period, the power-on reset signal POR may be turned into a logic high level. At this time, the stabilization circuit 430 may enable the charging control signal CCT to a logic low level to prevent glitches from occurring in the power-on reset signal POR. However, even when an unexpected glitch occurs in the power-on reset signal POR, the stabilization circuit 430 may prevent the power-on reference voltage PREF from being driven to the level of the ground voltage VSS. When a glitch occurs in the power-on reset signal POR, the discharge control signal generator 510 may detect the glitch in the power-on reset signal POR to enable the discharge control signal DCCT, and a failure in which both the charging control signal CCT and the discharge control signal DCCT are enabled may occur. However, the first control signal generator 511 having the delayer 610 may prevent both the charging control signal CCT and the discharge control signal DCCT from being enabled during a period in which any one of the charging control signal CCT and the discharge control signal DCCT is enabled. Referring together Figure 6, even when a glitch occurs in the power-on reset signal POR, the voltage level of the enable signal EN of the discharge control signal generator 510 may continue to be maintained during the delay time corresponding to the delay amount of the delayer 610. Therefore, the control signal CON output from the second gate circuit 630 may not be converted to a logic low level, but may stay at a logic high level, and the discharge control signal DCCT may be fixed to a logic low level and may remain disabled. The stabilization circuit 430 may drive the power-on reference voltage PREF to the level of the power supply voltage VCC through the charging driver 532 based on the charging control signal CCT. On the contrary, even if an unexpected glitch occurs in the power-on reset signal POR after the power-on reset signal POR is enabled to a logic low level, the delayer 610 of the second control signal generator 522 may prevent the charging control signal CCT from being enabled. Therefore, even when a glitch occurs in the power-on reset signal POR during the delay time corresponding to the delay amount of the delayer 610 , the charging control signal CCT may not be enabled and the stabilization circuit 430 may drive the power-on reference voltage PREF to the level of the ground voltage VSS through the discharge driver 531 .

[0038] Although some embodiments have been described above, it will be appreciated by those skilled in the art that the described embodiments are merely exemplary. Therefore, the power-on reset signal generating device should not be limited based on the described embodiments. Instead, the power-on reset signal generating device described herein should be limited only according to the attached claims in combination with the above description and the accompanying drawings.

[0039] CROSS-REFERENCE TO RELATED APPLICATIONS

[0040] This application claims the benefit of Korean Application No. 10-2019-0157542 filed on November 29, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference in their entirety as if fully set forth herein.

Claims

1. A power-on reset signal generating device, the power-on reset signal generating device comprising: a reference voltage generator configured to detect a voltage level of a power supply voltage to generate a power-on reference voltage; a signal driver configured to drive the power-on reference voltage to generate a power-on reset signal; a discharge control circuit configured to enable a discharge control signal during a predetermined amount of time when the power-on reset signal is enabled; a charge control circuit configured to enable a charge control signal during the predetermined amount of time when the power-on reset signal is disabled; as well as A voltage driver is configured to drive the power-on reference voltage to a ground voltage based on the discharge control signal, and to drive the power-on reference voltage to the power supply voltage based on the charge control signal.

2. The power-on reset signal generating device according to claim 1, wherein: The discharge control circuit includes a first control signal generator configured to generate the discharge control signal that remains enabled during the predetermined amount of time when the power-on reset signal is enabled.

3. The power-on reset signal generating device according to claim 2, wherein: The charging control circuit comprises: a first inverter configured to invert the power-on reset signal to generate a complementary signal of the power-on reset signal; a second control signal generator configured to generate a signal that remains enabled during the predetermined amount of time when the complementary signal of the power-on reset signal is enabled; and a second inverter configured to invert the signal output from the second control signal generator to generate the charging control signal.

4. The power-on reset signal generating device according to claim 2, wherein: The first control signal generator comprises: a delayer configured to delay the power-on reset signal to generate a delayed signal; a first gate circuit, the first gate circuit being configured to perform a gate operation on the power-on reset signal and the delay signal to generate an enable signal; a second gate circuit, the second gate circuit being configured to perform a gate operation on the power-on reset signal and the enable signal to generate a control signal; a capacitor configured to be charged based on the control signal and output the discharge control signal; and A discharger is configured to discharge the capacitor to maintain the discharge control signal in an enabled state during the predetermined amount of time.

5. The power-on reset signal generating device according to claim 1, wherein: The voltage driver comprises: a discharge driver configured to drive the level of the power-on reference voltage to the ground voltage based on the discharge control signal; and A charging driver is configured to drive the level of the power-on reference voltage to the power supply voltage based on the charging control signal.

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