Display device

Abstract

A display device is provided. The display device includes: a display panel configured to display an image for each of a plurality of frame periods; and an input sensing unit directly disposed on the display panel and configured to sense a user input. The display device further includes: a first driver configured to control driving of the display panel; and a second driver configured to control driving of the input sensing unit. A frame period includes a display period and a blank period adjacent to the display period. A duration of the blank period may randomly vary during a set reference period.

Description

[0001] This application claims the priority and benefit of Korean Patent Application No. 10-2019-0159059, filed on Dec. 3, 2019, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to a display device, and more particularly, to a display device having improved display quality. BACKGROUND ART

[0003] Development of electronic devices such as smart phones, tablet computers, laptop computers, and smart televisions is in progress. These electronic devices include a display device for providing information. The electronic device also includes various suitable electronic modules in addition to the display device.

[0004] The display device includes an input sensing panel as an input device. The input sensing panel may be disposed on a display panel that displays an image. SUMMARY OF THE INVENTION

[0005] Aspects of embodiments of the present disclosure relate to a display device that prevents the display quality from deteriorating due to signal interference between an input sensing unit and a display panel, or reduces the degree to which the display quality deteriorates due to signal interference between the input sensing unit and the display panel.

[0006] Embodiments of the present disclosure provide a display device including: a display panel configured to display an image for each of a plurality of frame periods; an input sensing unit directly disposed on the display panel to sense a user input; a first driver configured to control driving of the display panel; and a second driver configured to control driving of the input sensing unit.

[0007] In an embodiment, the frame period may include a display period and a blank period adjacent to the display period. The duration of the blank period may randomly vary during a set reference period.

[0008] In an embodiment of the present disclosure, a display device includes: a display panel configured to display an image; an input sensing unit directly disposed on the display panel and configured to sense a user input for each of a plurality of sensing frame periods; a first driver configured to control driving of the display panel; and a second driver configured to control driving of the input sensing unit.

[0009] In an embodiment, the sensing frame period may include a sensing period and an edge period adjacent to the sensing period. The duration of the edge period may randomly vary during a set reference period. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings are included to provide a further understanding of the present disclosure, and the drawings are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, are used to describe the principles of the present disclosure. In the drawings:

[0011] Figure 1A is a perspective view of a display device according to an embodiment of the present disclosure;

[0012] Figure 1B is an exploded perspective view of a display device according to an embodiment of the present disclosure;

[0013] Figure 2 is a cross-sectional view schematically showing a display module according to an embodiment of the present disclosure;

[0014] Figure 3 is a block diagram of a display device according to an embodiment of the present disclosure;

[0015] Figure 4A is Figure 3 a block diagram of the first driver and the display panel shown in;

[0016] Figure 4B is Figure 4A an equivalent circuit diagram of one pixel among a plurality of pixels shown in;

[0017] Figure 5 is a waveform diagram showing driving signals for driving Figure 4B the pixel shown in;

[0018] Figure 6A is a waveform diagram showing Figure 3 the configuration of the second driver and the input sensing unit shown in;

[0019] Figure 6B is a cross-sectional view showing the structure of a display panel and an input sensing unit according to an embodiment of the present disclosure;

[0020] Figure 7A is a block diagram showing a controller according to an embodiment of the present disclosure;

[0021] Figure 7B is a waveform diagram showing n frame periods included in a reference period according to an embodiment of the present disclosure;

[0022] Figure 7C is a waveform diagram showing Figure 7B each of the n frame periods shown in;

[0023] Figure 8 is a waveform diagram showing n frame periods included in a reference period according to an embodiment of the present disclosure;

[0024] Figure 9A is a block diagram showing a controller according to an embodiment of the present disclosure;

[0025] Figure 9B is a waveform diagram showing n sensing frame periods included in a reference sensing period according to an embodiment of the present disclosure;

[0026] Figure 9C is showing Figure 9B a waveform diagram of each of the n sensing frame periods shown in; and

[0027] Figure 10 is a waveform diagram showing n sensing frame periods included in a reference sensing period according to an embodiment of the present disclosure. Detailed Description

[0028] As used herein, when describing embodiments of the present disclosure, the use of the term "may" means "one or more embodiments of the present disclosure". It will be understood that when an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present.

[0029] Throughout the specification, like reference numerals denote like elements. In the figures, the thickness, ratio, and dimensions of elements may be exaggerated for effective description of the technical content. As used herein, the terms "substantially", "about", "approximately", and similar terms are used as approximate terms and not as terms of degree, and are intended to account for inherent deviations in measured or calculated values recognized by those of ordinary skill in the art.

[0030] As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items.

[0031] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another (other) element, component, region, layer, or portion. Thus, without departing from the teachings of the present disclosure, the first element, first component, first region, first layer, or first portion discussed below may be named the second element, second component, second region, second layer, or second portion. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are also intended to include the plural forms.

[0032] For ease of description, spatial relative terms such as "under", "below", "lower", "above", and "upper" may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. It will be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in a general dictionary, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0034] It will also be understood that the terms "comprising" and "having" when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0035] Hereinafter, the present disclosure will be explained in more detail with reference to the accompanying drawings.

[0036] Figure 1A is a perspective view of a display device according to an embodiment of the present disclosure, Figure 1B is an exploded perspective view of a display device according to an embodiment of the present disclosure. Figure 2 is a cross-sectional view schematically showing a display module according to an embodiment of the present disclosure.

[0037] Referring to Figure 1A and Figure 1B , the display device DD may be a device activated according to an electrical signal. The display device DD may be implemented in various suitable forms. For example, the display device DD may be used in large electronic devices such as televisions, monitors, or outdoor digital signage, or may be used in medium and small electronic devices such as personal computers, laptop computers, personal digital assistants, car navigation devices, game consoles, portable electronic devices, or cameras. These are example embodiments, and the display device DD may also be adopted in other electronic devices as long as the display device DD does not depart from the present disclosure. In the embodiments shown in Figure 1A and Figure 1B , the display device DD is shown as a smart phone by way of example.

[0038] The display device DD can display an image IM toward a third direction DR3 on a display surface DS parallel (e.g., substantially parallel) to each of a first direction DR1 and a second direction DR2. For example, the display surface DS can be parallel (e.g., substantially parallel) to a plane defined by the first direction DR1 and the second direction DR2. The image IM can include a still image and a moving image. In Figure 1A a watch window and an icon are shown as examples of the image IM. The display surface DS on which the image IM is displayed can correspond to the front surface of the display device DD and can correspond to the front surface of the window WP.

[0039] In the present embodiment, the front surface (or top surface) and the rear surface (or bottom surface) of each member are defined with respect to the direction along which the image IM is displayed. The front surface and the rear surface of each member can face each other through the member in the third direction DR3, and the normal direction of each of the front surface and the rear surface can be parallel (e.g., substantially parallel) to the third direction DR3. The directions indicated by the first direction DR1 to the third direction DR3 are relative and can be converted to different directions. In this specification, "when viewed in a plane" can mean "when viewed in the third direction DR3".

[0040] The display device DD according to an embodiment of the present disclosure can sense a user input TC applied from the outside. The user input TC includes various suitable types or kinds of external inputs (such as a part of the user's body, light, heat, and / or pressure). In some embodiments, the display device DD can sense the user input TC applied to the front surface (e.g., the display surface DS), but the embodiments of the present disclosure are not limited thereto. In addition, depending on the structure of the display device DD, the display device DD can sense the user input TC applied to the side surface and / or the rear surface of the display device DD, and is not limited to any one embodiment.

[0041] The display device DD can include a window WP, an anti-reflection panel RPP, a display module DM, and a housing HU. In the present embodiment, the window WP and the housing HU are combined (e.g., joined together) to form the appearance of the display device DD.

[0042] The window WP can include (e.g., can be) an optically transparent insulating material. For example, the window WP can include (e.g., can be) glass and / or plastic. The window WP can have a multi-layer structure or a single-layer structure. For example, the window WP can include a plurality of plastic films bonded by an adhesive, or can include a glass substrate and a plastic film bonded by an adhesive.

[0043] As described above, the front surface of the window WP defines the display surface DS of the display device DD. For example, the window WP may include a display surface DS having a transmissive area TA and a border area BZA. The transmissive area TA may be an optically transparent area. For example, the transmissive area TA may be an area having a visible light transmittance of about 90% or more.

[0044] Compared with the transmissive area TA, the border area BZA may be an area having a lower light transmittance. The border area BZA defines the shape of the transmissive area TA. The border area BZA may be adjacent to the transmissive area TA and may partially or completely surround the transmissive area TA.

[0045] The border area BZA may have a predetermined or set color. The border area BZA may cover the peripheral area NAA of the display module DM to prevent the peripheral area NAA from being viewed from the outside. According to an embodiment of the present disclosure, the border area BZA may be omitted from the window WP.

[0046] An anti-reflection panel RPP may be disposed under the window WP. The anti-reflection panel RPP reduces the reflectance of external light incident from above the window WP. In an embodiment of the present disclosure, the anti-reflection panel RPP may be omitted, and the anti-reflection panel RPP may be a component included in the display module DM. In some embodiments, the anti-reflection panel RPP may be omitted from the display device DD. In some embodiments, the anti-reflection panel RPP may be included in the display module DM (for example, the anti-reflection panel RPP may be an integral part of the display module DM).

[0047] The display module DM may display an image IM and may sense a user input TC. The display module DM includes a front surface IS having an active area AA and a peripheral area NAA. The active area AA may be an area activated according to an electrical signal.

[0048] In the present embodiment, the active area AA may be an area for displaying the image IM and may also (for example, simultaneously) be an area for sensing the user input TC. The transmissive area TA at least overlaps with the active area AA. For example, the transmissive area TA overlaps with all or at least a part of the active area AA. Thus, through the transmissive area TA, a user can view the image IM and / or can provide the user input TC. However, in some embodiments, the area for displaying the image IM and the area for sensing an external input may be separated from each other in the active area AA, and is not limited to any one embodiment.

[0049] The peripheral area NAA may be an area covered by the border area BZA. The peripheral area NAA is adjacent to the active area AA. The peripheral area NAA may partially or completely surround the active area AA. A driving circuit, driving lines, etc. may be disposed in the peripheral area NAA to drive the active area AA.

[0050] The driving circuit unit DC is electrically connected to the display module DM. The driving circuit unit DC includes a main circuit board MB and a flexible circuit board FCB.

[0051] The main circuit board MB may include various suitable driving circuits for driving the display module DM, connectors for supplying power, etc. The flexible circuit board FCB may be connected to the main circuit board MB and the display module DM. For example, the flexible circuit board FCB may be connected between the main circuit board MB and the display module DM to connect the main circuit board MB to the display module DM. The driving circuit unit DC may also include a driving chip DIC mounted on the flexible circuit board FCB. In an embodiment of the present disclosure, the driving chip DIC may (for example, may also) be mounted or directly mounted on the display module DM.

[0052] The housing HU is combined with the window WP (for example, the housing HU is coupled to the window WP). The housing HU and the window WP are combined to provide a predetermined or set internal space. The display module DM may be accommodated in the internal space (for example, may be located in the internal space). The housing HU may include (for example, may be) a material having high rigidity (for example, relatively high rigidity). For example, the housing HU may include (for example, may be) glass, plastic, and / or metal, or may include a plurality of frames and / or plates, the plurality of frames and / or plates including a combination of glass, plastic, and / or metal (for example, consisting of a combination of glass, plastic, and / or metal). The housing HU can safely protect the components of the display device DD accommodated in the internal space (for example, located in the internal space) from the influence of external shocks.

[0053] In some embodiments, a battery module or the like may be disposed between the display module DM and the housing HU, and the battery module is used to supply power required for the overall operation of the display device DD.

[0054] Referring to Figure 1B and Figure 2 , the display module DM according to an embodiment may include a display panel DP and an input sensing unit ISU.

[0055] The display panel DP may display an image IM according to an electrical signal (shown in Figure 1A ), and the input sensing unit ISU may sense a user input TC applied from the outside (in Figure 1AAs shown in []. The user input TC may include various suitable types or kinds of input provided from outside the display device DD. In addition to contact by a part of the body (such as the user's hand), the user input TC may also include input applied near or adjacent to the display device DD at a predetermined or set distance (e.g., hovering). Further, the user input TC may include various suitable types or kinds of input such as force, pressure, temperature, and / or light.

[0056] Referring to Figure 2 , the display panel DP includes a substrate layer BL, a display circuit layer DP-CL, a display element layer DP-OLED, and a packaging layer (or a so-called thin film encapsulation layer) TFE.

[0057] The substrate layer BL may include a synthetic resin layer. The synthetic resin layer is formed on a working substrate for manufacturing the display panel DP. Thereafter, a conductive layer, an insulating layer, etc. are formed on the synthetic resin layer. When the working substrate is removed, the synthetic resin layer corresponds to the substrate layer BL. The synthetic resin layer may be a polyimide resin layer, and its material is not limited thereto. In addition, the substrate layer BL may include a glass substrate, a metal substrate, an organic / inorganic composite substrate, etc.

[0058] The display circuit layer DP-CL is disposed on the substrate layer BL. The display circuit layer DP-CL includes circuit elements and at least one insulating layer. Hereinafter, the insulating layer included in the display circuit layer DP-CL is referred to as an intermediate insulating layer. The intermediate insulating layer includes at least one intermediate inorganic film and at least one intermediate organic film. The circuit elements include signal lines, pixel driving circuits, etc. The display circuit layer DP-CL may be formed via processes of forming an insulating layer, a semiconductor layer, and a conductive layer by coating, deposition, etc. and via a process of patterning the insulating layer, the semiconductor layer, and the conductive layer by a photolithography process.

[0059] The display element layer DP-OLED may include light-emitting elements (e.g., organic light-emitting elements) and a pixel defining film. The display element layer DP-OLED will be described in more detail later with reference to Figure 6B More specifically, the display element layer DP-OLED will be described.

[0060] The packaging layer TFE encapsulates (e.g., covers) the display element layer DP-OLED. The packaging layer TFE may include at least one organic film and at least one inorganic film. The (one or more) inorganic films may protect the display element layer DP-OLED from the influence of moisture and / or oxygen. The (one or more) inorganic films may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, etc., and are not limited thereto.

[0061] The input sensing unit ISU may be directly disposed on the display panel DP. According to an embodiment, the input sensing unit ISU may be directly disposed on the encapsulation layer TFE. As used herein, "directly disposed on..." excludes attachment via a separate adhesive layer. For example, the input sensing unit ISU directly disposed on the display panel DP may be formed with the display panel DP through a continuous process (e.g., during a continuous process).

[0062] The input sensing unit ISU includes sensing electrodes and sensing lines. The sensing electrodes and sensing lines may have a single-layer structure or a multi-layer structure. The input sensing unit ISU will be described in more detail later with reference to Figure 6B more detail.

[0063] Figure 3 is a block diagram of a display device according to an embodiment of the present disclosure, Figure 4A is Figure 3 a block diagram of the first driver and the display panel shown in Figure 4B is Figure 4A an equivalent circuit diagram of one pixel among the pixels shown in Figure 5 is a waveform diagram showing drive signals for driving the pixels shown in Figure 4B Herein.

[0064] Referring to Figure 3 and Figure 4A , the display device DD further includes a first driver 200, a second driver 300, and a controller 100. The first driver 200 controls the driving of the display panel DP, and the second driver 300 controls the driving of the input sensing unit ISU. The first driver 200 may include a gate driver 210 and a data driver 220.

[0065] The controller 100 controls the driving of the first driver 200 and the second driver 300. The controller 100 generates image data RGB by converting the data format of the input image signal according to the interface specification between the controller 100 and the data driver 220. The controller 100 outputs the image data RGB and various control signals DCS and GCS.

[0066] The gate driver 210 receives a gate control signal GCS from the controller 100. The gate control signal GCS may include a vertical start signal STV for starting the operation of the gate driver 210 ( Figure 5as shown in FIG. 0), a clock signal for determining when to output a signal, etc. The gate driver 210 generates a plurality of gate signals and sequentially outputs the plurality of gate signals to a plurality of gate lines GIL1 to GILn and GWL1 to GWLn, which will be described later. In addition, the gate driver 210 generates a plurality of light emission control signals in response to the gate control signal GCS and outputs the plurality of light emission control signals to a plurality of light emission control lines EL1 to ELn, which will be described later.

[0067] Although Figure 4A a plurality of gate signals and a plurality of light emission control signals output from one gate driver 210 are shown, embodiments of the present disclosure are not limited thereto. As an embodiment of the present disclosure, a driving circuit for generating and outputting a plurality of gate signals and a driving circuit for generating and outputting a plurality of light emission control signals may be separately provided.

[0068] The data driver 220 receives the data control signal DCS and the image data RGB from the controller 100. The data driver 220 converts the image data RGB into a data signal and outputs the data signal to a plurality of data lines DL1 to DLm, which will be described later. The data signal is an analog voltage corresponding to the gradation value of the image data RGB.

[0069] The display panel DP includes a plurality of gate lines GIL1 to GILn and GWL1 to GWLn, a plurality of light emission control lines EL1 to ELn, a plurality of data lines DL1 to DLm, and a plurality of pixels PX. The plurality of gate lines GIL1 to GILn and GWL1 to GWLn extend in a first direction DR1 and are arranged in a second direction DR2 perpendicular to the first direction DR1. Each of the plurality of light emission control lines EL1 to ELn may be disposed side by side with a corresponding gate line among the plurality of gate lines GIL1 to GILn and GWL1 to GWLn. For example, each of the plurality of light emission control lines EL1 to ELn may extend in the first direction DR1 and may be adjacent to a corresponding gate line among the plurality of gate lines GIL1 to GILn and GWL1 to GWLn. The plurality of data lines DL1 to DLm cross the plurality of gate lines GIL1 to GILn and GWL1 to GWLn in an insulating manner. For example, the data lines DL1 to DLm may be electrically insulated from the gate lines GIL1 to GILn and GWL1 to GWLn.

[0070] Each of the plurality of pixels PX is connected to a corresponding gate line among the plurality of gate lines GIL1 to GILn and GWL1 to GWLn, a corresponding light emission control line among the plurality of light emission control lines EL1 to ELn, and a corresponding data line among the plurality of data lines DL1 to DLm. Although Figure 4AAn example is shown in which each of a plurality of pixels PX is connected to two of a plurality of gate lines GIL1 to GILn and GWL1 to GWLn, but embodiments of the present disclosure are not limited thereto. For example, each pixel PX may be connected to three of a plurality of gate lines GIL1 to GILn and GWL1 to GWLn.

[0071] The display panel DP receives a first driving voltage ELVDD and a second driving voltage ELVSS. The first driving voltage ELVDD may be supplied to the plurality of pixels PX through a first power line PL1. The second driving voltage ELVSS may be supplied to the plurality of pixels PX through an electrode formed in the display panel DP or through a second power line PL2 (shown in Figure 4B .

[0072] The display panel DP receives an initialization voltage Vint. The initialization voltage Vint may be supplied to the plurality of pixels PX through an initialization voltage line VIL.

[0073] Referring to Figure 4B , each of the plurality of pixels PX includes a light-emitting element OLED and a circuit unit CC for controlling the light emission of the light-emitting element OLED. The plurality of pixels PX may include red pixels that emit red light, green pixels that emit green light, and blue pixels that emit blue light. The light-emitting element OLED in each red pixel, the light-emitting element OLED in each green pixel, and the light-emitting element OLED in each blue pixel may include an organic light-emitting layer having materials different from each other (for example, including materials different from each other or consisting of materials different from each other).

[0074] The circuit unit CC may include a plurality of transistors T1 to T7 and a capacitor CP. The plurality of transistors T1 to T7 and the capacitor CP may control the amount of current flowing into the light-emitting element OLED in response to corresponding data signals in the data signals and corresponding gate signals in the gate signals.

[0075] Each of the plurality of transistors T1 to T7 may include an input electrode (or source electrode), an output electrode (or drain electrode), and a control electrode (or gate electrode). In this specification, for convenience, one of the input electrode and the output electrode may be referred to as the first electrode, and the other may be referred to as the second electrode. Hereinafter, for ease of description, the plurality of transistors T1 to T7 are respectively referred to as the first transistor T1 to the seventh transistor T7.

[0076] The first electrode of the first transistor T1 may be connected to the first power line PL1 via the fifth transistor T5. The first driving voltage ELVDD is supplied to the first power line PL1. The second electrode of the first transistor T1 is connected to the anode of the light-emitting element OLED via the sixth transistor T6.

[0077] The first transistor T1 can control the amount of current flowing into the light-emitting element OLED in response to a voltage applied to the control electrode of the first transistor T1.

[0078] The second transistor T2 is connected between the first data line DL1 and the first electrode of the first transistor T1. The control electrode of the second transistor T2 is connected to the first current gate line GWL1. When the first current gate signal is provided to the first current gate line GWL1, the second transistor T2 is turned on to electrically connect the first data line DL1 to the first electrode of the first transistor T1.

[0079] The third transistor T3 is connected between the second electrode of the first transistor T1 and the control electrode of the first transistor T1. The control electrode of the third transistor T3 is connected to the first current gate line GWL1. When the first current gate signal is provided to the first current gate line GWL1, the third transistor T3 is turned on to electrically connect the second electrode of the first transistor T1 to the control electrode of the first transistor T1. Thus, when the third transistor T3 is turned on, the first transistor T1 is connected in the form of a diode.

[0080] The fourth transistor T4 is connected between the node ND and the initialization voltage line VIL. The control electrode of the fourth transistor T4 is connected to the first previous gate line GIL1. The node ND can be the control electrode of the first transistor T1 and the node to which the fourth transistor T4 is connected. When the first previous gate signal is provided to the first previous gate line GIL1, the fourth transistor T4 is turned on to supply the initialization voltage Vint to the node ND.

[0081] The fifth transistor T5 is connected between the first power line PL1 and the first electrode of the first transistor T1. The sixth transistor T6 is connected between the second electrode of the first transistor T1 and the anode of the light-emitting element OLED. The control electrodes of the fifth transistor T5 and the sixth transistor T6 are connected to the first light emission control line EL1.

[0082] The seventh transistor T7 is connected between the initialization voltage line VIL and the anode of the light-emitting element OLED. The control electrode of the seventh transistor T7 is connected to the first current gate line GWL1. When the first current gate signal is provided to the first current gate line GWL1, the seventh transistor T7 is turned on to supply the initialization voltage Vint to the anode of the light-emitting element OLED.

[0083] The seventh transistor T7 can improve the black display ability of the pixel PX. For example, when the seventh transistor T7 is turned on, the parasitic capacitor of the light-emitting element OLED is discharged. Then, when implementing black luminance, the light-emitting element OLED does not emit light regardless of the leakage current from the first transistor T1, so the black display ability can be improved.

[0084] In addition, although the control electrode of the seventh transistor T7 is shown as being connected to the first current gate line GWL1 in Figure 4B , embodiments of the present disclosure are not limited thereto. For example, the control electrode of the seventh transistor T7 may be connected to another gate line that provides a gate signal different from the first current gate signal (e.g., Figure 4A the second current gate line GWL2 shown in

[0085] Although the first transistor T1 to the seventh transistor T7 are shown as PMOS transistors in Figure 4B , the first transistor T1 to the seventh transistor T7 are not limited thereto. For example, some or all of the first transistor T1 to the seventh transistor T7 included in the circuit unit CC (e.g., constituting the circuit unit CC) may be composed of NMOS transistors (e.g., may be NMOS transistors).

[0086] A capacitor CP is provided between the first power line PL1 and the node ND. The capacitor CP stores a voltage corresponding to the corresponding data signal. When the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current flowing through the first transistor T1 can be determined according to the voltage stored in the capacitor CP.

[0087] The light-emitting element OLED may be electrically connected to the sixth transistor T6 and the second power line PL2. The anode of the light-emitting element OLED is connected to the sixth transistor T6, and the cathode of the light-emitting element OLED is connected to the second power line PL2. The second driving voltage ELVSS may be applied to the second power line PL2. The second driving voltage ELVSS is lower than the first driving voltage ELVDD. Therefore, the light-emitting element OLED can emit light according to a voltage corresponding to the difference between the signal (e.g., voltage) transmitted through the sixth transistor T6 and the second driving voltage ELVSS received through the second power line PL2.

[0088] Referring to Figure 5 , the display device DD displays a unit image for each of the frame periods Fk-1, Fk, and Fk+1. Figure 4A Each of the pixels PX shown in

[0089] Figure 5 receives a corresponding data signal for each of the frame periods Fk-1, Fk, and Fk+1. Figure 4B The frame periods Fk-1, Fk, and Fk+1 of the pixel PX shown in

[0090] The k-th frame period Fk includes a blank period FBk and BBk and a display period Dk. The blank periods FBk and BBk can be respectively set (e.g., occur) between the display period Dk-1 and the display period Dk and between the display period Dk and the display period Dk+1. The blank periods FBk and BBk can be defined as periods during which the pixel PX does not operate. The blank periods FBk and BBk can include a front blank period FBk set (e.g., occurring) before the display period Dk and a back blank period BBk set (e.g., occurring) after the display period Dk.

[0091] The display period Dk can include a scanning period SPk and an emission period EPk. The first gate signal GIS1 to the n-th gate signal GISn are activated during the scanning period SPk. In this embodiment, Figure 5 the first gate signal GIS1 to the n-th gate signal GISn shown in is described as being activated when it has a low level. Figure 5 The low level of the first gate signal GIS1 to the n-th gate signal GISn shown in can be the turn-on voltage of the transistor to which the corresponding signal among the first gate signal GIS1 to the n-th gate signal GISn is applied. For example, Figure 5 the low level of each of the first gate signal GIS1 to the n-th gate signal GISn shown in can be the turn-on voltage of the corresponding transistor to which the gate signal is applied. The first gate signal GIS1 to the n-th gate signal GISn can be sequentially activated during the scanning period SPk.

[0092] The scanning period SPk can start at the rising edge of the vertical start signal STV (e.g., at the start point of the pulse). When the scanning period SPk has started, the first gate signal GIS1 is first activated. For example, the first gate signal GIS1 can be first activated among the first gate signal GIS1 to the n-th gate signal GISn, and the first gate signal GIS1 can be activated at the moment when the scanning period SPk starts or after the moment when the scanning period SPk starts. Through the activated first gate signal GIS1, the node ND can be initialized to the initialization voltage Vint. The first gate signal GIS1 is the gate signal applied to the first previous gate line GIL1.

[0093] Thereafter, the second gate signal GIS2 applied to the second previous gate line GIL2 is activated during the scanning period SPk. The second transistor T2 and the third transistor T3 are turned on by the second gate signal GIS2, and the data signal applied to the first data line DL1 is provided to the first electrode of the first transistor T1. In some embodiments, the second previous gate line GIL2 is connected to the first current gate line GWL1 (as Figure 4A shown).

[0094] When the n-th gate signal GISn applied to the n-th previous gate line GILn is activated, the scan period SPk ends and the emission period EPk starts. For example, at a moment corresponding to the end of the moment when the n-th gate signal GISn is applied to the n-th previous gate line GILn, the scan period SPk may end and the emission period EPk may start. During the emission period EPk, a current path is formed in response to the emission control signal ES between the node ND and the light-emitting element OLED. For example, during the emission period EPk, a current path may be formed between the first power line PL1 and the light-emitting element OLED. The emission control signal ES has a low level during the emission period EPk. As a result, the light-emitting element OLED emits light during the emission period EPk. The emission control signal ES is deactivated during the scan period SPk. For example, the emission control signal ES has a high level during the scan period SPk.

[0095] Figure 6A is a block diagram showing Figure 3 the configuration of the second driver and the input sensing unit shown in Figure 6B is a cross-sectional view showing the structure of a display panel and an input sensing unit according to an embodiment of the present disclosure.

[0096] Referring to Figure 6A and Figure 6B According to an embodiment of the present disclosure, the input sensing unit ISU may include first sensing electrodes IE1-1 to IE1-5, first sensing lines SL1-1 to SL1-5 respectively connected to the first sensing electrodes IE1-1 to IE1-5, second sensing electrodes IE2-1 to IE2-4, and second sensing lines SL2-1 to SL2-4 respectively connected to the second sensing electrodes IE2-1 to IE2-4. The first sensing electrodes IE1-1 to IE1-5 cross the second sensing electrodes IE2-1 to IE2-4. The first sensing electrodes IE1-1 to IE1-5 are arranged along the second direction DR2, and each of the first sensing electrodes IE1-1 to IE1-5 extends along the first direction DR1.

[0097] Each of the first sensing electrodes IE1-1 to IE1-5 includes a corresponding first sensing portion SP1 in the first sensing portion SP1 and a corresponding first connection portion CP1 in the first connection portion CP1. Each of the first sensing portion SP1 and each of the first connection portion CP1 are provided in the active area AA. Each of the second sensing electrodes IE2-1 to IE2-4 includes a corresponding second sensing portion SP2 in the second sensing portion SP2 and a corresponding second connection portion CP2 in the second connection portion CP2. Each of the second sensing portion SP2 and each of the second connection portion CP2 are provided in the active area AA.

[0098] Figure 6AThe first sensing electrodes IE1-1 to IE1-5 and the second sensing electrodes IE2-1 to IE2-4 according to an embodiment are shown, but the shapes of the first sensing electrodes IE1-1 to IE1-5 and the second sensing electrodes IE2-1 to IE2-4 are not limited thereto. In an embodiment of the present disclosure, the first sensing electrodes IE1-1 to IE1-5 and the second sensing electrodes IE2-1 to IE2-4 may have a shape that does not distinguish each sensor (sensing part) and each connector (connecting part) therefrom (e.g., a bar shape). Although exemplarily shown as having a diamond shape, the first sensing part SP1 and the second sensing part SP2 are not limited thereto and may have any suitable shape (including different polygonal shapes).

[0099] The first sensing parts SP1 of one of the first sensing electrodes IE1-1 to IE1-5 are arranged along a first direction DR1, and the second sensing parts SP2 of one of the second sensing electrodes IE2-1 to IE2-4 are arranged along a second direction DR2. Each first connecting part CP1 connects adjacent first sensing parts SP1, and each second connecting part CP2 connects adjacent second sensing parts SP2.

[0100] The first sensing electrodes IE1-1 to IE1-5 and the second sensing electrodes IE2-1 to IE2-4 may have a mesh shape. Since the first sensing electrodes IE1-1 to IE1-5 and the second sensing electrodes IE2-1 to IE2-4 have a mesh shape, the parasitic capacitance with the electrodes AE and CE of the display panel DP can be reduced. For example, the parasitic capacitance between the first sensing electrodes IE1-1 to IE1-5 and the second sensing electrodes IE2-1 to IE2-4 of the input sensing unit ISU and the electrodes AE and CE of the display panel DP can be reduced. In addition, since the first sensing electrodes IE1-1 to IE1-5 and the second sensing electrodes IE2-1 to IE2-4 do not overlap with the light-emitting layer EML, they may not be visible to the user of the display device DD.

[0101] The first sensing lines SL1-1 to SL1-5 are respectively connected to the first ends of the first sensing electrodes IE1-1 to IE1-5. The second sensing lines SL2-1 to SL2-4 are respectively connected to the first ends of the second sensing electrodes IE2-1 to IE2-4. In an embodiment of the present disclosure, the first sensing lines SL1-1 to SL1-5 may also be respectively connected to the second ends (e.g., the ends opposite to the first ends) of the first sensing electrodes IE1-1 to IE1-5. In addition, the second sensing lines SL2-1 to SL2-4 may also be respectively connected to the second ends (e.g., opposite ends) of the second sensing electrodes IE2-1 to IE2-4. The first sensing lines SL1-1 to SL1-5 and the second sensing lines SL2-1 to SL2-4 may be disposed in the peripheral area NAA.

[0102] The second driver 300 may include a sense line driver 310 and a readout unit 320. The sense line driver 310 may be electrically connected to the first ends of the first sense lines SL1-1 to SL1-5, and the readout unit 320 may be electrically connected to the first ends of the second sense lines SL2-1 to SL2-4.

[0103] The sense line driver 310 may sequentially output sense signals to the first sense lines SL1-1 to SL1-5 for each sense frame period. The sense signals output from the sense line driver 310 may be applied to the first sensing electrodes IE1-1 to IE1-5 through the first sense lines SL1-1 to SL1-5.

[0104] The readout unit 320 may receive output signals read from the second sense lines SL2-1 to SL2-4. For example, when sense signals are applied to the first sensing electrodes IE1-1 to IE1-5, a capacitance is formed between the first sensing electrodes IE1-1 to IE1-5 and the second sensing electrodes IE2-1 to IE2-4. When a user input TC (shown in Figure 1A is received), the capacitance between the first sensing electrodes IE1-1 to IE1-5 and the second sensing electrodes IE2-1 to IE2-4 may be changed in the area of the input sensing unit ISU (e.g., the area corresponding to the user input TC (such as the position of the user's touch)). The readout unit 320 may receive such a capacitance change as an output signal. For example, the capacitance change may be provided to the readout unit 320 through the second sense lines SL2-1 to SL2-4.

[0105] In a display device according to an embodiment of the present disclosure, the input sensing unit ISU may be directly disposed on the display panel DP.

[0106] As Figure 6B shown, the display element layer DP-OLED may include a pixel defining film PDL and a light emitting element OLED (e.g., an organic light emitting diode). The pixel defining film PDL may include (e.g., may be) an organic material. The first electrode AE is disposed on the display circuit layer DP-CL. The pixel defining film PDL is formed on the first electrode AE. For example, the pixel defining film PDL may be on the display circuit layer DP-CL and may cover a part (e.g., side (lateral part)) of the first electrode AE. An opening OP is defined in the pixel defining film PDL. The opening OP of the pixel defining film PDL exposes at least a part of the first electrode AE. In an embodiment of the present disclosure, the pixel defining film PDL may be omitted.

[0107] The display panel DP may include a light-emitting region PXA and a non-light-emitting region NPXA adjacent to the light-emitting region PXA. The light-emitting region PXA may be provided in plurality. The non-light-emitting region NPXA may surround the light-emitting region PXA. In the present embodiment, the light-emitting region PXA is defined to correspond to a portion of the first electrode AE exposed by the opening OP.

[0108] The hole control layer HCL may be commonly provided in the light-emitting region PXA and the non-light-emitting region NPXA. For example, the hole control layer HCL may be on the first electrode AE and the pixel defining film PDL (e.g., may cover the first electrode AE and the pixel defining film PDL). The light-emitting layer EML is provided on the hole control layer HCL. The light-emitting layer EML may be provided in a region corresponding to the opening OP. Thus, the light-emitting layer EML may be individually formed in each pixel PX. The light-emitting layer EML may include (e.g., may be) an organic material and / or an inorganic material. The light-emitting layer EML may generate light of a predetermined color or a set color.

[0109] Although the light-emitting layer EML is shown as being patterned in the present embodiment, the light-emitting layer EML may be provided in the light-emitting region PXA (e.g., the entire light-emitting region PXA). In some embodiments, the light-emitting layer EML may be formed by a method of forming a layer (e.g., a layer including an organic material and / or an inorganic material) on the hole control layer HCL and then patterning the layer to form the light-emitting layer EML. In some embodiments, the light-emitting layer EML may be formed by a method of forming an organic material and / or an inorganic material in the light-emitting region PXA (e.g., the entire light-emitting region PXA). In this case, the light-emitting layer EML may generate white light. In addition, the light-emitting layer EML may have a multi-layer structure referred to as tandem (or referred to as "cascaded").

[0110] The electron control layer ECL is provided on the light-emitting layer EML. The electron control layer ECL may be commonly formed in the light-emitting region PXA and the non-light-emitting region NPXA. The second electrode CE is provided on the electron control layer ECL. The second electrode CE is commonly provided in the pixel PX.

[0111] The encapsulation layer TFE is provided on the second electrode CE. The encapsulation layer TFE encapsulates (e.g., covers) the display element layer DP-OLED. The encapsulation layer TFE includes at least one insulating layer. The encapsulation layer TFE according to an embodiment of the present disclosure may include at least one inorganic film (hereinafter, referred to as an encapsulation inorganic film). The encapsulation layer TFE according to an embodiment of the present disclosure may include at least one organic film (hereinafter, referred to as an encapsulation organic film) and at least one encapsulation inorganic film. In some embodiments, the encapsulation inorganic film may be at the top of the encapsulation layer TFE.

[0112] The encapsulation inorganic film protects the display element layer DP - OLED from moisture and / or oxygen, and the encapsulation organic film protects the display element layer DP - OLED from foreign substances such as dust particles. The encapsulation inorganic film may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, etc., and is not limited thereto. The encapsulation organic film may include an acrylic organic film, and is not limited thereto.

[0113] The input sensing unit ISU according to an embodiment of the present disclosure includes a substrate layer IL1, a first conductive layer and a second conductive layer disposed on the substrate layer IL1, and a first insulating layer IL2 and a second insulating layer IL3. The substrate layer IL1 may include (for example, may be) an inorganic material, and may include, for example, a silicon nitride layer. The inorganic film (for example, the encapsulation inorganic film) disposed on the top of the encapsulation layer TFE may also include (for example, may be) silicon nitride, and the silicon nitride layer of the encapsulation layer TFE and the substrate layer IL1 may be formed under different deposition conditions.

[0114] The first conductive layer is disposed on the substrate layer IL1. The first conductive layer may include a first sensing portion SP1, a second sensing portion SP2, and a second connection portion CP2. The second conductive layer is disposed on the first conductive layer. The second conductive layer may include a first connection portion CP1. The first insulating layer IL2 is disposed between the first conductive layer and the second conductive layer. When viewed in cross - section, the first conductive layer and the second conductive layer are spaced apart and separated from each other by the first insulating layer IL2. Contact holes for partially exposing the first sensing portion SP1 may be provided in the first insulating layer IL2, and the first connection portion CP1 may be connected to the first sensing portion SP1 through the contact holes. The second insulating layer IL3 is disposed on the first insulating layer IL2. The second insulating layer IL3 may cover the second conductive layer. The second insulating layer IL3 protects the second conductive layer from the external environment.

[0115] The first sensing portion SP1 does not overlap with the light - emitting region PXA, and the first sensing portion SP1 overlaps with the non - light - emitting region NPXA. The grid lines of the first sensing portion SP1 may define a plurality of grid holes. The grid lines may have a three - layer structure of titanium / aluminum / titanium. The grid holes may correspond one - to - one with the light - emitting regions PXA. However, the embodiments of the present disclosure are not limited thereto. For example, each grid hole may correspond to two or more light - emitting regions PXA.

[0116] An anti-reflection panel RPP may be disposed on an input sensing unit ISU. As an example, the anti-reflection panel RPP may include a polarizing film. In addition to the polarizing film, the anti-reflection panel RPP may further include a protective film and additional functional films. A first adhesive film AF1 may be disposed between the anti-reflection panel RPP and the input sensing unit ISU. Accordingly, the anti-reflection panel RPP may be bonded to the input sensing unit ISU through the first adhesive film AF1. A window WP may be bonded to the anti-reflection panel RPP through a second adhesive film AF2. The first adhesive film AF1 and the second adhesive film AF2 may include an optically clear adhesive.

[0117] Figure 7A is a block diagram showing a controller according to an embodiment of the present disclosure. Figure 7B is a waveform diagram showing n frame periods included in a reference period according to an embodiment of the present disclosure, Figure 7C is a diagram showing Figure 7B a waveform diagram of each of the n frame periods shown in

[0118] Referring to Figure 4A and Figure 7A , the controller 100 provides a gate control signal GCS to the gate driver 210. The gate control signal GCS may include a vertical start signal STV, a gate clock signal CK, an inverted gate clock signal CKB, etc. The controller 100 provides a sensing start signal BSYNC to the sensing line driver 310.

[0119] The controller 100 may receive a vertical synchronization signal VSYNC and a main clock signal MCLK from the outside. The controller 100 may generate a gate clock signal CK and an inverted gate clock signal CKB based on the main clock signal MCLK, and may generate a vertical start signal STV and a sensing start signal BSYNC based on the vertical synchronization signal VSYNC.

[0120] As an embodiment of the present disclosure, the controller 100 may include a blank period determination unit 110. The blank period determination unit 110 may vary the durations of the blank periods FBk and BBk by randomly adjusting the output timing of the vertical start signal STV during a preset or set reference period T-ref. For example, the blank period determination unit 110 may control the durations of the blank periods FBk and BBk. For example, the blank period determination unit 110 may randomly adjust the output timing of the vertical start signal STV such that the durations of the blank periods FBk and BBk are randomly set (e.g., randomly set within a set range).

[0121] As Figure 7BAs shown in [Figure], the reference period T-ref may include n frame periods F1 to Fn (hereinafter referred to as the first frame period F1 to the nth frame period Fn). Here, n may be a natural number of 1 or greater. For example, in the case where the display panel DP (shown in Figure 4A operates at a frequency of approximately 60 Hz, when the duration of the reference period T-ref is set to approximately one second, the reference period T-ref may include approximately 60 frame periods. As another example, in the case where the display panel DP operates at approximately 120 Hz, when the duration of the reference period T-ref is set to approximately one second, the reference period T-ref may include approximately 120 frame periods. In the case where the display panel DP operates at approximately 120 Hz, when the duration of the reference period T-ref is set to approximately 0.5 seconds, the reference period T-ref may include approximately 60 frame periods. However, the duration of the reference period T-ref and the number of frame periods included in the reference period T-ref are not limited thereto and may be variously and appropriately changed.

[0122] The first frame period F1 to the nth frame period Fn may have different durations in the reference period T-ref. For example, the durations of the first frame period F1 to the nth frame period Fn may be randomly changed in the reference period T-ref. For example, the duration of each of the first frame period F1 to the nth frame period Fn may be randomly set within a set range.

[0123] The first frame period F1 may include a first front blanking period FB1, a first display period D1, and a first back blanking period BB1. The second frame period F2 may include a second front blanking period FB2, a second display period D2, and a second back blanking period BB2. In addition, the nth frame period Fn may include an nth front blanking period FBn, an nth display period Dn, and an nth back blanking period BBn.

[0124] As an example of the present disclosure, the first front blanking period FB1 to the nth front blanking period FBn may have different durations. The sum of the durations of the first front blanking period FB1 to the nth front blanking period FBn may be equal to the sum of the durations of n reference front blanking periods. Here, the duration of each reference front blanking period may be defined as the average of the durations of the first front blanking period FB1 to the nth front blanking period FBn.

[0125] On the other hand, the first display period D1 to the nth display period Dn may have the same duration, and the first post blanking period BB1 to the nth post blanking period BBn may have the same duration. Therefore, since the first pre blanking period FB1 to the nth pre blanking period FBn have durations that vary randomly in the reference period T-ref, the durations of the first frame period F1 to the nth frame period Fn may vary randomly in the reference period T-ref.

[0126] Referring to Figure 7C , the duration of each of the first pre blanking period FB1 to the nth pre blanking period FBn may be determined according to the output timing of the vertical start signal STV.

[0127] At the first rising edge of the vertical start signal STV (e.g., at the start point of the first pulse), the first display period D1 of the first frame period F1 may start. The first pre blanking period FB1 has a first duration Tf1 in the first frame period F1. At the second rising edge of the vertical start signal STV (e.g., at the start point of the second pulse), the second display period D2 of the second frame period F2 may start. In the second frame period F2, the second pre blanking period FB2 has a second duration Tf2 that may be different from the first duration Tf1. For example, the second duration Tf2 may be larger than the first duration Tf1. At the nth rising edge of the vertical start signal STV (e.g., at the start point of the nth pulse), the nth display period Dn of the nth frame period Fn may start. In the nth frame period Fn, the nth pre blanking period FBn has an nth duration Tfn that may be different from the first duration Tf1 and the second duration Tf2. For example, the nth duration Tfn may be larger than the first duration Tf1 and may be smaller than the second duration Tf2.

[0128] The durations Tf1 to Tfn of the first pre blanking period FB1 to the nth pre blanking period FBn may have at least one value among i preset or set values (i is a natural number of two or more). When i is equal to n, the durations Tf1 to Tfn of the first pre blanking period FB1 to the nth pre blanking period FBn may have different values. However, when i is less than n, at least two of the first pre blanking period FB1 to the nth pre blanking period FBn may have the same duration.

[0129] The first display period D1 to the nth display period Dn may have the same duration, and the first post blanking period BB1 to the nth post blanking period BBn may have the same duration. In this case, the durations of the first frame period F1 to the nth frame period Fn may vary according to the durations of the first pre blanking period FB1 to the nth pre blanking period FBn. Therefore, the durations of the first frame period F1 to the nth frame period Fn may be randomly changed in the reference period T-ref. The sum of the durations of the first frame period F1 to the nth frame period Fn may be equal to the sum of the durations of n reference frame periods. Here, the duration of each reference frame period may be determined according to the driving frequency of the display panel DP. For example, when the driving frequency is about 60 Hz, the duration of the reference frame period may be set to about 16.7 ms (which is about 1 / 60 (1 / 60 s) of the reference period T-ref). For example, when the driving frequency is about 60 Hz and the duration of the reference period T-ref is about 1 s, the duration of the reference frame period may be set to about 16.7 ms (which is about 1 / 60 s).

[0130] As Figure 7C shown, the reference period T-ref may include n sensing frame periods SF1 to SFn (hereinafter, referred to as the first sensing frame period SF1 to the nth sensing frame period SFn). For example, in Figure 7C it is shown that the driving frequency of the display panel DP and the driving frequency of the input sensing unit ISU are the same, but the embodiments of the present disclosure are not limited thereto. When the driving frequency of the display panel DP and the driving frequency of the input sensing unit ISU are the same, the number of sensing frame periods SF1 to SFn included in the reference period T-ref may be the same as the number of frame periods F1 to Fn included in the reference period T-ref. However, when the driving frequency of the display panel DP and the driving frequency of the input sensing unit ISU are different, the number of sensing frame periods SF1 to SFn included in the reference period T-ref may be different from the number of frame periods F1 to Fn included in the reference period T-ref. For example, when the display panel DP is driven at about 120 Hz and the input sensing unit ISU is driven at about 60 Hz, the reference period T-ref may include n frame periods F1 to Fn and n / 2 (1 / 2×n) sensing frame periods.

[0131] Each sensing period SD, each front porch period FP, and each back porch period BP may be included in a corresponding one of the sensing frame periods SF1 to SFn. The edge periods FP and BP may be set (e.g., occur) between the sensing periods SD and may be defined as periods during which the input sensing unit ISU does not operate. The edge periods FP and BP may include a front porch period FP set (e.g., occurring) before the sensing period SD and a back porch period BP set (e.g., occurring) after the sensing period SD.

[0132] The sensing period SD may include a sensing signal output period SSP and a readout period ROP. The first sensing signals SS1-1 to the L-th sensing signal SS1-L are activated during the sensing signal output period SSP. The first sensing signals SS1-1 to the L-th sensing signal SS1-L may be output from the sensing line driver 310 and may be sequentially provided to the first sensing lines SL1-1 to SL1-L provided in the input sensing unit ISU. In some embodiments, the number L may be 5, and the first sensing lines SL1-1 to SL1-L may correspond to Figure 6A the first sensing lines SL1-1 to SL1-5 shown in. In this embodiment, Figure 7C the first sensing signals SS1-1 to the L-th sensing signal SS1-L shown in are described as being activated when the first sensing signals SS1-1 to the L-th sensing signal SS1-L have a high level. The first sensing signals SS1-1 to the L-th sensing signal SS1-L may be sequentially activated during the sensing signal output period SSP.

[0133] When the start time of the sensing period SD coincides with the start time of the display periods D1 to Dn, the coupling capacitance between the input sensing unit ISU and the display panel DP increases, and thus, a phenomenon in which the brightness of the pixel rows of the display panel DP decreases may occur. When the start time of the sensing period SD and the start times of the display periods D1 to Dn always coincide in dozens or hundreds of frame periods, the positions of the pixel rows whose brightness decreases do not change, and thus, horizontal line blot may appear in the display panel DP.

[0134] However, according to embodiments of the present disclosure, the start times of display periods D1 to Dn vary randomly during a reference period T-ref. Accordingly, during the reference period T-ref, a situation where the start time of the sensing period SD coincides with the start times of the display periods D1 to Dn and a situation where the start time of the sensing period SD does not coincide with the start times of the display periods D1 to Dn may occur randomly. In this case, although the phenomenon of the brightness reduction of pixel rows may not be completely eliminated, the positions of the pixel rows with reduced brightness may change for each frame period. Therefore, since the positions of the pixel rows with reduced brightness are spatially dispersed for each frame period, the phenomenon of horizontal line streaks appearing in the display panel DP can be prevented or reduced. For example, the positions of the pixel rows with reduced brightness may vary randomly for each frame period.

[0135] Figure 8 is a waveform diagram showing n frame periods included in a reference period according to an embodiment of the present disclosure.

[0136] Referring to Figure 8 , the first frame period F1 to the nth frame period Fn may have different durations in the reference period T-ref. For example, the durations of the first frame period F1 to the nth frame period Fn may vary randomly in the reference period T-ref.

[0137] The first frame period F1 may include a first front blank period FB1, a first display period D1, and a first back blank period BB1. The second frame period F2 may include a second front blank period FB2, a second display period D2, and a second back blank period BB2. In addition, the nth frame period Fn may include an nth front blank period FBn, an nth display period Dn, and an nth back blank period BBn.

[0138] As an example of the present disclosure, the first back blank period BB1 to the nth back blank period BBn may have different durations. The sum of the durations of the first back blank period BB1 to the nth back blank period BBn may be equal to the sum of the durations of n reference back blank periods. Here, the duration of each reference back blank period may be defined as the average of the durations of the first back blank period BB1 to the nth back blank period BBn.

[0139] The first display period D1 to the nth display period Dn may have the same duration, and the first front blank period FB1 to the nth front blank period FBn may have the same duration. Therefore, since the first back blank period BB1 to the nth back blank period BBn have randomly varying durations in the reference period T-ref, the durations of the first frame period F1 to the nth frame period Fn may vary randomly in the reference period T-ref.

[0140] The first post-blank period BB1 has a first duration Tb1 in the first frame period F1. In the second frame period F2, the second post-blank period BB2 has a second duration Tb2 that can be different from the first duration Tb1. For example, the second duration Tb2 can be greater than the first duration Tb1. In the nth frame period Fn, the nth post-blank period BBn has an nth duration Tbn that can be different from the first duration Tb1 and the second duration Tb2. For example, the nth duration Tbn can be greater than the first duration Tb1 and can be less than the second duration Tb2.

[0141] The durations Tb1 to Tbn of the first post-blank period BB1 to the nth post-blank period BBn can have at least one value among i preset or set values (i is a natural number of two or greater). When i is equal to n, the durations Tb1 to Tbn of the first post-blank period BB1 to the nth post-blank period BBn can have different values. However, when i is less than n, at least two of the first post-blank period BB1 to the nth post-blank period BBn can have the same duration.

[0142] The first display period D1 to the nth display period Dn can have the same duration, and the first pre-blank period FB1 to the nth pre-blank period FBn can have the same duration. In this case, the durations of the first frame period F1 to the nth frame period Fn can vary according to the durations of the first post-blank period BB1 to the nth post-blank period BBn. For example, the durations of the first frame period F1 to the nth frame period Fn can vary randomly within a reference period T-ref. The sum of the durations of the first frame period F1 to the nth frame period Fn can be equal to the sum of the durations of n reference frame periods. Here, the duration of each reference frame period can be determined according to the driving frequency of the display panel DP. For example, when the driving frequency is approximately 60 Hz, the duration of the reference frame period can be set to approximately 16.7 ms (which is approximately 1 / 60 (1 / 60 s) of the reference period T-ref). For example, when the driving frequency is approximately 60 Hz and the duration of the reference period T-ref is approximately 1 s, the duration of the reference frame period can be set to approximately 16.7 ms (which is approximately 1 / 60 s).

[0143] Because the duration of the post-blank period of each frame period is variable (e.g., varies randomly), the start times of the display periods D1 to Dn vary randomly during the reference period T-ref. Therefore, the sensing period SD can occur randomly during the reference period T-ref (refer to Figure 7CThe case where the start time of ) coincides with the start times of display periods D1 to Dn, and the case where the start time of sensing period SD does not coincide with the start times of display periods D1 to Dn. In this case, although the phenomenon of the brightness reduction of pixel rows may not be completely eliminated, the positions of the pixel rows with reduced brightness can be changed for each frame period. Therefore, since the positions of the pixel rows with reduced brightness are spatially dispersed for each frame period, the phenomenon of horizontal line streaks appearing in display panel DP can be prevented or reduced. For example, the positions of the pixel rows with reduced brightness can be randomly changed for each frame period.

[0144] Figure 9A is a block diagram showing a controller according to an embodiment of the present disclosure. Figure 9B is a waveform diagram showing n sensing frame periods included in a reference sensing period according to an embodiment of the present disclosure, Figure 9C is showing Figure 9B the waveform diagram of each sensing frame period among the n sensing frame periods shown in.

[0145] Referring to Figure 9A , controller 100 provides a gate control signal GCS to gate driver 210. The gate control signal GCS may include a vertical start signal STV, a gate clock signal CK, an inverted gate clock signal CKB, etc. Controller 100 provides a sensing start signal BSYNC to sensing line driver 310.

[0146] As an example of the present disclosure, controller 100 may include an edge period determination unit 120. The edge period determination unit 120 can change the durations of edge periods FP and BP by randomly adjusting the output time of the sensing start signal BSYNC during a preset or set reference sensing period ST-ref. For example, the edge period determination unit 120 can control the durations of edge periods FP and BP. For example, the edge period determination unit 120 can randomly adjust the output time of the sensing start signal BSYNC such that the durations of edge periods FP and BP are randomly set (e.g., randomly set within a set range).

[0147] As Figure 6A and Figure 9BAs shown, the reference sensing period ST-ref may include n sensing frame periods SF1 to SFn (hereinafter referred to as the first sensing frame period SF1 to the nth sensing frame period SFn). Here, n may be a natural number of 1 or greater. As an example of the present disclosure, when the input sensing unit ISU operates at approximately 60 Hz and the duration of the reference sensing period ST-ref is set to approximately one second, the reference sensing period ST-ref may include approximately 60 sensing frame periods. As another example, when the input sensing unit ISU operates at approximately 120 Hz and the duration of the reference sensing period ST-ref is set to approximately one second, the reference sensing period ST-ref may include approximately 120 sensing frame periods. When the input sensing unit ISU operates at approximately 120 Hz and the duration of the reference sensing period ST-ref is set to approximately 0.5 seconds, the reference sensing period ST-ref may include approximately 60 sensing frame periods. However, the duration of the reference sensing period ST-ref and the number of sensing frame periods included in the reference sensing period ST-ref are not limited thereto and may be variously and appropriately changed.

[0148] The first sensing frame period SF1 to the nth sensing frame period SFn may have different durations in the reference sensing period ST-ref. For example, the durations of the first sensing frame period SF1 to the nth sensing frame period SFn may vary randomly in the reference sensing period ST-ref. For example, the durations of the first sensing frame period SF1 to the nth sensing frame period SFn may be randomly set within a set range.

[0149] The first sensing frame period SF1 may include a first front edge period FP1, a first sensing period SD1, and a first back edge period BP1. The second sensing frame period SF2 may include a second front edge period FP2, a second sensing period SD2, and a second back edge period BP2. In addition, the nth sensing frame period SFn may include an nth front edge period FPn, an nth sensing period SDn, and an nth back edge period BPn.

[0150] As an example of the present disclosure, the first front edge period FP1 to the nth front edge period FPn may have different durations. The sum of the durations of the first front edge period FP1 to the nth front edge period FPn may be equal to the sum of the durations of n reference front edge periods. Here, the duration of each reference front edge period may be defined as the average of the durations of the first front edge period FP1 to the nth front edge period FPn.

[0151] The first sensing period SD1 to the n-th sensing period SDn may have the same duration, and the first trailing edge period BP1 to the n-th trailing edge period BPn may have the same duration. Therefore, since the first leading edge periods FP1 to FPn have randomly varying durations in the reference sensing period ST-ref, the durations of the first sensing frame periods SF1 to SFn may vary randomly in the reference sensing period ST-ref.

[0152] Referring to Figure 9C , the duration of each of the first leading edge periods FP1 to FPn may be determined according to the output timing of the sensing start signal BSYNC.

[0153] At the first rising edge of the sensing start signal BSYNC (e.g., at the start point of the first pulse), the first sensing period SD1 of the first sensing frame period SF1 may start. The first leading edge period FP1 has a first duration Tf1 in the first sensing frame period SF1. At the second rising edge of the sensing start signal BSYNC (e.g., at the start point of the second pulse), the second sensing period SD2 of the second sensing frame period SF2 may start. In the second sensing frame period SF2, the second leading edge period FP2 has a second duration Tf2 that may be different from the first duration Tf1. For example, the second duration Tf2 may be larger than the first duration Tf1. At the n-th rising edge of the sensing start signal BSYNC (e.g., at the start point of the n-th pulse), the n-th sensing period SDn of the n-th sensing frame period SFn may start. In the n-th sensing frame period SFn, the n-th leading edge period FPn has an n-th duration Tfn that may be different from the first duration Tf1 and the second duration Tf2. For example, the n-th duration Tfn may be larger than the first duration Tf1 and may be smaller than the second duration Tf2.

[0154] The durations Tf1 to Tfn of the first leading edge periods FP1 to FPn may have at least one value among i preset or set values (i is a natural number of two or more). When i is equal to n, the durations Tf1 to Tfn of the first leading edge periods FP1 to FPn may have different values. However, when i is less than n, at least two of the first leading edge periods FP1 to FPn may have the same duration.

[0155] The first sensing period SD1 to the nth sensing period SDn may have the same duration, and the first trailing edge period BP1 to the nth trailing edge period BPn may have the same duration. In this case, the durations of the first sensing frame periods SF1 to the nth sensing frame periods SFn may vary according to the durations of the first leading edge periods FP1 to the nth leading edge periods FPn. For example, the durations of the first sensing frame periods SF1 to the nth sensing frame periods SFn may vary randomly in a reference sensing period ST-ref (refer to Figure 9B ). The sum of the durations of the first sensing frame periods SF1 to the nth sensing frame periods SFn may be equal to the sum of the durations of n reference sensing frame periods. Here, the duration of each reference sensing frame period may be determined according to the driving frequency of the input sensing unit ISU. For example, when the driving frequency is about 60 Hz, the duration of the reference sensing frame period may be set to about 16.7 ms (which is about 1 / 60 (1 / 60 s) of the reference sensing period ST-ref). For example, when the driving frequency is about 60 Hz and the duration of the reference sensing period ST-ref is about 1 s, the duration of the reference frame period may be set to about 16.7 ms (which is about 1 / 60 s).

[0156] As Figure 9C shown, the reference sensing period ST-ref may include n frame periods F1 to Fn. For example, the driving frequency of the display panel DP and the driving frequency of the input sensing unit ISU are shown to be the same in Figure 9C , but embodiments of the present disclosure are not limited thereto. When the driving frequencies of the display panel DP and the input sensing unit ISU are the same, the number of sensing frame periods SF1 to SFn included in the reference sensing period ST-ref may be the same as the number of frame periods F1 to Fn included in the reference sensing period ST-ref. However, when the driving frequencies of the display panel DP and the input sensing unit ISU are different, the number of sensing frame periods SF1 to SFn included in the reference sensing period ST-ref may be different from the number of frame periods F1 to Fn included in the reference sensing period ST-ref. For example, when the display panel DP is driven at about 120 Hz and the input sensing unit ISU is driven at about 60 Hz, the reference sensing period ST-ref may include n sensing frame periods SF1 to SFn and may include 2n frame periods.

[0157] Each scanning period SP, each emission period EP, each front blanking period FB, and each back blanking period BB may be included in a corresponding one of frame periods F1 to Fn. The blanking periods FB and BB may be defined as periods during which the display panel DP does not operate. The blanking periods FB and BB may include the front blanking period FB and the back blanking period BB.

[0158] When the start time of the scanning period SP coincides with the start times of the first sensing period SD1 to the nth sensing period SDn, the coupling capacitance between the input sensing unit ISU and the display panel DP increases. Therefore, a phenomenon in which the brightness of the pixel rows of the display panel DP decreases may occur. When the start time of the scanning period SP and the start times of the first sensing period SD1 to the nth sensing period SDn always coincide in dozens or hundreds of frame periods, the positions of the pixel rows with decreased brightness do not change. Therefore, horizontal line streaks may appear in the display panel DP.

[0159] However, according to an embodiment of the present disclosure, the start times of the sensing periods SD1 to SDn vary randomly during the reference sensing period ST-ref. Therefore, during the reference sensing period ST-ref, a situation where the start time of the scanning period SP coincides with the start times of the first sensing period SD1 to the nth sensing period SDn and a situation where the start time of the scanning period SP does not coincide with the start times of the first sensing period SD1 to the nth sensing period SDn may occur randomly. In this case, although the phenomenon of the brightness decrease of the pixel rows may not be completely eliminated, the positions of the pixel rows with decreased brightness may change for each frame period. Therefore, since the positions of the pixel rows with decreased brightness change for each frame period, the phenomenon of horizontal line streaks appearing in the display panel DP can be prevented or reduced. For example, the positions of the pixel rows with decreased brightness may vary randomly for each frame period.

[0160] Figure 10 is a waveform diagram showing n sensing frame periods included in a reference sensing period according to an embodiment of the present disclosure.

[0161] Referring to Figure 10 , the first sensing frame period SF1 to the nth sensing frame period SFn may have different durations in the reference sensing period ST-ref. For example, the durations of the first sensing frame period SF1 to the nth sensing frame period SFn may vary randomly in the reference sensing period ST-ref.

[0162] As an example of the present disclosure, the first trailing edge period BP1 to the nth trailing edge period BPn may have different durations. The sum of the durations of the first trailing edge period BP1 to the nth trailing edge period BPn may be equal to the sum of the durations of n reference trailing edge periods. Here, the duration of each reference trailing edge period may be defined as the average of the durations of the first trailing edge period BP1 to the nth trailing edge period BPn.

[0163] The first sensing period SD1 to the nth sensing period SDn may have the same duration, and the first leading edge period FP1 to the nth leading edge period FPn may have the same duration. Therefore, since the first trailing edge period BP1 to the nth trailing edge period BPn have randomly varying durations in the reference sensing period ST-ref, the durations of the first sensing frame periods SF1 to the nth sensing frame periods SFn may randomly vary in the reference sensing period ST-ref.

[0164] The first trailing edge period BP1 has a first duration Tb1 in the first sensing frame period SF1. In the second sensing frame period SF2, the second trailing edge period BP2 has a second duration Tb2 that may be different from the first duration Tb1. For example, the second duration Tb2 may be greater than the first duration Tb1. In the nth sensing frame period SFn, the nth trailing edge period BPn has an nth duration Tbn that may be different from the first duration Tb1 and the second duration Tb2. For example, the nth duration Tbn may be greater than the first duration Tb1 and may be less than the second duration Tb2.

[0165] The durations Tb1 to Tbn of the first trailing edge period BP1 to the nth trailing edge period BPn may have at least one value among i preset or set values (i is a natural number of two or greater). When i is equal to n, the durations Tb1 to Tbn of the first trailing edge period BP1 to the nth trailing edge period BPn may have different values. However, when i is less than n, at least two of the first trailing edge period BP1 to the nth trailing edge period BPn may have the same duration.

[0166] The first sensing period SD1 to the n-th sensing period SDn may have the same duration, and the first front-edge period FP1 to the n-th front-edge period FPn may have the same duration. In this case, the durations of the first sensing frame periods SF1 to the n-th sensing frame periods SFn may vary according to the durations of the first back-edge periods BP1 to the n-th back-edge periods BPn. For example, the durations of the first sensing frame periods SF1 to the n-th sensing frame periods SFn may vary randomly in the reference sensing period ST-ref. The sum of the durations of the first sensing frame periods SF1 to the n-th sensing frame periods SFn may be equal to the sum of the durations of n reference sensing frame periods. Here, the duration of each reference sensing frame period may be determined according to the driving frequency of the input sensing unit ISU. For example, when the driving frequency is about 60 Hz, the duration of the reference sensing frame period may be set to about 16.7 ms (which is about 1 / 60 (1 / 60 s) of the reference sensing period ST-ref). For example, when the driving frequency is about 60 Hz and the duration of the reference sensing period ST-ref is about 1 s, the duration of the reference sensing frame period may be set to about 16.7 ms (which is about 1 / 60 s).

[0167] Since the duration of the back-edge period of each sensing frame period is variable (e.g., varies randomly), the start times of the sensing periods SD1 to SDn vary randomly during the reference sensing period ST-ref. Therefore, during the reference sensing period ST-ref, the situation where the start times of the sensing periods SD1 to SDn coincide with the start time of the scanning period SP ( Figure 9C shown in) and the situation where the start times of the sensing periods SD1 to SDn do not coincide with the start time of the scanning period SP may occur randomly. In this case, although the phenomenon of the brightness reduction of the pixel rows may not be completely eliminated, the positions of the pixel rows with reduced brightness may change for each frame period. Therefore, since the positions of the pixel rows with reduced brightness change for each frame period, the phenomenon of horizontal line artifacts appearing in the display panel DP can be prevented or reduced. For example, the positions of the pixel rows with reduced brightness may vary randomly for each frame period.

[0168] According to an embodiment of the present disclosure, in a preset or set reference period / reference sensing period, by randomly varying the durations of the blank periods / edge periods included in the frame period / sensing frame period, the positions of the pixels whose brightness is reduced due to the coupling capacitance between the display panel and the input sensing unit can be spatially dispersed (e.g., can vary randomly over time) in the display panel.

[0169] Therefore, it is possible to prevent or reduce the phenomenon that the brightness of pixel rows continuously decreases, and thus horizontal line streaks are observed in the display panel.

[0170] Although example embodiments of the present disclosure have been described herein, it is understood that those skilled in the art can make various, appropriate changes and modifications within the spirit and scope of the present disclosure defined by the claims and their equivalents.

[0171] Therefore, the example embodiments described herein are not intended to limit the technical spirit and scope of the present disclosure, and all technical spirits within the scope of the claims and their equivalents will be construed as being included within the scope of the present disclosure.

Claims

1. A display device, the display device comprises: a display panel configured to display an image for each of a plurality of frame periods; an input sensing unit directly located on the display panel for sensing user input; a first driver configured to control the driving of the display panel; and a second driver configured to control the driving of the input sensing unit, wherein the frame period includes a display period and a blank period adjacent to the display period, and the duration of the blank period varies randomly within a set range during a set reference period, wherein the display panel operates at a single driving frequency during the reference period, wherein the reference period includes n frame periods among the plurality of frame periods, wherein the duration of each of the n frame periods varies randomly according to the duration of the blank period.

2. The display device according to claim 1, the display device further comprising a controller configured to control the driving of the first driver and the second driver, wherein, the controller includes a blank period determination unit configured to control the duration of the blank period during the reference period.

3. The display device according to claim 2, wherein, the blank period includes a front blank period before the display period and a rear blank period after the display period.

4. The display device according to claim 3, wherein, the blank period determination unit is configured to randomly vary the duration of the front blank period during the reference period.

5. The display device according to claim 3, wherein, the blank period determination unit is configured to randomly vary the duration of the rear blank period during the reference period.

6. The display device according to claim 1, wherein, the sum of the durations of the n frame periods is equal to the sum of the durations of n reference frame periods, and the duration of each of the n reference frame periods is set according to the driving frequency of the display panel.

7. The display device according to any one of claims 1 to 5, wherein, the display period has a constant duration during the reference period.

8. The display device according to claim 1, wherein, the display panel includes: a plurality of pixels; a plurality of gate lines connected to the plurality of pixels; and a plurality of data lines connected to the plurality of pixels, wherein the first driver includes: a gate driver configured to drive the plurality of gate lines; and a data driver configured to drive the plurality of data lines, wherein the display device further includes a controller configured to control the driving of the gate driver and the data driver.

9. The display device according to claim 8, wherein, the gate driver is configured to start driving each of the plurality of gate lines by receiving a vertical start signal from the controller, and The controller is configured to randomly vary an output timing of the vertical start signal during the reference period.

10. The display device according to claim 1, wherein, the display panel includes: a plurality of pixels configured to generate light and display an image, each pixel including a light-emitting element; and a thin film encapsulation layer configured to cover the plurality of pixels.

11. The display device according to claim 10, wherein, the input sensing unit is directly located on the thin film encapsulation layer.

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