Operating Modular Multilevel Converters

Abstract

A method for operating an MMC comprises controlling a plurality of submodules (SM1, ..., SMN) of an arm (A) of the MMC in a plurality of subsequent time periods. Each of the plurality of submodules comprises a respective capacitor (C). Controlling comprises sampling a value of a reference voltage in each time period and determining an integer n submodules required for approximating the sampled value. For each of a subset of the n submodules, determining a temperature characterizing the submodule. Inserting all submodules except one of the subsets. Determining a duty cycle depending on the determined temperature. Inserting the remaining submodules for a duration given by the duty cycle.

Description

Technical Field

[0001] The invention relates to a modular multilevel converter and a method for operating a modular multilevel converter. Background Art

[0002] Modular multilevel converters MMC may represent an enabling technology in the field of medium and high voltage power transmission for example. The scalability and excellent output waveform of MMC even at low frequencies are particularly advantageous.

[0003] In order to control the MMC, for example, a carrier-based pulse width modulation PWM scheme, such as a phase-shifted carrier PSCPWM, can be used. However, these schemes may suffer from relatively high switching losses, which may be particularly disadvantageous in the case of a medium or large number of unit cells in each converter arm. On the other hand, a carrier-free sorting scheme such as the nearest level control NLC may only achieve reduced accuracy, especially for a low to medium number of unit cells in each arm. The reduced accuracy may particularly lead to an increase in total harmonic distortion THD. NLC and other methods may involve thermal imbalances between unit cells within an arm, which may lead to an overall reduction in life and reliability or even the destruction of the MMC. Summary of the invention

[0004] Therefore, it is an object to provide an improved concept for operating an MMC providing reduced switching losses without reducing the MMC accuracy or lifetime.

[0005] This object is achieved by the subject matter of the independent claims. Further embodiments and examples are subject matter of the dependent claims.

[0006] The improved concept is based on the idea of ​​operating the MMC according to a modulation scheme by applying a modified Nearest Level Control (NLC) process, wherein all submodules except one are plugged according to the NLC scheme, while the remaining submodules are plugged according to a Pulse Width Modulation (PWM) scheme, the duty cycle of which depends on the temperature associated with the submodule.

[0007] In this way, the advantages of NLC can be achieved while its disadvantages are largely avoided without creating significant temperature imbalances.

[0008] According to the improved concept, a method for operating a modular multi-level converter is provided. The method includes controlling a plurality of submodules of an arm of an MMC in a plurality of subsequent time periods. Each of the plurality of submodules includes a corresponding capacitor. The control includes sampling a value of a reference voltage in each time period and determining an integer n of submodules required for the sampled value of the approximate voltage in the plurality of submodules. A subset of n submodules is selected from the plurality of submodules. For each submodule in the subset, a temperature is determined, wherein the temperature characterizes the corresponding submodule. Then, all submodules except one submodule in the subset, i.e., n-1 submodules, are inserted into the arm, in particular throughout the corresponding time period. The nth submodule is denoted as the remaining submodule. Depending on the determined temperature, a duty cycle for the remaining submodule is determined. Then, the remaining submodule is inserted into the arm for a duration given by the duty cycle. In particular, the duration of inserting the remaining submodule is given by the product of the duty cycle and the duration of the corresponding time period.

[0009] Here, approximating a sampled value of a voltage means determining an arm-achievable voltage level equal to or greater than the sampled value of a voltage, which is approximate to the above sampled value.

[0010] According to several embodiments of the method, the duty cycle is determined such that a total voltage across all capacitors in the n submodules of the subset of submodules matches the sampled reference voltage, for example to a tolerance value.

[0011] By inserting all submodules except the remaining submodules during the entire period and inserting the remaining submodules for the duration given by the duty cycle, the disadvantage of limited accuracy of the known carrier-free schemes is avoided. The limited accuracy stems from the fact that the sampled voltage generally does not exactly match the total voltage drop across all n capacitors. Since a properly adjusted duty cycle can be used to insert the remaining submodules, the voltage matching and therefore the accuracy of the MMC can be significantly improved. For the same reason, the average switching rate of multiple submodules is reduced as a whole. Therefore, switching losses are also reduced, especially for PSC PWM.

[0012] Here, inserting a submodule means connecting the capacitors of the corresponding submodules so that the capacitors are electrically connected in series between the input terminal and the output terminal of the submodule. For a submodule at the end of an arm, this means that the capacitors are electrically connected in series between an adjacent submodule and the end of the arm. For other submodules, this means that the capacitors are electrically connected in series between two adjacent submodules.

[0013] According to several embodiments, the integer n is determined depending on the sampled values ​​of the reference voltage and the corresponding rated voltages of the capacitors. In particular, if the rated voltages of all capacitors are the same, the integer n is given by the ratio of the sampled values ​​to the rated voltage values, rounded to the next higher integer. In particular, if the rated voltage values ​​of the capacitors differ from one another, the integer n is given by the ratio of the sampled values ​​to the average of the rated voltage values, rounded to the next higher integer.

[0014] According to several embodiments, the method includes sorting the plurality of submodules in ascending or descending order according to the voltages on their respective capacitors, and generating a sorted list of the submodules based on the sorting. The subset of n submodules corresponds to the first n entries of the sorted list.

[0015] According to several embodiments, depending on the direction of the current flowing in the arm, the subset of submodules corresponds to the n entries in the sorted list as submodules of the plurality of submodules having the lowest voltage on their corresponding capacitors or the n entries in the sorted list having the highest voltage on their corresponding capacitors. In particular, if the capacitors of the inserted submodules are charged or if the insertion is to be charged, the subset corresponds to the n entries with the lowest capacitor voltages, and if the capacitors of the inserted submodules are discharged or if the insertion is to be discharged, the subset corresponds to the n entries with the highest capacitor voltages. In this way, the imbalance of the voltages of the inserted submodules can be minimized.

[0016] According to several embodiments, a minimum temperature among the determined temperatures is identified and the duty cycle is determined depending on the minimum temperature.

[0017] According to several embodiments, each submodule of the plurality of submodules comprises a switching arrangement for inserting, bypassing and / or blocking the respective submodule.

[0018] According to several embodiments, the temperature characterizing the individual submodules is given by a junction temperature of a switching element of the respective submodule, in particular a junction temperature of a switching arrangement of the respective submodule.

[0019] According to some embodiments, a switching arrangement of one of the plurality of submodules, in particular each of the plurality of submodules, comprises a first switching element and a second switching element. The first and second switching elements and the capacitor of the respective submodule are arranged according to a half-bridge topology.

[0020] According to several embodiments, the second switching element is arranged in parallel with the series arrangement of the first switching element and the capacitor.

[0021] According to some embodiments, the switching arrangement of one of the plurality of submodules, in particular each of the plurality of submodules, comprises a third switching element and a fourth switching element. The first, second, third and fourth switching elements and the capacitor of the respective submodule are arranged according to a full bridge topology.

[0022] According to several embodiments, the temperature characterizing each submodule is given by the junction temperature of the switching element in the corresponding submodule having the smallest junction temperature relative to all other switching elements of the same submodule.

[0023] According to some embodiments, the temperature characterizing each submodule is given by a junction temperature of a first switching element of the corresponding submodule.

[0024] According to some embodiments, the temperature characterizing each submodule is given by a junction temperature of a second switching element of the corresponding submodule.

[0025] Which junction temperature represents the characteristic temperature of the submodule may depend, for example, on the specific application, the operating mode and / or the load of the MMC. For example, if the switching rate of the second switching element is significantly higher than the switching rate of the first switching element, for example in a half-bridge topology, the junction temperature of the second switching element may represent the characteristic temperature, or vice versa.

[0026] The junction temperature may for example be determined by means of temperature measurement, for example using an on-chip sensing diode.Alternatively or additionally, the junction temperature may be determined based on a measurement of a temperature sensitive electrical parameter TSEP or based on a thermal model.

[0027] In an MMC supplying power to a load, plugging in all but the remaining submodules for the entire period and plugging in the remaining submodules for the duration given by the duty cycle may in principle cause greater thermal stress to some switching elements than to other switching elements. This imbalance can be avoided or reduced by using a temperature-dependent duty cycle for the remaining submodules.

[0028] According to several embodiments, in order to insert one of the plurality of submodules, the first switching element of the corresponding submodule is closed and the second switching element of the corresponding submodule is opened, so that the capacitor of the corresponding submodule can be charged and discharged depending on the current direction in the arm. If the submodule is inserted, the current can flow from the input terminal of the submodule to the capacitor of the submodule via the first switch, and from the capacitor to the output terminal of the submodule for charging the capacitor. In order to discharge the capacitor, the current flow can be reversed.

[0029] According to several embodiments, to bypass one of the plurality of submodules, a first switching element of the corresponding submodule is opened and a second switching element of the corresponding submodule is closed such that a capacitor of the corresponding submodule is effectively disconnected from the arm.

[0030] According to several embodiments, to block one of the plurality of submodules, both the first and second switching elements of the corresponding submodule are opened. In case the first switching element comprises a freewheeling diode, the capacitor of the corresponding submodule may be charged or not, depending on the direction of the current in the arm.

[0031] Here, an open switching element means being in an off state, i.e., in a high resistance state. In addition, a closed switching element means being in an on state, i.e., in a low resistance state. It should be noted that the term open switching element also includes keeping the switching element open. Similarly, the term closed switching element also includes keeping the switching element closed.

[0032] According to some embodiments, the method further comprises determining a temperature difference between a minimum temperature among the determined temperatures characterizing the submodules and a determined temperature characterizing a reference submodule of the sorted list. The reference submodule may, for example, correspond to the nth submodule in the sorted list. If the temperature difference is greater than a predetermined threshold, the remaining submodule is given by the submodule for which the minimum temperature is determined.

[0033] According to several embodiments, if the temperature difference is less than a predetermined threshold, the remaining submodules are given by the reference submodule.

[0034] According to several embodiments, if the temperature difference is greater than a predetermined threshold, the duty cycle is determined according to the following equation:

[0035]

[0036] Where d is the duty cycle, V ref is the sampled value of the reference voltage, and the summation is performed on all submodules in the subset of submodules, V i is the voltage on the capacitor of the ith submodule, and V min is the voltage on the capacitor of the submodule that determines the minimum temperature.

[0037] According to several embodiments, if the temperature difference is equal to or less than a predetermined threshold, the duty cycle is determined according to the following equation:

[0038]

[0039] Where V r is the voltage on the capacitor of the reference submodule.

[0040] According to several embodiments, if equation (1) would result in a negative duty cycle, the duty cycle is determined according to equation (2).

[0041] According to several embodiments, if equation (1) would result in a negative duty cycle, the remaining submodule is given by the reference submodule.

[0042] According to several embodiments, the predetermined threshold is in the order of a few tenths of a Kelvin or in the order of one or several Kelvins.

[0043] According to the improved concept, a modular multi-level converter is also provided. The MMC includes a control unit and an arm having a plurality of submodules, wherein the submodules in the plurality of submodules are particularly arranged in series with each other. Each of the plurality of submodules includes a corresponding capacitor. The control unit is configured to sample the value of the reference voltage in each of a plurality of subsequent time periods and determine an integer n of submodules required for the approximate sampled value in the plurality of submodules. The control unit is also configured to determine a temperature characterizing the corresponding submodule for each of a subset of n submodules in the plurality of submodules. The control unit is also configured to insert all submodules except one remaining submodule in the subset of n submodules into the arm, and determine a duty cycle depending on the determined temperature, and insert the remaining submodules into the arm for a duration given by the duty cycle.

[0044] According to several embodiments of the MMC, each of the plurality of sub-modules comprises a respective switching arrangement designed for inserting, bypassing and blocking the respective sub-module.

[0045] According to several embodiments of the MMC, each switching arrangement comprises a first and a second switching element. The first and the second switching elements and the corresponding capacitors of one of the submodules are arranged according to a half-bridge topology.

[0046] According to some embodiments of the MMC, the control unit is configured to close the first switching element of the corresponding submodule and open the second switching element so that the capacitor of the corresponding submodule can be charged or discharged in order to insert the corresponding submodule.

[0047] According to some embodiments of the MMC, the control unit is configured to open a first switching element and close a second switching element of a corresponding submodule so that a capacitor of the corresponding submodule is disconnected from the arm to bypass the corresponding submodule.

[0048] According to some embodiments of the MMC, the control unit is configured to open the first and second switching elements of the corresponding submodule to block the corresponding submodule.

[0049] According to several embodiments of the MMC, the switching arrangement, in particular the first and / or the second switching element, of one of the submodules comprises at least one insulated gate bipolar transistor IGBT.

[0050] According to several embodiments of the MMC, the control unit comprises a gate driver for controlling the switching arrangement, in particular the switching elements, such as IGBTs.

[0051] Further embodiments and examples according to the improved concept can be easily derived from various embodiments and examples of the method according to the improved concept, and vice versa. In particular, individual or several components or arrangements described with respect to the MMC can be implemented accordingly for the method according to the improved system.

[0052] In the following, the present invention is explained in detail with respect to exemplary embodiments by reference to the accompanying drawings. Components that are functionally identical or have the same effect may be represented by the same reference numerals. The same components or components with the same function or effect may be described only with respect to the figure in which they first appear. Their description is not necessarily repeated in subsequent figures. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In the accompanying drawings,

[0054] Figure 1a A block diagram showing an exemplary implementation of an MMC according to the improved concept;

[0055] Figure 1b A block diagram showing an arm of another exemplary embodiment of the MMC according to the improved concept;

[0056] Figure 1c A block diagram showing submodules of another exemplary embodiment of an MMC according to the improved concept;

[0057] Figure 2a shows a set of curves representing the temperature versus time of a submodule representing another exemplary embodiment of an MMC according to the improved concept; and

[0058] Figure 2b A set of curves representing the temperature versus time of the submodules of the MMC are shown. DETAILED DESCRIPTION

[0059] Figure 1a A block diagram of an exemplary implementation of an MMC according to the improved concept is shown.

[0060] The MMC includes several, in a specific non-limiting example, three upper arms

[0061] Au1, ...Au3, and as many as, in a specific non-limiting example, three lower arms A11, A12, A13 are included. Each pair of upper and lower arms is coupled in series, such as Au1 / A11, Au2 / A12, and Au3 / A13. The respective terminals P1, P2, P3 of the AC port PAC of the MMC are connected between each of the arms connected in series. In the example shown, the respective upper inductance components Lu1, Lu2, Lu3 are connected between each of the upper arms Au1, ...Au3 and the respective terminals P1, P2, P3. Similarly, the respective lower inductance components Ll1, Ll2, Ll3 are connected between each of the lower arms A11, ...A13 and the respective terminals P1, P2, P3. Each pair of serially connected upper and lower arms Au1 / Al1, Au2 / Al2, Au3 / Al3 together with the corresponding upper and lower inductive components Lu1 / Ll1, Lu2 / Ll2, Lu3 / Ll3 form a leg of the MMC.

[0062] Instead of or in addition to the upper inductor components Lu1, ..., Lu3 and the lower inductor components Ll1, ... Ll3, a corresponding inductor component (not shown) may be connected between each of the terminals P1, P2, P3 and the corresponding leg.

[0063] Alternatively, the MMC may include a respective switch k1 , k2 , k3 arranged between each of the legs and the respective terminal P1 , P2 , P3 to disconnect the respective leg from the respective terminal P1 , P2 , P3 .

[0064] The upper arms Au1, Au2, and Au3 are connected to each other and to the DC port PDC. The lower arms A11, A12, and A13 are connected to each other and to the DC port PDC.

[0065] The MMC also includes a resistor R coupled between the upper arms Au1, Au2, Au3 and the DC port PDC. Alternatively, the resistor R may be coupled between the lower arms A11, A12, A13 and the DC port PDC, or an additional resistor (not shown) may be coupled between the lower arms A11, A12, A13 and the DC port PDC.

[0066] Optionally, the MMC comprises a further switch k for bypassing the resistor R.

[0067] The MMC comprises a control unit CU coupled to each of the arms Au1, ... Au3, Al1, ..., Al3. Optionally, the control unit CU may be coupled to switches k, k1, ... k3 in order to open and close each of them.

[0068] Figure 1bA block diagram of arm A of another exemplary embodiment of the MMC according to the improved concept is shown. For example, arm A may represent Figure 1a One of the arms Au1, ...Au3, Al1, ..., Al3 shown in .

[0069] The arm A comprises a plurality of submodules SM1, SM2, SM3, SMN coupled in series with each other. The number of four submodules shown should be understood as a non-limiting example. In particular, according to an embodiment of the improved concept, the arm A may comprise any number of submodules equal to or greater than two, such as Figure 1b Indicated by the dotted line in .

[0070] Figure 1c A block diagram of a submodule SM according to another exemplary embodiment of the MMC according to the improved concept is shown. For example, the submodule SM may represent Figure 1b One of the sub-modules SM1, ..., SMN shown in .

[0071] As a non-limiting example, the submodule SM is implemented according to a half-bridge topology. According to other embodiments, the submodule may be implemented differently than according to a full-bridge topology, for example.

[0072] According to the half-bridge topology, the submodule comprises a capacitor C having one terminal coupled to the input terminal T1 of the submodule SM via a first switching element S1. The other terminal of the capacitor C is coupled to the output terminal T2 of the submodule. A second switching element S2 is connected between the input terminal T1 and the output terminal T2.

[0073] The first and second switching elements S1, S2 may, for example, each include a respective transistor I1, I2, which is, for example, an insulated gate bipolar transistor IGBT. Figure 1c Depicted in FIG as a normally conducting n-type transistor. It will be clear to the skilled person that other options are possible.

[0074] The first switching element S1 may be connected to the capacitor via the collector terminal of the first transistor I1 and to the input terminal T1 via the emitter terminal of the first transistor I1. Optionally, the first diode D1 may be connected to the first transistor T1 such that the cathode of the diode D1 is connected to the collector terminal of the first transistor T1 and the anode of the diode D1 is connected to the emitter terminal of the first transistor T1. The second switching element S2 may be connected to the capacitor via the anode terminal of the second transistor I2 and to the input terminal T1 via the collector terminal of the second transistor I2. Optionally, the second diode D2 may be connected to the second transistor T2 such that the cathode of the diode D2 is connected to the collector terminal of the second transistor T2 and the anode of the diode D2 is connected to the emitter terminal of the second transistor T2. The respective gate terminals of the transistors T1, T2 are coupled to the control unit CU and may be controlled by the control unit CU.

[0075] Depending on the position of the particular submodule within the series connection of submodules, the input terminal T1 is coupled to the AC port PAC or a corresponding inductive element of the arm, for example directly or via one or more other submodules of the same arm. Depending on the position of the particular submodule within the series connection of submodules, the output terminal T2 is coupled to the DC port PDC, for example directly or via a resistor R and / or via one or more other submodules of the same arm.

[0076] During operation of the MMC, the steps described below with respect to a given sample period are periodically performed. In the following, an operation mode is described in which the MMC is used to convert a three-phase AC input voltage applied at an AC port PAC into an output voltage supplied at a DC output port PDC. Similarly, the MMC can be used to convert an input DC input voltage applied at a DC port PDC into an output voltage supplied at an AC port PAC. In addition, the following description mainly relates to a submodule of the first upper arm Au1 as a representative example. The operation of the other arms of the MMC is similar. Assuming that according to Figure 1c All submodules of the first upper arm Au1 are implemented, wherein all capacitors C of the submodules within the arm Au1 have the same rated voltage, wherein the rated voltage is given by a predetermined maximum voltage allowed to charge the capacitor and is usually given by the dielectric strength of the capacitor's dielectric.

[0077] During the sampling period, the reference voltage applied at the terminal P1 of the AC port PAC is measured and supplied to the control unit CU. The control unit CU then determines how many submodules in the arm Au1 need to approximate the sampled reference voltage. The number of required submodules n is, for example, given by n=[V ref / V rate ] + Given, where V ref is the absolute value of the sampled reference voltage, Vrate is the rated voltage of the capacitor and [...] + If the argument is a non-integer, it is the next larger integer, otherwise it is the argument itself.

[0078] Then, the control unit CU determines a subset of the n submodules of arm Au1. To this end, the control unit CU can set a sorted list of the submodules of arm Au1, which is sorted in ascending order or descending order of the current voltage values ​​on the capacitors of the submodules. Depending on the current direction in arm Au1, the subset includes the n submodules with the highest or lowest voltage on their capacitors, so as to minimize or avoid the imbalance of the capacitor voltage in arm Au1. For example, in the case where the insertion of a module in arm Au1 will result in the charging of its capacitor, the n submodules with the lowest voltage on its capacitor constitute a subset of the n submodules. On the other hand, in the case where the insertion of a module in arm Au1 will result in the discharge of its capacitor, the n submodules with the highest voltage on its capacitor constitute a subset of the n submodules.

[0079] Then, for all n submodules of the subset, a temperature characterizing the individual submodules is determined and supplied to the control unit CU. The temperature may correspond to the junction temperature of a switching element of the respective submodule, for example one of the transistors I1, I2. Depending on the specific application or operating mode of the MMC, the characterizing temperature may be given by the junction temperature of the first transistor I1 or by the junction temperature of the second transistor I2 or by the minimum junction temperature of the junction temperatures of the first and second transistors.

[0080] All but one of the n submodules of the subset are then inserted into arm Au1, specifically leaving one remaining submodule throughout the sample period.

[0081] The remaining submodules may be determined, for example, based on the position in the sorted list. For example, the remaining submodule may be the nth submodule in the sorted list. For example, where the sorted list is sorted in ascending order relative to the capacitor voltage, the remaining submodule may be the submodule with the largest capacitor voltage among the n submodules of the subset. For example, where the sorted list is sorted in descending order relative to the capacitor voltage, the remaining submodule may be the submodule with the smallest capacitor voltage among the n submodules of the subset.

[0082] The control unit CU can then determine the duty cycle for the remaining submodules depending on the determined temperature. In this regard, please refer to equations (1) and (2) above for details. It should be noted that the minimum characterization temperature is not necessarily the same as the lowest junction temperature among all transistors in arm Au1. For example, considering the specific operating mode or application of the MCC, for a given arm Au1, all first transistors I1 in arm Au1 may have a junction temperature that is higher than all junction temperatures of the second transistors I2. If the characterization temperature is given by the junction temperature of the first transistor I1, the minimum characterization temperature may be greater than the junction temperature of the second transistor I2.

[0083] The remaining submodules are then inserted according to the determined duty cycle, in particular within a duration given by the product of the duration of the sample period and the duty cycle.

[0084] In this way, the sampled voltage can be approximated in a particularly precise manner, wherein the majority of submodules have a particularly low switching rate.

[0085] In the same way, all other arms Au2, Au3, A11, A12, A13 are controlled. Therein, the remaining submodules of several arms can be inserted, for example, according to a predetermined phase shift relative to each other, for example according to a PSC type method.

[0086] Figure 2a Shown is the characteristic temperature in degrees Celsius of an arm of an MMC according to the improved concept versus time in seconds.

[0087] In the example shown, equation (1) is used to determine the duty cycle, assuming that equation (1) provides a positive result as long as the temperature difference between the characterization temperature of the remaining submodules and the minimum characterization temperature is greater than one degree Celsius. Otherwise, equation (2) is used. One can see that Figure 2a The temperature difference is limited to 1 Kelvin.

[0088] For comparison, Figure 2b The characteristic temperature of the arm of the MMC in degrees Celsius is shown against the time in seconds, where the duty cycle is not determined in a temperature-dependent manner. Instead, only equation (2) is used. Here, the temperature difference is significantly larger, i.e. up to about four Kelvin.

[0089] By means of the MMC or the method according to the improved concept, the disadvantages of known methods such as PSC PWM and NLC can be overcome, in particular low precision, high THD, high switching losses, temperature imbalance, reduced lifetime and risk of device destruction. The advantages of the improved concept allow efficient operation of the MMC for a larger range of submodules or unit cells per arm. In particular, the improved concept may be most advantageous for a low or medium number of submodules per arm, for example five to 100 submodules per arm or 5 to 50 submodules per arm or 10 to 15 submodules per arm.

[0090] Thus, the improved concept makes it possible to exploit the advantages of MMC controllability without the significant disadvantages of controllability. In particular, thermal stress management, which is critical for the reliability and lifetime of MMCs, is addressed in a beneficial manner.

[0091] Reference numerals

[0092] CU Control Unit

[0093] A, Au1, Au2, Au3 Arm

[0094] Al1, Al2, Al3

[0095] Lu1, Lu2, Lu3 inductor components

[0096] Ll1, Ll2, Ll3

[0097] k, k1, k2, k3 switch

[0098] R Resistor

[0099] PAC, PDC ports

[0100] P1, P2, P3 AC port terminals

[0101] SM, SM1, SM2, SM3, SMN submodules

[0102] S1, S2 switching elements

[0103] T1, T2 input and output terminals

[0104] I1, I2 transistors

[0105] D1, D2 diodes

[0106] C Capacitor

Claims

1. A method for operating a modular multilevel converter MMC, wherein the method comprises controlling a plurality of submodules (SM1, ..., SMN) of an arm (A) of the MMC in a plurality of subsequent time periods, each of the plurality of submodules (SM1, ..., SMN) comprising a respective capacitor (C), wherein the controlling comprises controlling in each time period - Sample the reference voltage value; - an integer number n of submodules required to determine approximate sample values ​​in said plurality of submodules (SM1, . . . , SMN); - for each submodule in a subset of n submodules of said plurality of submodules (SM1, . . . , SMN), determining a temperature characterizing the respective submodule; - inserting all but one remaining submodule from a subset of n submodules; - determining a duty cycle depending on the determined temperature; - inserting the remaining submodules for a duration given by the duty cycle; wherein a minimum temperature of the determined temperatures is identified and the remaining submodules and the duty cycle are determined as a function of the minimum temperature.

2. The method according to claim 1, wherein: The temperature that characterizes the respective submodule is given by the junction temperature of the switching element of the respective submodule.

3. The method according to claim 1 or 2, wherein: Each submodule of the plurality of submodules (SM1, . . . , SMN) comprises a switching arrangement (S1, S2) for inserting, bypassing and / or blocking the respective submodule.

4. The method according to claim 3, wherein - a switching arrangement (S1, S2) of one of the plurality of submodules comprises a first switching element (S1) and a second switching element (S2); The first and second switching elements ( S1 , S2 ) and the capacitor (C) of each submodule are arranged according to a half-bridge topology.

5. The method according to claim 4, wherein: To insert one of the plurality of submodules (SM1, . . . , SMN), the first switching element (S1) of the corresponding submodule is closed and the second switching element (S2) of the corresponding submodule is opened, so that the capacitor (C) of the corresponding submodule can be charged or discharged.

6. The method according to claim 1 or 2, - further comprising sorting the plurality of submodules (SM1, . . . , SMN) in ascending or descending order with respect to the voltage on their respective capacitors (C); as well as - Generate a sorted list of submodules based on the sorting; - where the subset of n submodules corresponds to the first n entries of the sorted list.

7. The method according to claim 6, - further comprising determining a temperature difference between a minimum temperature among the determined temperatures characterizing the submodules and a determined temperature of a reference submodule of the characterizing sorted list; And among them If the temperature difference is greater than a predetermined threshold, the remaining submodule is given by the submodule for which the minimum temperature was determined.

8. The method according to claim 7, wherein: If the temperature difference is less than a predetermined threshold, the remaining submodules are given by the reference submodule.

9. A modular multilevel converter comprising a control unit (CU) and an arm (A) having a plurality of submodules (SM1, ..., SMN); wherein - each of the plurality of submodules (SM1, ..., SMN) comprises a respective capacitor (C); and - the control unit (CU) is configured to, during each of a plurality of subsequent time periods, - Sample the reference voltage value; - an integer number n of submodules required to determine approximate sample values ​​in said plurality of submodules (SM1, . . . , SMN); - for each submodule of a subset of n submodules of said plurality of submodules (SM1, . . . , SMN), determining a temperature characteristic of the respective submodule; - inserting all but one remaining submodule from a subset of n submodules; - determining a duty cycle depending on the determined temperature; - inserting the remaining submodules for a duration given by the duty cycle; wherein a minimum temperature of the determined temperatures is identified and the remaining submodules and the duty cycle are determined as a function of the minimum temperature.

10. The modular multilevel converter according to claim 9, wherein: Each of the plurality of submodules (SM1, . . . , SMN) comprises a respective switching arrangement (S1, S2) designed for inserting, bypassing and blocking the respective submodule.

11. The modular multilevel converter according to claim 9 or 10, wherein - a switching arrangement (S1, S2) of one of the plurality of submodules (SM1, . . . , SMN) comprises a first switching element and a second switching element (S1, S2); The first and second switching elements ( S1 , S2 ) and the capacitor (C) of each submodule are arranged according to a half-bridge topology.

12. The modular multilevel converter according to claim 11, wherein: The control unit (CU) is configured to close a first switching element (S1) of one of the plurality of submodules (SM1, . . . , SMN) and open a second switching element (S2) thereof for inserting the corresponding submodule so that a capacitor (C) of the corresponding submodule can be charged or discharged.

13. The modular multilevel converter according to claim 9 or 10, wherein: The switching arrangement (S1, S2) of one of the submodules comprises at least one insulated gate bipolar transistor (I1, I2).

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