Packaging component, electronic device and packaging method

Abstract

The present application discloses a packaging component, an electronic device and a packaging method. The packaging component includes: a substrate, a packaging chip, a first semiconductor chip, a fan-out area and a first molding compound. The packaging chip is arranged on the substrate and electrically connected to the substrate. The first semiconductor chip is arranged on the packaging chip and electrically connected to the substrate. Therefore, the packaging size of the packaging component can be reduced; the fan-out area is arranged on the packaging chip and is arranged adjacent to the first semiconductor chip. The fan-out area is electrically connected to the first semiconductor chip and the substrate, and the area of ​​the fan-out area and the first semiconductor chip is approximately equal to the area of ​​the packaging chip. Therefore, the first semiconductor chip of the present application is electrically connected to the substrate through the fan-out area, which can reduce the length of the welding wire to reduce the probability of adverse phenomena such as signal attenuation, crosstalk, and parasitic capacitance in the welding wire, and the first molding compound is used to encapsulate the first semiconductor chip, the packaging chip and the substrate.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a packaging component, an electronic device and a packaging method. Background Art

[0002] Semiconductor chips are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras and other electronic devices. With the continuous development of integrated electronic technology, the performance requirements of semiconductor chips are also increasing, such as enhanced functionality, reduced size, reduced energy consumption and cost.

[0003] In order to adapt to the development trend of multifunctional, miniaturized, portable, high-speed, low-power and high-reliability microelectronic packaging technology, the system-level packaging (SIP) technology, as an emerging heterogeneous integration technology, has become the packaging form of more and more chips. The system-level packaging is to integrate multiple functional chips and components in one package to achieve a complete function. The system-level packaging is a new packaging technology with the advantages of short development cycle, more functions, lower power consumption, better performance, lower cost, smaller size and lighter weight.

[0004] However, with the increasing demand for package components and functions, the existing system-level package components have larger package sizes, longer traces, and parasitic capacitance in the bonding wires. Summary of the invention

[0005] In order to solve the above-mentioned problems existing in the semiconductor packaging assembly in the prior art, the present application provides a packaging assembly and a packaging method.

[0006] In order to solve the above problems, the present application provides a packaging component, which includes:

[0007] substrate;

[0008] A packaging chip is arranged on the substrate, and the packaging chip is electrically connected to the substrate;

[0009] A first semiconductor chip is disposed on the package chip, and the first semiconductor chip is electrically connected to the substrate;

[0010] a fan-out region, disposed on the packaged chip and adjacent to the first semiconductor chip, the fan-out region electrically connecting the first semiconductor chip and the substrate, wherein a total area of ​​the fan-out region and the first semiconductor chip is approximately equal to an area of ​​the packaged chip;

[0011] The first molding compound is used to encapsulate the first semiconductor chip, the packaging chip and the substrate.

[0012] In order to solve the above technical problems, the present application also provides an electronic device, which includes the above packaging component.

[0013] In order to solve the above technical problems, the present application also provides a packaging method, which includes:

[0014] providing a substrate;

[0015] A packaging chip is arranged on the substrate, wherein the packaging chip is electrically connected to the substrate;

[0016] Fanning out the first semiconductor chip to obtain a fan-out region, wherein the fan-out region is disposed adjacent to the first semiconductor chip;

[0017] The first semiconductor chip and the fan-out region are arranged on the packaged chip, the first semiconductor chip is electrically connected to the substrate, wherein the fan-out region is electrically connected to the first semiconductor chip and the substrate, and the total area of ​​the fan-out region and the first semiconductor chip is approximately equal to the area of ​​the packaged chip;

[0018] The first semiconductor chip, the packaged chip, and the substrate are packaged by a first molding compound.

[0019] Compared with the prior art, the packaging component of the present application includes: a substrate, a packaging chip, a first semiconductor chip, a fan-out area and a first molding compound, wherein the packaging chip is arranged on the substrate and electrically connected to the substrate, and the first semiconductor chip is arranged on the packaging chip and electrically connected to the substrate, so that the packaging size of the packaging component can be reduced; the fan-out area is arranged on the packaging chip and is arranged adjacent to the first semiconductor chip, the fan-out area is electrically connected to the first semiconductor chip and the substrate, and the area of ​​the fan-out area and the first semiconductor chip is approximately equal to the area of ​​the packaging chip. Therefore, the first semiconductor chip of the present application is electrically connected to the substrate through the fan-out area, which can reduce the length of the bonding wire to reduce the probability of adverse phenomena such as signal attenuation, crosstalk, and parasitic capacitance in the bonding wire, and the first molding compound is used to encapsulate the first semiconductor chip, the packaging chip and the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 It is a schematic structural diagram of a first embodiment of a packaging assembly provided by the present application;

[0022] Figure 2It is a schematic structural diagram of a first embodiment of a first semiconductor chip and a fan-out area in a package assembly provided by the present application;

[0023] Figure 3 is a schematic structural diagram of a second embodiment of a packaging assembly provided by the present application;

[0024] Figure 4 is a schematic structural diagram of a second embodiment of a first semiconductor chip and a fan-out region in a package assembly provided by the present application;

[0025] Figure 5 It is a flow chart of the packaging method provided by this application.

[0026] The figures are marked as follows: packaging component 10; substrate 100; packaging chip 200; first semiconductor chip 300; fan-out area 400; first molding compound 500; first solder pad 110; second solder pad 410; first connecting wire 610; first surface 430; second surface 420; third surface 440; second connecting wire 630; third solder pad 310; third connecting wire 620; fourth solder pad 120; fifth solder pad 320; first solder ball 210; second solder ball 130; filling glue 700. DETAILED DESCRIPTION

[0027] The present application is further described in detail below in conjunction with the accompanying drawings and examples. It is particularly noted that the following examples are only used to illustrate the present application, but are not intended to limit the scope of the present application. Similarly, the following examples are only some embodiments of the present application rather than all embodiments, and all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of the present application.

[0028] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0029] See also Figure 1-Figure 4 , Figure 1 is a schematic structural diagram of a first embodiment of a packaging component 10 provided in the present application, Figure 2is a schematic structural diagram of a first embodiment of a first semiconductor chip 300 and a fan-out region 400 in a package component 10 provided in the present application, Figure 3 is a schematic structural diagram of a second embodiment of a packaging component 10 provided in the present application, Figure 4 It is a schematic structural diagram of a second embodiment of the first semiconductor chip 300 and the fan-out region 400 in the packaging component 10 provided in the present application.

[0030] The present application provides a package assembly 10 , which may include a substrate 100 , a package chip 200 , a first semiconductor chip 300 , a fan-out region 400 , and a first molding material 500 .

[0031] The packaged chip 200 may be disposed on the substrate 100 , and the packaged chip 200 may be electrically connected to the substrate 100 .

[0032] The first semiconductor chip 300 may be disposed on the package chip 200 and electrically connected to the substrate 100 .

[0033] The fan-out region 400 may be disposed on the package chip 200 and adjacent to the first semiconductor chip 300 . The fan-out region 400 may electrically connect the first semiconductor chip 300 and the substrate 100 , so that the first semiconductor chip 300 is electrically connected to the substrate 100 through the fan-out region 400 .

[0034] The total area of ​​the fan-out region 400 and the first semiconductor chip 300 may be approximately equal to the area of ​​the packaged chip 200. Specifically, the total area of ​​the fan-out region 400 and the first semiconductor chip 300 may be less than or equal to the area of ​​the packaged chip 200, so that the first semiconductor chip 300 and the fan-out region 400 can be simultaneously disposed on the surface of the packaged chip 200 away from the substrate 100. The difference between the area of ​​the packaged chip 200 and the total area of ​​the fan-out region 400 and the first semiconductor chip 300 is within a preset threshold range.

[0035] The first molding material 500 may be used to encapsulate the first semiconductor chip 300 , the packaged chip 200 , and the substrate 100 .

[0036] Therefore, the first semiconductor chip 300 of the packaging component 10 provided in the present application is electrically connected to the substrate 100 through the fan-out area 400, which can reduce the length of the welding wire to reduce the probability of adverse phenomena such as signal attenuation, crosstalk, and parasitic capacitance in the welding wire; and because the fan-out area 400 and the first semiconductor chip 300 are both placed on the packaging chip 200, the packaging size of the packaging component 10 can be reduced.

[0037] See also Figure 1-Figure 4 , the present application provides a packaging component 10.

[0038] The package assembly 10 may include a substrate 100. The substrate 100 may be made of the same material as in the prior art, for example, the substrate 100 may be formed of a semiconductor material, the semiconductor material being silicon, such as bismaleimide triazine (BT), polyimide or an organic material such as Ajinomoto build-up film (ABF).

[0039] The package assembly 10 may further include a package chip 200 . The package chip 200 may be disposed on the substrate 100 , and the package chip 200 may be electrically connected to the substrate 100 .

[0040] The packaged chip 200 may include at least two second semiconductor chips (not shown). The second semiconductor chip may be a memory semiconductor chip for storing data. The memory semiconductor chip may be a cache memory chip that temporarily stores and provides data used in the logic operation of the system on chip.

[0041] Specifically, at least two second semiconductor chips may be packaged in a ball grid array packaging manner to form a packaged chip 200. The packaged chip 200 is packaged in a ball grid array manner and is directly disposed on the substrate 100. The packaged chip 200 may be electrically connected to the substrate 100 by using solder balls or solder bumps of the packaged chip 200 close to the surface of the substrate 100 as external leads.

[0042] In this embodiment, the packaged chip 200 adopts a standard BGA package, and the second semiconductor chips of different storage types can be packaged into the packaged chip 200 to save packaging costs. For example, different types of memory chips may include volatile memory chips and / or non-volatile memory chips. Volatile memory chips may include, for example, dynamic random access memory (DRAM), static random access memory (static RAM, SRAM), thyristor random access memory (thyristor RAM, TRAM), zero capacitor random access memory (zero capacitor RAM, ZRAM), etc. Non-volatile memory chips may include, for example, flash memory, magnetic random access memory (magnetic RAM, MRAMO), spin transfer torque random access memory (spin-transfer torque MRAM, STT-MRAM), ferroelectric random access memory (ferroelectric RAM, FRAM), phase change random access memory (phase change RAM, PRAM), resistive random access memory (resistive RAM, RRAM), etc.

[0043] The second semiconductor chips may be stacked or arranged in parallel.

[0044] Specifically, the at least two second semiconductor chips may include two second semiconductor chips, and the two second semiconductor chips may be stacked or arranged in parallel to expand the storage capacity of the package chip 200 .

[0045] In an embodiment of the present application, the at least two second semiconductor chips may include four second semiconductor chips, which may be stacked to expand the storage capacity of the package chip 200. Compared with the existing multiple semiconductor chips arranged in a flat pattern, the size of the package substrate 100 is reduced.

[0046] In an embodiment of the present application, the at least two second semiconductor chips may include six second semiconductor chips, which may be stacked to expand the storage capacity of the package chip 200. Compared with the existing multiple semiconductor chips arranged in a flat pattern, the size of the package substrate 100 is reduced.

[0047] In one embodiment, the at least two semiconductor chips may include eight second semiconductor chips, which may be stacked to expand the storage capacity of the package chip 200. Compared with the existing arrangement of multiple semiconductor chips in a flat pattern, the size of the package substrate 100 is reduced.

[0048] The packaged chip 200 may further include a second molding compound. The second molding compound may be used to package at least two second semiconductor chips to form the packaged chip 200.

[0049] The second molding compound can be made of the same material as in the prior art. For example, the second molding compound can be made of epoxy, resin, moldable polymer, etc. The material of the second molding compound is not limited in this application.

[0050] The package assembly 10 further includes a first semiconductor chip 300, which can be disposed on the package chip 200 and electrically connected to the substrate 100. Specifically, the first semiconductor chip 300 can be disposed on a surface of the package chip 200 away from the substrate 100.

[0051] The first semiconductor chip 300 may be a processor that performs a logic operation of data. For example, the first semiconductor chip 300 may include a system on chip (SOC) such as an application processor that performs a logic operation.

[0052] In one embodiment, a DAF film may be disposed on the surface of the first semiconductor chip 300 close to the package chip 200 to fix the first semiconductor chip 300 on the package chip 200. In other embodiments, other films may also be disposed to fix the first semiconductor chip 300 on the package chip 200.

[0053] The package assembly 10 further includes a fan-out region 400, which may be disposed on the package chip 200 and adjacent to the first semiconductor chip 300, and the fan-out region 400 may electrically connect the first semiconductor chip 300 and the substrate 100. Furthermore, the total area of ​​the fan-out region 400 and the first semiconductor chip 300 may be approximately equal to the area of ​​the package chip 200.

[0054] Specifically, the total area of ​​the fan-out region 400 and the first semiconductor chip 300 may be less than or equal to the area of ​​the package chip 200, so that the first semiconductor chip 300 and the fan-out region 400 can be simultaneously disposed on the surface of the package chip 200 away from the substrate 100. The difference between the area of ​​the package chip 200 and the total area of ​​the fan-out region 400 and the first semiconductor chip 300 is within a preset threshold range.

[0055] like Figure 1 and Figure 2 As shown, Figure 2 yes Figure 1 FIG. 4 is a schematic structural diagram of a first embodiment of a first semiconductor chip 300 and a fan-out region 400. FIG.

[0056] The fan-out area 400 can be arranged around two sides of the first semiconductor chip 300, that is, two adjacent sides of the first semiconductor chip 300 can be fanned out to diffuse the circuit of the first semiconductor chip 300 to reduce the difficulty of wire bonding, facilitate processing and manufacturing, and improve product yield.

[0057] In one embodiment, the fan-out region 400 may also be disposed around one side of the first semiconductor chip 300 or around an opposite side of the first semiconductor chip 300 .

[0058] In one embodiment, the fan-out region 400 may also be disposed around a portion of a side of the first semiconductor chip 300 .

[0059] like Figure 3 and Figure 4 As shown, Figure 4 yes Figure 3 FIG. 1 is a schematic structural diagram of a second embodiment of a first semiconductor chip 300 and a fan-out region 400. FIG.

[0060] The fan-out region 400 may also be arranged around the entire first semiconductor chip 300 , that is, fan out the entire first semiconductor chip 300 , for diffusing the circuits of the first semiconductor chip 300 to reduce the difficulty of wire bonding, facilitate processing and manufacturing, and improve product yield.

[0061] In other embodiments, the area of ​​the fan-out region 400 of the first semiconductor chip 300 may be determined according to actual conditions.

[0062] See also Figure 1 The package assembly 10 further includes a first molding material 500, which can be used to package the first semiconductor chip 300, the packaged chip 200 and the substrate 100. The first molding material 500 can be made of the same material as the second molding material, which will not be described in detail herein.

[0063] The package assembly 10 further includes a first connection line 610, which may include a gold wire, a copper wire, an alloy wire, etc. The substrate 100 may be provided with a first pad 110, and the fan-out region 400 may be provided with a second pad 410. One end of the first connection line 610 may be connected to the first pad 110, and the other end may be connected to the second pad 410.

[0064] The package assembly 10 may further include a second connection line 630 disposed in the fan-out region 400. Specifically, the second connection line 630 may include a gold wire, a copper wire, an alloy wire, etc. A third pad 310 may be provided on the surface of the first semiconductor chip 300 away from the package chip 200. One end of the second connection line 630 is connected to the second pad 410, and the other end is connected to the third pad 310, so that the first semiconductor chip 300 can be electrically connected to the substrate 100 through the first connection line 610 and the second connection line 630.

[0065] The fan-out region 400 may further include a redistribution layer, which may have a first surface 430 and a second surface 420 disposed opposite to each other, the first surface 430 of the redistribution layer may contact the first semiconductor chip 300, and the second pad 410 may be disposed on the second surface 420 of the redistribution layer.

[0066] Specifically, the second pad 410 on the second surface 420 of the fan-out region 400 can be arranged away from the first semiconductor chip 300. For example, the second pad 410 can be arranged at the edge of the second surface 420 of the redistribution layer to reduce the density of the circuit, reduce the difficulty of wire bonding, and improve the yield rate.

[0067] In one embodiment, the third pad 310 on the first semiconductor chip 300 may be disposed close to the fan-out region 400. For example, the third pad 310 may be disposed at an edge of the first semiconductor chip 300 to shorten the line of the second connection line 630.

[0068] The package assembly 10 further includes a third connection wire 620, specifically, the third connection wire 620 may include a gold wire, a copper wire, an alloy wire, etc. The substrate 100 may be provided with a fourth pad 120. A fifth pad 320 may be provided on the surface of the first semiconductor chip 300 away from the package chip 200. One end of the third connection wire 620 may be connected to the fourth pad 120, and the other end may be connected to the fifth pad 320, so that the first semiconductor chip 300 is electrically connected to the substrate 100.

[0069] Further, the redistribution layer may have a third surface 440, and the third surface 440 may be arranged opposite to the first surface 430 and the second surface 420. The third surface 440 of the redistribution layer may be located in the same plane as the surface of the first semiconductor chip 300 close to the package chip 200, so that the first semiconductor chip 300 and the fan-out region 400 can be stably placed on the package chip 200.

[0070] The package assembly 10 further includes a first solder ball 210, which is disposed on the surface of the packaged chip 200 close to the substrate 100. The packaged chip 200 uses a ball grid array packaging method to package at least two second semiconductor chips to form the packaged chip 200, so that the packaged chip 200 is electrically connected to the substrate 100 through the first solder ball 210 as an external lead of the packaged chip 200.

[0071] The packaging component 10 may also include a filling glue 700, which may be disposed between the packaging chip 200 and the substrate 100, so as to fill the gap between the first solder ball 210 and the substrate 100 after the packaging chip 200 and the substrate 100 are welded together, thereby effectively preventing defects such as voids and bubbles from occurring between the packaging chip 200 and the substrate 100 through the filling glue 700.

[0072] The package assembly 10 further includes a second solder ball 130 . The second solder ball 130 may be disposed on a surface of the substrate 100 away from the package chip 200 .

[0073] Therefore, the package assembly 10 provided in the present application is packaged into a packaged chip 200 by BGA packaging of multiple second semiconductor chips to expand the storage capacity of the packaged chip 200. Compared with the existing multiple semiconductor chips arranged in a flat pattern, the size of the package substrate 100 is reduced. The fan-out area 400 is arranged adjacent to the first semiconductor chip 300, and the second pad 410 and the second connecting line 630 on the second surface 420 of the fan-out area 400 are used to diffuse the circuit of the first semiconductor chip 300, thereby reducing the density of the circuit and facilitating processing and manufacturing. The first semiconductor chip 300 and the fan-out area 400 can both be arranged on the packaged chip 200 to reduce the size of the entire substrate 100 and save processing costs; and the first semiconductor chip 300 can be electrically connected to the substrate 100 through the fan-out area 400, which can reduce the length of the welding wire to reduce the probability of adverse phenomena such as signal attenuation, crosstalk, and parasitic capacitance in the welding wire.

[0074] The present application also provides an electronic device, which includes the packaging assembly 10 in any of the above embodiments. In different embodiments, the electronic device includes but is not limited to a cellular phone, a smart phone, other wireless communication devices, a personal digital assistant, an audio player, other media players, a music recorder, a video recorder, a camera, other media recorders, a radio, a medical device, a calculator, a programmable remote control, a pager, a netbook computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a moving picture expert group (MPEG-1 or MPEG-2) audio layer 3 (MP3) player, a portable medical device, and a digital camera and a combination thereof.

[0075] See also Figure 5 , Figure 5 It is a flow chart of the packaging method provided by this application.

[0076] The present application also provides a packaging method, the method comprising:

[0077] Step S101: Provide a substrate 100, wherein the substrate 100 can be made of the same material as the prior art, for example, the substrate 100 can be formed of a semiconductor material, which is silicon, such as bismaleimide triazine (BT), polyimide or an organic material of Ajinomoto build-up film (ABF).

[0078] Step S102: placing a packaged chip 200 on the substrate 100, wherein the packaged chip 200 is electrically connected to the substrate 100;

[0079] The packaged chip 200 may include at least two second semiconductor chips (not shown). The second semiconductor chip may be a memory semiconductor chip for storing data. The memory semiconductor chip may be a cache memory chip that temporarily stores and provides data used in the logic operation of the system on chip.

[0080] Specifically, at least two second semiconductor chips may be packaged in a ball grid array packaging manner to form a packaged chip 200. The packaged chip 200 is packaged in a ball grid array manner and is directly disposed on the substrate 100. The packaged chip 200 may be electrically connected to the substrate 100 by using solder balls or solder bumps of the packaged chip 200 close to the surface of the substrate 100 as external leads.

[0081] In this embodiment, the packaged chip 200 adopts a standard BGA package, and second semiconductor chips of different storage types can be packaged into the packaged chip 200 to save packaging costs.

[0082] The second semiconductor chips may be stacked or arranged in parallel.

[0083] Specifically, the at least two second semiconductor chips may include two second semiconductor chips, and the two semiconductor chips may be stacked or arranged in parallel to expand the storage capacity of the package chip 200 .

[0084] In an embodiment of the present application, the at least two second semiconductor chips may include four second semiconductor chips, which may be stacked to expand the storage capacity of the package chip 200. Compared with the existing multiple semiconductor chips arranged in a flat pattern, the size of the package substrate 100 is reduced.

[0085] In an embodiment of the present application, the at least two second semiconductor chips may include six second semiconductor chips, which may be stacked to expand the storage capacity of the package chip 200. Compared with the existing multiple semiconductor chips arranged in a flat pattern, the size of the package substrate 100 is reduced.

[0086] In one embodiment, the at least two semiconductor chips may include eight second semiconductor chips, and the eight semiconductor chips may be stacked to expand the storage capacity of the package chip 200. Compared with the existing multiple semiconductor chips arranged in a flat pattern, the size of the package substrate 100 is reduced.

[0087] The packaged chip 200 may further include a second molding compound. The second molding compound may be used to package at least two second semiconductor chips to form the packaged chip 200.

[0088] Before the packaged chip 200 is disposed on the substrate 100 , the first solder balls 210 may be implanted on the surface of the packaged chip 200 close to the substrate 100 .

[0089] The packaged chip 200 is packaged by using a ball grid array packaging method to package at least two second semiconductor chips to form the packaged chip 200 , and the first solder balls 210 are used as external leads of the packaged chip 200 so that the packaged chip 200 is electrically connected to the substrate 100 .

[0090] After the packaging chip 200 is set on the substrate 100, a filling glue 700 can also be implanted between the packaging chip 200 and the substrate 100 to fill the gap between the first solder ball 210 and the substrate 100 after the packaging chip 200 and the substrate 100 are welded. The filling glue 700 can effectively prevent defects such as voids and bubbles from occurring between the packaging chip 200 and the substrate 100.

[0091] Step S103 : fanning out the first semiconductor chip 300 to obtain a fan-out region 400 , wherein the fan-out region 400 is disposed adjacent to the first semiconductor chip 300 .

[0092] Specifically, the fan-out area 400 can be set around two sides of the first semiconductor chip 300, that is, two adjacent sides of the first semiconductor chip 300 can be fanned out to diffuse the circuit of the first semiconductor chip 300 to reduce the difficulty of wire bonding, facilitate processing and manufacturing, and improve product yield.

[0093] In one embodiment, the fan-out region 400 may also be disposed around one side of the first semiconductor chip 300 or around an opposite side of the first semiconductor chip 300 .

[0094] In one embodiment, the fan-out region 400 may also be disposed around a portion of a side of the first semiconductor chip 300 .

[0095] In one embodiment, the fan-out area 400 can also be set around the entire first semiconductor chip 300, that is, fan out the entire first semiconductor chip 300, to diffuse the circuit of the first semiconductor chip 300, so as to reduce the difficulty of wire bonding, facilitate processing and manufacturing, and improve product yield.

[0096] In other embodiments, the area of ​​the fan-out region 400 of the first semiconductor chip 300 may be determined according to actual conditions.

[0097] Step S104: The first semiconductor chip 300 and the fan-out area 400 are arranged on the packaging chip 200, and the first semiconductor chip 300 is electrically connected to the substrate 100, wherein the fan-out area 400 is electrically connected to the first semiconductor chip 300 and the substrate 100, and wherein the total area of ​​the fan-out area 400 and the first semiconductor chip 300 is approximately equal to the area of ​​the packaging chip 200.

[0098] Step S105 : encapsulating the first semiconductor chip 300 , the packaged chip 200 and the substrate 100 by using a first molding compound 500 .

[0099] Specifically, the first molding material 500 can be made of the same material as in the prior art. For example, the first molding material 500 can be made of epoxy, resin, moldable polymer, etc. The material of the first molding material 500 is not limited in this application.

[0100] Furthermore, after the first semiconductor chip 300 , the packaged chip 200 and the substrate 100 are packaged with the first molding material 500 , second solder balls 130 may be implanted on a surface of the substrate 100 away from the packaged chip 200 .

[0101] Therefore, the package assembly 10 provided in the present application is packaged into a packaged chip 200 by BGA packaging of multiple second semiconductor chips to expand the storage capacity of the packaged chip 200. Compared with the existing multiple semiconductor chips arranged in a flat pattern, the size of the package substrate 100 is reduced. The fan-out area 400 is arranged adjacent to the first semiconductor chip 300, and the second pad 410 and the second connecting line 630 on the second surface 420 of the fan-out area 400 are used to diffuse the circuit of the first semiconductor chip 300, thereby reducing the density of the circuit and facilitating processing and manufacturing. The first semiconductor chip 300 and the fan-out area 400 can both be arranged on the packaged chip 200 to reduce the size of the entire substrate 100 and save processing costs; and the first semiconductor chip 300 can be electrically connected to the substrate 100 through the fan-out area 400, which can reduce the length of the welding wire to reduce the probability of adverse phenomena such as signal attenuation, crosstalk, and parasitic capacitance in the welding wire.

[0102] Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A packaging component, characterized in that: The packaging assembly comprises: substrate; A packaging chip is arranged on the substrate, and the packaging chip is electrically connected to the substrate; A first semiconductor chip is disposed on the package chip, and the first semiconductor chip is electrically connected to the substrate; a fan-out region, disposed on the packaged chip and adjacent to the first semiconductor chip, the fan-out region electrically connecting the first semiconductor chip and the substrate, wherein a total area of ​​the fan-out region and the first semiconductor chip is less than or equal to an area of ​​the packaged chip; A first molding compound, used for packaging the first semiconductor chip, the packaging chip and the substrate; Among them, the substrate is provided with a first solder pad, and the fan-out area is provided with a second solder pad; the packaging component also includes a first connecting wire, one end of the first connecting wire is connected to the first solder pad, and the other end is connected to the second solder pad; the fan-out area includes a redistribution layer, the redistribution layer has a first surface and a second surface arranged opposite to each other, the first surface of the redistribution layer is in contact with the first semiconductor chip, and the second solder pad is arranged on the second surface of the redistribution layer; the packaging component also includes a second connecting wire arranged in the redistribution layer, and the surface of the first semiconductor chip away from the packaging chip is provided with a third solder pad, one end of the second connecting wire is connected to the second solder pad, and the other end is connected to the third solder pad.

2. The packaging assembly according to claim 1, characterized in that: The packaging component also includes a third connecting wire, the substrate is provided with a fourth pad, the surface of the first semiconductor chip away from the packaging chip is provided with a fifth pad, one end of the third connecting wire is connected to the fourth pad, and the other end is connected to the fifth pad.

3. The packaging assembly according to claim 1, characterized in that: The redistribution layer has: The third surface, the third surface of the redistribution layer is arranged opposite to the first surface and the second surface of the redistribution layer, and the third surface of the redistribution layer and the surface of the first semiconductor chip close to the packaged chip are located in the same plane.

4. The packaging assembly according to any one of claims 1 to 3, characterized in that: The packaging assembly further comprises: A first solder ball is disposed on a surface of the packaged chip close to the substrate; The second solder ball is arranged on the surface of the substrate away from the packaged chip.

5. The packaging assembly according to claim 4, characterized in that: The packaging assembly further comprises: The filling glue is arranged between the packaged chip and the substrate.

6. The packaging assembly according to claim 1, characterized in that: The packaged chip comprises: At least two second semiconductor chips, wherein the at least two second semiconductor chips are stacked or arranged in parallel; The second molding compound is used to encapsulate the at least two second semiconductor chips.

7. An electronic device, characterized in that: The electronic device comprises the packaging assembly according to any one of claims 1 to 6.

8. A packaging method, characterized in that: The method comprises: providing a substrate; A packaging chip is arranged on the substrate, wherein the packaging chip is electrically connected to the substrate; Fanning out the first semiconductor chip to obtain a fan-out region, wherein the fan-out region is disposed adjacent to the first semiconductor chip; The first semiconductor chip and the fan-out region are arranged on the packaged chip, the first semiconductor chip is electrically connected to the substrate, the fan-out region is electrically connected to the first semiconductor chip and the substrate, and the total area of ​​the fan-out region and the first semiconductor chip is less than or equal to the area of ​​the packaged chip; encapsulating the first semiconductor chip, the packaged chip and the substrate by a first molding compound; Among them, the substrate is provided with a first solder pad, and the fan-out area is provided with a second solder pad; the packaging component also includes a first connecting wire, one end of the first connecting wire is connected to the first solder pad, and the other end is connected to the second solder pad; the fan-out area includes a redistribution layer, the redistribution layer has a first surface and a second surface arranged opposite to each other, the first surface of the redistribution layer is in contact with the first semiconductor chip, and the second solder pad is arranged on the second surface of the redistribution layer; the packaging component also includes a second connecting wire arranged in the redistribution layer, and a third solder pad is provided on the surface of the first semiconductor chip away from the packaging chip, and one end of the second connecting wire is connected to the second solder pad, and the other end is connected to the third solder pad.

Images