A multi-channel radio frequency transceiver chip

Abstract

The present invention discloses a multi-channel radio frequency transceiver chip, including a power division synthesis network, a radio frequency port, a plurality of radio frequency transceiver channels and radio frequency antennas corresponding to the radio frequency transceiver channels one by one; the radio frequency port is respectively connected to each radio frequency transceiver channel through the power division synthesis network, and the radio frequency transceiver channel is also connected to the corresponding radio frequency antenna; each of the radio frequency transceiver channels includes a digitally controlled attenuator, a first switching switch, an AMP amplifier, a driving amplifier DRV, a second switching switch, a digital phase shifter, a third switching switch, a limiter, a low noise amplifier LNA, a power amplifier PA and a fourth switching switch; the first switching switch, the second switching switch, the third switching switch and the fourth switching switch are all single-pole double-throw switches. The present invention integrates a plurality of radio frequency transceiver channels, can use different radio frequency channels and corresponding radio frequency antennas to complete signal transceiver in different directions, and provides convenience for signal transceiver work.

Description

Technical Field

[0001] The invention relates to a radio frequency chip, in particular to a multi-channel radio frequency transceiver chip. Background Art

[0002] RF chips are widely used in communications, especially in the Ka band and even higher frequency bands, where integrated chips are often required for signal transmission and reception to reduce the size of the equipment.

[0003] However, at present, the channel resources of RF transceiver chips are limited, and signals can often only be transmitted and received in one direction, which brings some inconvenience to the signal transmission and reception. Summary of the invention

[0004] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a multi-channel RF transceiver chip that integrates multiple RF transceiver channels and can use different RF channels and corresponding RF antennas to complete signal reception and transmission in different directions, thereby providing convenience for signal reception and transmission.

[0005] The object of the present invention is achieved through the following technical solutions: a multi-channel radio frequency transceiver chip, comprising a power division synthesis network, a radio frequency port, a plurality of radio frequency transceiver channels and radio frequency antennas corresponding to the radio frequency transceiver channels one by one; the radio frequency port is respectively connected to each radio frequency transceiver channel through the power division synthesis network, and the radio frequency transceiver channel is also connected to the corresponding radio frequency antenna;

[0006] Each of the radio frequency transceiver channels includes a digitally controlled attenuator, a first switch, an AMP amplifier, a driving amplifier DRV, a second switch, a digital phase shifter, a third switch, a limiter, a low noise amplifier LNA, a power amplifier PA and a fourth switch; the first switch, the second switch, the third switch and the fourth switch are all single-pole double-throw switches;

[0007] One end of the digitally controlled attenuator is connected to the power division and synthesis network, the other end of the digitally controlled attenuator is connected to the fixed end of the first switching switch, the input end of the AMP amplifier is connected to a moving end of the second switching switch, the output end of the AMP amplifier is connected to a moving end of the first switching switch, the input end of the driving amplifier DRV is connected to the other moving end of the first switching switch, the output end of the driving amplifier DRV is connected to the other moving end of the second switching switch, the fixed end of the second switching switch is also connected to the fixed end of the third switching switch through a digital phase shifter, the input end of the limiter is connected to a moving end of the fourth switching switch, the output end of the limiter is connected to a moving end of the third switching switch through a low noise amplifier LNA, the input end of the power amplifier is connected to the other moving end of the third switching switch, the output end of the power amplifier is connected to the other moving end of the fourth switching switch, and the fixed end of the fourth switching switch is connected to the RF antenna.

[0008] Preferably, the number of the RF transceiver channels and the number of RF antennas are both four, and the power division synthesis network may include a 1-to-4 power divider, the combining end of the power divider is connected to the RF port, and the power dividing ends of the power divider are respectively connected to four RF transceiver channels; the power division synthesis network may also include three 1-to-2 power dividers, wherein the combining end of the first power divider is connected to the RF port, and the two power dividing ends of the first power divider are respectively connected to the combining ends of the second power divider and the third power divider, and the power dividing ends of the second power divider and the third power divider are respectively connected to two RF transceiver channels.

[0009] The beneficial effects of the present invention are as follows: the present invention integrates multiple RF transceiver channels, and can use different RF channels and corresponding RF antennas to complete signal transmission and reception in different directions, thus providing convenience for signal transmission and reception. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a schematic diagram of the principle of the present invention;

[0011] Figure 2 It is a schematic diagram of the principle of a power amplifier PA;

[0012] Figure 3 Schematic diagram of the principle of digital phase shifter. DETAILED DESCRIPTION

[0013] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following.

[0014] like Figure 1As shown, a multi-channel RF transceiver chip includes a power division synthesis network, a RF port, a plurality of RF transceiver channels and RF antennas corresponding to the RF transceiver channels one by one; the RF port is connected to each RF transceiver channel through the power division synthesis network, and the RF transceiver channel is also connected to the corresponding RF antenna;

[0015] Each of the radio frequency transceiver channels includes a digitally controlled attenuator, a first switch, an AMP amplifier, a driving amplifier DRV, a second switch, a digital phase shifter, a third switch, a limiter, a low noise amplifier LNA, a power amplifier PA and a fourth switch; the first switch, the second switch, the third switch and the fourth switch are all single-pole double-throw switches;

[0016] One end of the digitally controlled attenuator is connected to the power division and synthesis network, the other end of the digitally controlled attenuator is connected to the fixed end of the first switching switch, the input end of the AMP amplifier is connected to a moving end of the second switching switch, the output end of the AMP amplifier is connected to a moving end of the first switching switch, the input end of the driving amplifier DRV is connected to the other moving end of the first switching switch, the output end of the driving amplifier DRV is connected to the other moving end of the second switching switch, the fixed end of the second switching switch is also connected to the fixed end of the third switching switch through a digital phase shifter, the input end of the limiter is connected to a moving end of the fourth switching switch, the output end of the limiter is connected to a moving end of the third switching switch through a low noise amplifier LNA, the input end of the power amplifier is connected to the other moving end of the third switching switch, the output end of the power amplifier is connected to the other moving end of the fourth switching switch, and the fixed end of the fourth switching switch is connected to the RF antenna.

[0017] In an embodiment of the present application, the number of RF transceiver channels and RF antennas are both four, and the power division synthesis network may include a 1-to-4 power divider, the combining end of the power divider is connected to the RF port, and the power division ends of the power divider are each connected to four RF transceiver channels; the power division synthesis network may also include three 1-to-2 power dividers, wherein the combining end of the first power divider is connected to the RF port, and the two power division ends of the first power divider are respectively connected to the combining ends of the second power divider and the third power divider, and the power division ends of the second power divider and the third power divider are each connected to two RF transceiver channels.

[0018] like Figure 2As shown, in an embodiment of the present application, the power amplifier PA includes field effect tubes T1~T3, resistors R1~R3, capacitors C1~C7, inductors Lg, inductors Ld, signal input port RFin and signal output port RFout; the drain of the field effect tube T3 is connected to the VDD power supply terminal through the inductor Ld, the source of the field effect tube T3 is connected to the drain of the field effect tube T2, the gate of the field effect tube T3 is connected to the Vg3 port through the resistor R3, and a grounded capacitor C4 is also connected between the resistor R3 and the Vg3 port, and a grounded capacitor C3 is also connected between the resistor R3 and the gate of the field effect tube T3; the source of the field effect tube T2 is connected to the drain of the field effect tube T1, and the gate of the field effect tube T2 is connected to the Vg3 port. The gate is connected to the Vg2 port through a resistor R2, a grounded capacitor C5 is further connected between the resistor R2 and the Vg2 port, and a grounded capacitor C2 is further connected between the resistor R2 and the field effect transistor T2; the source of the field effect transistor T1 is grounded, the gate of the field effect transistor T1 is connected to the signal input port RFin through an inductor Lg and a capacitor C7 in sequence, one end of the resistor R1 is connected between the inductor Lg and the gate of the field effect transistor T1, the other end of the resistor R1 is grounded through a capacitor C1, a grounded capacitor C6 is further connected between the inductor Lg and the capacitor C7, and a Vg1 port is further connected between the resistor R1 and the capacitor C1; the signal output port RFout is connected to the drain of the field effect transistor T3;

[0019] The field effect transistors T1 to T3 are all PMOS field effect transistors; wherein the three ports Vg1, Vg2 and Vg3 are gate voltage ports, which are used to respectively access the start-up voltages of the field effect transistors T1, T2 and T3.

[0020] In the embodiment of the present application, the power amplifier further includes an inductor Lm and a capacitor Cm, one end of the inductor Lm is connected to the source of the field effect transistor T3, and the other end of the inductor Lm is grounded through the capacitor Cm.

[0021] like Figure 3 As shown, the digital phase shifter includes a coupler, the coupler includes a first coupling part and a second coupling part, the first end of the first coupling part is connected to the signal input port through a first LC network, and the second end of the first coupling part is connected to the first load circuit; the first end of the second coupling part is connected to the signal output port, and the second end is connected to the second load circuit. In an embodiment of the present application, the first LC network includes an inductor Lm1 and a capacitor Cm1, one end of the inductor Lm1 is connected to the first end of the first coupling part, the other end of the inductor Lm1 is connected to the signal input port, one end of the capacitor Cm1 is connected between the inductor Lm1 and the signal input port, and the other end of the capacitor Cm1 is grounded.

[0022] In an embodiment of the present application, the second LC network includes an inductor Lm2 and a capacitor Cm2, one end of the inductor Lm2 is connected to the first end of the second coupling portion, the other end of the inductor Lm2 is connected to the signal output port, one end of the capacitor Cm2 is connected between the inductor Lm2 and the signal output port, and the other end of the capacitor Cm2 is grounded.

[0023] In an embodiment of the present application, the first load circuit and the second load circuit include the same circuit structure, which includes an inductor L1, an inductor L2, a variable capacitor Cv1, a variable capacitor Cv2, a resistor R4, a resistor R5, a resistor R6, a capacitor C8, and a capacitor C9;

[0024] One end of the resistor R6 is connected to the Vref port, and the other end of the resistor R6 is grounded through the inductor L1, the variable capacitor Cv1, and the capacitor C8 in sequence; one end of the inductor L2 is connected to the common end of the resistor R6 and the inductor L1, and the other end of the inductor L2 is grounded through the variable capacitor Cv2 and the capacitor C9 in sequence; one end of the resistor R4 is connected between the variable capacitor Cv1 and the capacitor C8, and the other end of the resistor R4 is connected to the VC1 port; one end of the resistor R5 is connected between the variable capacitor Cv2 and the capacitor C9, and the second end of the resistor R5 is connected to the VC2 port;

[0025] For the circuit structure in the first load circuit, the common end of the resistor R6 and the inductor L1 is connected to the second end of the first coupling portion; for the circuit structure in the second load circuit, the common end of the resistor R6 and the inductor L1 is connected to the second end of the second coupling portion.

[0026] The working principle of the present invention is as follows: during the transmission operation, the radio frequency signal is divided into 4 paths with equal amplitude and phase through a 1-to-4 power division synthesis network, and is transmitted to each channel digital controlled attenuator respectively, and is transmitted to the SPDT switch after amplitude adjustment. At this time, the working mode of each switch is at the transmitting end, and the radio frequency signal is transmitted to the driving amplifier, and is transmitted to the switch again after amplification, and then transmitted to the digital phase shifter through the switch for phase adjustment, and then transmitted to the transmitting branch through the switch for power amplification, and finally the signal is output through the switch.

[0027] During the receiving operation, the RF signal is input from each branch to each transceiver channel, and the receiving branch is selected through the switch. It first undergoes large signal limiting, then low-noise amplification, and then is output to the digital phase shifter through the switch for phase adjustment. Then it enters the receiving branch through the switch for low-noise amplification again, and is output to the digital attenuator through the switch for amplitude adjustment, and finally is output through the 4-in-1 combiner.

[0028] In the present invention, assuming that the PA operates in current mode and the output is linear, if the VDD is higher, the Pout is higher and a large number of field effect tube stacks are required to ensure the reliability of the PA. However, a large number of field effect tube stacks will lead to an increase in parasitic capacitance or resistance loss, resulting in a decrease in PAE. After three stacks are selected in the present application, a matching network composed of Lm and Cm is connected to the source of the field effect tube T3. The network is used to match the source impedance of the field effect tube T3, thereby improving the impedance and improving the PAE of the power amplifier. Through simulation, it is found that this can increase the PAE by 6%. At the same time, this structure will not cause excessive loss even if an inductor with a medium quality factor is used, because it is not connected in series on the path of the main output signal. Taking into account the power loss and voltage disturbance caused by overlap, the present invention adjusts the voltage and current phases by connecting R2 / C2 and R3 / C3 to the gate of the field effect tube during design, thereby reducing overlap, thereby reducing power loss and adjusting voltage disturbance. Due to the reduction in loss, the PAE of the power amplifier can be further improved.

[0029] In an embodiment of the present application, the Vc1 port and the Vc2 port are variable capacitance control ports, and the Vref port is connected to a fixed voltage; in the first load circuit, the capacitance of the variable capacitor Cv1 is controlled by the control voltage input to the Vc1 port, and the capacitance of the variable capacitor Cv2 is controlled by the control voltage input to the Vc2 port. After the capacitance of the variable capacitor Cv1 and the variable capacitor Cv2 changes, the resonant frequency of the LC resonant circuit (the resonant circuit composed of the variable capacitor Cv1 and the inductor L1 and the resonant circuit composed of the variable capacitor Cv2 and the inductor L2) in which they are located will also change, and the resonant frequency is different from the resonant frequency of the external input (the resonant frequency from the first coupling part). The frequency difference in the corresponding phase shift changes; similarly, in the second load circuit, there is also a frequency difference between the resonant frequency of the LC resonant circuit and the resonant frequency of the external input (the resonant frequency from the second coupling part), which corresponds to the phase shift change; by adjusting the frequency difference in the first load circuit or the second load circuit (can also be adjusted together), the phase shift value can be adjusted; and in the first load circuit or the second load circuit, the change in the frequency difference depends on the capacitance value of the variable capacitor Cv1 and the variable capacitor Cv2, and the capacitance value is controlled by the voltage of the Vc1 port and the Vc2 port, so the change in voltage causes the capacitance to change, the frequency difference changes, and the change in frequency difference causes the phase shift to change, thereby achieving phase shift. In this application, an LC network composed of Lm1 and Cm1, and an LC network composed of Lm2 and Cm2 are applied to the input and output ports to achieve impedance conversion of the input and output ports, thereby maintaining relatively stable input and output impedances.

[0030] It should be noted that, without departing from the spirit and essence of the present invention, technicians familiar with the field may make various corresponding changes and modifications based on the present invention, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present invention.

Claims

1. A multi-channel radio frequency transceiver chip, characterized in that: It includes a power division synthesis network, a radio frequency port, a plurality of radio frequency transceiver channels and radio frequency antennas corresponding to the radio frequency transceiver channels one by one; the radio frequency port is connected to each radio frequency transceiver channel through the power division synthesis network, and the radio frequency transceiver channel is also connected to the corresponding radio frequency antenna; Each of the radio frequency transceiver channels includes a digitally controlled attenuator, a first switch, an AMP amplifier, a driving amplifier DRV, a second switch, a digital phase shifter, a third switch, a limiter, a low noise amplifier LNA, a power amplifier PA and a fourth switch; the first switch, the second switch, the third switch and the fourth switch are all single-pole double-throw switches; One end of the digitally controlled attenuator is connected to the power division and synthesis network, the other end of the digitally controlled attenuator is connected to the fixed end of the first switch, the input end of the AMP amplifier is connected to a moving end of the second switch, the output end of the AMP amplifier is connected to a moving end of the first switch, the input end of the driving amplifier DRV is connected to the other moving end of the first switch, the output end of the driving amplifier DRV is connected to the other moving end of the second switch, the fixed end of the second switch is also connected to the fixed end of the third switch through a digital phase shifter, the input end of the limiter is connected to a moving end of the fourth switch, the output end of the limiter is connected to a moving end of the third switch through a low noise amplifier LNA, the input end of the power amplifier is connected to the other moving end of the third switch, the output end of the power amplifier is connected to the other moving end of the fourth switch, and the fixed end of the fourth switch is connected to the radio frequency antenna; The number of the radio frequency transceiver channels and radio frequency antennas is four; The power division and synthesis network includes a 1-to-4 power divider, the combining end of the power divider is connected to the RF port, and the power dividing ends of the power divider are respectively connected to four RF transceiver channels; The power division synthesis network includes three 1-to-2 power dividers, wherein the combining end of the first power divider is connected to the RF port, the two power division ends of the first power divider are respectively connected to the combining ends of the second power divider and the third power divider, and the power division ends of the second power divider and the third power divider are each connected to two RF transceiver channels.

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