Display substrate and preparation method thereof, and display panel

Abstract

The present disclosure provides a display substrate, which includes: a substrate having a display side and a back side opposite to each other; a display structure arranged on the display side of the substrate, the display structure including a positive voltage interface for providing a positive voltage and a plurality of pixel circuits, each pixel circuit including a plurality of transistors; a shielding structure arranged between the substrate and the display structure, the shielding structure being made of a conductive material and electrically connected to the positive voltage interface; the orthographic projection of at least part of the active area of ​​the transistor on the substrate coincides with the orthographic projection of the shielding structure on the substrate; an insulating isolation layer arranged between the shielding structure and the display structure. The present disclosure also provides a method for preparing a display substrate and a display panel.

Description

Technical Field

[0001] The present disclosure relates to the technical field of display substrates, and in particular to a display substrate and a preparation method thereof, and a display panel. Background Art

[0002] The display panel may include a display substrate and a cover plate (CG, Cover Galss) made of materials such as glass, and a metal heat dissipation layer (SCF) may be further provided on a side of the display substrate facing away from the cover plate.

[0003] In practice, it is found that when the above display panel is subjected to more friction, poor display will occur, such as causing reference Figure 1 The four-screen phenomenon. Summary of the invention

[0004] The present disclosure provides a display substrate and a method for preparing the same, and a display panel.

[0005] In a first aspect, an embodiment of the present disclosure provides a display substrate, comprising:

[0006] a substrate having opposing display and back sides;

[0007] A display structure disposed on the display side of the substrate, the display structure comprising a positive voltage interface for providing a positive voltage and a plurality of pixel circuits, each pixel circuit comprising a plurality of transistors;

[0008] A shielding structure is provided between the substrate and the display structure, the shielding structure is made of a conductive material and is electrically connected to the positive voltage interface; the orthographic projection of at least part of the active area of ​​the transistor on the substrate coincides with the orthographic projection of the shielding structure on the substrate;

[0009] An insulating isolation layer is provided between the shielding structure and the display structure.

[0010] In some embodiments, an orthographic projection of an active region of each of the transistors on the substrate coincides with an orthographic projection of the shielding structure on the substrate.

[0011] In some embodiments, the shielding structure includes a plurality of connecting portions, a plurality of shielding portions;

[0012] Each of the shielding parts corresponds to an active area of ​​a transistor, and the orthographic projection of the active area of ​​the transistor on the substrate coincides with the orthographic projection of the corresponding shielding part on the substrate;

[0013] Each of the shielding parts is electrically connected to the positive pressure interface through a connecting part.

[0014] In some embodiments, the display structure further includes:

[0015] A plurality of positive pressure signal lines extending along a first direction, each of the positive pressure signal lines connecting a plurality of pixel circuits arranged in a row along the first direction and electrically connected to the positive pressure interface;

[0016] Each of the shielding parts is electrically connected to the positive pressure signal line through a connecting part.

[0017] In some embodiments, the connection portion includes a plurality of first connection portions and a plurality of second connection portions extending along the first direction;

[0018] A plurality of shielding parts corresponding to transistors in a plurality of pixel circuits arranged in a row in the first direction are respectively connected to the same second connecting part through the first connecting parts;

[0019] At one end of the display substrate along the first direction, each of the second connecting portions is connected to a positive voltage signal line through a via hole in the isolation layer.

[0020] In some embodiments, the connection portion further includes a third connection portion;

[0021] In at least some of the pixel circuits adjacent to each other in a direction perpendicular to the first direction, at least some of the shielding parts corresponding to transistors located in different pixel circuits are connected to each other through a third connecting part.

[0022] In some embodiments, the connection portion includes a fourth connection portion;

[0023] The shielding parts corresponding to the multiple transistors of each pixel circuit are connected to the fourth connecting part, and the fourth connecting part is connected to the positive voltage signal line through a via hole in the isolation layer in the pixel circuit.

[0024] In some embodiments, the display structure further includes:

[0025] A gate insulating layer disposed on a side of the active region of each transistor facing away from the substrate;

[0026] A first gate layer is arranged on a side of the gate insulating layer facing away from the substrate, and the gate of the transistor is located in the first gate layer.

[0027] In some embodiments, the transistor is a P-type transistor.

[0028] In some embodiments, the display structure further includes:

[0029] A first interlayer insulating layer located on a side of the first gate layer facing away from the substrate;

[0030] A second gate layer located on a side of the first insulating layer facing away from the substrate;

[0031] a second interlayer insulating layer located on a side of the second gate layer facing away from the substrate;

[0032] a source-drain layer located on a side of the second interlayer insulating layer facing away from the substrate;

[0033] A planarization layer located on a side of the source / drain layer facing away from the substrate;

[0034] A light emitting device is located on a side of the planarization layer away from the substrate.

[0035] In some embodiments, each of the pixel circuits comprises:

[0036] A storage capacitor, a first electrode of which is connected to a positive voltage signal terminal, and the positive voltage signal terminal is electrically connected to a positive voltage interface;

[0037] A first transistor, a gate of which is connected to the reset signal terminal, a first electrode of which is connected to the second electrode of the storage capacitor, and a second electrode of which is connected to the initialization signal terminal;

[0038] a second transistor, a gate of which is connected to the gate signal terminal, and a first electrode of which is connected to the second electrode of the storage capacitor;

[0039] a third transistor, a gate of which is connected to the second electrode of the storage capacitor, and a second electrode of which is connected to the second electrode of the second transistor;

[0040] a fourth transistor, a gate of which is connected to the gate signal terminal, a first electrode of which is connected to the first electrode of the third transistor, and a second electrode of which is connected to the data signal terminal;

[0041] a fifth transistor, whose gate is connected to the control signal terminal, whose first electrode is connected to the positive voltage signal terminal, and whose second electrode is connected to the first electrode of the third transistor;

[0042] a sixth transistor, a gate of which is connected to the control signal terminal, and a first electrode of which is connected to the second electrode of the second transistor;

[0043] a seventh transistor, a gate of which is connected to the gate signal terminal, a first electrode of which is connected to the second electrode of the sixth transistor, and a second electrode of which is connected to the initialization signal terminal;

[0044] The light emitting device has a first electrode connected to the second electrode of the sixth transistor and a second electrode connected to the negative voltage signal terminal.

[0045] In some embodiments, at least an orthographic projection of an active area of ​​the second transistor and an active area of ​​the fourth transistor on the substrate coincides with an orthographic projection of the shielding structure on the substrate.

[0046] In a second aspect, an embodiment of the present disclosure provides a display panel, comprising:

[0047] Any of the above display substrates;

[0048] a cover plate, which is located outside the display side of the substrate of the display substrate;

[0049] The metal heat dissipation layer is located on the back side of the substrate of the display substrate.

[0050] In a third aspect, an embodiment of the present disclosure provides a method for preparing a display substrate, wherein the display substrate is any one of the above-mentioned substrates, and the preparation method comprises:

[0051] A shielding structure, an isolation layer and a display structure are sequentially formed on the display side of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the detailed embodiments, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more obvious to those skilled in the art by describing the detailed embodiments with reference to the accompanying drawings. In the accompanying drawings:

[0053] Figure 1 This is a photograph of a four-screen phenomenon;

[0054] Figure 2 A schematic diagram of a top view of a stacking relationship of a portion of a structure at a pixel circuit in a display substrate of an embodiment of the present disclosure;

[0055] Figure 3 A schematic diagram of the cross-sectional stacking relationship of a portion of the structure at an active area in a display panel according to an embodiment of the present disclosure;

[0056] Figure 4 is a circuit diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure;

[0057] Figure 5 for Figure 4 A driving timing diagram of a pixel circuit;

[0058] Figure 6 A schematic diagram of a top view of a shielding structure at a pixel circuit in a display substrate according to an embodiment of the present disclosure;

[0059] Figure 7 A schematic diagram of a connection method between a second connection portion and a positive pressure signal line in a display substrate according to an embodiment of the present disclosure;

[0060] Figure 8 It is a schematic diagram of a top view of the structure of a semiconductor layer at a pixel circuit in a display substrate of an embodiment of the present disclosure;

[0061] Fig. 9 It is a schematic diagram of a top view of the structure of a first gate layer at a pixel circuit in a display substrate of an embodiment of the present disclosure;

[0062] Fig.10 is a schematic diagram of a top view of the structure of a second gate layer at a pixel circuit in a display substrate of an embodiment of the present disclosure;

[0063] Fig.11 A schematic diagram of a top view of the structure of a source-drain layer at a pixel circuit in a display substrate according to an embodiment of the present disclosure;

[0064] The meanings of the various figure marks in the embodiments of the present disclosure are as follows: 1. shielding structure; 11. shielding part; 121. first connecting part; 122. second connecting part; 123. third connecting part; 2. active area; 5. gate; 31. positive voltage signal line; 39. data signal line; 91. substrate; 92. metal heat dissipation layer; 93. isolation layer; 94. gate insulation layer; 99. cover plate; T1. first transistor; T2. second transistor; T3. third transistor; T4. fourth transistor; T5. fifth transistor; T6. sixth transistor; T7. seventh transistor; OLED, light-emitting device; Cst, storage capacitor; VDD, positive voltage signal terminal; VSS, negative voltage signal terminal; Reset, reset signal terminal; Gate, gate signal terminal; Data, data signal terminal; EM, control signal terminal; Vinit, initialization signal terminal; N1, first node. DETAILED DESCRIPTION

[0065] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the display substrate and its preparation method, and the display panel provided by the present disclosure are described in detail below with reference to the accompanying drawings.

[0066] The present disclosure will be described more fully below with reference to the accompanying drawings, but the embodiments shown may be embodied in different forms and should not be construed as being limited to the embodiments set forth in the present disclosure. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete and to enable those skilled in the art to fully understand the scope of the present disclosure.

[0067] The present disclosure may be described with reference to plan views and / or cross-sectional views by means of ideal schematic views of the present disclosure. Therefore, the exemplary illustrations may be modified according to manufacturing techniques and / or tolerances.

[0068] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0069] The terms used in the present disclosure are only used to describe specific embodiments and are not intended to limit the present disclosure. The term "and / or" as used in the present disclosure includes any and all combinations of one or more related enumerated items. The singular forms "one" and "the" as used in the present disclosure are also intended to include plural forms, unless the context clearly indicates otherwise. The terms "including", "made of..." as used in the present disclosure specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0070] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined in this disclosure.

[0071] The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0072] In the embodiments of the present disclosure, "same-layer arrangement" of multiple structures means that multiple structures are formed by the same material layer, so they are in the same layer in terms of stacking relationship, but it does not mean that the distance between them and the substrate is equal, nor does it mean that they are completely the same as other layer structures between them and the substrate; thus, the positional relationship of different structures relative to the substrate also refers to the stacking relationship of the layers they are in, rather than the absolute position or distance relative to the substrate.

[0073] In the embodiments of the present disclosure, "patterning process" refers to the steps of forming a structure with a specific pattern, which may be a photolithography process, and the photolithography process includes one or more steps of forming a material layer, coating a photoresist, exposing, developing, etching, and photoresist stripping; of course, the patterning process may also be other processes such as an imprinting process and an inkjet printing process.

[0074] In some related technologies, a pixel circuit may be provided in a display substrate, and the pixel circuit includes a light emitting device for emitting light for display.

[0075] The display panel includes a display substrate, and in order to protect the display substrate, the display panel also includes a cover plate (CG) arranged on the display side of the display substrate, and the cover plate may be made of glass or the like; and in order to enhance heat dissipation, a metal heat dissipation layer (SCF) may also be provided (e.g. attached or bonded) on the back side of the display substrate.

[0076] The copper rod friction test is used to simulate the condition of the display panel being rubbed to test its performance. When the copper rod friction test is performed on the display panel of the above structure, it is found that it is easy to produce poor display (such as the four-split screen phenomenon).

[0077] The reasons for the above display defects may be: when the display panel is rubbed, the cover plate generates a negative voltage (such as -500V) due to static electricity accumulation, and the metal heat dissipation layer generates a positive voltage (such as 200V) due to static electricity accumulation, thereby generating an external electric field (Eexternal) in the display panel pointing from the metal heat dissipation layer to the cover plate; the direction of the external electric field is the same as or opposite to the direction of the original driving electric field (Einternal) used to turn on the transistor in the pixel circuit, thereby causing the transistor characteristics in the pixel circuit to drift, making it easier or more difficult to turn on than normal, affecting the display quality.

[0078] For example, when the pixel circuit is located on the display side of the display substrate and the transistor therein is a top-gate P-type transistor (such as a polysilicon transistor), its gate is located on the substrate side of the active region and is turned on when a low voltage is applied. Therefore, in the active region, the original driving electric field (Einternal) is directed from the substrate to the gate, that is, the driving electric field is in the same direction as the external electric field, which is equivalent to the driving electric field "enhancing" the original driving electric field, or the driving electric field "weakening" the electric field that turns off the transistor, resulting in a decrease in the threshold voltage (Vth) of the transistor, making it more likely to cause undesired conduction, affecting the display.

[0079] Further, yes Figure 4 In the pixel circuit shown, when the second transistor T2 and the fourth transistor T4 generate leakage current due to unexpected conduction, the first node N1 may be charged incorrectly, the voltage may be too high, and the brightness of the corresponding light emitting device OLED may be too low.

[0080] Moreover, the display substrate can be divided into four areas, and the conduction signals of the control signal terminals EM in the pixel circuits in different areas are provided separately, so that the pixel circuits in the four areas are affected by the leakage current for different times, and the brightness of the light-emitting device OLED is also low to different degrees, resulting in the reference Figure 1 The four-screen phenomenon.

[0081] It should be understood that if the external electric field is opposite to the original driving electric field, it is equivalent to the external electric field "weakening" the driving electric field, which will make the transistor unable to conduct as expected, and thus will also affect the display quality.

[0082] First, refer to Figures 2 to 11 , the present disclosure provides a display substrate, which includes:

[0083] a substrate 91 having opposing display and back sides;

[0084] A display structure provided on the display side of the substrate 91, the display structure comprising a positive voltage interface for providing a positive voltage and a plurality of pixel circuits, each pixel circuit comprising a plurality of transistors;

[0085] A shielding structure 1 is provided between the substrate 91 and the display structure, the shielding structure 1 is made of a conductive material and is electrically connected to the positive voltage interface; the orthographic projection of the active area 2 of at least part of the transistor on the substrate 91 coincides with the orthographic projection of the shielding structure 1 on the substrate 91;

[0086] An insulating isolation layer 93 is provided between the shielding structure 1 and the display structure.

[0087] The display substrate of the embodiment of the present disclosure includes a substrate 91 for carrying other structures. The substrate 91 can be made of materials such as glass and polymer, and includes a display side for emitting light for display, and a back side opposite to the display side.

[0088] Reference Figure 2 , Figure 3 The back side of the display substrate can be used to set (such as attaching or bonding) a metal heat dissipation layer 92 (SCF), and the display side thereof is provided with a display structure, the display structure includes a plurality of pixel circuits (pixel units), and each pixel circuit includes a light-emitting device OLED and a plurality of transistors for driving the light-emitting device OLED to emit light (of course, each transistor must have an active area 2).

[0089] The display substrate of the disclosed embodiment also has a shielding structure 1 (LS) made of a conductive material (such as a metal material) located between the substrate 91 and the active area 2. The shielding structure 1 is located at least at the position of the active area 2 of the corresponding part of the transistor, thereby shielding the electric field directed to the corresponding active area 2.

[0090] In order to prevent the shielding structure 1 from being electrically connected to the active area 2 , an insulating isolation layer 93 is provided between the two.

[0091] The display substrate also includes a positive voltage interface, which can be in the form of a pad (Pad), a connector (Pin), etc., which is used to connect to a driver chip (Driver IC), etc., so that a positive voltage (Vdd) can be obtained during the display process, that is, the power supply voltage loaded on the positive electrode of the light-emitting device OLED to make it emit light.

[0092] The shielding structure 1 is also electrically connected to the positive voltage interface (including direct connection or indirect connection), so when displayed, the shielding structure 1 also carries a positive voltage.

[0093] The display substrate may further include the above metal heat dissipation layer 92 , that is, the metal heat dissipation layer 92 may be directly disposed on (eg attached to, bonded to) the back side of the substrate 91 .

[0094] When the above display substrate is driven, the shielding structure 1 will naturally obtain a positive voltage, so the specific driving timing can be the same as when there is no shielding structure.

[0095] In the embodiment of the present disclosure, a shielding structure 1 is provided between the active area 2 of the transistor and the back side of the substrate 91 (i.e., the metal heat dissipation layer 92), so that the shielding structure 1 can shield the above external electric field (Eexternal) directed from the metal heat dissipation layer 92 to the cover plate 99; moreover, the shielding structure 1 is electrically connected to the positive voltage interface, so that it will stabilize as a positive voltage (Vdd) during display, and the positive voltage is a voltage that originally exists in many positions of the pixel circuit, so it itself will not affect the characteristics of the transistor. Therefore, the embodiment of the present disclosure eliminates the influence of the external electric field on the transistor by providing the shielding structure 1, avoids poor display (such as the four-split screen phenomenon), and improves the display quality.

[0096] In some embodiments, each pixel circuit comprises:

[0097] A storage capacitor Cst, a first electrode of which is connected to the positive voltage signal terminal VDD, and the positive voltage signal terminal VDD is electrically connected to the positive voltage interface;

[0098] A first transistor T1, whose gate 5 is connected to the reset signal terminal Reset, whose first electrode is connected to the second electrode of the storage capacitor Cst, and whose second electrode is connected to the initialization signal terminal Vinit;

[0099] A second transistor T2, whose gate 5 is connected to the gate signal terminal Gate, and whose first electrode is connected to the second electrode of the storage capacitor Cst;

[0100] A third transistor T3, whose gate 5 is connected to the second electrode of the storage capacitor Cst, and whose second electrode is connected to the second electrode of the second transistor T2;

[0101] A fourth transistor T4, whose gate 5 is connected to the gate signal terminal Gate, whose first electrode is connected to the first electrode of the third transistor T3, and whose second electrode is connected to the data signal terminal Data;

[0102] A fifth transistor T5, whose gate 5 is connected to the control signal terminal EM, a first electrode is connected to the positive voltage signal terminal VDD, and a second electrode is connected to the first electrode of the third transistor T3;

[0103] a sixth transistor T6, whose gate 5 is connected to the control signal terminal EM and whose first electrode is connected to the second electrode of the second transistor T2;

[0104] A seventh transistor T7, whose gate 5 is connected to the gate signal terminal Gate, whose first electrode is connected to the second electrode of the sixth transistor T6, and whose second electrode is connected to the initialization signal terminal Vinit;

[0105] The light emitting device OLED has a first electrode connected to the second electrode of the sixth transistor T6, and a second electrode connected to the negative voltage signal terminal VSS.

[0106] As one form of the embodiment of the present disclosure, the pixel circuit can refer to Figure 4, which is the above 7T1C structure. Among them, the light-emitting device OLED can be in the form of an organic light-emitting diode (OLED, Organic Light Emitting Diode) and the like, and its positive electrode (first electrode) is electrically connected to the above positive voltage interface through the positive voltage signal terminal VDD to obtain a positive electrode voltage (Vdd), and its negative electrode (second electrode) is connected to the negative voltage signal terminal VSS to obtain a negative electrode voltage (Vss).

[0107] The driving timing of the above pixel circuit can be divided into a reset phase, a write phase, and a light-emitting structure in each cycle (each frame). The voltage of some signal terminals in each phase can be referred to Figure 5 (wherein the high voltage is the on signal and the low voltage is the off signal), the positive voltage signal terminal VDD and the negative voltage signal terminal VSS can respectively continuously provide the positive voltage and the negative voltage, and the initialization signal terminal Vinit continuously provides the initialization voltage.

[0108] Among them, the specific structure and driving timing of the pixel circuit available in the embodiments of the present disclosure are various and are not limited to the above forms, so they will not be described in detail here.

[0109] In some embodiments, at least the orthographic projections of the active regions 2 of the second transistor T2 and the active regions 2 of the fourth transistor T4 on the substrate 91 coincide with the orthographic projections of the shielding structure 1 on the substrate 91 .

[0110] When the above pixel circuit of 7T1C structure is adopted, the third transistor T3 is a driving transistor, so the voltage of the gate 5 of the third transistor T3 is most likely to affect the display. At this time, the gate 5 of the third transistor T3 is connected to the first node N1, and the signal of the first node N1 is easily affected by the leakage current of the second transistor T2 and the fourth transistor T4. Therefore, the active area 2 of at least these two transistors needs to correspond to the above shielding structure 1.

[0111] In some embodiments, the orthographic projection of the active region 2 of each transistor on the substrate 91 coincides with the orthographic projection of the shielding structure 1 on the substrate 91 .

[0112] As one embodiment of the present disclosure, refer to Figure 2 , the active areas 2 of all transistors in all pixel circuits (such as all 7 transistors in the pixel circuit of the 7T1C structure above) correspond to the shielding structure 1, thereby achieving the best shielding effect.

[0113] It is also feasible if only some of the pixel circuits have transistors corresponding to the shielding structure 1 , or only some of the transistors in the pixel circuits correspond to the shielding structure 1 .

[0114] In some embodiments, the shielding structure 1 includes a plurality of connecting portions, a plurality of shielding portions 11;

[0115] Each shielding portion 11 corresponds to an active region 2 of a transistor, and the orthographic projection of the active region 2 of the transistor on the substrate 91 coincides with the orthographic projection of the corresponding shielding portion 11 on the substrate 91;

[0116] Each shielding portion 11 is electrically connected to the positive pressure interface via a connecting portion.

[0117] As one embodiment of the present disclosure, the shielding structure 1 may not be a complete layer, but may be referred to as Figure 6 The shielding structure 1 includes a plurality of shielding parts 11 corresponding to the active area 2 of the transistor (i.e., the part that actually plays a shielding role), and the shielding part 11 is discontinuous. Therefore, in order to make each shielding part 11 obtain the positive voltage (Vdd), it is necessary to set a plurality of connecting parts to realize the electrical connection between the shielding part 11 and the positive voltage interface (i.e., the shielding part 11 must be connected to the positive voltage interface at least through the connecting part). Therefore, the shielding structure 1 in the above form is not a complete layer, but has many "missing parts".

[0118] In some embodiments, the display structure further comprises:

[0119] A plurality of positive pressure signal lines 31 extending along a first direction, each positive pressure signal line 31 connecting a plurality of pixel circuits arranged in a row along the first direction and electrically connected to a positive pressure interface;

[0120] Each shielding portion 11 is electrically connected to the positive pressure signal line 31 via a connecting portion.

[0121] Each pixel circuit of the display substrate requires a positive voltage, but the positive voltage interface can obviously only be located at a certain position of the display substrate (such as at one end of the display substrate). Fig.11 , set along the first direction ( Fig.11 The positive voltage signal line 31 extends in the up and down directions (in the middle), and is connected to a plurality of pixel circuits arranged in a row (such as a column) along the first direction (such as a positive voltage signal terminal VDD connected to each pixel circuit), and is electrically connected to the positive voltage interface, so that the positive voltage can be introduced into each pixel circuit.

[0122] When the positive pressure signal line 31 is provided, the shielding portion 11 may be connected to the positive pressure signal line 31 via the connecting portion to achieve electrical connection with the positive pressure interface.

[0123] In some embodiments, as a mode of the embodiment of the present disclosure, the connection portion includes a plurality of first connection portions 121 and a plurality of second connection portions 122 extending along the first direction;

[0124] A plurality of shielding parts 11 corresponding to transistors in a plurality of pixel circuits arranged in a row in the first direction are respectively connected to the same second connecting part 122 through the first connecting parts 121;

[0125] At one end of the display substrate along the first direction, each second connection portion 122 is connected to a positive voltage signal line 31 through a via hole in the isolation layer 93 .

[0126] As one embodiment of the present disclosure, reference may be made to Figure 6 , the shielding structure 1 has multiple Figure 6 The shielding parts 11 corresponding to the transistors of the plurality of pixel circuits in the same column are connected to one second connecting part 122 through their respective first connecting parts 121. Figure 7 Each second connection portion 122 is connected to a positive voltage signal line 31 (such as the positive voltage signal line 31 corresponding to the same column of pixels) at one end (upper end or lower end) of the display substrate along the first direction through a via located in the isolation layer 93, so as to obtain the positive voltage through the positive voltage signal line 31 and introduce the positive voltage into the shielding portion 11.

[0127] The connection part required for the above structure is simple in form and easy to prepare.

[0128] In some embodiments, the connection portion further includes a third connection portion 123;

[0129] In at least some of the pixel circuits adjacent to each other in a direction perpendicular to the first direction, at least some of the shielding portions 11 corresponding to transistors located in different pixel circuits are connected to each other through the third connecting portion 123 .

[0130] According to the above structure, each second connection part 122 and its corresponding first connection part 121 and shielding part 11 actually obtain the positive voltage only from one end of the second connection part 122. In order to reduce the transmission resistance, Figure 6 , in a direction perpendicular to the first direction ( Figure 6 The shielding parts 11 corresponding to the adjacent pixel circuits in the left and right directions (in the middle) can also be connected through the third connecting part 123, so that a "lateral connection" is generated in the shielding structure 1, or even the shielding structure 1 forms a "grid-like" structure.

[0131] In some embodiments, as another embodiment of the present disclosure, the connection portion includes a fourth connection portion;

[0132] The shielding part 11 corresponding to the multiple transistors of each pixel circuit is connected to the fourth connection part, and the fourth connection part is connected to the positive voltage signal line 31 through the via hole in the isolation layer 93 in the pixel circuit.

[0133] As another embodiment of the present disclosure, each shielding part 11 corresponding to each transistor of each pixel circuit may be directly connected to the positive voltage signal line 31 at the position of the pixel circuit through a fourth connecting part. Specifically, each shielding part 11 may be directly connected to the positive voltage signal line 31 through a fourth connecting part, or each shielding part 11 corresponding to a pixel circuit may be first connected as a whole through a fifth connecting part, and the integrated structure is then connected to the positive voltage signal line 31.

[0134] The above method can ensure that each shielding part 11 can be connected to the positive pressure signal line 31 “closely” to reduce the transmission resistance.

[0135] It should be understood that it is also feasible if the shielding structure 1 is electrically connected to the positive pressure interface by other means.

[0136] For example, the shielding structure 1 may be connected to other structures with a positive voltage, such as the shielding structure 1 is connected to the first electrode of the storage capacitor Cst.

[0137] For another example, some structures with positive voltage in the pixel circuit (such as the positive voltage signal line 31) may extend to the shielding part 11 and be directly connected to the shielding part 11 through the vias in the isolation layer 93 (it can also be understood that the connecting part is not part of the shielding structure, but belongs to the display structure or the pixel circuit).

[0138] In some embodiments, the display structure further comprises:

[0139] A gate insulating layer 94 disposed on the side of the active region 2 of each transistor facing away from the substrate 91;

[0140] A first gate layer is provided on the side of the gate insulating layer 94 facing away from the substrate 91 , and the gate 5 of the transistor is located in the first gate layer.

[0141] The gate 5 of each transistor of the pixel circuit may be located on the side of the active region 2 away from the substrate 91 , that is, it may be a top-gate transistor.

[0142] In some embodiments, the transistor is a P-type transistor.

[0143] The above transistors may be P-type transistors, that is, their active regions 2 are made of P-type semiconductors, such as polysilicon (p-Si).

[0144] When the transistor is of top gate type and P type, the direction of its driving electric field (Einternal) is the same as the direction of the external electric field (Eexternal) pointing from the metal heat dissipation layer 92 to the cover plate 99, so it is more likely to produce poor display and is more suitable for the embodiment of the present disclosure.

[0145] It should be understood that the shielding structure 1 of the embodiment of the present disclosure can also be used for other types of transistors such as bottom-gate transistors and N-type transistors.

[0146] In some embodiments, the display structure further comprises:

[0147] A first interlayer insulating layer located on a side of the first gate layer facing away from the substrate 91;

[0148] A second gate layer located on a side of the first insulating layer facing away from the substrate 91;

[0149] A second interlayer insulating layer located on a side of the second gate layer facing away from the substrate 91;

[0150] A source-drain layer located on a side of the second interlayer insulating layer away from the substrate 91;

[0151] A planarization layer located on a side of the source and drain layer facing away from the substrate 91;

[0152] The light emitting device OLED is located on the side of the planarization layer facing away from the substrate 91 .

[0153] The display substrate may further include the above various layer structures.

[0154] Exemplarily, a partial structure of a display substrate is introduced below.

[0155] For example, on the display side of the substrate 91, the following layer structures may be sequentially arranged in a direction gradually away from the substrate 91:

[0156] (1) Shielding structure 1 (LS).

[0157] The shielding structure 1 is made of conductive materials such as metal.

[0158] Reference Figure 6 The shielding structure 1 may include the above connecting parts (such as the first connecting part 121 , the second connecting part 122 , and the third connecting part 123 ) and the shielding part 11 .

[0159] (2) Isolation layer 93.

[0160] The isolation layer 93 is made of an insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

[0161] The isolation layer 93 may be formed with vias for electrically connecting the shielding structure 1 to the positive pressure interface (eg, connected to the positive pressure signal line 31 ).

[0162] (3) Semiconductor layer (POLY).

[0163] The semiconductor layer is composed of semiconductor materials such as polycrystalline silicon.

[0164] Reference Figure 8 The active region 2 of each transistor is arranged in the semiconductor layer, and part of the semiconductor material in the semiconductor layer can be conductive, thereby constituting part of the electrode, connecting wire, etc. of the transistor.

[0165] (4) Gate insulating layer 94 (GI).

[0166] The gate insulating layer 94 is made of an insulating material such as silicon nitride, silicon oxide, or silicon nitride oxide.

[0167] The gate insulating layer 94 is used to separate the active area 2 and the gate 5 of the transistor, and may also be formed with a via hole for electrically connecting the shielding structure 1 to a positive voltage interface (eg, connected to a positive voltage signal line 31 ).

[0168] (5) First gate layer (GATE1).

[0169] The first gate layer is made of conductive materials such as metal.

[0170] Reference Fig. 9 The gate 5 of each transistor is arranged in the first gate layer, and each signal terminal connected to the gate 5 (such as the gate signal terminal Gate, the control signal terminal EM, the reset signal terminal Reset) and the corresponding signal lines (such as the gate signal line, the control signal line, the reset signal line) can also be located in the first gate layer.

[0171] Each signal end may be a structure extending from a corresponding signal line, or may be a part of the corresponding signal line.

[0172] In addition, the second electrode of the storage capacitor Cst is connected to the gate 5 of the third transistor T3, so it can also be located in the first gate layer (that is, the second electrode of the storage capacitor Cst and the gate 5 of the third transistor T3 can be an integrated structure).

[0173] (6) First interlayer insulating layer (ILD1).

[0174] The first interlayer insulating layer is made of insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

[0175] The first interlayer insulating layer may also be provided with vias for electrically connecting the shielding structure 1 to the positive voltage interface (eg, connected to the positive voltage signal line 31 ).

[0176] (7) Second gate layer (GATE2).

[0177] The second gate layer is made of conductive materials such as metal.

[0178] Reference Fig.10 , some signal terminals (such as the initialization signal terminal Vinit) and corresponding signal lines (such as the initialization signal line), the first electrode of the storage capacitor Cst, etc. can be arranged in the second gate layer.

[0179] (8) Second interlayer insulating layer (ILD2).

[0180] The second interlayer insulating layer is made of insulating materials such as silicon nitride, silicon oxide, and silicon nitride oxide.

[0181] The second interlayer insulating layer may also be provided with vias for electrically connecting the shielding structure 1 to the positive voltage interface (eg, connected to the positive voltage signal line 31 ).

[0182] (9) Source and drain layer (SD1).

[0183] The source and drain layers are made of conductive materials such as metal.

[0184] Reference Fig.11 The positive voltage signal line 31 and the positive voltage signal terminal VDD may be arranged in the source-drain layer, and part of the signal terminals (such as the data signal terminal Data) and the corresponding signal lines (such as the data signal line 39) may also be located in the source-drain layer.

[0185] In addition, some connection lines connecting different structures may be provided in the source / drain layer.

[0186] (10) Planarization layer (PLN).

[0187] The planarization layer is made of an organic insulating material.

[0188] The planarization layer is used to eliminate the step difference of the structure below, and may have a via hole for connecting the first electrode of the light-emitting device OLED with a transistor (such as the second electrode of the sixth transistor T6 ).

[0189] (11) The first electrode of the light-emitting device OLED.

[0190] Specifically, the first electrode of the light-emitting device OLED can be the anode of the organic light-emitting diode, which can be composed of metal oxide conductive materials such as indium tin oxide (ITO) and connected to the transistor (such as the second electrode of the sixth transistor T6) through a via in the planarization layer.

[0191] (12) Pixel definition layer (PDL).

[0192] The pixel defining layer is made of an organic insulating material.

[0193] The pixel defining layer is used to define the range of the light emitting device OLED through an opening therein.

[0194] (13) The light-emitting layer of the light-emitting device OLED.

[0195] The light-emitting layer is the layer actually used for emitting light in the light-emitting device OLED, which can be the light-emitting layer of an organic light-emitting diode. The light-emitting layer of an organic light-emitting diode is composed of organic materials, which at least includes an organic light-emitting layer (EML), and may also include other stacked auxiliary layers such as an electron injection layer (EIL), an electron transport layer (ETL), a hole injection layer (HIL), and a hole transport layer (HTL).

[0196] The light-emitting layer of the organic light-emitting diode may be a whole-layer structure, which contacts the positive electrode of the organic light-emitting diode at the opening of the pixel defining layer, thereby forming an organic light-emitting diode.

[0197] (14) A second electrode of the light-emitting device OLED.

[0198] Specifically, the second electrode of the light emitting device OLED may be the cathode of the organic light emitting diode, which may be made of a metallic conductive material such as aluminum.

[0199] The cathode of the organic light emitting diode may be a whole-layer structure, so that it is also a negative voltage signal terminal VSS.

[0200] (15) Encapsulation layer.

[0201] The encapsulation layer may be a stacked structure of alternating organic layers and inorganic layers, and is used to encapsulate other structures therein to prevent other structures (especially the light-emitting layer) from coming into contact with water and oxygen in the environment and aging.

[0202] Among them, the complete film layers in the above-mentioned structures can be formed by solution process, deposition process, etc.; and if the above-mentioned structures have specific shapes, they can be formed by patterning process.

[0203] It should be understood that the specific layer structure of the display substrate described above is only illustrative and may be subject to many changes.

[0204] Second, refer to Figure 3 , an embodiment of the present disclosure provides a display panel, comprising:

[0205] Any of the above display substrates;

[0206] A cover plate 99, which is located outside the display side of the substrate 91 of the display substrate;

[0207] The metal heat dissipation layer 92 is located on the back side of the substrate 91 of the display substrate.

[0208] The above display substrate can be combined with the cover plate 99 (CG) and the metal heat dissipation layer 92 (SCF) to form a display panel with display function.

[0209] Among them, refer to Figure 3The cover plate 99 is located on the display side of the display substrate, and can be connected to the display substrate by means of frame sealing glue or the like; and the metal heat dissipation layer 92 is located on the back side of the display substrate, and can be connected to the display substrate by means of attachment (bonding) or the like.

[0210] Therefore, the external electric field (Eexternal) generated by friction etc. in the display panel is directed from the metal heat dissipation layer 92 to the cover plate 99, and the shielding structure 1 is located between the metal heat dissipation layer 92 and the active area 2 of the transistor, thereby effectively shielding the influence of the external electric field on the active area 2, improving the display quality of the display panel, and avoiding disadvantages such as the four-split screen phenomenon.

[0211] The display panel may also include a driving chip, a circuit board, a power supply, a housing, a bracket and other structures, which will not be described in detail here.

[0212] Specifically, the display panel may be an organic light emitting diode (OLED) display panel, electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, or any other product or component with a display function.

[0213] In a third aspect, an embodiment of the present disclosure provides a method for preparing a display substrate, wherein the display substrate is any one of the above-mentioned substrates, and the preparation method comprises:

[0214] A shielding structure, an isolation layer and a display structure are sequentially formed on the display side of the substrate.

[0215] Obviously, on the same side of the substrate, the structures farther away from the substrate need to be formed "later", so when preparing the above display substrate, it is necessary to form the above shielding structure, isolation layer, display structure, etc. in sequence on the display side of the substrate.

[0216] Among them, the shielding structure, isolation layer, and display structure can all be formed by a composition process, etc., and the display structure can include the above multiple layer structures, each of which can also be formed in turn by different composition processes, etc., which will not be described in detail here.

[0217] If necessary, the above metal heat dissipation layer can also be formed on the back side of the substrate by means of attachment (bonding) or the like, which will not be described in detail here.

[0218] The present disclosure has disclosed example embodiments, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A display substrate, comprising: a substrate having opposing display and back sides; A display structure disposed on the display side of the substrate, the display structure comprising a positive voltage interface for providing a positive voltage and a plurality of pixel circuits, each pixel circuit comprising a plurality of transistors; A shielding structure is provided between the substrate and the display structure, the shielding structure is made of a conductive material and is electrically connected to the positive voltage interface; the orthographic projection of at least part of the active area of ​​the transistor on the substrate coincides with the orthographic projection of the shielding structure on the substrate; An insulating isolation layer is provided between the shielding structure and the display structure.

2. The display substrate according to claim 1, wherein: The orthographic projection of the active region of each transistor on the substrate coincides with the orthographic projection of the shielding structure on the substrate.

3. The display substrate according to claim 1, wherein: The shielding structure comprises a plurality of connecting parts and a plurality of shielding parts; Each of the shielding parts corresponds to an active area of ​​a transistor, and the orthographic projection of the active area of ​​the transistor on the substrate coincides with the orthographic projection of the corresponding shielding part on the substrate; Each of the shielding parts is electrically connected to the positive pressure interface through a connecting part.

4. The display substrate according to claim 3, wherein: The display structure also includes: A plurality of positive pressure signal lines extending along a first direction, each of the positive pressure signal lines connecting a plurality of pixel circuits arranged in a row along the first direction and electrically connected to the positive pressure interface; Each of the shielding parts is electrically connected to the positive pressure signal line through a connecting part.

5. The display substrate according to claim 4, wherein: The connecting portion includes a plurality of first connecting portions and a plurality of second connecting portions extending along a first direction; A plurality of shielding parts corresponding to transistors in a plurality of pixel circuits arranged in a row in the first direction are respectively connected to the same second connecting part through the first connecting parts; At one end of the display substrate along the first direction, each of the second connecting portions is connected to a positive voltage signal line through a via hole in the isolation layer.

6. The display substrate according to claim 5, wherein: The connecting portion further includes a third connecting portion; In at least some of the pixel circuits adjacent to each other in a direction perpendicular to the first direction, at least some of the shielding parts corresponding to transistors located in different pixel circuits are connected to each other through a third connecting part.

7. The display substrate according to claim 4, wherein: The connecting portion includes a fourth connecting portion; The shielding parts corresponding to the multiple transistors of each pixel circuit are connected to the fourth connecting part, and the fourth connecting part is connected to the positive voltage signal line through a via hole in the isolation layer in the pixel circuit.

8. The display substrate according to claim 1, wherein: The display structure also includes: A gate insulating layer disposed on a side of the active region of each transistor facing away from the substrate; A first gate layer is arranged on a side of the gate insulating layer facing away from the substrate, and the gate of the transistor is located in the first gate layer.

9. The display substrate according to claim 8, wherein: The transistor is a P-type transistor.

10. The display substrate according to claim 8, wherein: The display structure also includes: A first interlayer insulating layer located on a side of the first gate layer facing away from the substrate; A second gate layer located on a side of the first insulating layer facing away from the substrate; a second interlayer insulating layer located on a side of the second gate layer facing away from the substrate; a source-drain layer located on a side of the second interlayer insulating layer facing away from the substrate; A planarization layer located on a side of the source / drain layer facing away from the substrate; A light emitting device is located on a side of the planarization layer away from the substrate.

11. The display substrate according to claim 1, wherein: Each of the pixel circuits comprises: A storage capacitor, a first electrode of which is connected to a positive voltage signal terminal, and the positive voltage signal terminal is electrically connected to a positive voltage interface; A first transistor, a gate of which is connected to the reset signal terminal, a first electrode of which is connected to the second electrode of the storage capacitor, and a second electrode of which is connected to the initialization signal terminal; a second transistor, a gate of which is connected to the gate signal terminal, and a first electrode of which is connected to the second electrode of the storage capacitor; a third transistor, a gate of which is connected to the second electrode of the storage capacitor, and a second electrode of which is connected to the second electrode of the second transistor; a fourth transistor, a gate of which is connected to the gate signal terminal, a first electrode of which is connected to the first electrode of the third transistor, and a second electrode of which is connected to the data signal terminal; a fifth transistor, whose gate is connected to the control signal terminal, whose first electrode is connected to the positive voltage signal terminal, and whose second electrode is connected to the first electrode of the third transistor; a sixth transistor, a gate of which is connected to the control signal terminal, and a first electrode of which is connected to the second electrode of the second transistor; a seventh transistor, a gate of which is connected to the gate signal terminal, a first electrode of which is connected to the second electrode of the sixth transistor, and a second electrode of which is connected to the initialization signal terminal; The light emitting device has a first electrode connected to the second electrode of the sixth transistor and a second electrode connected to the negative voltage signal terminal.

12. The display substrate according to claim 11, wherein: At least the orthographic projections of the active regions of the second transistor and the fourth transistor on the substrate coincide with the orthographic projections of the shielding structure on the substrate.

13. A display panel comprising: The display substrate according to any one of claims 1 to 12; a cover plate, which is located on the display side of the substrate of the display substrate; The metal heat dissipation layer is located on the back side of the substrate of the display substrate.

14. A method for preparing a display substrate, wherein: The display substrate is the display substrate according to any one of claims 1 to 12, and the preparation method comprises: A shielding structure, an isolation layer and a display structure are sequentially formed on the display side of the substrate.

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