A current detection circuit with leading edge blanking

Abstract

The present invention discloses a current detection circuit with leading edge blanking, including a sampling circuit, a rectifier circuit, an adjustable leading edge blanking circuit, a filter circuit and a control circuit; the sampling circuit includes a sampling circuit A and a sampling circuit B; the two input ends of the rectifier circuit are respectively connected to the acquisition circuit A and the acquisition circuit B, and the output end of the rectifier circuit is respectively connected to the two input ends of the adjustable leading edge blanking circuit and the input end of the filter circuit; the output end of the filter circuit is connected to the input end of the control circuit. The present invention is no longer limited by whether the IC has a current leading edge blanking function, improves the CS filter bandwidth, and can sample a real current signal. In addition, the circuit of the present invention uses conventional discrete devices, does not require special design, and has a simple circuit and is easy to realize localization.

Description

Technical Field

[0001] The invention relates to the field of circuit leading edge blanking, and in particular to a current detection circuit with leading edge blanking. Background Art

[0002] Most topology circuits of switching power supplies often fail to work properly or even fail and crash due to unreasonable current detection. Due to the parasitic parameters of power devices and PCB trace interference, whether it is resistor sampling or current transformer sampling, a spike current will be generated when the MOS tube is turned on. If this spike is not processed, it will participate in PWM regulation in current mode control, causing the circuit to not operate normally, and it may also trigger overcurrent protection and cause abnormal failure under voltage mode control.

[0003] The patent with application number CN201821219163.9 discloses a MOS tube driving circuit for suppressing driving voltage spikes, including a push-pull circuit, an RCD absorption circuit, a gate resistor and a MOS tube; the RCD absorption circuit is composed of an absorption resistor R, an absorption capacitor C and a TVS tube; the cathode of the TVS tube is connected to the gate of the MOS tube; the anode of the TVS tube is connected to one end of the absorption capacitor; the other end of the absorption capacitor is connected to the source of the MOS tube; the absorption resistor is connected in parallel with the TVS tube. Although this circuit can suppress the gate-source forward driving spike voltage of the MOS tube, its application range is relatively limited and cannot meet the diversified design of today's switching power supplies.

[0004] Although some PWM ICs on the market have built-in leading edge blanking circuits, the leading edge blanking circuit has a relatively fixed time and a limited application range, and cannot meet the diverse designs of today's switching power supplies. Especially in high-power power supply applications, the control of the leading edge blanking time is more variable due to the emergence of new power devices. Summary of the invention

[0005] The object of the present invention is to overcome the deficiencies of the prior art and provide a current detection circuit with leading edge blanking.

[0006] The objective of the present invention is achieved through the following technical solutions:

[0007] A current detection circuit with leading edge blanking comprises a sampling circuit, a rectifier circuit, an adjustable leading edge blanking circuit, a filter circuit and a control circuit; the sampling circuit comprises a sampling circuit A and a sampling circuit B; two input ends of the rectifier circuit are respectively connected to the acquisition circuit A and the acquisition circuit B, and an output end of the rectifier circuit is respectively connected to two input ends of the adjustable leading edge blanking circuit and an input end of the filter circuit; and an output end of the filter circuit is connected to an input end of the control circuit.

[0008] The sampling circuit comprises a current transformer CT1 and a current transformer CT2. The input ends of the two current transformers are respectively arranged on the main circuit, and the output ends are arranged on the rectifier circuit.

[0009] The rectifier circuit includes two rectifier loops; a first rectifier loop is formed by a diode D1, a resistor R2, an NMOS tube Q2 and an output end of a current transformer CT1 connected in sequence; a second rectifier loop is formed by a diode D1, a resistor R2, an NMOS tube Q4 and an output end of a current transformer CT2 connected in sequence.

[0010] The adjustable leading edge blanking circuit includes capacitor C3, capacitor C4, NMOS tube Q1, NMOS tube Q3, diode D2, diode D3, resistor R5 and resistor R6; the source electrodes of NMOS tube Q1 and NMOS tube Q3 are grounded, and the gate electrodes are respectively connected to the output end of the current transformer of the rectifier circuit; capacitor C3 and resistor R5 are connected to form an adjustable leading edge control circuit A, and diode D2 is connected in parallel to resistor R5; capacitor C4 and resistor R6 are connected to form an adjustable leading edge control circuit B, and diode D3 is connected in parallel to resistor R6; the collector of NMOS tube Q1 is connected to PWM3 through adjustable leading edge control circuit A, and the collector of NMOS tube Q3 is connected to PWM4 through adjustable leading edge control circuit B.

[0011] The filter circuit is a filter voltage stabilization loop composed of capacitors C1, C2 and resistor R1.

[0012] The gate of the NMOS tube Q2 is connected to PWM1, and the gate of the NMOS tube Q4 is connected to PWM2. PWM1 and PWM2 are driven by the driving signal of the primary power MOS tube.

[0013] Beneficial effects of the present invention:

[0014] 1. The selection of PWM IC is more flexible and is no longer limited by whether the IC has the current leading edge blanking function;

[0015] 2. The current detection circuit can improve the CS filter bandwidth and sample the real current signal, which plays a vital role in the current control circuit;

[0016] 3. The current detection circuit uses conventional discrete devices, does not require special design, has a simple circuit, and is easy to achieve domestic production. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a circuit functional block diagram of the present invention;

[0018] Figure 2 It is a circuit schematic diagram of the present invention;

[0019] Figure 3 It is a timing diagram of the present invention. DETAILED DESCRIPTION

[0020] In order to have a clearer understanding of the technical features, purposes and effects of the present invention, specific embodiments of the present invention are now described with reference to the accompanying drawings.

[0021] In this embodiment, Figure 1 As shown, a current detection circuit with leading edge blanking includes a sampling circuit, a rectifier circuit, an adjustable leading edge blanking circuit, a filter circuit and a control circuit; the sampling circuit includes a sampling circuit A and a sampling circuit B; the two input ends of the rectifier circuit are respectively connected to the acquisition circuit A and the acquisition circuit B, and the output end of the rectifier circuit is respectively connected to the two input ends of the adjustable leading edge blanking circuit and the input end of the filter circuit; the output end of the filter circuit is connected to the input end of the control circuit.

[0022] The sampling circuit includes a current transformer CT1 and a current transformer CT2. The input ends of the two current transformers are respectively arranged on the main circuit, and the output ends are arranged on the rectifier circuit. The main function is to convert the larger current signal in the main circuit into a smaller voltage signal.

[0023] The rectifier circuit includes two rectifier loops; a first rectifier loop is composed of a diode D1, a resistor R2, an NMOS tube Q2 and an output end of a current transformer CT1 connected in sequence; a second rectifier loop is composed of a diode D1, a resistor R2, an NMOS tube Q4 and an output end of a current transformer CT2 connected in sequence; the main function is to rectify the alternating voltage signal sampled by the transformer into the required unidirectional voltage signal.

[0024] The adjustable leading edge blanking circuit includes capacitor C3, capacitor C4, NMOS tube Q1, NMOS tube Q3, diode D2, diode D3, resistor R5 and resistor R6; the source electrodes of NMOS tube Q1 and NMOS tube Q3 are grounded, and the gate electrodes are respectively connected to the output end of the current transformer of the rectifier circuit; capacitor C3 and resistor R5 are connected to form an adjustable leading edge control circuit A, and diode D2 is connected in parallel to resistor R5; capacitor C4 and resistor R6 are connected to form an adjustable leading edge control circuit B, and diode D3 is connected in parallel to resistor R6; the collector of NMOS tube Q1 is connected to PWM3 through adjustable leading edge control circuit A, and the collector of NMOS tube Q3 is connected to PWM4 through adjustable leading edge control circuit B.

[0025] The filter circuit is a filter voltage stabilization loop composed of capacitors C1, C2 and resistor R1; it filters out high-frequency noise in the voltage signal and sends a very high-quality voltage signal to the control circuit. The control part obtains very real current information and adjusts PWM more accurately or implements fault protection.

[0026] The gate of the NMOS tube Q2 is connected to PWM1, and the gate of the NMOS tube Q4 is connected to PWM2. PWM1 and PWM2 are driven by the driving signal of the primary power MOS tube.

[0027] When the power circuit current works in the AB direction through the current transformer CT1, PWM1 has turned on Q2 before. At this time, PWM3 can turn on Q1 through C3 and R5, and the current signal is short-circuited by Q1 and Q2 that are turned on at the same time to eliminate the current leading edge spike. The conduction time of Q1 can be adjusted by adjusting the values ​​of C3 and R5, that is, the leading edge blanking time t1 in the timing diagram. After that, the current signal works normally through loop 1. The current signal sampled from CT1 is then filtered by C1, R1, and C2 to obtain a relatively smooth and accurate current signal to the control IC.

[0028] When the power circuit current works in the CD direction through the current transformer CT2, PWM2 has turned on Q4 before. At this time, PWM4 can turn on Q3 through C4 and R6, and the current signal is short-circuited by Q3 and Q4 that are turned on at the same time, so as to eliminate the current front edge spike. The on time of Q3 can be adjusted by adjusting the values ​​of C4 and R6, that is, the t2 front edge blanking time in the timing diagram. After that, the current signal works normally through loop 2. The current signal sampled from CT2 is then filtered by C1, R1, and C2 to obtain a relatively smooth and accurate current signal to the control IC.

[0029] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention to be protected. The scope of the present invention to be protected is defined by the attached claims and their equivalents.

Claims

1. A current detection circuit with leading edge blanking, characterized in that: It includes a sampling circuit, a rectifying circuit, an adjustable leading edge blanking circuit, a filtering circuit and a control circuit; The sampling circuit includes a sampling circuit A and a sampling circuit B; The two input ends of the rectifier circuit are respectively connected to the acquisition circuit A and the acquisition circuit B, and the output end of the rectifier circuit is respectively connected to the two input ends of the adjustable leading edge blanking circuit and the input end of the filter circuit; The output end of the filter circuit is connected to the input end of the control circuit; The rectifier circuit includes two rectifier loops; A first rectifier circuit is formed by a diode D1, a resistor R2, an NMOS transistor Q2 and an output end of a current transformer CT1 connected in sequence; a second rectifier circuit is formed by a diode D1, a resistor R2, an NMOS transistor Q4 and an output end of a current transformer CT2 connected in sequence; The adjustable leading edge blanking circuit includes a capacitor C3, a capacitor C4, an NMOS transistor Q1, an NMOS transistor Q3, a diode D2, a diode D3, a resistor R5 and a resistor R6; The sources of the NMOS tubes Q1 and Q3 are grounded, and the gates are respectively connected to the output terminals of the current transformers of the rectifier circuits; The capacitor C3 and the resistor R5 are connected to form an adjustable leading edge control circuit A, and the diode D2 is connected in parallel to the resistor R5; the capacitor C4 and the resistor R6 are connected to form an adjustable leading edge control circuit B, and the diode D3 is connected in parallel to the resistor R6; The collector of the NMOS tube Q1 is connected to PWM3 through an adjustable leading edge control circuit A, and the collector of the NMOS tube Q3 is connected to PWM4 through an adjustable leading edge control circuit B; the PWM3 and PWM4 are driven by the secondary side synchronous rectification signal.

2. A current detection circuit with leading edge blanking according to claim 1, characterized in that: The sampling circuit comprises a current transformer CT1 and a current transformer CT2. The input ends of the two current transformers are respectively arranged on the main circuit, and the output ends are arranged on the rectifier circuit.

3. A current detection circuit with leading edge blanking according to claim 1, characterized in that: The filter circuit is a filter voltage stabilizing circuit formed by connecting capacitors C1, C2 and a resistor R1.

4. A current detection circuit with leading edge blanking according to claim 1, characterized in that: The gate of the NMOS tube Q2 is connected to PWM1, and the gate of the NMOS tube Q4 is connected to PWM2. PWM1 and PWM2 are driven by the driving signal of the primary power MOS tube.

Images