A fully digital controlled oscillator
By adopting a matrix structure of multiple inverters and switching devices in the fully digital controlled oscillator, the problems of phase jitter and synchronization error of fast lock full digital phase lock loop output are solved, and lower phase jitter and synchronization error are achieved. Improves the accuracy and stability of frequency adjustment.
Patent Information
- Application Number
- CN202110122749.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-01-29
- Publication Date
- 2024-12-17
- Estimated Expiration
- 2041-01-29
AI Technical Summary
The existing fast lock full digital phase-locking loop output has high phase jitter and synchronization errors, making it difficult to effectively trade off between the tuning range and the time jitter performance of CNC oscillators.
Design a fully digital controlled oscillator, adopting at least one stage of ring oscillator, each stage of ring oscillator is equipped with multiple inverters, and there are multiple sets of switching devices in parallel, including switches for fine-tuning and coarse adjustment, through full digital The control terminal adjusts the oscillation frequency output by the inverter to form a matrix structure to slow down phase jitter.
By connecting multiple MOS switches in parallel and series in the ring oscillator, phase jitter is effectively reduced, output synchronization error is reduced, and frequency adjustment accuracy and stability of the oscillator are improved.
Smart Images
Figure CN112953524B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of controlled oscillators, and in particular to a fully digital controlled oscillator. Background Art
[0002] With the increasingly widespread application of digital signal processing, digital phase-locked loops (DPLLs) are becoming more and more common in modern integrated circuit design, especially in high-performance digital circuit applications such as digital signal processors (DSPs) and microprocessors. Digital phase-locked loops are an indispensable circuit. Compared with traditional analog phase-locked loops (Analog Phase-Locked Loops), digital phase-locked loops use fewer nonlinear devices such as high-resistance resistors, capacitors, and inductors, and can be designed and manufactured using manufacturing processes compatible with high-speed digital logic circuits, making them easier to use in digital systems.
[0003] The digital-controlled oscillator (DCO) is the most critical and core part. The digital-controlled oscillator (DCO) outputs an oscillation waveform with a variable frequency, which determines the noise performance and power consumption of the entire phase-locked loop. The digital time converter (Time-to-Digital Converter) outputs the phase difference between the reference clock and the output clock fed back. A digital loop filter (Digital Loop Filter) replaces the analog loop filter to control the DCO. The phase difference with the reference clock controls the high or low oscillation frequency of the DCO output. The output oscillation signal is sent to the digital time converter by negative feedback to reduce the phase difference, and finally the output signal frequency is consistent with the reference clock frequency, that is, phase lock is achieved. Therefore, the entire DCO no longer needs to contain capacitors or inductors, and it also reduces the problems of leakage current and power supply noise.
[0004] Due to the steep high-frequency oscillation rate transfer curve of the digital controlled oscillator and the discreteness of the digital controlled oscillator, the output of the existing fast-locked fully digital phase-locked loop often has long-term phase jitter, which increases the synchronization error. Therefore, when designing a digital controlled oscillator, a trade-off must be made between the tuning range of the digital controlled oscillator and the time jitter performance. Summary of the invention
[0005] The technical problem to be solved by the present invention is that, in view of the technical defects of high phase jitter and high synchronization error in the output of a fast-locked fully digital phase-locked loop, a fully digital controlled oscillator is provided, including at least one stage of a ring oscillator, each stage of the ring oscillator is provided with a plurality of inverters, the output end of each of the inverters is connected in parallel with a plurality of groups of switch devices, and each group of the switch devices has at least 3 switches connected in series.
[0006] Furthermore, in each of the plurality of switch devices connected in parallel at the output end of the inverter, there are a plurality of first switch devices for fine-tuning the oscillation frequency output by the inverter and a plurality of second switch devices for coarse-tuning the oscillation frequency output by the inverter; in each group of the switch devices, at least two of the switches are connected to a full digital control end, and the oscillation frequency output by the inverter is fine-tuned or coarse-tuned through the full digital control end; and each of the switches connected to the full digital control end corresponds to a frequency adjustment gear, and each coarse adjustment gear is equal to 8 fine adjustment gears.
[0007] Furthermore, the switches are all P-MOS switches or N-MOS switches.
[0008] Furthermore, in each group of the first switch devices, the switches are arranged in sequence, the drain of the switch arranged at the first position is connected to the output end of the inverter, and its source is connected to the drain of the adjacent switch; the drain and source of the switch arranged at the end are both connected to the output end of the corresponding next-stage inverter or to the output end of the fully digitally controlled oscillator, and its gate is connected to the source of the adjacent switch; the drains of the remaining switches are all connected to the sources of the adjacent switches.
[0009] Furthermore, in each group of the second switch devices, the switches are arranged in sequence, the drain of the switch arranged at the first position is connected to the output end of the inverter, and its source is connected to the drain of the adjacent switch; the gate and source of the switch arranged at the end are both connected to the output end of the corresponding next-stage inverter or to the output end of the fully digitally controlled oscillator, and its drain is connected to the source of the adjacent switch; the drains of the remaining switches are all connected to the sources of the adjacent switches.
[0010] Furthermore, in the switch, unconnected gates are connected to the full digital control terminal through a digital control port in a predetermined order, and the full digital control terminal controls the opening or closing of the switch.
[0011] Furthermore, the predetermined order is: in each stage of the ring oscillator, multiple groups of the switch devices form a matrix structure, and each of the digital control ports is connected to the gate of each of the switches in sequence from the first column to the last column of the matrix and from top to bottom.
[0012] Furthermore, the predetermined order is: in each stage of the ring oscillator, multiple groups of the switch devices form a matrix structure, and each of the digital control ports is connected to the gate of each of the switches in sequence from the first row to the last row of the matrix and from left to right.
[0013] Furthermore, the total number of digital control ports is taken from any one of the following geometric progressions:
[0014] a n =a1q n-1 ;
[0015] Wherein, a1=32, q=2, and n is a natural number greater than or equal to 1.
[0016] Furthermore, in each stage of the ring oscillator, the number of the inverters is an odd number not less than 3.
[0017] Furthermore, in each stage of the ring oscillator, the output end of each inverter is connected to the input end of the adjacent inverter. The input end of the inverter arranged at the first position of each stage is respectively connected to an input signal; the output end of the inverter arranged at the end of each stage is connected to the output end of the fully digitally controlled oscillator; the inverter arranged at the first position of each stage is connected to the inverter arranged at the end to form a ring negative feedback loop.
[0018] Implementing one of the above technical solutions of the present invention has the following advantages or beneficial effects:
[0019] The purely digitally controlled oscillator of the present invention connects a plurality of MOS switches in parallel and in series in a ring oscillator. The MOS switches are controlled by digital characters, and the inverter drives different loads to fine-tune the output oscillation frequency of the fully digitally controlled oscillator. The fully digitally controlled oscillator can reduce phase jitter and effectively reduce output synchronization error. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. It is obvious that the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:
[0021] Figure 1 is a circuit diagram of a fully digitally controlled oscillator according to an embodiment of the present invention;
[0022] Figure 2 This is a circuit diagram of a 1*3-order fully digital controlled oscillator with control lines arranged in rows according to an embodiment of the present invention;
[0023] Figure 3 It is a circuit diagram of another 1*3-order fully digital controlled oscillator with control lines arranged in column direction according to an embodiment of the present invention. DETAILED DESCRIPTION
[0024] In order to make the purpose, technical solutions and advantages of the present invention clearer, the various exemplary embodiments to be described below will refer to the corresponding drawings, which constitute a part of the exemplary embodiments, wherein various exemplary embodiments that may be used to implement the present invention are described. Unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation methods described in the following exemplary embodiments do not represent all implementation methods consistent with the present disclosure. It should be understood that they are only examples of devices and methods consistent with some aspects of the present disclosure as detailed in the attached claims, and other embodiments may be used, or the embodiments listed herein may be modified in circuits and functions without departing from the scope and essence of the present invention. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details that hinder the description of the present invention.
[0025] In the description of the present invention, it should be understood that in the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly specified and specifically defined. It should be noted that, unless otherwise clearly specified and defined, the terms "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication connection; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. The terms "first", "second", "third"... etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the defined "first", "second", "third"... features may explicitly or implicitly include one or more of the said features.
[0026] In order to illustrate the technical solution of the present invention, a specific embodiment is provided below for illustration.
[0027] like Figure 1As shown, a fully digital controlled oscillator includes at least one ring oscillator, and each ring oscillator is provided with a plurality of inverters. That is, all inverters are arranged in a matrix of i rows and j columns, wherein i is any natural number greater than or equal to 1, j is a natural number not less than 3, and is an odd number (according to the Barkhausen criterion: if the oscillator is to generate oscillation, then the loop gain must be greater than or equal to 1 and the total phase shift is 360°, so the number of inversions in the loop must be an odd number), and the specific values of i and j are determined according to the actual situation of the controlled oscillator. Further, the output end of each inverter is connected to the input end of the inverter adjacent to it, and the input end of the inverter arranged at the first position of each level is respectively connected to an input signal Vin, and the output end of the inverter arranged at the end of each level is connected to the signal output end of the fully digital controlled oscillator, and the inverter arranged at the first position of each level is connected to the inverter arranged at the end, forming a circular negative feedback loop. The output end of each inverter of each stage is connected in parallel with multiple groups of switch devices, and each group of switch devices is connected in series with at least 3 switches. In the multiple groups of switch devices connected in parallel at the output end of each inverter, multiple groups of first switch devices for fine-tuning the oscillation frequency output by the inverter and multiple groups of second switch devices for coarse-tuning the oscillation frequency output by the inverter are provided. In each group of switch devices, at least 2 switches are connected to a full digital control end, and the oscillation frequency output by the inverter is fine-tuned or coarse-tuned through the full digital control end. In this embodiment, each group of switch devices is connected in series with 3 switches, and in each group of switch devices, 2 switches are connected to a full digital control end. The present invention adds a switch as a variable load to the existing ring oscillator, and adjusts the oscillation frequency of the ring oscillator by a coarse adjustment switch and a fine adjustment switch with a gear position, slowing down its phase jitter, thereby achieving the purpose of effectively reducing the synchronization error of the output. In this embodiment, the switches are preferably P-MOS switches or N-MOS switches. It should be noted that the use of MOS switches mainly utilizes the subthreshold state of the transistor to generate a small subthreshold current, which is well controlled by the gate voltage and is well applied in the low-voltage, low-power environment of the fully digitally controlled oscillator.
[0028] Further, in each group of first switch devices, the switches are arranged in sequence, the drain of the switch arranged in the first position is connected to the output of the inverter, and its source is connected to the drain of the adjacent switch; the drain and source of the switch arranged in the last position are both connected to the output of the corresponding next-stage inverter (i>1) or to the output of the fully digitally controlled oscillator (i=1), and its gate is connected to the source of the adjacent switch; the drains of the remaining switches are all connected to the source of the adjacent switch. In each group of second switch devices, the switches are arranged in sequence, the drain of the switch arranged in the first position is connected to the output of the inverter, and its source is connected to the drain of the adjacent switch; the gate and source of the switch arranged in the last position are both connected to the output of the corresponding next-stage inverter (i>1) or to the output of the fully digitally controlled oscillator (i=1), and its drain is connected to the source of the adjacent switch; the drains of the remaining switches are all connected to the source of the adjacent switch. In all switches, the unconnected gates are connected to the full digital control terminal through the digital control port in a predetermined order, and the full digital control terminal controls the opening or closing of the switch. The full digital control terminal usually uses a control word to control the switch. The full digital control terminal is a proprietary technology and will not be described in detail here. The MCU control unit and CPU terminal of the prior art can realize the corresponding functions.
[0029] Optionally, the predetermined order may be: in each stage of the ring oscillator, in a matrix structure formed by multiple groups of switch devices, each digital control port is connected to the gate of each switch in sequence from the first column to the last column of the matrix and from top to bottom.
[0030] Optionally, the predetermined order may also be: in each stage of the ring oscillator, in a matrix structure formed by multiple groups of switch devices, each digital control port is connected to the gate of each switch in sequence from the first row to the last row of the matrix and from left to right.
[0031] Furthermore, the total number of digital control ports is taken from any one of the following geometric progressions:
[0032] a n =a1q n-1 ;
[0033] Wherein, a1=32, q=2, and n is a natural number greater than or equal to 1.
[0034] The number of switches is considered to be m, and the number of digital control ports is considered to be n, and the relationship between the two is: mn=n / 2.
[0035] like Figure 2-3The example shown is a 1*3 order ring oscillator. In the ring oscillator, the gate of each switch is connected to a full digital control terminal (such as a full digital controller) through a digital control port in a predetermined order, and is controlled to open or close by a control word. One optional predetermined sequence is: in a matrix composed of multiple groups of switch devices connected in parallel at the output end of each inverter, the digital control port is connected to the gate of each switch in sequence from top to bottom in the row direction of the matrix, that is, starting from the switch in the first row and first column of the matrix, the gate of the switch is connected to the control line c1, then starting from the switch in the second row and first column, the gate of the switch is connected to the control line c2, and the other columns are connected in sequence according to this step; another optional predetermined sequence is: in a matrix composed of multiple groups of switch devices connected in parallel at the output end of each inverter, the digital control port is connected to the gate of each switch in sequence from left to right in the column direction of the matrix, that is, starting from the switch in the first row and first column of the matrix, the gate of the switch is connected to the control line c1, then starting from the switch in the first row and second column, the gate of the switch is connected to the control line c2, and the other rows are connected in sequence according to this step.
[0036] It should be noted that the advantage of using full digital control is that the phase-locked loop uses fewer nonlinear devices such as high-resistance resistors, capacitors and inductors, and can be designed and manufactured using a manufacturing process compatible with high-speed digital logic circuits. It has the advantages of high precision and is not affected by temperature and voltage. The loop bandwidth and center frequency are programmable and adjustable, and it is easy to build a high-order phase-locked loop.
[0037] like Figure 2-3As shown, it is an embodiment of a 1*3 order ring oscillator, in which a plurality of switch devices connected in parallel at the output end of each inverter include a first switch device for outputting a fine-tuning frequency and a second switch device for outputting a coarse-tuning frequency. The specific implementation is as follows: when the input signal Vin entering the ring oscillator is frequency modulated by the ring oscillator to form an output signal Vout, and then fed back through a negative feedback loop, if the oscillation frequency is too high (such as exceeding 10% of the normal oscillation frequency), it will pass through each inverter and perform coarse adjustment at the second switch device corresponding to the inverter in turn to reduce the oscillation frequency of the output signal Vout. If the oscillation frequency is only slightly high (exceeding 1% of the normal oscillation frequency), it will pass through each inverter and perform fine adjustment at the first switch device corresponding to the inverter in turn. Specifically, the control end sends a control word to each MOS switch of the first switch device through the digital control port. The control word sets the bias voltage of each MOS switch to its corresponding threshold value, so that the source and drain of each MOS switch are turned on. Under the action of the resistance of each MOS switch itself, the output signal Vout tends to a reasonable oscillation frequency, thereby achieving fine-tuning. If the oscillation frequency of the output signal Vout is too low, it will be coarsely adjusted at the second switch device corresponding to the inverter through each inverter in turn. If the oscillation frequency is only slightly low, it will be fine-tuned at the first switch device corresponding to the inverter through each inverter in turn, and output within a reasonable time delay. In this embodiment, each switch connected to the full digital control end corresponds to a frequency adjustment gear, and each coarse adjustment gear is equal to 8 fine adjustment gears. With a n = 128 (range 0, 1, ..., 127) as an example, there are 128 levels for coarse adjustment and 128 levels for fine adjustment, 1 level for coarse adjustment = 8 levels for fine adjustment, Value is the frequency level to be increased or decreased, and the corresponding pseudo code is:
[0038] if(value+fine>=0&&value+fine<=127)begin / *If fine-tuning of frequency is sufficient, only fine needs to be changed, and coarse does not need to be changed* /
[0039] coarse = coarse;
[0040] fine=fine+value;
[0041] end
[0042] else begin / *Frequency changes greatly, coarse and fine change at the same time* /
[0043] coarse=(value+(coarse*8)+fine) / 8;
[0044] fine=(value+(coarse*8)+fine)mod 8;
[0045] end
[0046] In summary, the pure digitally controlled oscillator of the present invention connects multiple MOS switches in parallel and series in a ring oscillator. The MOS switches are controlled by digital characters, and the inverter drives different loads to fine-tune the output oscillation frequency of the fully digitally controlled oscillator. The fully digitally controlled oscillator can reduce phase jitter and effectively reduce the output synchronization error.
[0047] The above are only preferred embodiments of the present invention. Those skilled in the art will appreciate that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application belong to the protection scope of the present invention.
Claims
1. A fully digital controlled oscillator, characterized in that: It comprises at least one ring oscillator, each ring oscillator is provided with a plurality of inverters, the output end of each inverter is connected in parallel with a plurality of switch devices, and each switch device is connected in series with at least 3 switches; All inverters are arranged in a matrix of i rows and j columns, i is any natural number greater than or equal to 1, j is a natural number not less than 3 and is an odd number; In the plurality of groups of switch devices connected in parallel at the output end of each inverter, there are a plurality of groups of first switch devices for fine-tuning the oscillation frequency output by the inverter and a plurality of groups of second switch devices for coarse-tuning the oscillation frequency output by the inverter; In each group of the switch devices, at least two of the switches are connected to a full digital control terminal, and the oscillation frequency output by the inverter is finely or roughly adjusted through the full digital control terminal; Each of the switches connected to the full digital control terminal corresponds to a frequency adjustment level, and each coarse adjustment level is equal to 8 fine adjustment levels; The switches are all P-MOS switches or N-MOS switches; In each group of the first switch devices, the switches are arranged in sequence, the drain of the switch arranged at the first position is connected to the output end of the inverter, and its source is connected to the drain of the adjacent switch; the drain and source of the switch arranged at the end are both connected to the output end of the corresponding inverter of the next stage or the output end of the fully digitally controlled oscillator, and its gate is connected to the source of the adjacent switch; the drains of the remaining switches are all connected to the source of the adjacent switch; In each group of the second switch devices, the switches are arranged in sequence, the drain of the switch arranged at the first position is connected to the output end of the inverter, and its source is connected to the drain of the adjacent switch; the gate and source of the switch arranged at the end are both connected to the output end of the corresponding inverter of the next stage or the output end of the fully digitally controlled oscillator, and its drain is connected to the source of the adjacent switch; the drains of the remaining switches are all connected to the source of the adjacent switches; In the switch, unconnected gates are connected to the full digital control terminal through the digital control port in a predetermined order, and the full digital control terminal controls the opening or closing of the switch.
2. The fully digital controlled oscillator according to claim 1, characterized in that: The predetermined order is: in each stage of the ring oscillator, multiple groups of the switch devices form a matrix structure, and each of the digital control ports is connected to the gate of each of the switches in sequence from the first column to the last column of the matrix and from top to bottom.
3. The fully digital controlled oscillator according to claim 1, characterized in that: The predetermined order is: in each stage of the ring oscillator, multiple groups of the switch devices form a matrix structure, and each of the digital control ports is connected to the gate of each of the switches in sequence from the first row to the last row of the matrix and from left to right.
4. The fully digital controlled oscillator according to claim 2 or 3, characterized in that: The total number of digital control ports is taken from any one of the following geometric progressions: a n =a1q n-1 ; Wherein, a1=32, q=2, and n is a natural number greater than or equal to 1.
5. The fully digital controlled oscillator according to claim 1, characterized in that: In each stage of the ring oscillator, the number of the inverters is an odd number not less than 3.
6. The fully digital controlled oscillator according to claim 1, characterized in that: In each stage of the ring oscillator, the output end of each inverter is connected to the input end of the adjacent inverter; The input terminals of the inverters arranged at the first position in each stage are respectively connected to an input signal; The output ends of the inverters arranged at the end of each stage are connected to the output end of the fully digital controlled oscillator; The inverter arranged at the first position in each stage is connected to the inverter arranged at the last position to form a circular negative feedback loop.