Imaging device

Abstract

The imaging device includes a first part, and the first part includes: a first semiconductor substrate; at least one first photoelectric conversion region; a first floating diffusion part; a first bonding part; a first wiring electrically connected between the first floating diffusion part and the first bonding part; at least one second photoelectric conversion region; a second floating diffusion part connected to the at least one second photoelectric conversion region; a second bonding part; a second wiring electrically connected between the second floating diffusion part and the second bonding part; a first region connected to a node for receiving a reference voltage; and a third wiring connected to the first region at a position between the first wiring and the second wiring. The imaging device includes a second part, the second part is joined to the first part via the first bonding part and the second bonding part, and the second part includes a readout circuit connected to the first bonding part and the second bonding part.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of Japanese Priority Patent Application JP2018 - 215381 filed on November 16, 2018 and Japanese Priority Patent Application JP2019 - 170593 filed on September 19, 2019, the entire contents of which are incorporated herein by reference. Technical field

[0003] The present disclosure relates to an imaging device. Background art

[0004] So far, by adopting microfabrication processes and increasing the mounting density, miniaturization of the area per pixel in two - dimensional structured imaging devices has been achieved. In recent years, in order to achieve further miniaturization of imaging devices, three - dimensional structured imaging devices have been developed. In such three - dimensional structured imaging devices, for example, as described in Patent Documents 1 to 3, a photodiode, a circuit for reading out the charge obtained by the photodiode (readout circuit), a circuit for controlling the charge readout from the photodiode (control circuit), etc. are provided on two stacked semiconductor substrates.

[0005] [Citation list]

[0006] [Patent documents]

[0007] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2014 - 22561

[0008] [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2010 - 219339

[0009] [Patent Document 3] Japanese Unexamined Patent Application Publication No. 2017 - 117828 Summary of the invention

[0010] Technical problem

[0011] Incidentally, in three - dimensional structured imaging devices, it is desired to further expand the dynamic range and further reduce noise. Therefore, it is desired to provide an imaging device capable of further expanding the dynamic range and further reducing noise.

[0012] Technical solution to solve the problem

[0013] The imaging device according to the first aspect of the present disclosure is configured to stack a first substrate, a second substrate, and a third substrate in this order. The first substrate has a pixel region including a plurality of sensor pixels for performing photoelectric conversion. The second substrate has a plurality of readout circuits, which are provided individually for one sensor pixel or a plurality of sensor pixels and output pixel signals based on charges output from the sensor pixels. The third substrate has a control circuit for controlling the sensor pixels and the readout circuits. The laminate including the first substrate and the second substrate has an interlayer insulating film and a plurality of bonding electrodes provided in a region located in the interlayer insulating film and opposite to the pixel region. The sensor pixels and the readout circuits are electrically connected to each other by bonding of the bonding electrodes.

[0014] In the imaging device according to the first aspect of the present disclosure, a plurality of sensor pixels are provided on the first substrate; a plurality of readout circuits are provided on the second substrate; and a control circuit is provided on the third substrate. Therefore, each sensor pixel can be configured to have a sufficiently large size, thereby ensuring a reproduced image with a wide dynamic range. In addition, this can make the size of the readout circuit sufficiently large, thereby avoiding an increase in dark-time noise such as RTS (Random Telegraph Signal) noise, for example. Further, in the imaging device according to an embodiment of the present disclosure, the sensor pixels and the readout circuits are electrically connected to each other by bonding of the bonding electrodes provided in a region opposite to the pixel region. Therefore, compared with the case where the sensor pixels and the readout circuits are electrically connected in one pixel on a common substrate, the size of a unit pixel can be reduced.

[0015] The imaging device according to the second aspect of the present disclosure is configured to stack a first substrate and a second substrate on each other. The first substrate has a pixel region including a plurality of sensor pixels for performing photoelectric conversion. The second substrate has a plurality of readout circuits and a control circuit, the plurality of readout circuits being provided individually for each of one sensor pixel or a plurality of sensor pixels and outputting pixel signals based on charges output from the sensor pixels, the control circuit controlling the sensor pixels and the readout circuits. The laminate including the first substrate and the second substrate has an interlayer insulating film and a plurality of bonding electrodes provided in a region located in the interlayer insulating film and opposite to the pixel region. The sensor pixels and the readout circuits are electrically connected to each other by bonding of the bonding electrodes.

[0016] In the imaging device according to the second aspect of the present disclosure, a plurality of sensor pixels are provided on a first substrate; and a plurality of readout circuits and control circuits are provided on a second substrate. Therefore, each sensor pixel can be configured to have a sufficiently large size, thereby ensuring a reproduced image with a wide dynamic range. In addition, this can make the size of the readout circuit sufficiently large, thereby avoiding an increase in dark-time noise such as RTS noise, for example.

[0017] According to one aspect of the present technology, an imaging device includes a first portion, the first portion including: a first semiconductor substrate; at least one first photoelectric conversion region provided in the first semiconductor substrate; a first floating diffusion portion connected to the at least one first photoelectric conversion region; a first bonding portion; a first wiring electrically connected between the first floating diffusion portion and the first bonding portion; at least one second photoelectric conversion region provided in the first semiconductor substrate; a second floating diffusion portion connected to the at least one second photoelectric conversion region; a second bonding portion; a second wiring electrically connected between the second floating diffusion portion and the second bonding portion; a first region connected to a node for receiving a reference voltage; and a third wiring connected to the first region and extending in the same direction as the first wiring and the second wiring at a position between the first wiring and the second wiring. The imaging device includes a second portion, the second portion being joined to the first portion via the first bonding portion and the second bonding portion, and the second portion including a readout circuit connected to the first bonding portion and the second bonding portion. The first portion further includes: a first transfer transistor for transferring charge from the first photoelectric conversion region to the first floating diffusion portion; and a second transfer transistor for transferring charge from the second photoelectric conversion region to the second floating diffusion portion. The readout circuit includes a first reset transistor, a first amplification transistor, and a first selection transistor electrically connected to the first bonding portion. The readout circuit includes a second reset transistor, a second amplification transistor, and a second selection transistor electrically connected to the second bonding portion. The readout circuit includes a first reset transistor and a first negative feedback circuit electrically connected to the first bonding portion and a second reset transistor and a second negative feedback circuit electrically connected to the second bonding portion. Each of the first negative feedback circuit and the second negative feedback circuit includes an operational amplifier and a feedback capacitor. The first portion further includes at least one insulating layer on the first semiconductor substrate, wherein the at least one insulating layer includes the first wiring, the second wiring, and the third wiring. The at least one insulating layer includes a first insulating layer and a second insulating layer, wherein the second insulating layer is closer to the second portion than the first insulating layer and has a lower dielectric constant than the first insulating layer. The first portion further includes a third bonding portion, wherein the third wiring electrically connects the first region to the third bonding portion, and wherein the first portion and the second portion are joined via the first bonding portion, the second bonding portion, and the third bonding portion. The at least one insulating layer includes a third insulating layer, the third insulating layer being on the second insulating layer and having a lower dielectric constant than the first insulating layer. The second portion further includes a third bonding portion joined to the first bonding portion and a fourth bonding portion joined to the second bonding portion.The second part further includes: a fourth wiring that electrically connects the third joint to the readout circuit; and a fifth wiring that electrically connects the fourth joint to the readout circuit. The second part further includes a sixth wiring that is electrically connected to the readout circuit located between the fourth wiring and the fifth wiring. The sixth wiring is aligned with the first wiring. The first part further includes a fifth joint, and wherein the second part further includes a sixth joint that engages with the fifth joint. The second part further includes: a second semiconductor substrate that includes the readout circuit; and an insulating layer on the second semiconductor substrate, the insulating layer including the fourth wiring, the fifth wiring, and the sixth wiring. The imaging device includes a third part that is joined to the second part and includes a processing circuit that processes signals from the readout circuit. According to one aspect of the present technology, the imaging device includes a first part that includes a first semiconductor substrate. The first semiconductor substrate includes: at least one first photoelectric conversion region; a first floating diffusion portion that is connected to the at least one first photoelectric conversion region; and a first transfer transistor that is configured to transfer charge from the at least one first photoelectric conversion region to the first floating diffusion portion. The imaging device includes: at least one second photoelectric conversion region that is provided in the first semiconductor substrate; a second floating diffusion portion that is connected to the at least one second photoelectric conversion region; and a second transfer transistor that is configured to transfer charge from the at least one second photoelectric conversion region to the second floating diffusion portion. The imaging device includes a well region and at least one first insulating layer on the first semiconductor substrate. The at least one first insulating layer includes: a first joint; a first wiring that is electrically connected between the first floating diffusion portion and the first joint; a second joint; a second wiring that is electrically connected between the second floating diffusion portion and the second joint; and a third wiring that is electrically connected to the well region and provides shielding between the first wiring and the second wiring. The imaging device includes a second part that is joined to the first part via the first joint and the second joint, and the second part includes a readout circuit that is connected to the first joint and the second joint. The imaging device includes a third part that is joined to the second part, and the third part includes a processing circuit that processes signals from the readout circuit.According to one aspect of the present technology, an imaging device includes a first portion including: a first photoelectric conversion region sharing a first floating diffusion portion; a first bonding portion; a first wiring electrically connecting the first floating diffusion portion and the first bonding portion; a second photoelectric conversion region sharing a second floating diffusion portion; a second bonding portion; a second wiring electrically connecting the second floating diffusion portion and the second bonding portion; a well region of a required conductivity type; a third wiring electrically connected to the well region, and the third wiring providing signal shielding between the first wiring and the second wiring; and a second portion joined to the first portion via the first bonding portion and the second bonding portion, and the second portion including a readout circuit electrically connected to the first bonding portion and the second bonding portion. The imaging device includes a third portion joined to the second portion, and the third portion includes a processing circuit that processes signals from the readout circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are included to provide a further understanding of the technology, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments, and together with the specification are used to explain the principles of the technology.

[0019] Figure 1 FIG. shows an exploded perspective configuration example of an imaging device according to an embodiment of the present disclosure.

[0020] Figure 2 FIG. shows Figure 1 an example of a functional block of the logic circuit shown.

[0021] Figure 3 FIG. shows Figure 1 an example of the sensor pixel and the readout circuit shown.

[0022] Figure 4 FIG. shows Figure 1 an example of a cross-sectional configuration in the vertical direction of the imaging device shown.

[0023] Figure 5 FIG. shows Figure 1 an example of a cross-sectional configuration in the horizontal direction of the imaging device shown.

[0024] Figure 6A FIG. shows Figure 4 a cross-sectional configuration example near the through-wiring in.

[0025] Figure 6B FIG. shows Figure 4 a cross-sectional configuration example near the through-wiring in.

[0026] Figure 6C FIG. shows Figure 4Example of the cross-sectional structure near the through-wiring

[0027] Figure 7A Shows Figure 4 Example of the cross-sectional structure near the through-wiring

[0028] Figure 7B Shows Figure 4 Example of the cross-sectional structure near the through-wiring

[0029] Figure 7C Shows Figure 4 Example of the cross-sectional structure near the through-wiring

[0030] Figure 8 Shows Figure 1 Modified example of the cross-sectional structure in the horizontal direction of the imaging device shown

[0031] Figure 9 Shows Figure 1 Modified example of the sensor pixel and the readout circuit shown

[0032] Figure 10 Shows Figure 1 Modified example of the cross-sectional structure in the horizontal direction of the imaging device shown

[0033] Figure 11 Shows Figure 1 Modified example of the cross-sectional structure in the vertical direction of the imaging device shown

[0034] Figure 12 Shows Figure 1 Modified example of the cross-sectional structure in the vertical direction of the imaging device shown

[0035] Figure 13 Shows Figure 1 Modified example of the cross-sectional structure in the vertical direction of the imaging device shown

[0036] Figure 14 Shows Figure 1 Modified example of the cross-sectional structure in the vertical direction of the imaging device shown

[0037] Figure 15 Shows Figure 1 Modified example of the cross-sectional structure in the vertical direction of the imaging device shown

[0038] Figure 16 Shows Figure 1 Modified example of the sensor pixel and the readout circuit shown

[0039] Figure 17 Shows Figure 1 Modified example of the readout circuit shown

[0040] Figure 18 shows Figure 1 a modified example of the sensor pixel and the readout circuit shown.

[0041] Figure 19 shows Figure 1 a modified example of the exploded perspective structure of the imaging device shown.

[0042] Figure 20 shows Figure 1 an example of the cross-sectional structure of the transistor in the first substrate shown.

[0043] Figure 21 shows Figure 1 an example of the cross-sectional structure of the transistor in the second substrate shown.

[0044] Figure 22 shows Figure 1 a modified example in which the sensor pixels are shared by the readout circuit in

[0045] Figure 23 shows Figure 1 a modified example in which the sensor pixels are shared by the readout circuit in

[0046] Figure 24 shows Figure 1 a modified example of the exploded perspective structure of the imaging device shown.

[0047] Figure 25 shows Figure 19 a modified example of the exploded perspective structure of the imaging device shown.

[0048] Figure 26 shows Figure 1 a modified example of the circuit structure of the imaging device shown.

[0049] Figure 27 shows Figure 1 a modified example of the cross-sectional structure in the vertical direction of the imaging device shown.

[0050] Figure 28 shows an imaging device having Figure 27 an example of the cross-sectional structure in the horizontal direction of the imaging device having the cross-sectional structure shown.

[0051] Figure 29 shows an imaging device having Figure 27 an example of the sensor pixel and the readout circuit of the imaging device having the cross-sectional structure shown.

[0052] Figure 30A is a schematic cross-sectional view in the vertical direction showing an example of the manufacturing method of the wiring structure shown in Figure 27 ​

[0053] Figure 30B is a schematic cross-sectional view showing the steps after the steps shown Figure 30A .

[0054] Figure 30C is a schematic cross-sectional view showing the steps after the steps shown Figure 30B .

[0055] Figure 30D is a schematic cross-sectional view showing the steps after the steps shown Figure 30C .

[0056] Figure 30E is a schematic cross-sectional view showing the steps after the steps shown Figure 30D .

[0057] Figure 30F is a schematic cross-sectional view showing the steps after the steps shown Figure 30E .

[0058] Figure 30G is a schematic cross-sectional view showing the steps after the steps shown Figure 30F .

[0059] Figure 30H is a schematic cross-sectional view showing the steps after the steps shown Figure 30G .

[0060] Figure 30I is a schematic cross-sectional view showing the steps after the steps shown Figure 30H .

[0061] Figure 31 shows Figure 27 a modified example of a bonding surface and wiring structure in the vicinity thereof in the imaging device shown

[0062] Figure 32 shows a cross-sectional structure in the vertical direction of a bonding surface and wiring structure in the vicinity thereof in the imaging device according to Comparative Example 1

[0063] Figure 33 shows a cross-sectional structure in the vertical direction of a bonding surface and wiring structure in the vicinity thereof in the imaging device according to Comparative Example 2

[0064] Figure 34 is an explanatory Figure 27 schematic cross-sectional view of misalignment in the imaging device shown

[0065] Figure 35 is an explanatory Figure 31 schematic cross-sectional view of misalignment in the imaging device shown

[0066] Figure 36 showsFigure 1 A modified example of the cross-sectional structure in the vertical direction of the imaging device shown.

[0067] Figure 37 Shows Figure 1 A modified example of the cross-sectional structure in the vertical direction of the imaging device shown.

[0068] Figure 38 Shows Figure 1 A modified example of the cross-sectional structure in the vertical direction of the imaging device shown.

[0069] Figure 39 Shows Figure 1 A modified example of the cross-sectional structure in the vertical direction of the imaging device shown.

[0070] Figure 40 Shows Figure 1 A modified example of the cross-sectional structure in the vertical direction of the imaging device shown.

[0071] Figure 41 Shows a modified example of the sensor pixels and readout circuit of an imaging device having Figure 27 the cross-sectional structure shown.

[0072] Figure 42 Shows a modified example of the sensor pixels and readout circuit of an imaging device having Figure 27 the cross-sectional structure shown.

[0073] Figure 43 Shows an example of the sensor pixels and readout circuit in the case where the Figure 27 wiring structure shown is applied to other positions.

[0074] Figure 44 Shows a modified example of the cross-sectional structure in the horizontal direction of an imaging device having Figure 27 the cross-sectional structure shown.

[0075] Figure 45 Shows a modified example of the cross-sectional structure in the horizontal direction of an imaging device having Figure 27 the cross-sectional structure shown.

[0076] Figure 46 Shows a modified example of the cross-sectional structure in the horizontal direction of an imaging device having Figure 27 the cross-sectional structure shown.

[0077] Figure 47 Shows a modified example of the cross-sectional structure in the horizontal direction of an imaging device having Figure 27 the cross-sectional structure shown.

[0078] Figure 48 Shows a modified example of the cross-sectional structure in the horizontal direction of an imaging device having Figure 27A modified example of the cross-sectional structure in the horizontal direction of the imaging device with the cross-sectional structure shown.

[0079] Figure 49 Shows an imaging device having Figure 27 A modified example of the cross-sectional structure in the horizontal direction of the imaging device with the cross-sectional structure shown.

[0080] Figure 50 Shows an imaging device having Figure 27 A modified example of the cross-sectional structure in the horizontal direction of the imaging device with the cross-sectional structure shown.

[0081] Figure 51 Shows an example of the schematic structure of an imaging system provided with any one of the imaging devices according to the above-described embodiments and their modified examples.

[0082] Figure 52 Shows Figure 51 An example of the imaging steps in the imaging system shown.

[0083] Figure 53 Is a block diagram showing an example of the schematic structure of a vehicle control system.

[0084] Figure 54 Is a diagram for assisting in explaining an example of the installation positions of the out-of-vehicle information detection unit and the imaging unit.

[0085] Figure 55 Is a diagram showing an example of the schematic structure of an endoscopic surgical system.

[0086] Figure 56 Is a block diagram showing an example of the functional structure of a camera and a camera control unit (CCU: camera control unit). Detailed Description of Specific Embodiments

[0087] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the description will be given in the following order.

[0088] 1. Embodiment (imaging device)... Figure 1 To FIG. 7

[0089] 2. Modified example (imaging device)... Figures 8 to 50

[0090] 3. Application example

[0091] An example of applying any one of the imaging devices according to the above-described embodiments and their modified examples to an imaging system... Figure 51 And Figure 52

[0092] 4. Industrial application examples

[0093] Industrial application example 1... An example of applying any of the imaging devices according to the above embodiments and their modified examples to a moving vehicle... Figure 53 and Figure 54

[0094] Industrial application example 2... An example of applying any of the imaging devices according to the above embodiments and their modified examples to a surgical system... Figure 55 and Figure 56

[0095] <1. Embodiment>

[0096] Structure

[0097] Figure 1 FIG. shows an example of a schematic structure of an imaging device 1 according to an embodiment of the present disclosure. The imaging device 1 includes three substrates (a first substrate 10, a second substrate 20, and a third substrate 30). The imaging device 1 is an imaging device having a three-dimensional structure formed by bonding the three substrates (the first substrate 10, the second substrate 20, and the third substrate 30) to each other. The first substrate 10, the second substrate 20, and the third substrate 30 are stacked in this order.

[0098] The first substrate 10 has a plurality of sensor pixels 12 that perform photoelectric conversion on a semiconductor substrate 11. The plurality of sensor pixels 12 are arranged in a matrix in a pixel region 13 on the first substrate 10. The first substrate 10 has, for example, a plurality of driving wirings 14 extending in a row direction. The plurality of driving wirings 14 are electrically connected to a vertical driving circuit 32a (described later).

[0099] The second substrate 20 has a readout circuit 22 on a semiconductor substrate 21. For one or more sensor pixels 12, the readout circuit 22 outputs a pixel signal based on charges output one by one from each sensor pixel 12. The plurality of readout circuits 22 are arranged in a matrix in a readout circuit region 23 on the second substrate 20. The second substrate 20 has, for example, a plurality of driving wirings extending in a row direction and a plurality of vertical signal lines VSL (described later) extending in a column direction. The plurality of driving wirings provided on the second substrate 20 are electrically connected to the vertical driving circuit 32a described later. The plurality of vertical signal lines VSL are electrically connected to a column signal processing circuit 32b described later.

[0100] The third substrate 30 has a logic circuit 32 and a booster circuit 33 on a semiconductor substrate 31. The logic circuit 32 controls each of the sensor pixels 12 and the readout circuit 22, and processes the pixel signals obtained from each readout circuit 22. As Figure 2As shown, the logic circuit 32 has, for example, a vertical drive circuit 32a, a column signal processing circuit 32b, a horizontal drive circuit 32c, and a system control circuit 32d. The logic circuit 32 outputs the output voltage Vout obtained for each sensor pixel 12 to the outside.

[0101] The vertical drive circuit 32a sequentially selects multiple sensor pixels 12 row by row, for example. The vertical drive circuit 32a is electrically connected to multiple drive wirings 14, for example, and sequentially selects multiple sensor pixels 12 row by row by sequentially outputting selection signals to the multiple drive wirings 14.

[0102] The column signal processing circuit 32b performs correlated double sampling (CDS) processing on the pixel signals output from each sensor pixel 12 in the row selected from the vertical drive circuit 32a, for example. The column signal processing circuit 32b extracts the signal level of the pixel signal by performing, for example, CDS processing to hold the pixel data corresponding to the amount of light received by each sensor pixel 12. The column signal processing circuit 32b is electrically connected to multiple vertical signal lines VSL described later, for example, and obtains pixel signals from each sensor pixel 12 in the row selected from the vertical drive circuit 32a through the multiple vertical signal lines VSL. The column signal processing circuit 32b has, for example, an ADC (Analog-to-Digital) for each vertical signal line VSL to convert the analog pixel signals obtained through the multiple vertical signal lines VSL into digital pixel signals.

[0103] For example, the horizontal drive circuit 32c sequentially outputs the pixel data held in the column signal processing circuit 32b to the outside as the output voltage Vout. The system control circuit 32d controls the driving of each block (vertical drive circuit 32a, column signal processing circuit 32b, and horizontal drive circuit 32c) in the logic circuit 32, for example. The boost circuit 33 generates a power supply potential VDD of a predetermined magnitude, for example.

[0104] Figure 3 An example of the sensor pixel 12 and the readout circuit 22 is shown. Hereinafter, as Figure 3 shown, the case where four sensor pixels 12 share one readout circuit 22 will be described. Here, "share" means that the outputs of multiple sensor pixels 12 are input to a common readout circuit 22.

[0105] Each sensor pixel 12 has the same components as each other. To distinguish the components of each sensor pixel 12, Figure 3The suffixes of the reference numerals that assign identification numbers (1, 2, 3, and 4) to the components of each sensor pixel 12. Hereinafter, in cases where it is necessary to distinguish the components of each sensor pixel 12 from each other, the suffixes of the reference numerals that assign identification numbers to the components of each sensor pixel 12 are used. However, in cases where it is not necessary to distinguish the components of each sensor pixel 12 from each other, the identification numbers of the suffixes of the reference numerals assigned to the components of each sensor pixel 12 are omitted.

[0106] Each sensor pixel 12 has, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion section FD that temporarily holds the charge output from the photodiode PD through the transfer transistor TR. For example, one floating diffusion section FD is provided for a plurality of sensor pixels 12 sharing the readout circuit 22. It should be noted that one floating diffusion section FD may also be provided for a single sensor pixel 12. In this case, in a plurality of sensor pixels 12 sharing the readout circuit 22, wirings are provided for electrically connecting the respective floating diffusion sections FD to each other.

[0107] The photodiode PD generates charge corresponding to the amount of received light by performing photoelectric conversion. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a region (p-well region 41 described later) in the semiconductor substrate 11 that is held at the reference potential VSS. The drain of the transfer transistor TR is electrically connected to the floating diffusion section FD, and the gate of the transfer transistor TR is electrically connected to the logic circuit 32 through a drive wiring 14 and a via wiring 42 described later. The transfer transistor TR is, for example, a CMOS (Complementary Metal Oxide Semiconductor) transistor.

[0108] The floating diffusion section FD is a floating diffusion region that temporarily holds the charge output from the photodiode PD through the transfer transistor TR. The input terminal of the readout circuit 22 is connected to the floating diffusion section FD. Specifically, a reset transistor RST described later is connected to the floating diffusion section FD, and the vertical signal line VSL is further connected to the floating diffusion section FD through an amplification transistor AMP and a selection transistor SEL described later. The floating diffusion section FD generates a capacitance Cfd. For example, as Figure 3 shown, a capacitance Cfd is generated between the wiring for connecting each sensor pixel 12 and the FD bonding electrode (or bonding portion) 17 and a region (e.g., p-well region 41) in the semiconductor substrate 11 that is held at the reference potential VSS.

[0109] The readout circuit 22 has, for example, a reset transistor RST, a selection transistor SEL, and an amplification transistor AMP. It should be noted that the selection transistor SEL may be omitted as needed. The source of the reset transistor RST (the input terminal of the readout circuit 22) is electrically connected to the floating diffusion portion FD, and the drain of the reset transistor RST is electrically connected to the wiring and the drain of the amplification transistor AMP, and the power supply potential VDD is applied to the above-mentioned wiring through the through-wiring 43 described later. The gate of the reset transistor RST is electrically connected to the logic circuit 32 through the through-wiring 42. The source of the amplification transistor AMP is connected to the drain of the selection transistor SEL, and the gate of the amplification transistor AMP is connected to the source of the reset transistor RST. The source of the selection transistor SEL (the output terminal of the readout circuit 22) is electrically connected to the logic circuit 32 through the vertical signal line VSL and the through-wiring 42, and the gate of the selection transistor SEL is electrically connected to the logic circuit 32 through the through-wiring 42.

[0110] When the transfer transistor TR is turned on, the transfer transistor TR transfers the charge of the photodiode PD to the floating diffusion portion FD. The reset transistor RST resets the potential of the floating diffusion portion FD to a predetermined potential. When the reset transistor RST is turned on, the reset transistor RST resets the potential of the floating diffusion portion FD to the power supply potential VDD. The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 22. The amplification transistor AMP generates a signal of a voltage corresponding to the level of the charge held in the floating diffusion portion FD as the pixel signal. The amplification transistor AMP constitutes a source follower type amplifier to output a pixel signal of a voltage corresponding to the level of the charge generated in the photodiode PD. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion portion FD and outputs a voltage corresponding to the potential to the logic circuit 32 through the vertical signal line VSL. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, CMOS transistors.

[0111] It should be noted that the selection transistor SEL may be provided between the power supply line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the wiring to which the power supply potential VDD is applied and is electrically connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is electrically connected to the logic circuit 32 through the through-wiring 42. The source of the amplification transistor AMP (the output terminal of the readout circuit 22) is electrically connected to the logic circuit 32 through the vertical signal line VSL and the through-wiring 42, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST.

[0112] Figure 4Shows an example of the cross-sectional structure in the vertical direction of the imaging device 1. Figure 4 Illustrates by way of example the cross-sectional structure of the position in the imaging device 1 opposite to the pixel region 13 (sensor pixel 12) and the cross-sectional structure of the region surrounding the pixel region 13. The imaging device 1 is configured to stack the first substrate 10, the second substrate 20, and the third substrate 30 in sequence, and the imaging device 1 further includes a color filter layer 40 and an optical receiving lens 50 on the back side (light incident surface side) of the first substrate 10. For example, the color filter layer 40 and the optical receiving lens 50 are provided one by one for each sensor pixel 12. In other words, the imaging device 1 is a back-illuminated type imaging device.

[0113] The first substrate 10 is configured to stack an insulating film (or insulating layer) 19 on the semiconductor substrate 11. The first substrate 10 has the insulating film 19 as an interlayer insulating film. The insulating film 19 is provided between the semiconductor substrate 11 and the second substrate 20. The first substrate 10 has a plurality of driving wirings 14 in the insulating film 19. Among the plurality of sensor pixels 12 arranged in a matrix form, the plurality of driving wirings 14 are arranged row by row in sequence. The semiconductor substrate 11 includes a silicon substrate. The semiconductor substrate 11 has, for example, a p-well region 41 on a part of the surface and in the vicinity of this position, and in a region other than the p-well region 41 (a region deeper than the p-well region 41), the semiconductor substrate 11 has a photodiode PD having a conductivity type different from that of the p-well region 41. The p-well region 41 includes a p-type semiconductor region. The photodiode PD includes a semiconductor region (specifically, an n-type) having a conductivity type different from that of the p-well region 41. The semiconductor substrate 11 has a floating diffusion portion FD in the p-well region 41 as a semiconductor region (specifically, an n-type) having a conductivity type different from that of the p-well region 41.

[0114] For each sensor pixel 12, the first substrate 10 has a photodiode PD, a transfer transistor TR, and a floating diffusion portion FD. The first substrate 10 is configured such that the transfer transistor TR and the floating diffusion portion FD are provided at a part on the front surface side (the side opposite to the light incident surface side, the second substrate 20 side) of the semiconductor substrate 11. The first substrate 10 has an element isolation portion that separates the respective sensor pixels 12. The element isolation portion is provided to extend in the normal direction (the direction perpendicular to the surface of the semiconductor substrate 11) of the semiconductor substrate 11. The element isolation portion is provided between two adjacent sensor pixels 12. The element isolation portion electrically isolates two adjacent sensor pixels 12 from each other. The element isolation portion includes, for example, silicon oxide. The first substrate 10 also has, for example, a fixed charge film that contacts the back surface of the semiconductor substrate 11. The fixed charge film is negatively charged to suppress the generation of dark current caused by the interface state on the light receiving surface side of the semiconductor substrate 11. The fixed charge film includes, for example, an insulating film having a negative fixed charge. Examples of materials for such an insulating film include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, or tantalum oxide. Due to the electric field induced by the fixed charge film, a hole storage layer is provided at the interface on the light receiving surface side of the semiconductor substrate 11. The hole storage layer is used to suppress the generation of electrons from the interface. The color filter layer 40 is provided on the back surface side of the first substrate 10. The color filter layer 40 is provided, for example, to contact the fixed charge film and is provided at a position opposite to the sensor pixel 12 with the fixed charge film interposed therebetween. The light receiving lens 50 is provided, for example, to contact the color filter layer 40 and is provided at a position opposite to the sensor pixel 12 with the color filter layer 40 and the fixed charge film interposed therebetween.

[0115] The first substrate 10 has a plurality of FD through wirings 15 and a plurality of VSS through wirings 16 in the insulating film 19. The plurality of FD through wirings 15 and the plurality of VSS through wirings 16 extend through the insulating film 19. The FD through wiring 15 corresponds to a specific example of the "third through wiring" of the present disclosure. The VSS through wiring 16 corresponds to a specific example of the "second through wiring" of the present disclosure. Each VSS through wiring 16 is disposed at an interval between two adjacent FD through wirings 15 among the plurality of FD through wirings 15. In addition, the first substrate 10 has a plurality of FD bonding electrodes 17 and one VSS bonding electrode (or bonding portion) 18 in the insulating film 19. The plurality of FD bonding electrodes 17 and the one VSS bonding electrode 18 are both exposed on the surface of the insulating film 19. The FD bonding electrode 17 corresponds to a specific example of the "first bonding electrode" of the present disclosure. The VSS bonding electrode 18 corresponds to a specific example of the "wiring electrode" of the present disclosure. A plurality of FD through wirings 15 and a plurality of VSS through wirings 16 are provided in a region opposite to the pixel region 13. Each VSS bonding electrode 18 is disposed in the same plane as each FD bonding electrode 17. The VSS bonding electrode 18 is disposed at an interval between two adjacent FD bonding electrodes 17 among the plurality of FD bonding electrodes 17.

[0116] In the case where one floating diffusion section FD is provided for the plurality of sensor pixels 12 of the common readout circuit 22, a plurality of FD through wirings 15 are provided one by one for each of the plurality of sensor pixels 12 of the common readout circuit 22. In the case where one floating diffusion section FD is provided for a single sensor pixel 12, a plurality of FD through wirings 15 are provided one by one for each sensor pixel 12.

[0117] Each FD through wiring 15 is connected to the floating diffusion section FD and the FD bonding electrode 17. In the case where one floating diffusion section FD is provided for the plurality of sensor pixels 12 of the common readout circuit 22, a plurality of VSS through wirings 16 are provided one by one for each of the plurality of sensor pixels 12 of the common readout circuit 22. In the case where one floating diffusion section FD is provided for a single sensor pixel 12, a plurality of VSS through wirings 16 are provided one by one for each sensor pixel 12. Each VSS through wiring 16 is connected to the p-well region 41 and the VSS bonding electrode 18. In either case, a plurality of VSS through wirings 16 are provided one by one for each readout circuit 22.

[0118] The second substrate 20 is configured to stack an insulating layer 28 on the semiconductor substrate 21. The second substrate 20 has the insulating layer 28 as an interlayer insulating film. The insulating layer 28 is provided between the semiconductor substrate 21 and the first substrate 10. The semiconductor substrate 21 includes a silicon substrate. The second substrate 20 has one readout circuit 22 for each of the four sensor pixels 12. The second substrate 20 is configured such that the readout circuit 22 is provided at a part on the front surface side (the third substrate 30 side) of the semiconductor substrate 21. The second substrate 20 is joined to the first substrate 10 such that the front surface of the semiconductor substrate 21 faces the front surface side of the semiconductor substrate 11.

[0119] The second substrate 20 has a plurality of FD through wirings 26 and a plurality of VSS through wirings 27 in the insulating layer 28. The plurality of FD through wirings 26 and the plurality of VSS through wirings 27 extend through the insulating layer 28. The FD through wiring 26 corresponds to a specific example of the "third through wiring" of the present disclosure. The VSS through wiring 27 corresponds to a specific example of the "second through wiring" of the present disclosure. Each VSS through wiring 27 is provided at an interval between two adjacent FD through wirings 26 among the plurality of FD through wirings 26. Further, the second substrate 20 has a plurality of FD bonding electrodes (or bonding portions) 24 and one VSS bonding electrode (or bonding portion) 25 in the insulating layer 28. The plurality of FD bonding electrodes 24 and the one VSS bonding electrode 25 are both exposed on the surface of the insulating layer 28. The FD bonding electrode 24 corresponds to a specific example of the "first bonding electrode" of the present disclosure. The VSS bonding electrode 25 corresponds to a specific example of the "wiring electrode" of the present disclosure. The plurality of FD bonding electrodes 24 are provided one by one for each FD bonding electrode 17 of the first substrate 10. The FD bonding electrode 24 is electrically connected to the FD bonding electrode 17. The FD bonding electrode 24 and the FD bonding electrode 17 include, for example, a copper material, and the FD bonding electrode 24 and the FD bonding electrode 17 are joined to each other. The VSS bonding electrode 25 is electrically connected to the VSS bonding electrode 18 of the first substrate 10. The VSS bonding electrode 25 and the VSS bonding electrode 18 include, for example, a copper material, and the VSS bonding electrode 25 and the VSS bonding electrode 18 are joined to each other. Each VSS bonding electrode 25 is provided, for example, in the same plane as each FD bonding electrode 24. The VSS bonding electrode 25 is provided at an interval between two adjacent FD bonding electrodes 24 among the plurality of FD bonding electrodes 24. The sensor pixel 12 and the readout circuit 22 are electrically connected to each other by the bonding of the FD bonding electrodes 17 and 24.

[0120] For example, as Figure 5 shown, the FD bonding electrodes 17 and 24 are respectively provided at positions opposite to the floating diffusion portion FD. Figure 5Shows an example of the cross-sectional structure in the FD bonding electrode 17 and the VSS bonding electrode 18, or an example of the cross-sectional structure in the FD bonding electrode 24 and the VSS bonding electrode 25. When four sensor pixels 12 share the floating diffusion section FD, the floating diffusion section FD is provided at the central part of the area including the four sensor pixels 12. Therefore, when the four sensor pixels 12 share the floating diffusion section FD, the FD bonding electrodes 17 and 24 are respectively provided at positions opposite to the central part of the area including the four sensor pixels 12. The FD bonding electrodes 17 and 24 are, for example, square.

[0121] For example, as Figure 5 shown, the VSS bonding electrodes 18 and 25 are respectively arranged in a lattice pattern surrounding each of the FD bonding electrodes 17 and 24 in the in-plane direction of the stack. When viewed from the stacking direction of the imaging device 1, the VSS bonding electrodes 18 and 25 respectively have openings at positions opposite to the four sensor pixels 12. The VSS bonding electrode 18, for example, has a lattice shape, in which a plurality of bonding wirings extending in the first array direction (e.g., row direction) and a plurality of bonding wirings extending in the second array direction (e.g., column direction) are arranged in the same plane and intersect each other (orthogonal to each other). Similarly, the VSS bonding electrode 25, for example, has a lattice shape, in which a plurality of bonding wirings extending in the first array direction (e.g., row direction) and a plurality of bonding wirings extending in the second array direction (e.g., column direction) are arranged in the same plane and intersect each other (orthogonal to each other). Here, the first array direction is one array direction (e.g., row direction) of the plurality of floating diffusion sections FD (or the plurality of sensor pixels 12). In addition, the second array direction is the other array direction (e.g., column direction) of the plurality of floating diffusion sections FD (or the plurality of sensor pixels 12).

[0122] A plurality of FD bonding electrodes 24 and a plurality of FD through wirings 26 are provided in the area opposite to the pixel area 13. For each FD through wiring 15, a plurality of FD through wirings 26 are provided one by one. Each FD through wiring 26 is connected to the FD bonding electrode 24 and the readout circuit 22 (specifically, the gate of the amplification transistor AMP). A plurality of VSS bonding electrodes 25 and a plurality of VSS through wirings 27 are provided in the area opposite to the pixel area 13. For each VSS through wiring 16, a plurality of VSS through wirings 27 are provided one by one. Each VSS through wiring 27 is connected to the VSS bonding electrode 25 and the area in the second substrate 20 to which the reference potential VSS is applied (the reference potential area of the readout circuit 22).

[0123] A stacked body including a first substrate 10 and a second substrate 20 has a plurality of through wirings 42 that extend through the first substrate 10 and the second substrate 20 in a region surrounding a pixel region 13. The through wirings 42 correspond to specific examples of the "first through wirings" of the present disclosure. For each driving wiring 14 of the first substrate 10, a plurality of through wirings 42 are provided one by one. Each through wiring 42 is connected to the driving wiring 14 and a vertical driving circuit 32a of a logic circuit 32. Accordingly, the logic circuit 32 controls sensor pixels 12 and a readout circuit 22 through the plurality of through wirings 42. Each through wiring 42 includes, for example, a TSV (Through-Silicon Via). It should be noted that instead of the through wirings 42, through wirings that extend through an insulating film 19 (hereinafter referred to as "through wiring a"), through wirings that extend through an insulating layer 28 (hereinafter referred to as "through wiring b"), bonding electrodes connected to the through wiring a (hereinafter referred to as "bonding electrode c"), and bonding electrodes connected to the through wiring b (hereinafter referred to as "bonding electrode d") may be provided. In this case, the bonding electrodes c and d include, for example, copper, and the bonding electrode c and the bonding electrode d are bonded to each other.

[0124] The stacked body including the first substrate 10 and the second substrate 20 further has a through wiring 43 and a through wiring 44 that respectively extend through the first substrate 10 and the second substrate 20 around the pixel region 13. The through wirings 43 and 44 include, for example, TSVs respectively. The through wiring 43 is connected to a booster circuit 33 of a third substrate 30 and is held at a power supply potential VDD. The power supply potential VDD is, for example, a value in a range of 2.5V to 2.8V. The through wiring 44 is electrically connected to a region in the third substrate 30 to which a reference potential VSS is applied (a reference potential region of the third substrate 30) and is held at the reference potential VSS. The reference potential VSS is, for example, 0V.

[0125] The third substrate 3 is configured to laminate an insulating layer 36 on a semiconductor substrate 31, for example. The third substrate 30 has the insulating layer 36 as an interlayer insulating film. The insulating layer 36 is provided between the semiconductor substrate 31 and the second substrate 20. The semiconductor substrate 31 includes a silicon substrate. The third substrate 30 is configured such that a logic circuit 32 is provided at a part on the front surface side (the second substrate 20 side) of the semiconductor substrate 31. The third substrate 30 is bonded to the second substrate 20 such that the front surface of the semiconductor substrate 31 faces the back surface side of the semiconductor substrate 21.

[0126] Figure 6A An example of a wiring structure for taking out an output voltage Vout to be output from the logic circuit 32 from the imaging device 1 is shown. Figure 6B An example of a wiring structure for supplying a reference potential to the booster circuit 33 is shown. Figure 6CShows an example of a wiring structure for supplying a reference potential VSS to a third substrate 30. A laminate including a first substrate 10 and a second substrate 20 has openings 45a, 46a, and 47a around a pixel region 13, and the openings 45a, 46a, and 47a extend through the first substrate 10 and the second substrate 20, respectively. A connection pad 45b is provided on the bottom surface of the opening 45a, and the connection pad 45b is connected to an output terminal of a logic circuit 32. For example, a bonding wire is connected to the connection pad 45b. A connection pad 46b is provided on the bottom surface of the opening 46a, and the connection pad 46b is connected to a booster circuit 33. For example, a bonding wire is connected to the connection pad 46b. A connection pad 47b is provided on the bottom surface of the opening 47a, and the connection pad 47b is connected to a region in the third substrate 30 to which the reference potential VSS is applied. For example, a bonding wire is connected to the connection pad 47b.

[0127] It should be noted that, as Figure 7A shown, a through-wiring 45c can be provided inside the opening 45a. In this case, for example, a connection pad 45d can be provided on the surface of the first substrate 10 that exposes the through-wiring 45c, and a bonding wire can be connected to the connection pad 45d. In addition, as Figure 7B shown, a through-wiring 46c can be provided inside the opening 46a. In this case, for example, a connection pad 46d can be provided on the surface of the first substrate 10 that exposes the through-wiring 46c, and a bonding wire can be connected to the connection pad 46d. Further, as Figure 7C shown, a through-wiring 47c can be provided inside the opening 47a. In this case, for example, a connection pad 47d can be provided on the surface of the first substrate 10 that exposes the through-wiring 47c, and a bonding wire can be connected to the connection pad 47d.

[0128] Beneficial effects

[0129] Next, the beneficial effects of the imaging device 1 according to the present embodiment will be described.

[0130] So far, by adopting a microfabrication process and increasing the mounting density, miniaturization of the area per pixel in a two-dimensional structure imaging device has been achieved. In recent years, in order to achieve further miniaturization of the imaging device and high-density pixel mounting, a three-dimensional structure imaging device has been developed. In such a three-dimensional structure imaging device, for example, a photodiode, a circuit for reading out the charge obtained by the photodiode (readout circuit), a circuit for controlling the charge readout from the photodiode (control circuit), etc. are provided on two stacked semiconductor substrates.

[0131] In the present embodiment, a plurality of sensor pixels 12 are provided on a first substrate 10; a plurality of readout circuits 22 are provided on a second substrate 20; and a logic circuit 32 is provided on a third substrate 30. This enables each sensor pixel 12 to be formed in a sufficiently large size, thereby ensuring the acquisition of a reproduced image with a wide dynamic range. In addition, this enables the readout circuit 22 to be formed in a sufficiently large size, thereby avoiding, for example, an increase in dark-time noise such as RTS noise. Further, this enables the logic circuit 32 to be formed in a sufficiently large size, thereby, for example, being able to sufficiently increase the output data rate and obtaining a moving image at a high frame rate. Further, in the present embodiment, the sensor pixel 12 and the readout circuit 22 are electrically connected to each other by bonding of FD bonding electrodes 17 and 24 provided in a region opposite to the pixel region 13. This can reduce the size of a unit pixel as compared with the case where the electrical connection between the sensor pixel 12 and the readout circuit 22 is performed in a single pixel on a common substrate.

[0132] Further, in the present embodiment, in a laminate including the first substrate 10 and the second substrate 20, a plurality of through wirings 42 are provided in a region surrounding the pixel region 13. The logic circuit 32 controls the sensor pixel 12 and the readout circuit 22 through the plurality of through wirings 42. Therefore, as compared with the case where each through wiring 42 is provided in a region opposite to the pixel region 13, it is ensured that each through wiring 42 is arranged away from the FD through wirings 15 and 26 that are electrically connected to the floating diffusion portion FD. As a result, signal interference between each through wiring 42 and each of the FD through wirings 15 and 26 can be reduced. Thereby, noise can be further reduced.

[0133] In addition, in the present embodiment, in a region of the insulating film 19 that is opposite to the pixel region 13, a plurality of VSS through wirings 16 are provided one by one for each readout circuit 22, and in a region of the insulating layer 28 that is opposite to the pixel region 13, a plurality of VSS through wirings 27 are provided one by one for each readout circuit 22. Further, in the present embodiment, each VSS through wiring 16 is electrically connected to a region (p-well region 41) maintained at a reference potential VSS in the first substrate 10, and each VSS through wiring 27 is electrically connected to a region maintained at the reference potential VSS in the second substrate 20. Therefore, each VSS through wiring 16 can function as a shield that reduces signal interference between adjacent FD through wirings 15, and each VSS through wiring 27 can also function as a shield that reduces signal interference between adjacent FD through wirings 26. Thereby, noise can be further reduced.

[0134] In addition, in the present embodiment, in a region located in the insulating film 19 and opposite to the pixel region 13, a plurality of FD through wirings 15 respectively electrically connected to the plurality of FD bonding electrodes 17 are provided, and in a region located in the insulating layer 28 and opposite to the pixel region 13, a plurality of FD through wirings 26 respectively electrically connected to the plurality of FD bonding electrodes 24 are provided. In addition, in the present embodiment, each VSS through wiring 16 is provided at an interval between two adjacent FD through wirings 15 among the plurality of FD through wirings 15, and each VSS through wiring 27 is provided at an interval between two adjacent FD through wirings 26 among the plurality of FD through wirings 26. Therefore, each VSS through wiring 16 can function as a shield for reducing signal interference between adjacent FD through wirings 15, and each VSS through wiring 27 can also function as a shield for reducing signal interference between adjacent FD through wirings 26. Thereby, noise can be further reduced.

[0135] In addition, in the present embodiment, a VSS bonding electrode 18 (wiring electrode) electrically connected to each VSS through wiring 16 is provided in the insulating film 19, and the respective VSS bonding electrodes 18 are respectively arranged in a lattice pattern surrounding the respective FD bonding electrodes 17. Further, in the present embodiment, a VSS bonding electrode 25 (wiring electrode) electrically connected to each VSS through wiring 27 is provided in the insulating layer 28, and the respective VSS bonding electrodes 25 are respectively arranged in a lattice pattern surrounding the respective FD bonding electrodes 24. Therefore, the VSS bonding electrode 18 can function as a shield for reducing signal interference between adjacent FD bonding electrodes 17, and each VSS bonding electrode 25 can also function as a shield for reducing signal interference between adjacent FD bonding electrodes 24. Thereby, noise can be further reduced.

[0136] <2. Modified Example>

[0137] Hereinafter, a modified example of the imaging device 1 according to the above embodiment will be described. It should be noted that in the following modified examples, the same components as those in the above embodiment are denoted by the same reference numerals.

[0138] Modified Example A

[0139] Figure 8 A modified example of the cross-sectional structure of the FD bonding electrode 17 and the VSS bonding electrode 18, or a modified example of the cross-sectional structure of the FD bonding electrode 24 and the VSS bonding electrode 25 is shown. In the imaging device 1 according to the above embodiment, for example, as Figure 8As shown, each VSS bonding electrode 18 may include a plurality of bonding electrodes 18a and a wiring 18b that electrically connects the plurality of bonding electrodes 18a to each other. In addition, in the imaging device 1 according to the above-described embodiment, for example, as Figure 8 shown, each VSS bonding electrode 25 may include a plurality of bonding electrodes 25a and a wiring 25b that electrically connects the plurality of bonding electrodes 25a to each other.

[0140] In this case, a plurality of bonding electrodes 18a are provided one by one for each VSS through-wiring 16, and a plurality of bonding electrodes 25a are provided one by one for each VSS through-wiring 27. In other words, the first substrate 10 has a plurality of bonding electrodes 18a in the insulating film 19 that are electrically connected to the plurality of VSS through-wirings 16 respectively, and the second substrate 20 has a plurality of bonding electrodes 25a in the insulating layer 28 that are electrically connected to the plurality of VSS through-wirings 27 respectively. Each of the bonding electrodes 18a and each of the bonding electrodes 25a are specific examples corresponding to the "second bonding electrode" of the present disclosure. In addition, the plurality of bonding electrodes 18a are each provided at an interval between two adjacent FD bonding electrodes 17 among the plurality of FD bonding electrodes 17, and the plurality of bonding electrodes 25a are each provided at an interval between two adjacent FD bonding electrodes 24 among the plurality of FD bonding electrodes 24.

[0141] Even in this case, the VSS bonding electrode 18 can function as a shield that reduces signal interference between adjacent FD bonding electrodes 17, and each VSS bonding electrode 25 can also function as a shield that reduces signal interference between adjacent FD bonding electrodes 24. Thereby, noise can be further reduced.

[0142] Modification B

[0143] Figure 9 A modification of the sensor pixel 12 and the readout circuit 22 is shown. Figure 10 A modification of the cross-sectional structure of the FD bonding electrode 17 and the VSS bonding electrode 18, or a modification of the cross-sectional structure of the FD bonding electrode 24 and the VSS bonding electrode 25 is shown.

[0144] In the imaging device 1 according to the above-described embodiment and its modifications, for example, as Figure 9 shown, one readout circuit 22 can share 8 sensor pixels 12 (2 × 4 sensor pixels 12). At this time, for example, as Figure 10As shown, the VSS bonding electrodes 18 and 25 are respectively arranged in a lattice pattern that surrounds the FD bonding electrodes 17 and 24 in the in-plane direction of the stack. The VSS bonding electrode 18, for example, has a lattice pattern formed in the same plane such that a plurality of bonding wirings extending in a first direction and a plurality of bonding wirings extending in a second direction cross each other (are orthogonal to each other). Similarly, the VSS bonding electrode 25, for example, has a lattice pattern formed in the same plane such that a plurality of bonding wirings extending in a first direction and a plurality of bonding wirings extending in a second direction cross each other (are orthogonal to each other). Here, the first direction is a direction that crosses the arrangement direction (e.g., row direction or column direction) of the plurality of floating diffusions FD (or the plurality of sensor pixels 12). In addition, the second direction is a direction that crosses the arrangement direction (e.g., row direction or column direction) of the plurality of floating diffusions FD (or the plurality of sensor pixels 12), and is also a direction that crosses (is orthogonal to) the first direction. Compared with Figure 5 the layout shown, this layout can increase the pitch interval between two adjacent FD bonding electrodes 17 and can also increase the pitch interval between two adjacent FD bonding electrodes 24, thereby also increasing the distance between the FD bonding electrode 17 and the VSS bonding electrode 18, or the distance between the FD bonding electrode 24 and the VSS bonding electrode 25. As a result, even when the unit pixel size is smaller, the VSS bonding electrode 18 can be arranged between two adjacent FD bonding electrodes 17, and the VSS bonding electrode 25 can also be arranged between two adjacent FD bonding electrodes 24. Therefore, even when the unit pixel size is smaller, the VSS bonding electrode 18 can function as a shield to reduce signal interference between adjacent FD bonding electrodes 17, and each VSS bonding electrode 25 can also function as a shield to reduce signal interference between adjacent FD bonding electrodes 24. This can further reduce noise.

[0145] Modification C

[0146] Figure 11Fig. 0 shows a modified example of the cross-sectional structure of the imaging device 1 in the vertical direction. In the imaging device 1 according to the above-described embodiment and its modified examples, an insulating material having a dielectric constant lower than that of any position other than the insulating layer 71 in the insulating film 19 provided on the first substrate 10 can be used to provide the insulating layer 71 that is on the same layer as the FD bonding electrode 17 and the VSS bonding electrode 18 in the insulating film 19 provided on the first substrate 10. Further, in the imaging device 1 according to the above-described embodiment and its modified examples, an insulating material having a dielectric constant lower than that of any position other than the insulating layer 72 in the insulating layer 28 provided on the second substrate 20 can be used to provide the insulating layer 72 that is on the same layer as the FD bonding electrode 24 and the VSS bonding electrode 25 in the insulating layer 28 provided on the second substrate 20. In this case, the capacitance Cfd can be reduced, thereby suppressing a decrease in conversion efficiency.

[0147] Further, in the imaging device 1 according to the above-described embodiment and its modified examples, for example, as Figure 12 shown, an insulating material having a dielectric constant lower than that of any position other than the insulating layers 71 and 73 in the insulating film 19 provided on the first substrate 10 can be used to provide the insulating layer 73 that is on the same layer as the connection wiring 47 (e.g., via hole) connected to the FD bonding electrode 17 and the VSS bonding electrode 18 in the insulating film 19 provided on the first substrate 10. Further, an insulating material having a dielectric constant lower than that of any position other than the insulating layers 72 and 74 in the insulating layer 28 provided on the second substrate 20 can be used to provide the insulating layer 74 that is on the same layer as the connection wiring 48 (e.g., via hole) connected to the FD bonding electrode 24 and the VSS bonding electrode 25 in the insulating layer 28 provided on the second substrate 20. In this case, the capacitance Cfd can be reduced, thereby suppressing a decrease in conversion efficiency.

[0148] Modified Example D

[0149] Figure 13 Fig. 12 shows a modified example of the cross-sectional structure of the imaging device 1 in the vertical direction. In the imaging device 1 according to the above-described embodiment and its modified examples, for example, as Figure 13As shown, the connection wiring 48 to be connected to the VSS bonding electrode 25 can be omitted, and in the region opposite to the pixel region 13, the wiring for connecting the VSS bonding electrode 25 and the region in the second substrate 20 to which the reference potential VSS is applied can be not provided. At this time, each VSS through-wiring 16 is electrically connected to the p-well region 41, and each VSS through-wiring 27 is electrically connected to the region in the second substrate 20 to which the reference potential VSS is applied. Even in this case, each VSS through-wiring 16 can function as a shield for reducing signal interference between adjacent FD through-wirings 15, and each VSS through-wiring 27 can also function as a shield for reducing signal interference between adjacent FD through-wirings 26. Thereby, the noise can be further reduced.

[0150] Modification E

[0151] Figure 14 A modification of the cross-sectional structure of the imaging device 1 in the vertical direction is shown. In the imaging device 1 according to the above-described embodiments and their modifications, for example, as Figure 14 As shown, the VSS bonding electrodes 18 and 25 can be omitted, and in the region opposite to the pixel region 13, the wiring for connecting the p-well region 41 of the first substrate 10 and the region in the second substrate 20 to which the reference potential VSS is applied can be not provided. At this time, each VSS through-wiring 16 is electrically connected to the p-well region 41, and each VSS through-wiring 27 is electrically connected to the region in the second substrate 20 to which the reference potential VSS is applied. Even in this case, each VSS through-wiring 16 can function as a shield for reducing signal interference between adjacent FD through-wirings 15, and each VSS through-wiring 27 can also function as a shield for reducing signal interference between adjacent FD through-wirings 26. Thereby, the noise can be further reduced.

[0152] Modification F

[0153] Figure 15 A modification of the cross-sectional structure of the imaging device 1 in the vertical direction is shown. In the imaging device 1 according to the above-described embodiments and their modifications, for example, as Figure 15As shown, the VSS bonding electrodes 18 and 25, and the connection wirings 47 and 48 respectively connected to the VSS bonding electrodes 18 and 25 can be omitted, and in the region opposite to the pixel region 13, the wiring for connecting the p-well region 41 of the first substrate 10 and the region where the reference potential VSS is applied in the second substrate 20 may not be provided. At this time, each VSS through-wiring 16 is electrically connected to the p-well region 41, and each VSS through-wiring 27 is electrically connected to the region where the reference potential VSS is applied in the second substrate 20. Even in this case, each VSS through-wiring 16 can function as a shield for reducing signal interference between adjacent FD through-wirings 15, and each VSS through-wiring 27 can also function as a shield for reducing signal interference between adjacent FD through-wirings 26. Thereby, the noise can be further reduced.

[0154] Modification G

[0155] Figure 16 A modification of the sensor pixel 12 and the readout circuit 22 is shown. In the above-described modifications D, E, and F, as the wiring for connecting the p-well region 41 of the first substrate 10 and the region where the reference potential VSS is applied in the second substrate 20, the through-wiring 44 can be used. In this case, the potential of the p-well region 41 of the first substrate 10 and the potential of the region where the reference potential VSS is applied in the second substrate 20 can be set to equal values (reference potential VSS).

[0156] Modification H

[0157] Figure 17 A modification of the readout circuit 22 is shown. In the imaging device 1 according to the above-described embodiment and its modifications, for example, as Figure 17 shown, the readout circuit 22 may include a negative feedback circuit that includes an operational amplifier OP and a feedback capacitor Cf instead of the amplification transistor AMP and the selection transistor SEL. The feedback capacitor Cf is connected to the first input terminal of the operational amplifier OP and the output terminal of the operational amplifier OP. The reset transistor RST is connected to the wiring to which the power supply potential VDD is applied, the first input terminal of the operational amplifier OP, and the first terminal of the feedback capacitor Cf. The wiring to which the power supply potential VDD is applied is connected to the second input terminal of the operational amplifier OP. For example, the power supply potential VDD and the reference potential VSS are applied as power supply voltages to the operational amplifier OP.

[0158] In this modification, the readout circuit 22 is provided with a negative feedback circuit including an operational amplifier OP and a feedback capacitor Cf. Since this ensures that the charge detection capacitance corresponds to the feedback capacitor Cf, high conversion efficiency can be achieved even if the capacitance Cfd of the floating diffusion portion FD is large.

[0159] Figure 18 shows a modified example of the sensor pixel 12 and the readout circuit 22. In the imaging device 1 according to any one of the above-described modified examples D to G, when the readout circuit 22 shown in Figure 17 is provided, the reference potential VSS1 of the first substrate 10 may be lower than the reference potential VSS2 of the second substrate 20. The reference potential VSS1 is lower than the reference potential VSS2, and the reference potential VSS1 is, for example, in the range of -0.5 V to -1 V. The reference potential VSS2 is, for example, a potential equal to the above-described reference potential VSS, and is, for example, 0 V. It should be noted that the region in the second substrate 20 to which the reference potential VSS2 is applied is the same as the region in the second substrate 20 to which the reference potential VSS is applied according to the above-described embodiment and its modified examples.

[0160] In this case, in the imaging device 1, as shown in the example of Figure 19 , the laminate including the first substrate 10 and the second substrate 20 may have the through-wiring 45 in the region surrounding the pixel region 13. The through-wiring 45 corresponds to a specific example of the "fourth through-wiring" of the present disclosure. The through-wiring 45 is a through-wiring to which the reference potential VSS1 is applied, and the through-wiring 45 includes, for example, a TSV. The through-wiring 45 is electrically connected to the negative boost circuit 34 described later and the p-well region 41 of the first substrate 10.

[0161] Furthermore, in the imaging device 1, as shown in the example of Figure 19 , the laminate including the second substrate 20 and the third substrate 30 may have the through-wiring 46 in the region surrounding the pixel region 13. The through-wiring 46 is a through-wiring to which the reference potential VSS2 is applied, and the through-wiring 46 includes, for example, a TSV. The through-wiring 46 is electrically connected to the region in the third substrate 30 to which the reference potential VSS2 is applied and the region in the second substrate 20 to which the reference potential VSS2 is applied.

[0162] Furthermore, in the imaging device 1, the third substrate 30 has a negative boost circuit 34 that generates a reference potential VSS1 of a predetermined magnitude. The negative boost circuit 34 controls the reference potential of the first substrate 10 through the through-wiring 45 to make the reference potential of the first substrate 10 lower than the reference potential of the second substrate 20.

[0163] In this modified example, the reference potential VSS1 of the first substrate 10 is lower than the reference potential VSS2 of the second substrate 20. Compared with the case where the reference potentials of the first substrate 10 and the second substrate 20 are equal to each other, this can expand the dynamic range of the floating diffusion portion FD. As a result, the erroneous transfer of charges can be suppressed, or the occurrence of black sinking during image display can be suppressed.

[0164] Modified Example I

[0165] Figure 20 Shows an example of a cross-sectional structure of a transistor in the first substrate 10. Figure 21 Shows an example of a cross-sectional structure of a transistor in the second substrate 20. In the imaging device 1 according to the above-described embodiments and their modifications, the design conditions of the transistors in the first substrate 10 and the transistors in the second substrate 20 may be different from each other.

[0166] For example, as Figure 20 shown, the transistor in the first substrate 10 has: a gate insulating film 51 provided on the semiconductor substrate 11; a gate electrode 52 provided in contact with the gate insulating film 51; a sidewall layer 53 provided in contact with the side surface of the gate electrode 52; and a source region and a drain region provided on the surface of the semiconductor substrate 11. As Figure 20 the example of shows, around the transistor in the first substrate 10, there are provided: a silicon oxide film 54 provided so as to cover the gate insulating film 51, the gate electrode 52, and the sidewall layer 53; a silicon nitride film 55 provided in contact with the silicon oxide film 54; an insulating layer 56 provided in contact with the silicon nitride film 55; a through-wiring 58 electrically connected to the gate electrode 52; and a through-wiring 57 electrically connected to the floating diffusion portion FD. The silicon oxide film 54 is provided to protect the front surface portion of the semiconductor substrate 11 or to make the thickness of the silicon oxide film on the front surface portion of the semiconductor substrate 11 uniform during ion implantation. The silicon nitride film 55 serves as an etch stop layer when forming through-holes to arrange the through-wirings 57 and 58 on the insulating layer 56.

[0167] For example, as Figure 21 shown, the transistor in the second substrate 20 has: a gate insulating film 61 provided on the semiconductor substrate 21; a gate electrode 62 provided in contact with the gate insulating film 61; a sidewall layer 63 provided in contact with the side surface of the gate electrode 62; and a source region and a drain region (impurity diffusion region 69) provided on the surface of the semiconductor substrate 21. As Figure 21 the example of shows, around the transistor in the second substrate 20, there are provided: a silicon oxide film 64 provided so as to cover the gate insulating film 61, the gate electrode 62, and the sidewall layer 63; a silicon nitride film 65 provided in contact with the silicon oxide film 64; an insulating layer 66 provided in contact with the silicon nitride film 65; a through-wiring 68 electrically connected to the gate electrode 62; and a through-wiring 67 electrically connected to the impurity diffusion region 69. The silicon oxide film 64 is provided to protect the front surface portion of the semiconductor substrate 21 or to make the thickness of the silicon oxide film on the front surface portion of the semiconductor substrate 21 uniform during ion implantation. The silicon nitride film 65 serves as an etch stop layer when forming through-holes to arrange the through-wirings 67 and 68 on the insulating layer 66.

[0168] In this modified example, the thickness of the gate insulating film 51 can be set to be greater than the thickness of the gate insulating film 61. In addition, in this modified example, the width of the sidewall layer 53 can be set to be greater than the width of the sidewall layer 63. Further, in this modified example, the impurity concentration of the source region and the drain region provided on the semiconductor substrate 11 can be lower than the impurity concentration of the impurity diffusion region 69 provided on the semiconductor substrate 21. In addition, in this modified example, the thickness of the silicon oxide film 54 can be set to be greater than the thickness of the silicon oxide film 64, and the thickness of the silicon nitride film 55 can be set to be less than the thickness of the silicon nitride film 65.

[0169] As described above, in this modified example, the design conditions of the transistors in the first substrate 10 and the transistors in the second substrate 20 are different. Therefore, the design conditions suitable for the transistors in the first substrate 10 can be applied to the transistors in the first substrate 10, and the design conditions suitable for the transistors in the second substrate 20 can be applied to the transistors in the second substrate 20. As a result, noise reduction, efficiency improvement, etc. can be achieved.

[0170] Modified Example J

[0171] Figure 22 and Figure 23 respectively show modified examples in which the readout circuit 22 shares the sensor pixels 12. In the imaging device 1 according to the above-described embodiments and their modified examples, for example, as Figure 22 shown, the number of sensor pixels 12 shared by one readout circuit 22 can be two. In addition, in the imaging device 1 according to the above-described embodiments and their modified examples, for example, as Figure 23 shown, one sensor pixel 12 can be provided for each readout circuit 22.

[0172] Modified Example K Figure 24 and Figure 25 respectively show the configuration of the imaging device 2 according to an embodiment of the present disclosure. The imaging device 2 is configured such that in the imaging device 1 according to the above-described embodiments and their modified examples, instead of the second substrate 20 and the third substrate 30, a second substrate 80 is provided, and circuits provided on the second substrate 20 and the third substrate 30 (specifically, a plurality of readout circuits 22, a logic circuit 32, a booster circuit 33, and a negative booster circuit 34) are provided on the second substrate 80. Even in this case, similar to the imaging device 1 according to the above-described embodiments and their modified examples, each sensor pixel 12 can be set to a sufficiently large size, thereby ensuring a reproduced image with a wide dynamic range. In addition, this can make the readout circuit 22 adopt a sufficiently large size, thereby, for example, avoiding an increase in dark-time noise such as RTS noise.

[0173] Modified Example L

[0174] Figure 26 FIG. 1 shows an example of the circuit configuration of the imaging device 1 according to the above-described embodiments and modifications thereof. The imaging device 1 according to this modification is a CMOS image sensor incorporating a line-parallel ADC.

[0175] As Figure 26 shown, in addition to a pixel region 13 in which a plurality of sensor pixels 12 each including a photoelectric conversion element are two-dimensionally arranged in a row and column manner (matrix mode), the solid-state imaging device 1 according to this modification further includes a vertical drive circuit 32a, a column signal processing circuit 32b, a reference voltage supply unit 38, a horizontal drive circuit 32c, a horizontal output line 37, and a system control circuit 32d.

[0176] In such a system configuration, the system control circuit 32d generates clock signals, control signals, etc. serving as reference signals for the operations of the vertical drive circuit 32a, the column signal processing circuit 32b, the reference voltage supply unit 38, the horizontal drive circuit 32c, etc. based on the master clock MCK, and the system control circuit 32d supplies the above signals to the vertical drive circuit 32a, the column signal processing circuit 32b, the reference voltage supply unit 38, the horizontal drive circuit 32c, etc.

[0177] In addition, the vertical drive circuit 32a is provided on the first substrate 10 together with each sensor pixel 12 in the pixel region 13, and the vertical drive circuit 32a is also provided on the second substrate 20 in which the readout circuit 22 is arranged. The column signal processing circuit 32b, the reference voltage supply unit 38, the horizontal drive circuit 32c, the horizontal output line 37, and the system control circuit 32d are provided on the third substrate 30.

[0178] For the sensor pixel 12, in addition to the photodiode PD, a configuration having, for example, a transfer transistor TR (not shown here) that transfers the charge obtained by photoelectric conversion through the photodiode PD to the floating diffusion section FD can be used. In addition, for the readout circuit 22, a three-transistor configuration having, for example, a reset transistor RST that controls the potential of the floating diffusion section FD, an amplification transistor AMP that outputs a signal corresponding to the potential of the floating diffusion section FD, and a selection transistor SEL for pixel selection (not shown here) can be used.

[0179] In the pixel region 13, for such an m-row / n-column pixel array, the sensor pixels 12 are two-dimensionally arranged, and drive wirings 14 are arranged row by row, while vertical signal lines VSL are arranged column by column. Each end of the plurality of drive wirings 14 is connected to each output end corresponding to each row of the vertical drive circuit 32a. The vertical drive circuit 32a includes a shift register or the like to control row addressing and row scanning of the pixel region 13 through the plurality of drive wirings 14.

[0180] The column signal processing circuit 32b has, for example, ADCs (analog-to-digital conversion circuits) 35-1 to 35-m provided for each pixel column of the pixel region 13, that is, for each vertical signal line VSL. Each ADC converts an analog signal output column by column from each sensor pixel 12 in the pixel region 13 into a digital signal as an output.

[0181] The reference voltage supply unit 38 has, for example, a DAC (digital-to-analog conversion circuit) 38A as a device for generating a reference voltage Vref having a so-called ramp waveform, and the level of the reference voltage Vref of the ramp waveform changes at a slope over time. It should be noted that the device for generating the reference voltage Vref having a ramp waveform is not limited to the DAC 38A.

[0182] Under the control of a control signal CS1 given from the system control circuit 32d, the DAC 38A generates a reference voltage Vref having a ramp waveform based on a clock CK given from the system control circuit 32d, and supplies the obtained voltage to the ADCs 35-1 to 35-m in the column signal processing circuit 32b.

[0183] It should be noted that the ADCs 35-1 to 35-m are each configured to selectively enable an A / D conversion operation corresponding to each operation mode, and the operation modes include a normal frame rate mode in a progressive scanning method for reading information of all the sensor pixels 12 and a high-speed frame rate mode in which the exposure time of the sensor pixels 12 is set to 1 / N and the frame rate is increased by N times (for example, doubled compared to the normal frame rate mode). The switching of the operation mode is performed under the control of control signals CS2 and CS3 given from the system control circuit 32d. Further, instruction information for switching between each operation mode of the normal frame rate mode and the high-speed frame rate mode is given from an external system controller (not shown) to the system control circuit 32d.

[0184] All the ADCs 35-1 to 35-m have the same configuration, and here, the ADC 35-m is taken as an example for description. The ADC 35-m is configured to have a comparator 35A, an up / down counter (represented as U / DCNT in the drawing) 35B as an example of a counting device, a transfer switch 35C, and a storage device 35D.

[0185] Comparator 35A compares the signal voltage Vx on the vertical signal line VSL corresponding to the signal to be output from each sensor pixel 12 in n columns of the pixel region 13 with the reference voltage Vref of the ramp waveform provided from the reference voltage supply unit 38. For example, when the reference voltage Vref is greater than the signal voltage Vx, the output Vco becomes the "H" level, and when the reference voltage Vref is less than or equal to the signal voltage Vx, the output Vco becomes the "L" level.

[0186] The up / down counter 35B is an asynchronous counter, and under the control of the control signal CS2 given from the system control circuit 32d, the clock CK is provided to the up / down counter 35B from the system control circuit 32d simultaneously with the DAC 38A. Synchronized with the clock CK, the up / down counter 35B performs a decrement (DOWN) count or an increment (UP) count, thereby measuring the comparison time period from the start to the end of the comparison operation of the comparator 35A.

[0187] Specifically, in the normal frame rate mode, in the operation of reading out the signal from a single sensor pixel 12, the up / down counter 35B measures the comparison time at the first readout operation by performing a decrement count during the first readout operation, and then measures the comparison time at the second readout operation by performing an increment count during the second readout operation.

[0188] In contrast, in the high-speed frame rate mode, the up / down counter 35B retains the count result of the sensor pixels 12 in a certain row as it is, and continues to measure the comparison time at the first readout operation by performing a decrement count on the previous count result of the sensor pixels 12 in the next row during the first readout operation, and then measures the comparison time at the second readout operation by performing an increment count during the second readout operation.

[0189] In the normal frame rate mode, under the control of the control signal CS3 given from the system control circuit 32d, when the counting operation of the up / down counter 35B of the sensor pixels 12 in a specific row is completed, the transmission switch 35C is placed in the on (closed) state to transfer the count result of the up / down counter 35B to the storage device 35D.

[0190] In contrast, in the high-speed frame rate mode where, for example, N = 2, when the counting operation of the up / down counter 35B of the sensor pixels 12 in a specific row is completed, the transmission switch 35C remains in the off (open) state, and then when the counting operation of the up / down counter 35B of the sensor pixels 12 in the next row is completed, the transmission switch 35C is continuously placed in the on state to transfer the count results of two vertical pixels from the up / down counter 35B to the storage device 35D.

[0191] In this manner, through the operations of the comparators 35A and the up / down counters 35B in each of the ADCs 35-1 to 35-m, the analog signals provided column by column from each sensor pixel 12 in the pixel region 13 through the vertical signal lines VSL are converted into N-bit digital signals and stored in the storage device 35D.

[0192] The horizontal drive circuit 32c includes a shift register or the like to control the column addressing and column scanning of the ADCs 35-1 to 35-m in the column signal processing circuit 32b. Under the control of the horizontal drive circuit 32c, the N-bit digital signals that have been A / D converted by each of the ADCs 35-1 to 35-m are sequentially read out onto the horizontal output line 37 and output as image data through the horizontal output line 37.

[0193] It should be noted that since the circuits and the like for performing various signal processes on the image data output through the horizontal output line 37 have no direct relation to the present disclosure, they are not specifically shown; however, such circuits can be provided in addition to the above-described components.

[0194] The imaging device 1 according to this modification of the above-described configuration, which incorporates a row-parallel ADC, can selectively transmit the count result of the up / down counter 35B to the storage device 35D through the transfer switch 35C, so that the counting operation of the up / down counter 35B and the operation of reading out the count result of the up / down counter 35B onto the horizontal output line 37 can be independently controlled.

[0195] Modification M

[0196] Figure 27 A modification of the cross-sectional configuration of the imaging device 1 in the vertical direction is shown. In particular, Figure 27 A modification of the bonding surface of the first substrate 10 and the second substrate 20 facing the pixel region 13 and the wiring structure near the bonding surface is shown. Figure 28 Shown is Figure 27 An example of the cross-sectional configuration in the horizontal direction of the FD bonding electrodes 17 and 24 and the VSS bonding electrodes 18 and 25 on the bonding surface of the first substrate 10 and the second substrate 20 shown. Figure 29 Shown is having Figure 27An example of a sensor pixel and a readout circuit of a wiring structure near a bonding surface of a first substrate 10 and a second substrate 20 shown. The difference between this modified example and the above-described embodiments and modified examples is that the FD bonding electrodes 17 and 24 are directly connected to the FD through-wiring 15 and 26 without passing through vias (the above-described connection wirings 47 and 48) inserted therebetween, and the VSS bonding electrodes 18 and 25 are directly connected to the VSS through-wiring 16 and 27 without passing through vias (the above-described connection wirings 47 and 48) inserted therebetween. In a region opposite to the pixel region 13, the FD bonding electrodes 17 and 24 electrically connect the sensor pixel 12 and the readout circuit 22 to each other, and in a region opposite to the pixel region 13, the VSS bonding electrodes 18 and 25 electrically connect the sensor pixel 12 and the readout circuit 22 to each other. Another difference between this modified example and the above-described embodiments and modified examples is that the FD bonding electrodes 17 and 24 and the VSS bonding electrodes 18 and 25 have two or more shapes.

[0197] For example, as Figure 27 shown, the widths of the FD bonding electrode 17, the FD bonding electrode 24, and the VSS bonding electrodes 18 and 25 can be different from each other. In one example, the width of each of the VSS bonding electrodes 18 and 25 can be smaller than the width of each of the FD bonding electrodes 17 and 24. In another example, the lengths of the FD bonding electrodes 17 and 24 and the VSS bonding electrodes 18 and 25 in the stacking direction can be different from each other. Alternatively, for example, as Figure 27 shown, the lengths of the VSS bonding electrode 18 on the first substrate 10 side and the VSS bonding electrode 25 on the second substrate 20 side in the optical axis direction can be different from each other. In this case, each VSS bonding electrode 18 on the first substrate 10 side is formed inside the insulating film 19 and is not exposed on, for example, the bonding surface of the first substrate 10 and the second substrate 20. In other words, the VSS bonding electrode 18 and the VSS bonding electrode 25 facing each other are separated from each other with the insulating film 19 therebetween. In this case, each VSS through-wiring 16 can also function as a shield for reducing signal interference between adjacent FD through-wirings 15, and each VSS through-wiring 27 can also function as a shield for reducing signal interference between adjacent FD through-wirings 26.

[0198] For example, the wiring structure can be manufactured as described below.

[0199] Figures 30A to 30I An example of a method for manufacturing the FD bonding electrode 17 and the VSS bonding electrode 18 on the first substrate 10 side is shown in step order. First, as Figure 30A shown, for example, the FD through-wiring 15 and the VSS through-wiring 16 are formed by a damascene technique. Thereafter, as Figure 30BAs shown, an insulating film 19B with a predetermined thickness is deposited on an insulating film 19A including an FD through-wiring 15 and a VSS through-wiring 16. Thereafter, as Figure 30C shown, the insulating film 19B on the FD through-wiring 15 and the VSS through-wiring 16 is selectively etched to form an opening H1. Thereafter, as Figure 30D shown, for example, a metal film M1 such as copper (Cu) is provided to fill the opening H1, and the metal film M1 is deposited on the insulating film 19B. Then, as Figure 30E shown, for example, the metal film M1 on the insulating film 19B is removed by etching. Thereby, a part (FD bonding electrode 17A) of the FD bonding electrode 17 and the VSS bonding electrode 18 is formed. Thereafter, as Figure 30F shown, an insulating film 19C with a predetermined thickness is deposited on the insulating film 19B including the FD bonding electrode 17A and the VSS bonding electrode 18. Thereafter, as Figure 30G shown, the insulating film 19 on the FD bonding electrode 17A is selectively etched to form an opening H2. Thereafter, as Figure 30H shown, for example, a metal film M2 such as copper (Cu) is provided to fill the opening H2, and the metal film M2 is deposited on the insulating film 19. Finally, as Figure 30I shown, for example, the metal film M2 on the insulating film 19 is removed by etching. In this way, the first substrate 10 including the FD bonding electrode 17 and the VSS bonding electrode 18 having different lengths in the stacking direction is completed.

[0200] It should be noted that although Figure 27 shows an example in which the widths of the FD bonding electrode 17 and the FD bonding electrode 24 are different from each other, as Figure 31 shown, the FD bonding electrode 17 and the FD bonding electrode 24 may have the same width. In addition, although Figure 27 shows an example in which the VSS bonding electrode 18 and the VSS bonding electrode 25 have the same width, similar to the FD bonding electrodes 17 and 24 shown in Figure 27 the widths of the VSS bonding electrode 18 and the VSS bonding electrode 25 may be different from each other (not shown).

[0201] As Figure 1As shown, in an imaging device 1 having a stacked body of a first substrate 10 including a plurality of sensor pixels 12 and a floating diffusion section FD and a second substrate 20 including a readout circuit 22 (which outputs a pixel signal based on charges output from the sensor pixels 12), it is desirable to provide shield wirings (e.g., VSS through wirings 16 or 27) between each signal terminal (e.g., FD through wiring 15 or 26) and at least four signal terminals adjacent to the relevant signal terminal in the row direction and the column direction. In the case where shield wirings are provided, for each shield wiring on the bonding surface of the first substrate 10 and the second substrate 20, in addition to providing FD bonding electrodes 17 and 24 that electrically connect the sensor pixels 12 and the readout circuit 22, bonding electrodes for the shield wirings (e.g., VSS bonding electrodes 18 or 25) are also provided. However, in an imaging device that requires high resolution, the pixel size decreases as the number of pixels increases. This reduces the distance between signal terminals and reduces the space for arranging the bonding electrodes of the shield wirings between the signal terminals. In this case, each VSS through wiring 16 can also function as a shield that reduces signal interference between adjacent FD through wirings 15, and each VSS through wiring 27 can also function as a shield that reduces signal interference between adjacent FD through wirings 26. Thereby, noise can be reduced.

[0202] In particular, when the first substrate 10 and the second substrate 20 are bonded to each other, the wiring pitch of the plurality of FD bonding electrodes 17 and 24 and the plurality of VSS bonding electrodes 18 and 25 becomes closer to the connection misalignment amount on each bonding surface. Therefore, it is difficult to arrange the shield wirings between adjacent signal terminals. For example, when the connection misalignment amount is large, as Figure 32 and Figure 33 shown, for example, conduction is established between the VSS bonding electrode 18 on the first substrate 10 side and the FD bonding electrode 24 on the second substrate 20 side. Conduction is established between the FD bonding electrode 17 on the first substrate 10 side and the VSS bonding electrode 25 on the second substrate 20 side. This prevents signal transmission between the first substrate 10 and the second substrate 20, which may cause large image defects on the reproduced image. Whether the bonding electrodes 17, 18, 24, and 25 on the through wirings 15, 16, 26, and 27 have a single-layer structure ( Figure 32 ) or a stacked structure ( Figure 33 ), the above situation will occur.

[0203] In contrast, according to this modification example, for example, the length of the VSS bonding electrode 18 on the first substrate 10 side in the optical axis direction is less than the length of the VSS bonding electrode 25 on the second substrate 20 side, thereby preventing the VSS bonding electrode 18 from being exposed on the bonding surface of the first substrate 10 and the second substrate 20. Therefore, as Figure 34 andFigure 35 As shown, even when a connection misalignment occurs between the first substrate 10 and the second substrate 20, contact between the VSS bonding electrode 18 on the first substrate 10 side and the FD bonding electrode 24 on the second substrate 20 side can be prevented (or alternatively, mitigated).

[0204] Furthermore, according to this modification example, the VSS bonding electrodes 18 and 25 are provided at the ends of the VSS through wirings 16 and 27. Thus, for example, compared with the wiring structure of the imaging device 1 shown in Figure 15 the separation distance from the VSS bonding electrode 25 on the second substrate 20 side is reduced. Therefore, the function as a shield for reducing signal interference between adjacent FD through wirings 15 and 26 can be improved. Thus, compared with the case of adopting the wiring structure shown in Figure 15 noise can be further reduced.

[0205] Modification Example N

[0206] Figure 36 shows a modification example of the cross-sectional structure of the imaging device 1 in the vertical direction, and particularly shows a modification example of the wiring structure at and near the bonding surface between the first substrate 10 and the second substrate 20 opposite the pixel region 13. Although the above Modification Example M refers to an example in which the VSS bonding electrode 18 on the first substrate 10 side has a smaller length, as shown in Figure 36 the VSS bonding electrode 25 on the second substrate 20 side can have a smaller length. Similar to the above Modification Example M, in this case, the function as a shield for reducing signal interference between adjacent FD through wirings 15 and 26 can be improved. Therefore, noise can also be reduced.

[0207] Modification Example O

[0208] Figure 37 shows a modification example of the cross-sectional structure of the imaging device 1 in the vertical direction, and particularly shows a modification example of the wiring structure at and near the bonding surface between the first substrate 10 and the second substrate 20 opposite the pixel region 13. Although the above Modification Example M refers to an example in which the VSS bonding electrodes 18 and 25 are provided at the ends of the VSS through wirings 16 and 27, as shown in Figure 37As shown, wiring layers 78 and 85 can be provided at the end portions of the VSS through wirings 16 and 27 with the through holes v78 and v85 therebetween, respectively. In this case, each wiring layer 78 is electrically connected to the p-well region 41 via the corresponding intermediate through hole v78 and the corresponding VSS through wiring 16. In addition, each wiring layer 85 is electrically connected to the region to which the reference potential VSS is to be applied via the corresponding through hole v85 and the corresponding VSS through wiring 27. In this case, each VSS through wiring 16 and each wiring layer 78 can also function as a shield that reduces signal interference between the adjacent FD through wirings 15 and 26, and each VSS through wiring 27 and each wiring layer 85 can also function as a shield that reduces signal interference between the adjacent FD through wirings 26. In addition, by forming the wiring layers 78 and 85 with a width wider than the width of the VSS bonding electrode 18 described in the modification example M and the like, the function as a shield is further improved. Therefore, for example, compared with the case of adopting the Figure 15 wiring structure shown, the noise can be further reduced.

[0209] Modification Example P

[0210] Figure 38 A modification example of the cross-sectional structure of the imaging device 1 in the vertical direction is shown. In particular, a modification example of the wiring structure at and near the bonding surface of the first substrate 10 and the second substrate 20 opposite to the pixel region 13 is shown. Although the above modification example O refers to an example in which the wiring layers 78 and 85 are provided at the end portions of the VSS through wirings 16 and 27, as Figure 38 shown, a wiring layer can be provided at the end portion of one of the VSS through wirings 16 and 27, and a through hole can be provided at the end portion of the other of the VSS through wirings 16 and 27. For example, as Figure 38 shown, the wiring layer 78 can be provided on the first substrate 10 side, and the through hole v85 can be provided on the second substrate 20 side. In this case, each VSS through wiring 16 can also function as a shield that reduces signal interference between the adjacent FD through wirings 15, and each VSS through wiring 27 can also function as a shield that reduces signal interference between the adjacent FD through wirings 26. Therefore, the noise can be reduced.

[0211] Modification Example Q

[0212] Figure 39FIG. 0 shows a modified example of the cross-sectional structure of the imaging device 1 in the vertical direction. In particular, it shows a modified example of the wiring structure at and near the bonding surface between the first substrate 10 and the second substrate 20 facing the pixel region 13. Through holes v78 and v85 can be provided at the end portions of the VSS through wirings 16 and 27, respectively. In this case, each VSS through wiring 16 can also function as a shield to reduce signal interference between adjacent FD through wirings 15, and each VSS through wiring 27 can also function as a shield to reduce signal interference between adjacent FD through wirings 26. Therefore, noise can be reduced.

[0213] Modified Example R

[0214] Figure 40 FIG. 7 shows a modified example of the cross-sectional structure of the imaging device 1 in the vertical direction. In particular, it shows a modified example of the wiring structure at and near the bonding surface between the first substrate 10 and the second substrate 20 facing the pixel region 13. A VSS bonding electrode can be provided at one of the end portions of the VSS through wiring 16 and the end portion of the VSS through wiring 27, and a through hole can be provided at the other end portion. For example, a VSS bonding electrode 18 can be provided at the end portion on the first substrate 10 side, and a through hole v85 can be provided at the end portion on the second substrate 20 side. In this case, each VSS through wiring 16 can also function as a shield to reduce signal interference between adjacent FD through wirings 15, and each VSS through wiring 27 can also function as a shield to reduce signal interference between adjacent FD through wirings 26. Therefore, noise can be reduced.

[0215] Modified Example S

[0216] Figure 41 FIG. 14 shows a modified example of the sensor pixel 12 and the readout circuit 22. In the above-described modified examples M to R, for example, a reference potential such as VSS or GND can be applied to the VSS through wiring 16 in the first substrate 10, and any other voltage can be applied to the VSS through wiring 27 in the second substrate 20.

[0217] Modified Example T

[0218] Figure 42 FIG. 21 shows a modified example of the sensor pixel 12 and the readout circuit 22. In the above-described modified examples M to R, for example, a reference potential such as VSS or GND can be applied to the VSS through wiring 27 in the second substrate 20, and any other voltage can be applied to the VSS through wiring 16 in the first substrate 10.

[0219] Modified Example U

[0220] Figure 43 shows an example of a sensor pixel and a readout circuit in a case where the bonding surface and the wiring structure in the vicinity thereof shown in Figure 27 are applied to other positions. The above-described modification examples M to T refer to the case where the pixel signal is at the terminal of the floating diffusion portion FD. However, as shown in Figure 43 , the pixel signal may be at the output terminal (e.g., Vsig) of the readout circuit 22.

[0221] Similar to the above-described modification examples M to T, in the case of a structure in which the floating diffusion portion FD is connected between two silicon substrates (between the semiconductor substrate 11 and the semiconductor substrate 21), the capacitance between the terminal of the floating diffusion portion FD and the other terminal may increase, resulting in a decrease in the conversion efficiency of the pixel. In contrast, as in this modification example, when the output terminal of the amplifying transistor AMP is connected between two silicon substrates, the capacitance of the terminal of the floating diffusion portion FD is equal to the capacitance in a typical imaging device. Therefore, a decrease in the conversion efficiency can be prevented (or alternatively, mitigated).

[0222] Modification Example V

[0223] Figures 44 to 50 shows a modification of the cross-sectional structure in the horizontal direction of the FD bonding electrode 17 and the VSS bonding electrode 18 of the imaging device 1 having the wiring structure shown in Figure 27 etc. and a modification of the cross-sectional structure in the horizontal direction of the FD bonding electrode 24 and the VSS bonding electrode 25 of the imaging device 1 having the wiring structure shown in Figure 27 etc. It should be noted that, as an example, as in the case shown in Figure 5 , Figures 44 to 50 shows a case where four sensor pixels 12 share the floating diffusion portion FD.

[0224] For example, as shown in Figure 44 , a plurality of VSS bonding electrodes 18 and 25 may be provided between the FD bonding electrodes 17 and 24 arranged in a row and column manner such that one of the VSS bonding electrodes 18 and 25 is provided in each space between the FD bonding electrodes 17 and 24. In one example, as shown in Figure 45 , in addition to the structure shown in Figure 44 , one of the VSS bonding electrodes 18 and 25 may be provided in each space between the FD bonding electrodes 17 and 24 adjacent to each other in the inclined direction. In another example, as shown in Figure 46As shown, one of the VSS bonding electrodes 18 and 25 can be provided in each space between the FD bonding electrodes 17 and 24 adjacent to each other in the row direction, and the VSS bonding electrodes 18 and 25 continuously arranged in the row direction can be provided in each space between the FD bonding electrodes 17 and 24 adjacent to each other in the column direction. In another example, as Figure 47 shown, one of the VSS bonding electrodes 18 and 25 can be provided in each space between the FD bonding electrodes 17 and 24 adjacent to each other in the column direction, and the VSS bonding electrodes 18 and 25 continuously arranged in the column direction can be provided in each space between the FD bonding electrodes 17 and 24 adjacent to each other in the row direction. In another example, as Figure 48 shown, with respect to the FD bonding electrodes 17 and 24 arranged in a row and column manner, for example, one VSS bonding electrode 18 can be provided in each space between the FD bonding electrodes 17 and 24 on the side of the first substrate 10, and the VSS bonding electrodes 25 continuously arranged in a lattice pattern can be provided on the side of the second substrate 20. In another example, as Figure 49 shown, when one of the VSS bonding electrodes 18 and 25 is provided in each space between the FD bonding electrodes 17 and 24 arranged in a row and column manner, the length of the VSS bonding electrode 25 can be greater than the length of the VSS bonding electrode 18. In another example, as Figure 50 shown, when one of the VSS bonding electrodes 18 and 25 is provided in each space between the FD bonding electrodes 17 and 24 arranged in a row and column manner, the length of the VSS bonding electrode 25 can be less than the length of the VSS bonding electrode 18.

[0225] In Figures 44 to 50 any of the above structures shown, the VSS via wirings 16 and 27 and the VSS bonding electrodes 18 and 25 can also function as shields that reduce signal interference between the adjacent FD via wirings 15 and 26. Therefore, noise can be reduced.

[0226] <3. Application Example>

[0227] Figure 51 An example of the schematic configuration of a camera system 3 provided with the imaging device 1 according to the above-described embodiment and any of its modifications is shown.

[0228] The imaging system 3 is an electronic device including an imaging device such as a digital camera, a video camera, etc., or a mobile terminal device such as a smart phone, a tablet terminal, etc. The imaging system 3 includes, for example, the imaging device 1, the optical system 141, the shutter device 142, the control circuit 143, the DSP circuit 144, the frame memory 145, the display unit 146, the storage unit 147, the operation unit 148, and the power supply unit 149 according to the above-described embodiments and any variations thereof. In the imaging system 3, the imaging device 1, the DSP circuit 144, the frame memory 145, the display unit 146, the storage unit 147, the operation unit 148, and the power supply unit 149 according to the above-described embodiments and any variations thereof are connected to each other via the bus 150.

[0229] The optical system 141 is configured to have one lens or a plurality of lenses, and guides light (incident light) from a subject to the imaging device 1 and forms an image of such light on the light receiving surface of the imaging device 1. The shutter device 142 is provided between the optical system 141 and the imaging device 1 to control the light exposure period and the light shielding period of the imaging device 1 according to the control of the control circuit 143. The imaging device 1 accumulates signal charges within a fixed time period based on the light that forms an image on the light receiving surface through the optical system 141 and the shutter device 142. The signal charges accumulated in the imaging device 1 are transmitted as image data according to a drive signal (timing signal) provided from the control circuit 143. The control circuit 143 outputs a drive signal for controlling the transmission operation of the imaging device 1 and the shutter operation of the shutter device 142 to drive the imaging device 1 and the shutter device 142.

[0230] The DSP circuit 144 is a signal processing circuit that processes the image data to be output from the imaging device 1. The frame memory 145 temporarily stores the image data processed by the DSP circuit 144 frame by frame. The display unit 146 includes, for example, a panel-type display unit such as a liquid crystal panel and an organic EL (Electro Luminescence) panel, and displays a moving image or a still image imaged by the imaging device 1. The storage unit 147 records the image data of the moving image or the still image imaged by the imaging device 1 on a recording medium such as a semiconductor memory, a hard disk, etc. The operation unit 148 issues operation instructions regarding various functions of the imaging system 3 according to the user's operation. The power supply unit 149 appropriately supplies various power supplies serving as the operation power of the imaging device 1, the DSP circuit 144, the frame memory 145, the display unit 146, the storage unit 147, and the operation unit 148 to these supply targets.

[0231] Next, an explanation of the imaging steps in the imaging system 3 is given.

[0232] Figure 52An example of a flowchart of the imaging operation in the imaging system 3 is shown. The user instructs the start of imaging by operating the operation unit 148 (step S101). Thereafter, the operation unit 148 sends an imaging instruction to the control circuit 143 (step S102). Once the imaging instruction is received, the control circuit 143 starts to control the shutter device 142 and the imaging device 1. The imaging device 1 (specifically, the system control circuit 32d) performs imaging by a predetermined imaging method under the control of the control circuit 143 (step S103). The shutter device 142 controls the light exposure period and the light shielding period of the imaging device 1 under the control of the control circuit 143.

[0233] The imaging device 1 outputs the image data obtained by imaging to the DSP circuit 144. Here, the image data refers to data corresponding to the entire pixels of the pixel signal generated based on the charges temporarily stored in the floating diffusion section FD. The DSP circuit 144 performs predetermined signal processing (such as noise reduction processing, etc.) based on the image data input from the imaging device 1 (step S104). The DSP circuit 144 causes the frame memory 145 to store the image data that has undergone the predetermined signal processing, and the frame memory 145 causes the storage section 147 to store the image data (step S105). In this way, the imaging in the imaging system 3 is performed.

[0234] In this application example, the imaging device 1 according to the above-described embodiment and any of its modified examples is applied to the imaging system 3. Therefore, it is possible to reduce the size, expand the dynamic range, and reduce the noise, so that an imaging system 3 with a small size, a wide dynamic range, and high definition can be provided.

[0235] <4. Industrial Application Examples>

[0236] Industrial Application Example 1

[0237] The technology according to the present disclosure is applicable to various products. For example, the technology according to the present disclosure can be implemented as a device mounted on any of the following moving bodies, such as: automobiles, electric vehicles, hybrid vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots, etc.

[0238] Figure 53 is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the embodiments of the present disclosure can be applied.

[0239] The vehicle control system 12000 includes a plurality of electronic control units connected to each other through a communication network 12001. In Figure 53In the example shown, the vehicle control system 12000 includes: a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and a vehicle-mounted network interface (I / F) 12053 are shown.

[0240] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device for the following devices: a driving force generation device such as an internal combustion engine or a drive motor for generating the driving force of the vehicle; a driving force transmission mechanism for transmitting the driving force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating the braking force of the vehicle, etc.

[0241] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 serves as a control device for the following devices: a keyless entry system; a smart key system; an electric window device; or various lights such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, radio waves or signals from various switches sent from a mobile device replacing the key can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door lock device, electric window device, or lights, etc.

[0242] The outside vehicle information detection unit 12030 detects information on the outside of the vehicle including the vehicle control system 12000. For example, the outside vehicle information detection unit 12030 is connected to a camera unit 12031. The outside vehicle information detection unit 12030 causes the camera unit 12031 to capture an image of the outside of the vehicle and receives the captured image. Based on the received image, the outside vehicle information detection unit 12030 can perform detection processing or distance detection processing on objects such as pedestrians, vehicles, obstacles, signs, or letters on the road surface.

[0243] The camera unit 12031 is an optical sensor for receiving light and outputting an electrical signal corresponding to the amount of received light. The camera unit 12031 can output this electrical signal as an image or can output this electrical signal as ranging information. In addition, the light received by the camera unit 12031 can be visible light or non-visible light such as infrared light.

[0244] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting the driver's state. For example, the driver state detection unit 12041 includes a camera for photographing the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or can determine whether the driver is dozing off.

[0245] Based on the information outside or inside the vehicle acquired by the out-vehicle information detection unit 12030 or the in-vehicle information detection unit 12040, the microcomputer 12051 can calculate control target values for the driving force generation device, the steering mechanism, or the braking device, and can output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control for implementing functions of an advanced driver assistance system (ADAS), and the functions of the advanced driver assistance system include: collision avoidance or impact mitigation of the vehicle, following driving based on a following distance, constant-speed driving, vehicle collision warning, or lane departure warning of the vehicle, etc.

[0246] In addition, the microcomputer 12051 can control the driving force generation device, the steering mechanism, or the braking device, etc., based on the information outside or inside the vehicle acquired by the out-vehicle information detection unit 12030 or the in-vehicle information detection unit 12040, so as to perform cooperative control for autonomous driving that enables the vehicle to drive autonomously without relying on the driver's operation.

[0247] In addition, based on the information outside the vehicle acquired by the out-vehicle information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 can control the headlights to switch from high beams to low beams according to the position of the vehicle in front or the oncoming vehicle detected by the out-vehicle information detection unit 12030, so as to perform cooperative control for preventing (or alternatively, reducing) glare.

[0248] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device, and the output device can visually or auditorily notify information to passengers in the vehicle or outside the vehicle. In Figure 53 the example, as the output device, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are shown. For example, the display unit 12062 can include at least one of an on-board display and a head-up display.

[0249] Figure 54 This is a diagram showing an example of the installation position of the imaging unit 12031.

[0250] In Figure 54 the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0251] The imaging units 12101, 12102, 12103, 12104, and 12105 are, for example, arranged at the positions of the front nose, rearview mirror, rear bumper, rear door of the vehicle 12100, and the upper part of the windshield inside the vehicle. The imaging unit 12101 arranged at the front nose and the imaging unit 12105 arranged at the upper part of the windshield inside the vehicle mainly acquire images in front of the vehicle 12100. The imaging units 12102 and 12103 arranged at the rearview mirror mainly acquire images on the sides of the vehicle 12100. The imaging unit 12104 arranged at the rear bumper or rear door mainly acquires images behind the vehicle 12100. The imaging unit 12105 arranged at the upper part of the windshield inside the vehicle is mainly used to detect the vehicle in front, pedestrians, obstacles, traffic lights, traffic signs, or lanes, etc.

[0252] Incidentally, Figure 54 This shows an example of the shooting ranges of the imaging units 12101 to 12104. The shooting range 12111 represents the shooting range of the imaging unit 12101 arranged at the front nose. The shooting ranges 12112 and 12113 represent the shooting ranges of the imaging units 12102 and 12103 arranged at the rearview mirror, respectively. The shooting range 12114 represents the shooting range of the imaging unit 12104 arranged at the rear bumper or rear door. For example, by superimposing the image data imaged by the imaging units 12101 to 12104, an aerial image of the vehicle 12100 seen from above is obtained.

[0253] At least one of the imaging units 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0254] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in the distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and thus extract the following three-dimensional object as the preceding vehicle: Specifically, the three-dimensional object is closest to the vehicle 12100 on the driving road and travels at a predetermined speed (for example, greater than or equal to 0 km / h) in substantially the same direction as the vehicle 12100. In addition, the microcomputer 12051 can preset the following distance to be maintained in front of the preceding vehicle and can perform automatic braking control (including following stop control) or automatic acceleration control (including following start control), etc. Therefore, cooperative control for realizing autonomous driving such as autonomous driving of the vehicle without relying on the driver's operation can be executed.

[0255] For example, the microcomputer 12051 can classify the three-dimensional object data regarding the three-dimensional object into three-dimensional object data of a two-wheeled vehicle, a standard vehicle, a large vehicle, a pedestrian, a utility pole, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies the obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can visually recognize and obstacles that the driver of the vehicle 12100 has difficulty visually recognizing. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle. When the collision risk is equal to or higher than the set value and thus there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver through the audio speaker 12061 or the display unit 12062, and performs forced deceleration or avoidance steering through the drive system control unit 12010. Therefore, the microcomputer 12051 can assist driving to avoid collisions.

[0256] At least one of the imaging units 12101 to 12104 may be an infrared camera for detecting infrared rays. For example, the microcomputer 12051 can identify a pedestrian by determining whether there is a pedestrian in the captured images of the imaging units 12101 to 12104. For example, such pedestrian identification is performed through the following process: extracting feature points in the captured images of the imaging units 12101 to 12104 that are infrared cameras; and determining whether the object is a pedestrian by performing pattern matching processing on a series of feature points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 to display a rectangular contour line for emphasis and superimpose it on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 to display an icon or the like for representing a pedestrian at a desired position.

[0257] As described above, an example of a mobile body control system to which the technology according to an embodiment of the present disclosure can be applied has been described. In the above configuration, the technology according to the present disclosure can be applied to the imaging unit 12301. Specifically, the imaging device 1 according to the above embodiment and any modification thereof can be applied to the imaging unit 12301. By applying the technology according to the present disclosure to the imaging unit 12301, a captured image with high accuracy and reduced noise can be obtained, and thus high-precision control can be performed by using the captured image in the mobile body control system.

[0258] [Industrial Application Example 2]

[0259] Figure 55 FIG. is a diagram showing an example of a schematic configuration of an endoscopic surgical system to which the technology (this technology) according to an embodiment of the present disclosure can be applied.

[0260] In Figure 55 it shows a state in which a surgeon (doctor) 11131 uses an endoscopic surgical system 11000 to perform surgery on a patient 11132 on a hospital bed 11133. As shown in the figure, the endoscopic surgical system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy treatment tool 11112, a support arm device 11120 for supporting the endoscope 11100 thereon, and a cart 11200 on which various devices for endoscopic surgery are installed.

[0261] The endoscope 11100 includes: a lens barrel 11101 having a region of a predetermined length starting from the distal end of the lens barrel 11101 to be inserted into the body cavity of a patient 11132; and a camera 11102 connected to the proximal end of the lens barrel 11101. In the illustrated example, an endoscope 11100 of a rigid scope configured to have a rigid lens barrel 11101 is shown. However, the endoscope 11100 may also be configured as a flexible scope having a flexible lens barrel 11101.

[0262] An opening for mounting an objective lens is provided at the distal end of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100 such that light generated by the light source device 11203 is guided to the distal end of the lens barrel 11101 through an optical fiber extending within the lens barrel 11101, and the light is irradiated onto an observation target in the body cavity of the patient 11132 via the above-described objective lens. It should be noted that the endoscope 11100 may be a direct view mirror, or may be a perspective view mirror or a side view mirror.

[0263] An optical system and an imaging element are provided within the camera 11102 such that reflected light (observation light) from the observation target is converged onto the imaging element through the optical system. The observation light is subjected to photoelectric conversion by the imaging element, and an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image, is generated. This image signal is sent as raw data to a CCU (camera control unit) 11201.

[0264] The CCU 11201 includes a central processing unit (CPU) or a graphics processing unit (GPU), etc., and the CCU 11201 controls the operations of the endoscope 11100 and the display device 11202 as a whole. In addition, the CCU 11201 receives the image signal from the camera 11102, and performs various image processing operations on the image signal, such as imaging processing (demosaicing processing), etc., for displaying an image based on the image signal.

[0265] Under the control of the CCU 11201, the display device 11202 displays an image based on the image signal (image processing has been performed on the image signal by the CCU 11201).

[0266] For example, the light source device 11203 includes a light source such as a light emitting diode (LED), and provides illumination light for imaging the surgical site to the endoscope 11100.

[0267] The input device 11204 is an input interface of the endoscopic surgery system 11000. A user can input various information or instructions into the endoscopic surgery system 11000 through the input device 11204. For example, the user will input instructions or the like for changing the imaging conditions (type of illumination light, magnification, focal length, etc.) of the endoscope 11100.

[0268] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing or cutting tissue, or sealing blood vessels, etc. The pneumoperitoneum device 11206 sends gas into the body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to expand the body cavity, thereby ensuring the field of view of the endoscope 11100 and ensuring the working space for the surgeon. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various forms such as text, image, or chart.

[0269] It should be noted that the light source device 11203 that provides illumination light for imaging the surgical site to the endoscope 11100 may include a white light source, which includes, for example, an LED, a laser light source, or a combination of an LED and a laser light source. In the case where the white light source includes a combination of red, green, and blue (RGB) laser light sources, since the output intensity and output timing of each color (each wavelength) can be controlled with high precision, the white balance of the captured image can be adjusted by the light source device 11203. In addition, in this case, if the observation object is irradiated with laser beams from each of the RGB laser light sources in a time-division manner and the driving of the imaging element of the camera 11102 is controlled in synchronization with the irradiation timing, images corresponding to the R, G, and B colors can also be captured in a time-division manner. According to this method, a color image can be obtained even if a color filter is not provided in the imaging element.

[0270] In addition, the light source device 11203 can be controlled to change the light intensity to be output every predetermined time. By controlling the driving of the imaging element of the camera 11102 in a time-division manner to obtain images synchronously with the moment of the light intensity change and then synthesizing these images, a high-dynamic-range image without underexposed blocked up shadows and overexposed highlights can be generated.

[0271] In addition, the light source device 11203 can be configured to provide light in a predetermined wavelength band prepared for special light observation. In special light observation, for example, by utilizing the wavelength dependence of light absorption in human tissue, light in a narrower band than the illumination light (i.e., white light) during normal observation is irradiated, and narrow-band observation (narrow-band imaging) for imaging a predetermined tissue such as blood vessels in the mucosal surface layer is performed with high contrast. Alternatively, in special light observation, fluorescence observation for obtaining an image by irradiating fluorescence generated by irradiating excitation light can be performed. In fluorescence observation, fluorescence from the human tissue can be observed by irradiating the human tissue with excitation light (autofluorescence observation), or a fluorescence image can be obtained by locally injecting a reagent such as indocyanine green (ICG) into the human tissue and irradiating the human tissue with excitation light corresponding to the fluorescence wavelength of the reagent. As described above, the light source device 11203 can be configured to provide such narrow-band light and / or excitation light suitable for special light observation.

[0272] Figure 56 is a diagram showing Figure 55 an example of the functional configuration of the illustrated camera 11102 and CCU 11201.

[0273] The camera 11102 includes a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera 11102 and the CCU 11201 are communicably connected to each other via a transmission cable 11400.

[0274] The lens unit 11401 is an optical system provided at a position connected to the lens barrel 11101. The observation light obtained from the distal end of the lens barrel 11101 is guided to the camera 11102 and enters the lens unit 11401. The lens unit 11401 includes a combination of a plurality of lenses (including a zoom lens and a focusing lens).

[0275] The number of imaging elements included in the imaging unit 11402 may be one (single-board type) or more (multi-board type). For example, when the imaging unit 11402 is configured as a multi-board type, image signals corresponding to R, G, and B are generated by respective imaging elements, and these image signals can be synthesized to obtain a color image. The imaging unit 11402 may also be configured to have a pair of imaging elements for respectively acquiring a right-eye image signal and a left-eye image signal for three-dimensional (3D) display. If 3D display is performed, the surgeon 11131 can more accurately grasp the depth of the biological tissue at the surgical site. It should be noted that when the imaging unit 11402 is configured as a stereo type, a plurality of lens unit 11401 systems are provided corresponding to the respective imaging elements.

[0276] In addition, the imaging unit 11402 does not have to be provided on the camera 11102. For example, the imaging unit 11402 may be provided within the lens barrel 11101 and immediately behind the objective lens.

[0277] The drive unit 11403 includes an actuator, and under the control of the camera control unit 11405, the drive unit 11403 moves the zoom lens and the focus lens of the lens unit 11401 along the optical axis by a predetermined distance. Thus, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0278] The communication unit 11404 includes a communication device for sending various information to the CCU 11201 and receiving various information from the CCU 11201. The communication unit 11404 sends the image signal obtained from the imaging unit 11402 as raw data to the CCU 11201 via the transmission cable 11400.

[0279] In addition, the communication unit 11404 receives a control signal for controlling the drive of the camera 11102 from the CCU 11201 and provides the control signal to the camera control unit 11405. For example, the above control signal includes information related to imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value during imaging, and / or information specifying the magnification and focus of the captured image.

[0280] It should be noted that imaging conditions such as the frame rate, exposure value, magnification, or focus as described above may be specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, an auto exposure (AE) function, an auto focus (AF) function, and an auto white balance (AWB) function are incorporated in the endoscope 11100.

[0281] The camera control unit 11405 controls the driving of the camera 11102 based on the control signal received from the CCU 11201 through the communication unit 11404.

[0282] The communication unit 11411 includes a communication device for sending various information to the camera 11102 and receiving various information from the camera 11102. The communication unit 11411 receives the image signal transmitted from the camera 11102 through the transmission cable 11400.

[0283] In addition, the communication unit 11411 sends a control signal for controlling the driving of the camera 11102 to the camera 11102. The above-mentioned image signal and the above-mentioned control signal can be transmitted through electrical communication, optical communication, etc.

[0284] The image processing unit 11412 performs various image processing operations on the image signal in the form of raw data transmitted from the camera 11102.

[0285] The control unit 11413 executes various controls related to photographing a surgical site or the like through the endoscope 11100 and displaying the captured image obtained by photographing the surgical site or the like. For example, the control unit 11413 generates a control signal for controlling the driving of the camera 11102.

[0286] In addition, based on the image signal that has been subjected to image processing by the image processing unit 11412, the control unit 11413 controls the display device 11202 to display the captured image of the surgical site or the like. Thus, the control unit 11413 can use various image recognition technologies to recognize various objects in the captured image. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, haze when using the energy treatment tool 11112, etc. by detecting the shape, color, etc. of the edges of the objects included in the captured image. When the control unit 11413 controls the display device 11202 to display the captured image, the control unit 11413 can use the recognition result to display various surgical assistance information in a manner superimposed on the image of the surgical site. In the case where the surgical assistance information is displayed in a superimposed manner and presented to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can perform the surgery reliably.

[0287] The transmission cable 11400 connecting the camera 11102 and the CCU 11201 is an electrical signal cable prepared for electrical signal communication, an optical fiber prepared for optical communication, or a composite cable prepared for both electrical communication and optical communication.

[0288] Although, here, in the illustrated example, the communication is performed in a wired communication manner using the transmission cable 11400, the communication between the camera 11102 and the CCU 11201 may also be performed in a wireless communication manner.

[0289] As described above, an example of an endoscopic surgical system to which the technology according to an embodiment of the present disclosure can be applied has been given. In the above configuration, the technology according to the present disclosure can be preferably applied to the imaging unit 11402 provided on the camera 11102 of the endoscope 11100. By applying the technology according to the present disclosure to the imaging unit 11402, the size of the imaging unit 11402 can be reduced or it can have high precision, so that an endoscope 11100 with a reduced size or an endoscope 11100 with high precision can be provided.

[0290] So far, the present disclosure has been described with reference to the embodiments, their variations, application examples, and industrial application examples; however, the present disclosure is not limited to the above embodiments and the like, but various modifications can be made. It should be noted that the effects described herein are merely exemplary. The effects of the present disclosure are not limited to the effects described herein. The present disclosure can have any effects other than the effects described herein.

[0291] In addition, for example, the present disclosure can be configured as follows. (1)

[0293] An imaging device, comprising:

[0294] A first substrate having a pixel region including a plurality of sensor pixels for performing photoelectric conversion;

[0295] A second substrate having a plurality of readout circuits provided individually for each of a single sensor pixel or a plurality of sensor pixels to output a pixel signal based on the charge output from the sensor pixel; and

[0296] A third substrate having a control circuit for controlling the sensor pixel and the readout circuit, wherein,

[0297] The first substrate, the second substrate, and the third substrate are stacked in this order,

[0298] The laminate including the first substrate and the second substrate has an interlayer insulating film and a plurality of first bonding electrodes provided in a region of the interlayer insulating film opposite to the pixel region, and,

[0299] The sensor pixel and the readout circuit are electrically connected to each other by bonding of the first bonding electrodes. (2)

[0301] The imaging device according to (1), wherein,

[0302] The laminate has a plurality of first through wirings in a region surrounding the pixel region, and

[0303] The control circuit controls the sensor pixels and the readout circuit through the plurality of first through wirings. (3)

[0305] The imaging device according to one or more of (1) to (2), wherein,

[0306] The laminate has a plurality of second through wirings in a region located in the interlayer insulating film and opposite to the pixel region, the plurality of second through wirings are provided one by one for each of the readout circuits, and

[0307] Each of the second through wirings is electrically connected to a region maintained at a reference potential in at least one of the first substrate or the second substrate. (4)

[0309] The imaging device according to one or more of (1) to (3), wherein,

[0310] The laminate has a plurality of third through wirings in a region located in the interlayer insulating film and opposite to the pixel region, the plurality of third through wirings are electrically connected to corresponding ones of the first bonding electrodes, and

[0311] Each of the second through wirings is provided at an interval between two adjacent third through wirings among the plurality of third through wirings. (5)

[0313] The imaging device according to one or more of (1) to (4), wherein,

[0314] The laminate has wiring electrodes in the interlayer insulating film, the wiring electrodes are electrically connected to each of the second through wirings, and,

[0315] The wiring electrodes are arranged in a lattice pattern surrounding each of the first bonding electrodes. (6)

[0317] The imaging device according to one or more of (1) to (5), wherein the wiring electrodes are arranged in a lattice pattern in the same plane such that a plurality of first bonding wirings extending in a first array direction of the plurality of sensor pixels and a plurality of second bonding wirings extending in a second array direction of the plurality of sensor pixels intersect each other. (7)

[0319] The imaging device according to one or more of (1) to (6), wherein the wiring electrodes are arranged in a lattice pattern in the same plane such that a plurality of first bonding wirings extending in a first direction intersecting the arrangement direction of the plurality of sensor pixels and a plurality of second bonding wirings extending in a second direction intersecting the arrangement direction of the plurality of sensor pixels and also intersecting the first direction intersect each other. (8)

[0321] The imaging device according to one or more of (1) to (7), wherein

[0322] the laminate has a plurality of second bonding electrodes in the interlayer insulating film, the plurality of second bonding electrodes being electrically connected to respective ones of the plurality of second through wirings, and

[0323] each of the plurality of second bonding electrodes is provided at an interval between two adjacent first bonding electrodes among the plurality of first bonding electrodes. (9)

[0325] The imaging device according to one or more of (1) to (8), wherein each of the readout circuits includes a negative feedback circuit having an operational amplifier. (10)

[0327] The imaging device according to one or more of (1) to (9), wherein the reference potential of the first substrate is lower than the reference potential of the second substrate. (11)

[0329] The imaging device according to one or more of (1) to (10), wherein

[0330] the laminate has a plurality of fourth through wirings in a region surrounding the pixel region,

[0331] the third substrate has a negative booster circuit, and

[0332] the negative booster circuit makes the reference potential of the first substrate lower than the reference potential of the second substrate by controlling the reference potential of the first substrate via the plurality of fourth through wirings. (12)

[0334] The imaging device according to one or more of (1) to (11), wherein

[0335] The laminate has a plurality of wiring electrodes in the interlayer insulating film. The wiring electrodes are electrically connected to respective second through wirings, and are arranged at a pitch between two adjacent first bonding electrodes among the plurality of first bonding electrodes, and

[0336] the first bonding electrodes and the wiring electrodes have two or more shapes. (13)

[0338] The imaging device according to one or more of (1) to (12), wherein part or all of the first bonding electrodes and the wiring electrodes have two different shapes from each other. (14)

[0340] The imaging device according to one or more of (1) to (13), wherein

[0341] the length of part or all of the wiring electrodes is less than the length of the first bonding electrodes, and

[0342] the wiring electrodes provided on the first substrate side and the wiring electrodes provided on the second substrate side face each other with the interlayer insulating film provided therebetween. (15)

[0344] The imaging device according to one or more of (1) to (14), wherein

[0345] the length, width, or both the length and width of the wiring electrodes provided on the first substrate side and the wiring electrodes provided on the second substrate side are different from each other, and

[0346] the wiring electrodes provided on the first substrate side and the wiring electrodes provided on the second substrate side face each other with the interlayer insulating film provided therebetween. (16)

[0348] The imaging device according to one or more of (1) to (15), wherein the wiring electrodes on one of the first substrate side and the second substrate side are exposed on the bonding surface of the first substrate and the second substrate, and the wiring electrodes on the other of the first substrate side and the second substrate side are formed in the interlayer insulating film. (17)

[0350] An imaging device, comprising:

[0351] a first substrate having a pixel region including a plurality of sensor pixels that perform photoelectric conversion; and

[0352] A second substrate having a plurality of readout circuits and control circuits, the plurality of readout circuits being provided for each of a single sensor pixel or a plurality of sensor pixels one by one to output pixel signals based on charges output from the sensor pixels, the control circuit controlling the sensor pixels and the readout circuits, wherein,

[0353] The first substrate and the second substrate are stacked on top of each other,

[0354] The laminate including the first substrate and the second substrate has an interlayer insulating film and a plurality of first bonding electrodes, the plurality of first bonding electrodes being provided in a region located in the interlayer insulating film and opposite to the pixel region, and,

[0355] The sensor pixels and the readout circuits are electrically connected to each other by bonding of the first bonding electrodes. (18)

[0357] The imaging device according to (17), wherein,

[0358] The laminate has a plurality of first through wirings in a region surrounding the pixel region, and

[0359] The control circuit controls the sensor pixels through the plurality of first through wirings. (19)

[0361] The imaging device according to one or more of (17) to (18), wherein,

[0362] The laminate has a plurality of second through wirings in a region located in the interlayer insulating film and opposite to the pixel region, the plurality of second through wirings being provided for each of the readout circuits one by one, and

[0363] Each of the second through wirings is electrically connected to a region maintained at a reference potential in at least one of the first substrate or the second substrate. (20)

[0365] The imaging device according to one or more of (17) to (19), wherein,

[0366] The laminate has a plurality of third through wirings in a region located in the interlayer insulating film and opposite to the pixel region, the plurality of third through wirings being electrically connected to corresponding ones of the first bonding electrodes, and

[0367] Each of the second through wirings is provided at an interval between two adjacent ones of the plurality of third through wirings. (21)

[0369] The imaging device according to one or more of (17) to (20), wherein,

[0370] The laminate has wiring electrodes in the interlayer insulating film, and the wiring electrodes are electrically connected to respective ones of the second through wirings, and,

[0371] The wiring electrodes are arranged in a lattice pattern surrounding each of the first bonding electrodes. (22)

[0373] The imaging device according to one or more of (17) to (21), wherein the wiring electrodes are arranged in a lattice pattern in the same plane such that a plurality of first bonding wirings extending in a first array direction of the plurality of sensor pixels and a plurality of second bonding wirings extending in a second array direction of the plurality of sensor pixels intersect each other. (23)

[0375] The imaging device according to one or more of (17) to (22), wherein the wiring electrodes are arranged in a lattice pattern in the same plane such that a plurality of first bonding wirings extending in a first direction intersecting the arrangement direction of the plurality of sensor pixels and a plurality of second bonding wirings extending in a second direction intersecting the arrangement direction of the plurality of sensor pixels and also intersecting the first direction intersect each other. (24)

[0377] The imaging device according to one or more of (17) to (23), wherein,

[0378] The laminate has a plurality of second bonding electrodes in the interlayer insulating film, and the plurality of second bonding electrodes are electrically connected to respective ones of the plurality of second through wirings, and

[0379] Each of the plurality of second bonding electrodes is provided at an interval between two adjacent first bonding electrodes among the plurality of first bonding electrodes. (25)

[0381] An imaging device, comprising:

[0382] A first part and a second part, the first part comprising:

[0383] A first semiconductor substrate;

[0384] At least one first photoelectric conversion region provided in the first semiconductor substrate;

[0385] A first floating diffusion portion connected to the at least one first photoelectric conversion region;

[0386] A first bonding portion;

[0387] A first wiring that is electrically connected between the first floating diffusion portion and the first joint portion;

[0388] At least one second photoelectric conversion region provided in the first semiconductor substrate;

[0389] A second floating diffusion portion connected to the at least one second photoelectric conversion region;

[0390] A second joint portion;

[0391] A second wiring that is electrically connected between the second floating diffusion portion and the second joint portion;

[0392] A first region connected to a node for receiving a reference voltage; and

[0393] A third wiring connected to the first region and extending in the same direction as the first wiring and the second wiring at a position between the first wiring and the second wiring;

[0394] The second portion is joined to the first portion via the first joint portion and the second joint portion, and the second portion includes a readout circuit connected to the first joint portion and the second joint portion. (26)

[0396] The imaging device according to (25), wherein the first portion further includes:

[0397] A first transfer transistor for transferring charge from the first photoelectric conversion region to the first floating diffusion portion; and

[0398] A second transfer transistor for transferring charge from the second photoelectric conversion region to the second floating diffusion portion. (27)

[0400] The imaging device according to one or more of (25) to (26), wherein the readout circuit includes:

[0401] A first reset transistor, a first amplification transistor, and a first selection transistor electrically connected to the first joint portion; and

[0402] A second reset transistor, a second amplification transistor, and a second selection transistor electrically connected to the second joint portion. (28)

[0404] The imaging device according to one or more of (25) to (27), wherein the readout circuit includes:

[0405] A first reset transistor and a first negative feedback circuit, electrically connected to the first joint; and

[0406] A second reset transistor and a second negative feedback circuit, electrically connected to the second joint. (29)

[0408] The imaging device according to one or more of (25) to (28), wherein each of the first negative feedback circuit and the second negative feedback circuit includes an operational amplifier and a feedback capacitor. (30)

[0410] The imaging device according to one or more of (25) to (29), wherein the first portion further includes:

[0411] At least one insulating layer on the first semiconductor substrate, wherein the at least one insulating layer includes the first wiring, the second wiring, and the third wiring. (31)

[0413] The imaging device according to one or more of (25) to (30), wherein the at least one insulating layer includes a first insulating layer and a second insulating layer, the second insulating layer is closer to the second portion than the first insulating layer, and has a lower dielectric constant than the first insulating layer. (32)

[0415] The imaging device according to one or more of (25) to (31), wherein the first portion further includes:

[0416] A third joint, wherein the third wiring electrically connects the first region to the third joint, and wherein the first portion and the second portion are joined via the first joint, the second joint, and the third joint. (33)

[0418] The imaging device according to one or more of (25) to (32), wherein the at least one insulating layer includes a third insulating layer, the third insulating layer is on the second insulating layer and has a lower dielectric constant than the first insulating layer. (34)

[0420] The imaging device according to one or more of (25) to (33), wherein the second portion further includes:

[0421] A third joint, the third joint being joined to the first joint; and

[0422] A fourth joint, the fourth joint being joined to the second joint. (35)

[0424] The imaging device according to one or more of (25) to (34), wherein the second part further includes:

[0425] A fourth wiring line that electrically connects the third joint to the readout circuit; and

[0426] A fifth wiring line that electrically connects the fourth joint to the readout circuit. (36)

[0428] The imaging device according to one or more of (25) to (35), wherein the second part further includes:

[0429] A sixth wiring line that is electrically connected to the readout circuit located between the fourth wiring line and the fifth wiring line. (37)

[0431] The imaging device according to one or more of (25) to (37), wherein the sixth wiring line is aligned with the first wiring line. (38)

[0433] The imaging device according to one or more of (25) to (37), wherein the first part further includes a fifth joint, and wherein the second part further includes a sixth joint that engages with the fifth joint. (39)

[0435] The imaging device according to one or more of (25) to (38), wherein the second part further includes:

[0436] A second semiconductor substrate that includes the readout circuit; and

[0437] An insulating layer on the second semiconductor substrate, the insulating layer including the fourth wiring line, the fifth wiring line, and the sixth wiring line. (40)

[0439] The imaging device according to one or more of (25) to (39), further including a third part that is joined to the second part, and the third part includes a processing circuit that processes signals from the readout circuit. (41)

[0441] An imaging device, comprising:

[0442] A first part, the first part including:

[0443] A first semiconductor substrate, the first semiconductor substrate including:

[0444] at least one first photoelectric conversion region;

[0445] a first floating diffusion portion connected to the at least one first photoelectric conversion region;

[0446] a first transfer transistor configured to transfer charges from the at least one first photoelectric conversion region to the first floating diffusion portion;

[0447] at least one second photoelectric conversion region disposed in the first semiconductor substrate;

[0448] a second floating diffusion portion connected to the at least one second photoelectric conversion region; and

[0449] a second transfer transistor configured to transfer charges from the at least one second photoelectric conversion region to the second floating diffusion portion; and

[0450] a well region; and

[0451] at least one first insulating layer on the first semiconductor substrate, the at least one first insulating layer including:

[0452] a first bonding portion;

[0453] a first wiring electrically connected between the first floating diffusion portion and the first bonding portion;

[0454] a second bonding portion;

[0455] a second wiring electrically connected between the second floating diffusion portion and the second bonding portion; and

[0456] a third wiring electrically connected to the well region and providing shielding between the first wiring and the second wiring. (42)

[0458] The imaging device according to one or more of (41), further comprising:

[0459] a second portion joined to the first portion via the first bonding portion and the second bonding portion, and the second portion including a readout circuit connected to the first bonding portion and the second bonding portion; and

[0460] a third portion joined to the second portion, and the third portion including a processing circuit configured to process signals from the readout circuit. (43)

[0462] An imaging device, comprising:

[0463] a first portion, the first portion including:

[0464] A first photoelectric conversion region that shares a first floating diffusion section;

[0465] A first junction;

[0466] A first wiring that electrically connects the first floating diffusion section and the first junction;

[0467] A second photoelectric conversion region that shares a second floating diffusion section;

[0468] A second junction;

[0469] A second wiring that electrically connects the second floating diffusion section and the second junction;

[0470] A well region of a required conductivity type;

[0471] A third wiring that is electrically connected to the well region and provides signal shielding between the first wiring and the second wiring; and

[0472] A second part that is joined to the first part via the first junction and the second junction, and the second part includes a readout circuit electrically connected to the first junction and the second junction. (44)

[0474] The imaging device according to (43), further comprising:

[0475] A third part that is joined to the second part, and the third part includes a processing circuit that processes signals from the readout circuit.

[0476] In the imaging device according to an embodiment of the present disclosure, a plurality of sensor pixels are provided on a first substrate; a plurality of readout circuits are provided on a second substrate; and a control circuit is provided on a third substrate, so that the dynamic range can be further expanded and the noise can be further reduced.

[0477] Those skilled in the art should understand that various modifications, combinations, sub - combinations, and changes can be made according to design requirements and other factors, as long as they are within the scope of the appended claims or their equivalents.

[0478] List of reference numerals

[0479] 1, 2 Imaging device

[0480] 3 Imaging system

[0481] 10 First substrate

[0482] 11 Semiconductor substrate

[0483] 12 Sensor pixel

[0484] 13 Pixel region

[0485] 14 Driving wiring

[0486] 15 FD through-wiring

[0487] 16 VSS through-wiring

[0488] 17 FD bonding electrode

[0489] 18, 18a VSS bonding electrode

[0490] 18b Wiring

[0491] 19 Insulating film

[0492] 20 Second substrate

[0493] 21 Semiconductor substrate

[0494] 22 Readout circuit

[0495] 23 Readout circuit region

[0496] 24 FD bonding electrode

[0497] 25, 25a VSS bonding electrode

[0498] 25b Wiring

[0499] 26 FD through-wiring

[0500] 27 VSS through-wiring

[0501] 28 Insulating layer

[0502] 30 Third substrate

[0503] 31 Semiconductor substrate

[0504] 32 Logic circuit

[0505] 32a Vertical driving circuit

[0506] 32b Column signal processing circuit

[0507] 32c Horizontal driving circuit

[0508] 32d System control circuit

[0509] 33 Boosting circuit

[0510] 34 Negative boosting circuit

[0511] 36 Insulating layer

[0512] 40 Color filter layer

[0513] 41 p-well region

[0514] 42 via wiring

[0515] 43 via wiring

[0516] 44 via wiring

[0517] 45,46 via wiring

[0518] 45a,46a,47a openings

[0519] 45b,46b,47b connection pads

[0520] 45c,46c,47c via wiring

[0521] 45d,46d,47d connection pads

[0522] 50 optical receiving lens

[0523] 51,61 gate insulating film

[0524] 52,62 gate electrodes

[0525] 53,63 sidewall layers

[0526] 54,64 silicon oxide film

[0527] 55,65 silicon nitride film

[0528] 56,66 insulating film

[0529] 57,58,67,68 via wiring

[0530] 69 impurity diffusion region

[0531] 71,72,73,74 insulating layers

[0532] 80 second substrate

[0533] AMP amplifier transistor

[0534] Cf feedback capacitor

[0535] Cfd capacitance

[0536] FD floating diffusion section

[0537] PD,PD1,PD2,PD3,PD4,PD5,PD6,PD7,PD8 photodiodes

[0538] RST reset transistor

[0539] SEL selection transistor

[0540] TR, TR1, TR2, TR3, TR4, TR5, TR6, TR7, TR8 transmission transistors

[0541] VDD power supply potential

[0542] VSS, VSS1, VSS2 reference potential

[0543] VSL vertical signal line.

Claims

1. An imaging device, comprising: The first part and the second part, the first part comprising: A first semiconductor substrate; At least one first photoelectric conversion region, which is provided in the first semiconductor substrate; A first floating diffusion portion, which is connected to the at least one first photoelectric conversion region; A first bonding portion; A first wiring, which is electrically connected between the first floating diffusion portion and the first bonding portion; At least one second photoelectric conversion region, which is provided in the first semiconductor substrate; A second floating diffusion portion, which is connected to the at least one second photoelectric conversion region; A second bonding portion; A second wiring, which is electrically connected between the second floating diffusion portion and the second bonding portion; A first region, which is connected to a node for receiving a reference voltage; A third wiring, which is connected to the first region and extends in the same direction as the first wiring and the second wiring at a position between the first wiring and the second wiring; and A third bonding portion, the third bonding portion being electrically connected to the third wiring, and the third bonding portion being provided in a lattice pattern surrounding the first bonding portion or the second bonding portion, The second part is joined to the first part via the first bonding portion and the second bonding portion, and the second part includes a readout circuit connected to the first bonding portion and the second bonding portion.

2. The imaging device according to claim 1, wherein, The first part further includes: A first transfer transistor for transferring charge from the first photoelectric conversion region to the first floating diffusion portion; and A second transfer transistor for transferring charge from the second photoelectric conversion region to the second floating diffusion portion.

3. The imaging device according to claim 2, wherein, The readout circuit includes: A first reset transistor, a first amplification transistor, and a first selection transistor, which are electrically connected to the first bonding portion; and A second reset transistor, a second amplification transistor, and a second selection transistor, which are electrically connected to the second bonding portion.

4. The imaging device according to claim 2, wherein, The readout circuit includes: A first reset transistor and a first negative feedback circuit, which are electrically connected to the first bonding portion; and A second reset transistor and a second negative feedback circuit, which are electrically connected to the second bonding portion.

5. The imaging device according to claim 4, wherein, The first negative feedback circuit and the second negative feedback circuit each include an operational amplifier and a feedback capacitor.

6. The imaging device according to any one of claims 1 to 5, wherein, The first part further includes: At least one insulating layer on the first semiconductor substrate, wherein the at least one insulating layer includes the first wiring, the second wiring, and the third wiring.

7. The imaging device according to claim 6, wherein, The at least one insulating layer includes a first insulating layer and a second insulating layer, the second insulating layer being closer to the second part than the first insulating layer and having a lower dielectric constant than the first insulating layer.

8. The imaging device according to claim 7, wherein, The first part and the second part are joined via the first bonding portion, the second bonding portion, and the third bonding portion.

9. The imaging device according to claim 7, wherein, The at least one insulating layer includes a third insulating layer, the third insulating layer being on the second insulating layer and having a lower dielectric constant than the first insulating layer.

10. The imaging device according to any one of claims 1 to 5, wherein, The second part further includes: A fourth bonding portion, the fourth bonding portion being joined to the first bonding portion; and A fifth bonding portion, the fifth bonding portion being joined to the second bonding portion.

11. The imaging device according to claim 10, wherein, The second part further includes: A fourth wiring that electrically connects the fourth joint portion to the readout circuit; and A fifth wiring that electrically connects the fifth joint portion to the readout circuit.

12. The imaging device according to claim 11, wherein, The second portion further includes: A sixth wiring that is electrically connected to the readout circuit located between the fourth wiring and the fifth wiring.

13. The imaging device according to claim 12, wherein, The sixth wiring is aligned with the first wiring.

14. The imaging device according to claim 12, wherein, The first portion further includes a fifth joint portion, and wherein the second portion further includes a sixth joint portion that engages with the fifth joint portion.

15. The imaging device according to claim 12, wherein, The second portion further includes: A second semiconductor substrate that includes the readout circuit; and An insulating layer on the second semiconductor substrate, the insulating layer including the fourth wiring, the fifth wiring, and the sixth wiring.

16. The imaging device according to any one of claims 1 to 5, further comprising: A third portion that is joined to the second portion, and the third portion includes a processing circuit that processes signals from the readout circuit.

17. An imaging device, comprising: A first portion, the first portion including: A first semiconductor substrate, the first semiconductor substrate including: At least one first photoelectric conversion region; A first floating diffusion portion that is connected to the at least one first photoelectric conversion region; A first transfer transistor that transfers charge from the at least one first photoelectric conversion region to the first floating diffusion portion; At least one second photoelectric conversion region that is provided in the first semiconductor substrate; A second floating diffusion portion that is connected to the at least one second photoelectric conversion region; and A second transfer transistor that transfers charge from the at least one second photoelectric conversion region to the second floating diffusion portion; and A well region; and At least one first insulating layer on the first semiconductor substrate, and the at least one first insulating layer includes: A first joint portion; A first wiring that is electrically connected between the first floating diffusion portion and the first joint portion; A second joint portion; A second wiring that is electrically connected between the second floating diffusion portion and the second joint portion; A third wiring that is electrically connected to the well region and provides shielding between the first wiring and the second wiring; and A third joint portion that is electrically connected to the third wiring, and the third joint portion is provided in a lattice pattern surrounding the first joint portion or the second joint portion; and A second portion that is joined to the first portion via the first joint portion and the second joint portion, and the second portion includes a readout circuit that is connected to the first joint portion and the second joint portion.

18. The imaging device according to claim 17, further comprising: A third portion that is joined to the second portion, and the third portion includes a processing circuit that processes signals from the readout circuit.

19. An imaging device, comprising: A first portion, the first portion including: A first photoelectric conversion region that shares a first floating diffusion portion; A first joint portion; A first wiring that electrically connects the first floating diffusion portion and the first joint portion; A second photoelectric conversion region that shares a second floating diffusion portion; A second joint portion; A second wiring that electrically connects the second floating diffusion portion and the second joint portion; A well region of a required conductivity type; A third wiring electrically connected to the well region, and the third wiring provides signal shielding between the first wiring and the second wiring; and A third joint electrically connected to the third wiring, and the third joint is disposed in a lattice pattern surrounding the first joint or the second joint; and A second portion joined to the first portion via the first joint and the second joint, and the second portion includes a readout circuit electrically connected to the first joint and the second joint.

20. The imaging device according to claim 19, further comprising: A third portion joined to the second portion, and the third portion includes a processing circuit that processes signals from the readout circuit.

Images