Semiconductor package

Abstract

A semiconductor device is disclosed. The semiconductor device includes a redistribution structure, a processor chip, and metal pillars. The redistribution structure includes a connection structure comprising conductive units, solder bumps, a first insulating layer, a second insulating layer, a third insulating layer, a plurality of first through-holes, and a plurality of second through-holes. The metal pillars have a first end and a second end. The first end of the metal pillar is connected to the redistribution structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and more particularly to a wafer-level chip scale package (WLCSP). Background Technology

[0002] In the semiconductor industry, the integration density within chips (dies) is growing rapidly. Chips contain a large number of active and passive electronic components, thus enabling the execution of various functions. These electronic components are fabricated on silicon wafers using semiconductor processes. After the electronic components are fabricated, the wafer can be separated into multiple chips. Each chip is then packaged, forming a protective package around the chip. The chip package also serves as the interface between the chip and a printed circuit board. Common applications of integrated circuits include mobile phone systems, television systems, personal computer systems, and network systems.

[0003] Various package types have been developed, such as dual in-line package (DIP), quad flat package (QFP), ball grid array (BGA), and wafer-level chip-scale package (WLCSP). DIPs have connection pins on two parallel sides. DIPs are typically mounted using through-holes or sockets for placement on printed circuit boards. DIPs typically consist of insulating material filling a metal lead frame.

[0004] QFPs typically have winged leads extending from the perimeter of the package. QFP contacts can only be located in the peripheral area of ​​the package, thus limiting the number of pins. BGAs can use the entire surface to form a contact array, allowing for a higher ball count. The shorter length between the contact array and the chip is advantageous for high-speed signal transmission. WLCSPs have package dimensions almost equal to chip dimensions. WLCSPs are typically smaller than BGA packages. However, existing WLCSPs have poor structural shape, resulting in poor signal integrity and structural stability. Therefore, the industry urgently needs new WLCSPs to achieve better signal integrity and structural stability. Summary of the Invention

[0005] After observing the aforementioned technical problems, the inventors proposed this invention to solve one or more of the aforementioned technical problems.

[0006] One object of the present invention is to provide a semiconductor device whose redistribution structure has a special connection structure, which can achieve better signal integrity and structural stability.

[0007] According to one aspect of the present invention, a semiconductor device is disclosed. The semiconductor device includes a redistribution structure, a processor chip, and metal pillars. The processor chip has an active side and a back side. The active side faces a first direction. The active side of the processor chip is connected to the redistribution structure.

[0008] The redistribution structure includes a connection structure comprising a conductive unit, solder bumps, a first insulating layer, a second insulating layer, a third insulating layer, a plurality of first through-holes, and a plurality of second through-holes. The conductive unit has a flange, a folded edge, an inclined sidewall, and a bottom. The solder bumps are located on the conductive unit and directly contact it. The first insulating layer is below the folded edge. The second insulating layer is below the bottom of the conductive unit and has a first through-hole area. The third insulating layer is below the second insulating layer and has a second through-hole area. The plurality of first through-holes are located within the first through-hole areas but are not below the bottom of the conductive unit. The plurality of second through-holes are located within the second through-hole areas, which are within the vertical projection of the conductive unit.

[0009] The metal pillar has a first end and a second end. The first end of the metal pillar is connected to the redistribution structure. The first end faces the first direction.

[0010] According to another aspect of the present invention, a semiconductor device is disclosed. The semiconductor device includes a redistribution structure, a processor chip, and metal pillars. The processor chip has an active side and a back side. The active side faces a first direction. The active side of the processor chip is connected to the redistribution structure.

[0011] The redistribution structure includes a connection structure comprising a conductive unit, solder bumps, a first insulating layer, a second insulating layer, a third insulating layer, a plurality of first through-holes, and a plurality of second through-holes. The conductive unit has a flange, a folded edge, an inclined sidewall, and a bottom. The solder bumps are located on the conductive unit and directly contact it. The first insulating layer is below the folded edge. The second insulating layer is below the bottom of the conductive unit and has a first through-hole area. The third insulating layer is below the second insulating layer and has a second through-hole area. The plurality of first through-holes are located within the first through-hole areas but are not below the bottom of the conductive unit. The plurality of second through-holes are located within the second through-hole areas, which are within the vertical projection of the conductive unit.

[0012] The metal pillar has a first end and a second end. The first end of the metal pillar is connected to the redistribution structure. The first end faces the first direction.

[0013] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: the redistribution structure has a special connection structure, which can achieve better signal integrity and structural stability. Attached Figure Description

[0014] Appendix Figure 1 This is a schematic diagram of one embodiment of a semiconductor device;

[0015] Appendix Figure 2 This is a cross-sectional view of the redistributed structure;

[0016] Appendix Figure 3 This is a cross-sectional view of another redistribution structure;

[0017] Appendix Figure 4 This is a schematic diagram of one embodiment of a semiconductor device;

[0018] Appendix Figure 5 This is a sectional view of the contact structure;

[0019] Appendix Figure 6 This is a cross-sectional view of another type of contact structure;

[0020] Appendix Figure 7 It is a cross-sectional view and a top view of a through hole;

[0021] Appendix Figure 8 These are cross-sectional views and top views of two through holes;

[0022] Appendix Figure 9 This is a cross-sectional view of two through holes;

[0023] Appendix Figure 10 It is a cross-sectional view and top view of three through holes;

[0024] Appendix Figure 11 It is a cross-sectional view of the through-hole area and a top view of the two through holes;

[0025] Appendix Figure 12 It is a cross-sectional view of the through-hole area and a top view of the four through holes;

[0026] Appendix Figure 13 It is a cross-sectional view of the through-hole area and a top view of the three through holes;

[0027] Appendix Figure 14 This is a top view of five through holes;

[0028] Appendix Figure 15 This is a top view of five through holes;

[0029] Appendix Figure 16 This is a top view of multiple through holes;

[0030] Appendix Figure 17This is a top view of multiple through holes;

[0031] Appendix Figure 18 This is a sectional view of the contact structure;

[0032] Appendix Figure 19 This is a schematic diagram of a semiconductor device with a DRAM module;

[0033] Appendix Figure 20 This is a schematic diagram of a part of the redistribution structure;

[0034] Appendix Figure 21 This is a side view of a semiconductor device;

[0035] Appendix Figure 22 This is a schematic diagram of one embodiment of the junction structure between the chip and the redistribution structure;

[0036] Appendix Figure 23 This is a schematic diagram of another embodiment of the contact structure between the chip and the redistribution structure;

[0037] Appendix Figure 24 This is a schematic diagram of another embodiment of the contact structure between the chip and the redistribution structure;

[0038] Appendix Figure 25 This is a schematic diagram of another embodiment of the contact structure between the chip and the redistribution structure;

[0039] Appendix Figure 26 This is a schematic diagram of another embodiment of the contact structure between the chip and the redistribution structure;

[0040] Appendix Figure 27 This is a schematic diagram of another embodiment of the contact structure between the chip and the redistribution structure;

[0041] Appendix Figure 28 This is a schematic diagram of a part of the redistribution structure;

[0042] Appendix Figure 29 This is a schematic diagram of an embodiment of a metal layer in a redistributed structure;

[0043] Appendix Figure 30 This is a schematic diagram of another embodiment of the metal layer in the redistribution structure;

[0044] Appendix Figure 31 This is a schematic diagram of another embodiment of the metal layer in the redistribution structure;

[0045] Appendix Figure 32 This is a top view of a semiconductor device;

[0046] Appendix Figure 33 This is a schematic diagram of a semiconductor package containing a DRAM module;

[0047] AppendixFigure 34 It is a detailed diagram of the redistribution structure;

[0048] Appendix Figure 35 This is a schematic diagram of one embodiment of a metal pillar;

[0049] Appendix Figure 36 This is a schematic diagram of another embodiment of the metal pillar;

[0050] Appendix Figure 37 This is a schematic diagram of a solder bump located at one end of a metal pillar;

[0051] Appendix Figure 38 This is a schematic diagram of a solder bump located at one end of a metal pillar;

[0052] Appendix Figure 39 This is a schematic diagram of a semiconductor device;

[0053] Appendix Figure 40 This is a schematic diagram of a semiconductor device;

[0054] Appendix Figure 41 It is a detailed diagram of the redistribution structure;

[0055] Appendix Figure 42 This is a top view and a cross-sectional view of a conductive via;

[0056] Appendix Figure 43 This is a top view and a cross-sectional view of a conductive via;

[0057] Appendix Figure 44 It is a cross-sectional view of multiple conductive vias;

[0058] Appendix Figure 45 It is a cross-sectional view of multiple conductive vias;

[0059] Appendix Figure 46 This is a top view of a conductive via;

[0060] Appendix Figure 47 This is a top view of a conductive via;

[0061] Appendix Figure 48 This is a top view of a conductive via;

[0062] Appendix Figure 49 This is a top view of a conductive via; and

[0063] Appendix Figure 50 This is a top view of a conductive via. Detailed Implementation

[0064] Appendix Figure 1 This is a schematic diagram of an embodiment of a semiconductor device. (See attached diagram.) Figure 2 This is a cross-sectional view of the redistributed structure. (Attached) Figure 3 This is a cross-sectional view of another redistribution structure. (Attached)Figure 4 This is a schematic diagram of one embodiment of a semiconductor device. (Attached) Figure 5 This is a sectional view of the contact structure. (Attached) Figure 6 This is a cross-sectional view of another type of contact structure. (Attached) Figure 7 This is a cross-sectional view and a top view of a through hole. (Attached) Figure 8 These are cross-sectional views and top views of two through holes. (Attached) Figure 9 This is a cross-sectional view of two through holes.

[0065] Appendix Figure 10 These are cross-sectional and top views of three through holes. (Attached) Figure 11 This is a sectional view of the through-hole area and a top view of the two through holes. (Attached) Figure 12 This is a sectional view of the through-hole area and a top view of the four through holes. (Attached) Figure 13 This is a cross-sectional view of the through-hole area and a top view of the three through holes. (Attached) Figure 14 This is a top view of the five through holes. (Attached) Figure 15 This is a top view of the five through holes. (Attached) Figure 16 This is a top view of multiple through holes. (Attached) Figure 17 This is a top view of multiple through holes. (Attached) Figure 18 It is a cross-sectional view of the contact structure.

[0066] According to one embodiment, refer to the appendix. Figure 1 and attached Figure 5 This paper discloses a contact structure 500. The contact structure 500 includes a conductive unit 205, solder bumps 206, a first insulating layer 501, a second insulating layer 502, a third insulating layer 503, and a plurality of through holes 1602. The conductive unit 205 has a flange 509. The conductive unit 205 includes a folded edge 506, an inclined sidewall 507, and a bottom 508. The solder bumps 206 are located on the conductive unit 205. The solder bumps 206 and the conductive unit 205 are in direct contact. The flange 509 is curved at the junction of the folded edge 506 and the inclined sidewall 507 (viewed from above the conductive unit 205).

[0067] The first insulating layer 501 is located below the folded edge 506. The second insulating layer 502 is located below the bottom 508 of the conductive unit 205. The third insulating layer 503 is located below the second insulating layer 502. The third insulating layer 503 has a through-hole area 512. The plurality of through holes 1602 are located in the through-hole area 512. The through-hole area 512 is located within the vertical projection 513 of the conductive unit 205.

[0068] The solder bumps include, but are not limited to, lead-containing and lead-free solders. Lead-containing solders include lead-tin (Pb-Sn) compositions, while lead-free solders include tin, copper, silver, or "SAC" compositions, as well as other eutectic materials having a common melting point and capable of forming conductive solder connections in electronic applications. In some embodiments, the conductive unit 250 includes an underbump metal (UBM). In some embodiments, the UBM structure includes one or more metal layers, such as titanium and copper layers. The UBM can be formed using a deposition process.

[0069] In some implementations, refer to the appendix. Figure 1 Appendix Figure 5 and attached Figure 16 The via region 512 is a second via region 512. The second insulating layer 502 has a first via region 511. The contact structure 500 includes a plurality of first vias 1601 located in the first via region 511. The plurality of first vias 1601 are not located below the bottom 508 of the conductive unit 205. In some embodiments, the via region 512 is located in a vertical projection of the flange 509.

[0070] In some embodiments, a large portion of the first through-hole region 511 is located below the bottom 508 and the inclined sidewall 507. That is, a large portion of the first through-hole region 511 is located below a vertical projection 515 of the bottom 506 and the inclined sidewall 507. A through-hole region is a location where a through-hole can be implemented. In some embodiments, a through-hole cannot be implemented outside the through-hole region. In some embodiments, the vertical projection 515 is annular when viewed from above.

[0071] See attached document Figure 5 and attached Figure 6 From the cross-sectional view, the through-hole region 516 is twice the size of the first through-hole region 511. This indicates that the through-hole region 516 has more space for implementing through-holes. A through-hole region 517, identical to the through-hole region 516, is formed in the fourth insulating layer 504. That is, the number of through-holes that can be implemented in the through-hole region 517 is the same as the number of through-holes that can be implemented in the through-hole region 516. In some embodiments, the number of through-holes in the through-hole region 516 is the same as the number of through-holes in the through-hole region 517. In some embodiments, each through-hole in the through-hole region 516 has a corresponding through-hole in the through-hole region 517. In some embodiments, the corresponding through-holes in the through-hole regions 516 and 517 are arranged perpendicularly.

[0072] The insulating layers 501, 502, 503 and 504 may be polyimide, benzocyclobutene (BCB), polybenzodioxazole (PBO) or other materials with similar insulating properties.

[0073] In some embodiments, the redistribution structure 102 further includes a through-hole region 518. The through-hole region 518 is the same size as the through-hole region 512 and allows the same number of through-holes to be implemented. In other words, when the through-hole region 512 allows for four through-holes, the through-hole region 518 also allows for four through-holes. In some embodiments, each through-hole in the through-hole region 512 has a corresponding through-hole in the through-hole region 518. In some embodiments, the corresponding through-holes in the through-hole regions 512 and 518 are arranged perpendicularly.

[0074] See attached document Figure 7 The through-hole 701 includes a flange 704, an inclined sidewall 705, and a bottom 706. Two rings can be used to represent the corresponding top views of the through-hole 701. The inner ring 703 represents the top view of the flange 702. The flange 702 is curved at the junction of the flange 704 and the inclined sidewall 705. The outer ring 707 is the top view of the circular edge of the through-hole 701.

[0075] In some implementations, refer to the appendix. Figure 8 The plurality of through holes 1602 includes a first through hole 801 and a second through hole 802. The first through hole 801 includes a first through hole flange 804, a first through hole inclined wall 803, and a first through hole bottom 807. The second through hole 802 includes a second through hole flange 805, a second through hole inclined wall 806, and a second through hole bottom 808. The first through hole flange 804 and the second through hole flange 805 have an overlapping area 809. In some embodiments, the first through hole flange 804 is a ring-shaped flange with a uniform width. In some embodiments, the first through hole flange 804 is a ring-shaped flange with inconsistent widths.

[0076] In some embodiments, the first through-hole flange 804 has a first width 810 at a first position 813 and a second width 812 at a second position 814. The second position 814 is closer to the center point 815 of the overlapping region 809 than the first position 813. In some embodiments, the second through-hole flange 805 is a ring flange with a uniform width. In some embodiments, the second through-hole flange 805 is a ring flange with inconsistent widths. In some embodiments, the second through-hole flange 805 has a first width 811 at a first position 816 and a second width 817 at a second position 818. The second position 818 is closer to the center point 815 of the overlapping region 809 than the first position 816.

[0077] According to another embodiment, refer to the appendix. Figure 1 Appendix Figure 2 Appendix Figure 4 and appendix Figure 5 The invention discloses a semiconductor device 100. The semiconductor device 100 includes a chip 101, a redistribution structure 102, a printed circuit board 401, and a non-volatile memory module 402. The chip 101 has an active side 103 and a back side 104.

[0078] The redistribution structure 102 has a front surface 201 and a rear surface 202. The front surface 201 is connected to the active side 103 of the chip 101 via a set of metal pillars 204. The redistribution structure 102 includes conductive units 205, first solder bumps 206, a first insulating layer 501, a second insulating layer 502, a third insulating layer 503, and a plurality of vias 1602. The conductive units 205 have flanges 509. The metal pillars 204 may be aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), or other suitable electrically conductive materials.

[0079] The conductive unit 205 includes a folded edge 506, an inclined sidewall 507, and a bottom 508. The rear surface 202 is a surface of the first insulating layer 501. The first solder bump 206 is located on the conductive unit 205. The first solder bump 206 is in direct contact with the conductive unit 205. The first insulating layer 501 is located below the folded edge 506. The second insulating layer 502 is located below the bottom 508 of the conductive unit 205. The third insulating layer 503 is located below the second insulating layer 502. The third insulating layer 503 has a through-hole area 512. The plurality of through holes 1602 are located in the through-hole area 512. The through-hole area 512 is located within the vertical projection 513 of the conductive unit 205.

[0080] The redistribution structure 102 is connected to the printed circuit board 401 via solder bumps 206. The non-volatile memory module 402 is connected to the printed circuit board 401 via multiple second solder bumps 403. The dynamic random access memory (DRAM) module 405 is connected to the redistribution structure 102 via multiple third solder bumps 406 and multiple metal pillars 107. The metal pillars 107 can be formed using a plating method. The material used to form the metal pillars 107 can be Cu, Al, W, Au, solder, or other suitable electrically conductive materials.

[0081] In some embodiments, the metal pillars 107 are connected to the redistribution structure 102 and the solder bumps 406. Electronic signals can be transmitted between the redistribution structure 102 and the DRAM module 405 via the metal pillars 107. In some embodiments, the non-volatile memory module 402 is a flash memory module.

[0082] In some embodiments, an adhesive layer 106 is provided on the back side 104 of the chip 101. A molding material 105 is filled between the chip 101 and the metal pillar 107. The molding material 105 is in direct contact with the redistribution structure 102. The adhesive layer 106 may be a die attach film (DAF) or similar. The molding material 105 may be a polymer composite material, such as a filled epoxy resin, a filled epoxy acrylate, or a polymer with suitable fillers.

[0083] In some implementations, refer to the appendix. Figure 2 The redistribution structure 102 further includes a fourth insulating layer 504 and a fifth insulating layer 505. Metal traces 207 are formed on the surfaces of the second insulating layer 502, the third insulating layer 503, the fourth insulating layer 504, and the fifth insulating layer 505 to form suitable contacts between vias. The metal traces 207 may be aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), or other suitable electrically conductive materials.

[0084] In some implementations, refer to the appendix. Figure 2 and attached Figure 3The conductive unit 205 is not required. The solder bump 206 is directly connected to the metal trace 207. In some embodiments, the redistribution structure 102 has four or more insulating layers. The metal trace thickness of each insulating layer can be different. For example, the metal trace thickness in the upper insulating layer can be greater than the metal trace thickness in the lower insulating layer. The difference in metal trace thickness in adjacent insulating layers can also be different. For example, the difference between the metal trace thickness of the first insulating layer 501 and the metal trace thickness of the second insulating layer 502 is defined as the first thickness difference. The difference between the metal trace thickness of the second insulating layer 5021 and the metal trace thickness of the third insulating layer 503 is defined as the second thickness difference, and so on. In this way, a first thickness difference, a second thickness difference, a third thickness difference, etc., can be obtained, depending on the number of insulating layers. In some embodiments, the first thickness difference, the second thickness difference, and the third thickness difference are substantially the same. In some embodiments, the first thickness difference is less than the second thickness difference, and the second thickness difference is greater than the third thickness difference. In other words, in the middle of the redistribution structure, the thickness of the metal traces between adjacent insulating layers may have a more significant difference. This has its advantages. For example, using similar metal trace thicknesses between the first set of insulating layers and then switching to a different metal trace thickness between the second set of insulating layers can eliminate the complexity of adjusting the metal trace thickness of each insulating layer.

[0085] In some embodiments, the via region 512 is a second via region 512. The second insulating layer 502 has a first via region 511. Refer to the attached drawing. Figure 16 The semiconductor device 100 further includes a plurality of first vias 1601 located in the first via region 511. The plurality of first vias 1601 are not located below the bottom 506 of the conductive unit 205.

[0086] According to another embodiment, refer to the appendix. Figure 1 Appendix Figure 5 and attached Figure 9 The contact structure 500 includes a conductive unit 205, a solder bump 206, a first insulating layer 501, a second insulating layer 502, a third insulating layer 503, a first through hole 801, and a second through hole 802. The conductive unit 205 has a flange 509. The conductive unit 205 includes a folded edge 506, an inclined sidewall 507, and a bottom 508. The solder bump 206 is located on the conductive unit 205. The solder bump 206 and the conductive unit 205 are in direct contact.

[0087] The first insulating layer 501 is located below the folded edge 506. The second insulating layer 502 is located below the bottom 508 of the conductive unit 205. The third insulating layer 503 is located below the second insulating layer 502.

[0088] The first through hole 801 has a first through hole flange 820. The first through hole flange 820 has a first through hole flange diameter 822. The first through hole 801 has a first through hole bottom edge 818. The first through hole 801 is located within the vertical projection of the conductive unit 205. The second through hole 802 has a second through hole flange 821. The second through hole flange 821 has a second flange diameter 823. The second through hole 802 has a second through hole bottom edge 819. The second through hole 802 is located within the vertical projection of the conductive unit 205. The bottom edge distance 824 is the distance between the bottom edges 818 and 819 of the first through hole. The diameter 822 of the first flange is greater than the bottom edge distance 824.

[0089] See attached document Figure 5 Appendix Figure 6 and appendix Figure 10 In some embodiments, three through holes 1001, 1002, and 1003 are implemented within the through hole region 511. The three through holes 1001, 1002, and 1003 are located within the vertical projection of the conductive unit 205. In some embodiments, the three through holes 1001, 1002, and 1003 are located within the vertical projection of the flange 509. Through hole 1001 has a folded edge 1004. Through hole 1002 has a folded edge 1005. Through hole 1003 has a folded edge 1006. Folded edges 1004 and 1005 have an overlapping area 1007. Folded edges 1005 and 1006 have an overlapping area 1008.

[0090] The overlapping regions 1007 and 1008 make the three through holes 1001, 1002, and 1003 more closely spaced. The closely spaced through holes 1001, 1002, and 1003 reduce stress. For through hole 1002, the presence of through holes 1001 and 1003 makes the surfaces 1010 on both sides of through hole 1001 uneven, thereby reducing the stress applied to the bottom 1009 of through hole 1002. Surface 1010 is formed by through holes 1001 and 1003 and trace 207 on the insulating layer 1013. Similarly, the stress applied to the bottom 1011 of through hole 1001 is also reduced. The stress applied to the bottom 1012 of through hole 1003 is also reduced.

[0091] In some implementations, refer to the appendix. Figure 16The contact structure 500 further includes a plurality of through holes 1601 located within the second insulating layer 502. No through holes in the second insulating layer 502 are located below the bottom 508 of the conductive unit 205. In some embodiments, the first through hole 801 and the second through hole 802 are located within the vertical projection of the flange 509.

[0092] In some implementations, refer to the appendix. Figure 8 The first through hole 801 includes a first through hole flange 804, a first through hole inclined wall 803, and a first through hole bottom 807. The second through hole 802 includes a second through hole flange 805, a second through hole inclined wall 806, and a second through hole bottom 808. The first through hole flange 804 and the second through hole flange 805 have an overlapping area 809.

[0093] In some embodiments, the first through-hole flange 804 is a ring-shaped flange with a uniform width. In some embodiments, the first through-hole flange 804 is a ring-shaped flange with varying widths. In some embodiments, the first through-hole flange 804 has a first width 810 at a first position 813 and a second width 812 at a second position 814. The second position 814 is closer to the center point 815 of the overlapping area 809 than the first position 813.

[0094] According to another embodiment, refer to the appendix. Figure 1 Appendix Figure 4 Appendix Figure 5 and appendix Figure 9 The semiconductor device 100 includes a chip 101, a redistribution structure 102, a printed circuit board 401, a non-volatile memory module 402, and a DRAM module 405.

[0095] The chip 101 has an active side 103 and a back side 104. The redistribution structure 102 has a front surface 201 and a rear surface 202. The front surface 201 is connected to the active side 103 of the chip 101 via a set of metal pillars 204. The redistribution structure 102 includes conductive units 205, solder bumps 206, a first insulating layer 501, a second insulating layer 502, a third insulating layer 503, a first via 801, and a second via 802. The rear surface 202 is a surface of the first insulating layer 501.

[0096] The conductive unit 205 has a flange 509. The conductive unit 205 includes a folded edge 506, an inclined sidewall 507, and a bottom 508. The solder bump 206 is located on the conductive unit 205. The solder bump 206 is in direct contact with the conductive unit 205. The first insulating layer 501 is located below the folded edge 506. The second insulating layer 502 is located below the bottom 508 of the conductive unit 205. The third insulating layer 503 is located below the second insulating layer 502.

[0097] See attached document Figure 5 and attached Figure 9 The first through hole 801 has a first through hole flange 820. The first through hole 801 and the second through hole 802 are implemented in the through hole region 512. The first through hole flange 820 has a first through hole flange diameter 822. The first through hole 801 has a first through hole bottom edge 818. The first through hole 801 is located within the vertical projection of the conductive unit 205. The second through hole 802 has a second through hole flange 821. The second through hole flange 821 has a second flange diameter 823. The second through hole 802 has a second through hole bottom edge 819. The second through hole 802 is located within the vertical projection of the conductive unit 205. The bottom edge distance 824 is the distance between the bottom edge 818 of the first through hole and the bottom edge 819 of the second through hole. The first flange diameter 822 is greater than the bottom edge distance 824.

[0098] See attached document Figure 4 The redistribution structure 102 is connected to the printed circuit board 401 via the solder bumps 206. The non-volatile memory module 402 is connected to the printed circuit board 401 via a plurality of second solder bumps 403. (See attached diagram) Figure 1 and attached Figure 4 The DRAM module 405 is connected to the redistribution structure 102 via a plurality of third solder bumps 406 and a plurality of metal pillars 107. In some embodiments, the second insulating layer 502 has no vias located below the bottom 508 of the conductive unit 205.

[0099] According to another embodiment, refer to the appendix. Figure 1 Appendix Figure 5 and appendix Figure 9 and appendix Figure 16 The contact structure 500 includes a conductive unit 205, a solder bump 206, a first insulating layer 501, a second insulating layer 502, a third insulating layer 503, a first through hole 801, a second through hole 802, a third through hole 825, and a fourth through hole 826.

[0100] The conductive unit 205 has a flange 509. The conductive unit 205 includes a folded edge 506, an inclined sidewall 507, and a bottom 508. The solder bump 206 is located on the conductive unit 205. The solder bump 206 is in direct contact with the conductive unit 205. The first insulating layer 501 is located below the folded edge 506. The second insulating layer 502 is located below the bottom 508 of the conductive unit 205. The third insulating layer 503 is located below the second insulating layer 502.

[0101] The first through-hole 801 is located in the third insulating layer 503. More than half of the first through-hole 801 lies within the vertical projection of the flange 509 of the conductive unit 205. The second through-hole 802 is located in the third insulating layer 503. More than half of the second through-hole 802 lies within the vertical projection of the flange 509 of the conductive unit 205.

[0102] The third through-hole 825 is located in the second insulating layer 502. More than half of the third through-hole 825 lies within the vertical projection of the folded edge 506 and the inclined sidewall 507 of the conductive unit 205. The fourth through-hole 826 is located in the second insulating layer 502. More than half of the fourth through-hole 826 lies within the vertical projection of the folded edge 506 and the inclined sidewall 507 of the conductive unit 205.

[0103] In some embodiments, the first through-hole 801, the second through-hole 802, the third through-hole 825, and the fourth through-hole 826 are symmetrical with respect to the first axis 827. In some embodiments, the first through-hole 801, the second through-hole 802, the third through-hole 825, and the fourth through-hole 826 are arranged along the second axis 828. In some embodiments, the contact structure 500 further includes a fifth through-hole 830 and a sixth through-hole 831. More than half of the fifth through-hole 830 lies within the vertical projection of the folded edge 506 and the inclined sidewall 507 of the conductive unit 205. More than half of the sixth through-hole 831 lies within the vertical projection of the folded edge 506 and the inclined sidewall 507. The through-holes 801, 802, 825, 826, 830, and 831 can be aluminum, copper, tungsten, gold, silver, or other suitable electrically conductive materials. The method for forming the metal through-holes can be plating.

[0104] See attached document Figure 5 and attached Figure 16In some embodiments, a plurality of through holes are implemented in the through-hole region 519 of the insulating layer 504. The insulating layer 504 is located below the insulating layer 503. In some embodiments, the through holes in the through-hole region 519 correspond to the through holes in the through-hole region 511. In some embodiments, the through holes in the through-hole region 511 and the through holes in the through-hole region 519 are arranged perpendicularly. In some embodiments, the number of through holes in the through-hole region 511 is the same as the number of through holes in the through-hole region 519.

[0105] In some embodiments, the arrangement of through holes in the through-hole region 519 is the same as that in the through-hole region 511. In some embodiments, the thickness of the through holes in the through-hole region 519 is less than the thickness of the through holes in the through-hole region 511. In some embodiments, refer to the attached diagram. Figure 2 and attached Figure 5 The conductive unit 205 shown, all through holes in through hole region 511, all through holes in through hole region 512, and all through holes in through hole region 519 are electrically connected through metal traces 207 in each insulating layer.

[0106] In some implementations, refer to the appendix. Figure 16 The third through hole 825, the fourth through hole 826, the fifth through hole 830, and the sixth through hole 831 are arranged in pairs relative to the center point 829. In some embodiments, refer to the attached drawing. Figure 8 The first through hole 801 includes a first through hole flange 804, a first through hole inclined wall 803, and a first through hole bottom 807. The second through hole 802 includes a second through hole flange 805, a second through hole inclined wall 806, and a second through hole bottom 808, and the first through hole flange 804 and the second through hole flange 805 have an overlapping area 809.

[0107] In some embodiments, the through holes 801 and 802 are implemented in the insulating layer 503. The through holes 825 and 826 are implemented in the insulating layer 502. See attached figure. Figure 8 With appendix Figure 16 The vias 830 and 831 are implemented in the insulating layer 502. The vias located in the two adjacent layers are not vertically aligned. In other words, the vias located in the two adjacent layers are displaced from each other. In some embodiments, vias 801, 802, 825, 826, 830, 831, and the conductive unit 205 are electrically connected via the metal trace 207.

[0108] In some embodiments, the first through hole 801 includes a first through hole flange 804, a first through hole inclined wall 803, and a first through hole bottom 807. The second through hole 802 includes a second through hole flange 805, a second through hole inclined wall 806, and a second through hole bottom 808. (See attached diagram.) Figure 11 The first edge 832 of the first through hole flange 804 contacts the second edge 833 of the second through hole flange 805.

[0109] See attached document Figure 9 and attached Figure 11 The through holes 801 and 802 are located in the through hole region 512. In some embodiments, edge 832 does not contact edge 833. The distance between edges 832 and 833 is less than the diameter of the flange 820 of through hole 801. The distance between edges 832 and 833 is less than the diameter of the flange 821 of through hole 802. In some embodiments, edges 832 and 833 contact at a single point. In some embodiments, the folded edges of through hole 801 and through hole 802 overlap, forming an overlapping region 809.

[0110] The close arrangement of the through holes 801 and 802 helps reduce the stress applied to the bottom of the through holes 801 and 802. For the through holes 801, the adjacent through holes 802 form an uneven metal surface on one side. This helps reduce the stress transmitted from that side. For the through holes 802, the adjacent through holes 801 form an uneven metal surface on one side. This helps reduce the stress transmitted from that side. Arranging two or more through holes below the conductive unit 205 improves the conductivity from the conductive unit 205 to the lower through holes and simultaneously reduces stress.

[0111] See attached document Figure 12 In some embodiments, two through holes 1201 and 1202 are located in the left through hole area 516. Two other through holes 1203 and 1204 are located in the right through hole area 516. Viewed from above, the through hole areas 516 form an annular shape. Viewed from above, the through hole areas 512 form a circular shape. In some embodiments, the distance between through holes 1201 and 1202 is less than the diameter of the flange of through hole 1201. The distance is also less than the diameter of the flange of through hole 1202. In some embodiments, through holes 1201 and 1202 contact at a single point. In some embodiments, through holes 1201 and 1202 have an overlapping area 1205.

[0112] See attached document Figure 13In some embodiments, three through holes 1301, 1302, and 1303 are implemented in the through hole region 512. In some embodiments, through holes 1301 and 1302 are in contact at one point. Through holes 1302 and 1303 are in contact at one point. In some embodiments, through holes 1301 and 1302 have an overlapping folded edge region 1304. Through holes 1302 and 1303 have an overlapping folded edge region 1305.

[0113] See attached document Figure 5 and attached Figure 14 In some embodiments, five through holes 1401 are implemented within the vertical projection 1402 of the flange 509 of the conductive unit 205. In some embodiments, three of the through holes 1401 are implemented along axis 1404. In some embodiments, three of the through holes 1401 are implemented along axis 1405. In some embodiments, all the through holes 1401 have nearly identical dimensions. In some embodiments, each of the through holes 1401 and an adjacent through hole 1401 have an overlapping folded edge region.

[0114] See attached document Figure 5 and attached Figure 15 In some embodiments, five through holes 1501 are implemented within the vertical projection 1502 of the flange 509 of the conductive unit 205. In some embodiments, three of the through holes 1501 are implemented along axis 1504. In some embodiments, three of the through holes 1501 are implemented along axis 1505. In some embodiments, all the through holes 1501 have nearly the same size. In some embodiments, each of the through holes 1501 and an adjacent through hole 1501 are in contact at a point.

[0115] See attached document Figure 5 and attached Figure 16 The through holes 801 and 802 are located within the vertical projection 1603 of the flange 509. In some embodiments, a small portion of the through hole 801 is located outside the vertical projection 1603 of the flange 509, and the majority of the through hole 801 is located within the vertical projection 1603. In some embodiments, a small portion of the through hole 802 is located outside the vertical projection 1603 of the flange 509, and the majority of the through hole 802 is located within the vertical projection 1603. In some embodiments, the through holes 801, 802, 825, and 826 are implemented along axis 828. In some embodiments, the through holes 830 and 831 are implemented along axis 827.

[0116] See attached document Figure 5 and attached Figure 17In some embodiments, the through holes 801 and 802 are located within the vertical projection 1701 of the flange 509. The through holes 801 and 802 have an overlapping folded edge region 1702. In some embodiments, a plurality of through holes 1703 are implemented within the vertical projection 1704 of the conductive unit 205.

[0117] According to another embodiment, refer to the appendix. Figure 1 Appendix Figure 4 Appendix Figure 5 and appendix Figure 9 With appendix Figure 16 The semiconductor device 100 includes a chip 101, a redistribution structure 102, a printed circuit board 401, a non-volatile memory module 402, and a DRAM module 405.

[0118] The chip 101 has an active side 103 and a back side 104. The redistribution structure 102 has a front surface 201 and a rear surface 202. The front surface 201 is connected to the active side 103 of the chip 101 via a set of metal pillars 204. The redistribution structure 102 includes conductive units 205, solder bumps 206, a first insulating layer 501, a second insulating layer 502, a third insulating layer 503, a first through-hole 801, a second through-hole 802, a third through-hole 825, and a fourth through-hole 826. The conductive unit 205 has a flange 509. The conductive unit 205 includes a folded edge 506, an inclined sidewall 507, and a bottom 508.

[0119] The solder bump 206 is located on the conductive unit 205. The solder bump 206 and the conductive unit 205 are in direct contact. The first insulating layer 501 is located below the folded edge 506. The second insulating layer 502 is located below the bottom 508 of the conductive unit 205. The third insulating layer 503 is located below the second insulating layer 502. The first through-hole 801 is located in the third insulating layer 503.

[0120] More than half of the first through-hole 801 lies within the vertical projection of the flange 509 of the conductive unit 205. The second through-hole 802 is located in the third insulating layer 503. More than half of the second through-hole 802 lies within the vertical projection of the flange 509 of the conductive unit 205. The third through-hole 825 is located in the second insulating layer 502. More than half of the third through-hole 825 lies within the vertical projection of the folded edge 506 and the inclined sidewall 507 of the conductive unit 205. The fourth through-hole 826 is located in the second insulating layer 502. More than half of the fourth through-hole 826 lies within the vertical projection of the folded edge 506 and the inclined sidewall 507 of the conductive unit 205.

[0121] The redistribution structure 102 is connected to the printed circuit board 401 via solder bumps 206. The non-volatile memory module 402 is connected to the printed circuit board 401 via multiple second solder bumps 403. The DRAM module 405 is connected to the redistribution structure 102 via multiple third solder bumps 406 and multiple metal pillars 107. In some embodiments, the first via 801, the second via 802, the third via 825, and the fourth via 826 are symmetrical with respect to the first axis 827.

[0122] See attached document Figure 5 and attached Figure 18 A through-hole 1801, a through-hole 1802, and a through-hole 1803 are implemented within the vertical projection of the conductive unit 205. A metal layer 1804 is implemented below the conductive unit 205. The metal layer 1804 is in direct contact with the bottom of the conductive unit 205. In some embodiments, the area of ​​a region of the metal layer 1804 is approximately equal to the area of ​​the bottom of the conductive unit 205.

[0123] In some embodiments, a region of the metal layer 1804 has an area larger than the bottom area of ​​the conductive unit 205. This region of the metal layer 1804 is located directly below the bottom of the conductive unit 205, allowing for good and complete contact with the bottom of the conductive unit 205. In some embodiments, vias are not implemented in region 1805. Region 1805 is located below the bottom of the conductive unit 205. In some embodiments, the metal layer 1804 is connected to the metal trace 207, such that the metal layer 1804, metal trace 207, vias 1801, 1802, and 1803 are all electrically connected. In some embodiments, a metal pillar 1806 is located above the conductive unit 205. In some embodiments, solder bumps replace the metal pillar 1806.

[0124] One objective of the above embodiments is to provide a contact structure that helps reduce stress in semiconductor packages. Another objective of the above embodiments is to provide a via arrangement below the conductive cells of the redistribution structure to achieve better conductivity. Yet another objective of the above embodiments is to provide a contact structure that is symmetrical about a center point, thereby achieving stress balance.

[0125] See attached document Figure 19 and attached Figure 20According to one embodiment, a semiconductor device 1900 is disclosed. The semiconductor device 1900 includes a chip 1901, a redistribution structure 1902, a plurality of conductive pillars 1903, a DRAM module 1904, and a plurality of solder bumps 1905. The chip 1901 has an active side 1906 and a back side 1907. The redistribution structure 1902 has a front surface 1908 and a rear surface 1909. The redistribution structure 1902 is connected to the chip 1901 via a plurality of conductive pillars 2001.

[0126] In some embodiments, the redistribution structure 1902 has multiple sublayers 2002. Each sublayer 2002 is an insulating layer. Each sublayer 2002 includes a metal trace 2003 and a via 2004. Electronic signals and power / ground levels are connected through the metal traces 2003 and vias 2004. In some embodiments, the redistribution structure 1902 includes multiple conductive units 2005 and multiple solder bumps 2006. Each solder bump 2006 is located on its corresponding conductive unit 2005. In some embodiments, the conductive unit is a bump underbody metal (UBM) layer.

[0127] In some embodiments, the semiconductor device 1900 includes an adhesive layer 1910. The adhesive layer 1910 is a die-attach film (DAF). In some embodiments, the semiconductor device 1900 includes passive devices 1911 and 1912. Passive device 1911 is a capacitor. Passive device 1912 is a capacitor. In some embodiments, passive device 1911 is an inductor. Passive device 1912 is an inductor. In some embodiments, passive devices 1911 and 1912 are located within a vertical projection 1913 of chip 1901. Viewed from above, the vertical projection 1913 is rectangular in shape because chip 1901 is rectangular.

[0128] In some embodiments, the passive device 1911 is connected to the rear surface 1909 of the redistribution structure 1902 via solder bumps 2009. In some embodiments, the passive device 1911 is an integrated passive device (IPD). In some embodiments, the semiconductor device 1900 includes passive devices 1914 and 1915. Passive device 1914 is a capacitor. Passive device 1915 is a capacitor. In some embodiments, passive device 1914 is an inductor. Passive device 1915 is an inductor. In some embodiments, passive devices 1914 and 1915 are located within the vertical projection 1913 of chip 1901.

[0129] In some embodiments, the semiconductor device 1900 includes passive devices 1916 and 1917. In some embodiments, passive device 1916 is a capacitor. Passive device 1917 is a capacitor. In some embodiments, passive device 1916 is an inductor. Passive device 1917 is an inductor. Passive devices 1916 and 1917 are located on the front surface 1908 of the redistribution structure 1902.

[0130] In some embodiments, passive devices 1916 and 1917 are located adjacent to the chip 1901. In some embodiments, passive devices 1916 and 1917 are closer to the chip 1901 than any conductive post 1903. In some embodiments, bottom filler 1919 surrounds the solder bump 1905. In some embodiments, a gap 1920 is formed between the DRAM module 1904 and the adhesive layer 1910. In some embodiments, the gap 1920 is not filled with bottom filler 1919. In some embodiments, the gap 1920 is also filled with bottom filler 1919.

[0131] In some embodiments, the semiconductor device 1900 includes a molding material 1918 that fills the void between one of the conductive pillars 1903 and the chip 1901. In some embodiments, the molding material 1918 surrounds all the conductive pillars 1903. In some embodiments, the semiconductor device 1900 includes an insulating layer 2007 located between the front surface 1908 of the redistribution structure 1902 and the active side 1906 of the chip 1901. In some embodiments, the insulating layer 2007 is a polymer layer. In some embodiments, the insulating layer 2007 is a polyimide layer. In some embodiments, the insulating layer 2007 and the molding material 1918 have the same material. In some embodiments, the insulating layer 2007 surrounds each conductive pillar 2001 located between the redistribution structure 1902 and the chip 1901.

[0132] In some embodiments, the insulating layer 2007 does not provide wiring for signal traces. That is, the insulating layer 2007 does not have any redistribution function. No metallic traces are formed on the insulating layer 2007 for wiring purposes. See attached figure. Figure 20 and attached Figure 24 In some embodiments, no redistribution of metal traces is provided below the front surface 1908 of the redistribution structure 1902 and above the passivation layer 2401.

[0133] See attached document Figure 22In some embodiments, the insulating layer 2007 is located between the active side 1906 of the chip 1901 and the front surface 1908 of the redistribution structure 1902. In some embodiments, the insulating layer 2007 comprises polyimide. In some embodiments, the insulating layer 2007 and the front surface 1908 of the redistribution structure 1902 are in direct contact. In some embodiments, the insulating layer 2007 and the active side 1906 of the chip 1901 are in direct contact.

[0134] See attached document Figure 22 The chip 1901 has a chip edge 2203. The insulating layer 2007 has an outer edge 2204. The chip edge 2203 is not perpendicular to the outer edge 2204 of the insulating layer 2007. There is a horizontal displacement 2208 between the chip edge 2203 and the outer edge 2204 of the insulating layer 2007.

[0135] The reason for the horizontal displacement 2208 is that during the wafer dicing process, the presence of a polymer insulating layer 2007 in the dicing track can cause some problems. If the insulating layer 2007 is formed above the dicing track before the dicing process, it may not be easy to cut the insulating layer 2007 during the dicing process because the insulating layer 2007 and the chip 1901 have different chemical and physical properties. In some cases, the dicing process may tear off the insulating layer 2007 and damage the structure of the semiconductor device 1900. Therefore, when forming the insulating layer 2007, it is best to keep it at a distance from the edge 2203 of the chip 1901. That is, the insulating layer 2007 should preferably not be located near the dicing track.

[0136] See attached document Figure 22 A recess 2205 is formed between the redistribution structure 1902 and the chip 1901. In some embodiments, the recess 2205 is filled with a molding material 1918. In some embodiments, the adhesive layer 1910 has an edge 2206. The edge 2206 of the adhesive layer 1910 is perpendicular to the chip edge 2203. In some embodiments, the molding material 1918 covers the chip edge 2203 and the edge 2206 of the adhesive layer 1910. In some embodiments, the edge 2206 of the adhesive layer is not perpendicular to the chip edge 2203. The edge 2206 of the adhesive layer 1910 forms a recess 2207 below the chip 1901. In some embodiments, the molding material 1918 fills the recess 2207.

[0137] See attached document Figure 22The conductive post 2001 is surrounded by an insulating layer 2007. The conductive post 2001 is connected to a through-hole 2004 of the redistribution structure 1902. The conductive post 2001 is also connected to the active side 1906 of the chip 1901. The conductive post 2001 can be used to transmit electronic signals between the redistribution structure 1902 and the chip 1901. In some embodiments, the insulating layer 2002 is made of the same material as the insulating layer 2007. In this case, the insulating layer 2007 and the insulating layer 2002 have the same chemical and physical properties, thus preventing mismatch between the two layers. For example, the insulating layer 2007 and the insulating layer 2002 have the same coefficient of thermal expansion, so changes in ambient temperature will inevitably cause warping.

[0138] See attached document Figure 23 In some embodiments, the insulating layer 2007 does not directly contact the insulating layer 2002. Molding material 1918 is filled between the front surfaces 1908 of the redistribution structure 1902. The molding material 1918 surrounds the upper portion of the conductive post 2001. The insulating layer 2007 surrounds the lower portion of the conductive post 2001.

[0139] See attached document Figure 24 The chip 1901 includes a passivation layer 2401. The passivation layer 2401 has an edge 2402. The edge 2402 and the edge 2403 of the chip 1901 are perpendicularly aligned. In some embodiments, the insulating layer 2007 has an outwardly curved surface 2405. The upper surface 2407 of the passivation layer 2401 is in direct contact with the molding material 1918. In some embodiments, the insulating layer 2007 has an edge 2408. The edge 2408 is not perpendicular to the edge 2402. There is a horizontal displacement 2409 between the edge 2408 and the edge 2402.

[0140] See attached document Figure 25 In some embodiments, the insulating layer 2007 has an outwardly curved surface 2501. The outwardly curved surface 2501 is in direct contact with the molding material 1918. The outwardly curved surface 2501 has a farthest point 2502. The farthest point 2502 is not located at the interface between the insulating layer 2007 and the passivation layer 2401. The farthest point 2502 is not located at the interface between the insulating layer 2007 and the front surface 1908 of the redistribution structure 1902. The farthest point 2502 is not perpendicular to the edge 2402 of the passivation layer 2401. The front surface 1908, the outwardly curved surface 2501, and the passivation layer 2401 form a recess 2503.

[0141] In some embodiments, the recess 2503 is filled with molding material 1918. A horizontal displacement 2504 exists between the farthest point 2502 and the edge 2402 of the passivation layer 2401. In some embodiments, a portion of the upper surface 2505 of the passivation layer 2401 is in direct contact with the molding material 1918.

[0142] See attached document Figure 26 In some embodiments, the insulating layer 2007 has an inwardly curved surface 2601. The inwardly curved surface 2601 has a farthest point 2602. The farthest point 2602 is located on the boundary between the inwardly curved surface 2601 and the upper surface of the passivation layer 2401. There is a horizontal displacement 2603 between the farthest point 2602 and the edge 2402 of the passivation layer 2401.

[0143] The front surface 1908 of the redistribution structure 1902, the inwardly curved surface 2601, and the passivation layer 2401 form a recess 2604. In some embodiments, the recess 2604 is filled with the molding material 1918. In some embodiments, the farthest point 2602 is located on the boundary between the inwardly curved surface 2601 and the front surface 1908 of the redistribution structure. In this case, there is a horizontal displacement 2603 between the farthest point 2602 and the front surface 1908 of the redistribution structure. In this case, a portion of the upper surface 2505 of the passivation layer 2401 is in direct contact with the molding material 1918.

[0144] See attached document Figure 27 In some embodiments, the insulating layer 2007 is not in direct contact with the front surface 1908 of the redistribution structure 1902. A gap 2701 exists between the front surface 1908 and the insulating layer 2007. In some embodiments, the molding material 1918 fills the gap 2701.

[0145] See attached document Figure 28In some embodiments, the redistribution structure 1902 includes insulating layers 2801, 2802, 2803, and 2804. The redistribution structure 1902 includes metal layers 2805, 2806, and 2807. Metal layer 2805 is not located above insulating layer 2801. Metal layer 2806 is located above insulating layer 2802. Metal layer 2807 is not located above insulating layer 2803. A plurality of conductive units 2005 are formed above insulating layer 2804. Metal layer 2805 is connected to the conductive post 2001 through a through-hole 2004. Metal layer 2806 is connected to metal layer 2805 through a through-hole 2004. Metal layer 2807 is connected to metal layer 2806 through a through-hole 2004.

[0146] See attached document Figure 28 Metal layer 2805 includes metal traces for transmitting signals and metal traces for power and ground. Metal layer 2806 includes metal traces for transmitting signals and metal traces for power and ground. Metal layer 2807 includes metal traces for transmitting signals and metal traces for power and ground. Metal layer 2806 is located between metal layers 2805 and 2807, and has a relatively large metal trace portion for power and ground connections. That is, compared to metal layers 2805 and 2807, metal layer 2806 has more power and ground areas.

[0147] The total length of the signal wiring metal traces in metal layer 2805 is longer than that in metal layer 2806. The total length of the signal wiring metal traces in metal layer 2807 is longer than that in metal layer 2806. The power and ground traces or metal regions in metal layer 2806 are longer than those in metal layer 2805. The power and ground traces or metal regions in metal layer 2806 are longer than those in metal layer 2807. By providing larger power and ground regions in the middle, metal layer 2806 helps maintain good signal integrity for signals transmitted to metal layers 2805 and 2807.

[0148] See attached document Figure 28 and attached Figure 29The metal layer 2806 has power ground areas 2901, 2902, and 2903. In some embodiments, the power ground area 2901 is formed of a mesh-like metal layer. The power ground area 2901 has a metal plate with a plurality of holes 2904 or slits 2904. The width of the holes 2904 is typically greater than the width of the metal traces 2905. The metal traces 2905 originate from the boundary lines of the power ground area 2901. The metal traces 2905 also originate from internal lines between the plurality of holes 2904. The power ground area 2901 is connected to a power supply level or a ground level.

[0149] See attached document Figure 28 and attached Figure 29 In some embodiments, the power ground region 2902 is formed by a plurality of metal traces 2905. The metal traces 2905 of the power ground region 2902 do not form a closed boundary. The metal traces 2905 are metal islands connected to the same power supply level or the same ground level. In some embodiments, the metal layer 2806 includes electrically isolated metal islands implemented in two power ground regions. For example, a plurality of metal islands 2908 are implemented between the power ground regions 2901 and 2902. A plurality of metal islands 2908 are implemented between the power ground regions 2902 and 2903. The metal islands 2908 are electrically isolated from each other so that they are not perpendicularly connected to another metal layer.

[0150] In some embodiments, a metal layer with a large power contact area may be provided between two metal layers having a larger signal metal trace portion. For example, refer to the attached figure. Figure 28 Compared to metal layer 2807, metal layer 2806 can have more contact areas. Compared to metal layer 2805, metal layer 2806 can have more contact areas. By placing a metal layer with a significant contact area between two metal layers with prominent signal metal traces, signal crosstalk can be prevented and signal integrity can be maintained.

[0151] See attached document Figure 30In some embodiments, the metal layer 2806 includes a plurality of power ground regions. For example, one of the power ground regions is formed by a metal element 3001. Another power ground region is formed by a metal element 3002. Another power ground region is formed by a metal element 3003. Another power ground region is formed by a metal element 3004. In some embodiments, each metal element 3001 is a polygon. In some embodiments, the metal element 3001 is a hexagon. In some embodiments, each polygon has more than half of its interior angles being approximately 120 degrees. In some embodiments, the metal layer 2806 includes a plurality of metal islands 2908 for two power ground intervals.

[0152] In some implementations, not every metal element is the same size. For example, a metal element 3003 may be twice the size of its neighboring metal elements 3003. The reason for implementing metal islands 2908 in the two power grounding zones is that these metal islands 2908 can, to some extent, prevent accidental short circuits between power grounding zones with two different voltage levels. The size of the metal islands 2908 is smaller than the size of the metal elements.

[0153] In some embodiments, the metal island 2908 may be implemented surrounding a signal trace. In some embodiments, the metal island 2908 may be implemented between two adjacent signal traces. In some embodiments, the metal island 2908 may be implemented between a signal trace and a power supply / ground interval. In some embodiments, the metal island 2908 may be implemented between one signal trace and another signal trace.

[0154] In some embodiments, the metal island 2908 is electrically isolated and not connected to any other power level or signal trace. The reason for implementing the metal island around a signal trace is that it provides a degree of shielding and insulation, allowing the surrounded signal trace to have better signal integrity. Another reason for implementing the metal island 2908 is to achieve a more uniform metal density in the metal layer 206, resulting in better packaging quality.

[0155] See attached document Figure 31 In some embodiments, the metal layer 2806 includes power ground areas 3101, 3102, and 3103. The power ground area 3101 has a plurality of holes 3104. Most of the holes 3104 have a width or diameter greater than the width of the metal traces 3105. The metal traces 3105 form the boundary and inner lines of each power ground area. In some embodiments, the holes are of different sizes. For example, the size of a hole 3106 is twice that of its adjacent holes.

[0156] See attached document Figure 19 Appendix Figure 20 and appendix Figure 21 The document discloses a semiconductor device 1900 according to another embodiment. The semiconductor device 1900 includes a redistribution structure 1902, a chip 1901, a DRAM module 1904, a printed circuit board 2101, and a non-volatile memory module 2102. The DRAM module 1904 is connected to the redistribution structure 1902 via solder bumps 1905 and conductive posts 1903. The chip 1901 is connected to the redistribution structure 1902 via conductive posts 2001. The redistribution structure 1902 is connected to the printed circuit board 2101 via solder bumps 2006. The non-volatile memory module 2102 is connected to the printed circuit board 2101 via solder bumps 2103.

[0157] In some embodiments, the semiconductor device 1900 includes a DRAM module 1904, a chip 1901, a redistribution structure 1902, a printed circuit board 2101, and a non-volatile memory module 2102. The chip 1901 is located between the redistribution structure 1902 and the DRAM module 1904. The area of ​​the DRAM module 1904 is larger than the area of ​​the chip 1901. The area of ​​the redistribution structure is larger than the area of ​​the DRAM module 1904. The redistribution structure 1902 is connected to the printed circuit board 2101. The non-volatile memory module 2102 is connected to the printed circuit board 2101. The redistribution structure 1902 is electrically connected to the non-volatile memory module 2102 through the printed circuit board 2101.

[0158] See attached document Figure 24 The passivation layer 2401 may be a single or multiple layers of silicon nitride (Si3N4), silicon dioxide (SiO2), silicon oxynitride (SiON), SiO2 / Si3N4, or other materials with dielectric properties. (See attached figure.) Figure 20 and attached Figure 28 The insulating layers 2002, 2801, 2802, 2803, and 2804 may be polyimide, benzocyclobutene (BCB), polybenzodioxazole (PBO), or other materials with similar insulating properties. (See attached diagram.) Figure 20 The solder bump 2006 and the solder bump 2006 include, but are not limited to, lead-containing and lead-free solders, such as lead-tin (Pb-Sn) compositions, while lead-free solders include tin, copper, silver or "SAC" compositions, as well as other eutectic materials having a common melting point and capable of forming conductive solder connections in electronic applications.

[0159] See attached documentFigure 20 The conductive unit 2005 includes an underbump metal (UBM). In some embodiments, the UBM structure includes one or more metal layers, such as a titanium layer and a copper layer. The UBM can be formed using a deposition method. The conductive pillar 2001 can be aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), or other suitable electrically conductive materials. The molding material 1918 can be a polymer composite material, such as a filled epoxy resin, a filled epoxy acrylate, or a polymer with suitable fillers. See Appendix Figure 20 and attached Figure 28 The metal traces 2003, through holes 2004, metal layers 2805, 2806 and 2807 may be Al, copper (Cu), tin (Sn), nickel (Ni), gold (Au) or silver (Ag), or other suitable electrically conductive materials.

[0160] Appendix Figure 33 It is a semiconductor package containing a DRAM module. (Attached) Figure 34 A more detailed diagram of the redistribution structure is shown. (Attached) Figure 35 An embodiment of a metal column is illustrated. (See attached diagram.) Figure 36 Another embodiment of the metal column is illustrated. (See attached diagram) Figure 37 The diagram shows a solder bump located at one end of a metal pillar. (Attached) Figure 38 The diagram shows a solder bump located at one end of a metal pillar. (Attached) Figure 39 This is a schematic diagram of a semiconductor device.

[0161] According to one embodiment, refer to the appendix. Figure 33 Appendix Figure 34 and appendix Figure 36 The semiconductor package 3300 includes a redistribution structure 3302, a processor chip 3303, and metal pillars 3307. The length of the metal pillars 3307 is greater than the thickness of the processor chip 3303. The metal pillars 3307 are disposed beside the processor chip 3303. The processor chip 3303 has an active side 3304 and a back side 3305. The active side 3304 faces a first direction 3306. The active side 3304 of the processor chip 3303 is connected to the redistribution structure 3302.

[0162] The metal pillar 3307 has a first end 3308 and a second end 3309. The metal pillar 3307 is connected to a redistribution structure 3302 of the first end 3308. The first end 3308 faces a first direction 3306. The first end 3308 has a first width 3502. The second end 3309 has a second width 3503. The first width 3502 is greater than the second width 3503. The metal pillar 3307 has a side surface 3314. The side surface 3314 is curved inward.

[0163] The metal pillar 3307 can be formed using a plating method. The material used for the metal pillar 3307 can be Cu, Al, W, Au, solder, or other suitable electrically conductive materials. In some embodiments, the material in the metal pillar 3307 is uniformly distributed. That is, the metal pillar 3307 does not contain a non-uniform distribution formed by a mixture of two different metallic materials. The processor chip 3303 includes at least one graphics processing unit (GPU).

[0164] See attached document Figure 36 The structure of the metal pillar 3307 can provide a large connection area at both ends. This large connection area makes it easier to form electrical contacts at both ends of the metal pillar 3307.

[0165] In some implementations, refer to the appendix. Figure 34 The semiconductor package 3300 further includes a set of metal vias 3406. These metal vias 3406 connect the active side 3304 of the processor chip 3303 and the redistribution structure 3302. The metal vias 3406 can be formed using a plating method. The material of the metal vias 3406 can be copper or aluminum or similar materials.

[0166] See attached document Figure 37 In some embodiments, the semiconductor package 3300 further includes an insulating layer 3601 located on a surface of the semiconductor package 3300. The insulating layer 3601 has at least one opening 3602. The insulating layer 3601 has an outwardly curved surface 3605 surrounding the opening 3602. The insulating layer 3601 may be polyimide, benzocyclobutene (BCB), polybenzobisOxazole (PBO), or other materials with similar insulating properties.

[0167] See attached document Figure 37In some embodiments, the semiconductor package 3300 further includes solder bumps 3603 located on the opening 3602. In some embodiments, the insulating layer 3601 is a polyimide layer. In some embodiments, refer to the attached... Figure 38 The opening 3602 has an opening width 3604. The opening width 3604 is smaller than the second width 3503 of the metal post 3307. In some embodiments, refer to the appendix. Figure 33 The semiconductor package 3300 further includes an adhesive layer 3311 located on the back side 3305 of the processor chip 3303. The adhesive layer 3311 may be a die-attach film (DAF) or similar.

[0168] According to another embodiment, refer to the appendix. Figure 33 Appendix Figure 34 and appendix Figure 36 The semiconductor package 3300 includes a redistribution structure 3302, a processor chip 3303, and metal pillars 3307. The metal pillars 3307 are disposed beside the processor chip 3303. The length of the metal pillars 3307 is greater than the thickness of the processor chip 3303. The processor chip 3303 has an active side 3304 and a back side 3305. The active side 3304 faces a first direction 3306. The active side 3304 of the processor chip 3303 is connected to the redistribution structure 3302.

[0169] The metal column 3307 has a first end 3308, a second end 3309, and a waist portion 3310. The metal column 3307 is connected to the redistribution structure 3302 via the first end 3308. The first end 3308 faces a first direction 3306. The first end 3308 has a first width 3502. The second end 3309 has a second width 3503. The waist portion 3310 has a waist width 3501. The first width 3502 is greater than the waist width 3501. The second width 3503 is greater than the waist width 3501. The metal column 3307 has a side surface 3314. The side surface 3314 is curved inward.

[0170] In some implementations, refer to the appendix. Figure 33 The semiconductor package 3300 further includes a molding material 3312, which is filled between the processor chip 3303 and the metal pillar 3307. The molding material 3312 may be a polymer composite material, such as a filled epoxy resin, a filled epoxy acrylate, or a polymer with appropriate fillers.

[0171] In some embodiments, there is no solder between the processor chip 3303 and the redistribution structure 3302. In some embodiments, an imaginary plane 3313 parallel to the redistribution structure 3302 and passing through one side surface of the processor chip 3303 will not intersect with the solder.

[0172] In some implementations, refer to the appendix. Figure 34 The redistribution structure 3302 further includes a first sublayer 3401, a second sublayer 3402, and a third sublayer 3403. In some embodiments, the redistribution structure 3302 further includes a fourth sublayer 3404 and a fifth sublayer 3405. The materials of the first sublayer 3401, the second sublayer 3402, the third sublayer 3403, the fourth sublayer 3404, and the fifth sublayer 3405 may be polyimide, benzocyclobutene (BCB), polybenzodioxazole (PBO), or other materials with similar insulating properties.

[0173] In some embodiments, the semiconductor package 3300 further includes an insulating layer 3601 located on one surface of the semiconductor package 3300. The insulating layer 3601 has at least one opening 3602. The insulating layer 3601 has an outwardly curved surface 3605 surrounding the opening 3602. In some embodiments, the semiconductor package further includes solder bumps 3603 located on the opening 3602.

[0174] According to another embodiment, refer to the appendix. Figure 33 The semiconductor package 3300 includes a redistribution structure 3302, a processor chip 3303, and metal pillars 3307. The metal pillars 3307 are disposed beside the processor chip 3303. The length of the metal pillars 3307 is greater than the thickness of the processor chip 3303. The processor chip 3303 has an active side 3304 and a back side 3305. The active side 3304 faces a first direction 3306. The active side 3304 of the processor chip 3303 is connected to the redistribution structure 3302.

[0175] See attached document Figure 36The metal column 3307 has a first end 3308, a second end 3309, and a waist portion 3310. The first end 3308 of the metal column 3307 is connected to the redistribution structure 3302. The first end 3308 faces a first direction 3306. The first end 3308 has a first width 3502. The second end 3309 has a second width 3503. The waist portion 3310 has a waist width 3501. The first width 3502 is greater than the second width 3503. The second width 3503 is greater than the waist width 3501. The metal column 3307 has a side surface 3314. The side surface 3314 is curved inward.

[0176] In some embodiments, the semiconductor package 3300 further includes a molding material 3312. The molding material 3312 surrounds the metal pillar 3307. In some embodiments, the metal pillar 3307 is a copper pillar. In some embodiments, the metal pillar 3307 and the molding material 3312 are in direct contact, and there is no insulating layer between the molding material 3312 and the metal pillar 3307. The metal pillar 3307 does not penetrate the silicon substrate.

[0177] In some implementations, refer to the appendix. Figure 34 The redistribution structure 3302 further includes a first sublayer 3401, a second sublayer 3402, and a third sublayer 3403. In some embodiments, the first sublayer 3401 includes a set of first metal traces 3407. The second sublayer 3402 includes a set of second metal traces 3408. The third sublayer 3403 includes a set of third metal traces 3409. In some embodiments, the redistribution structure 3302 further includes a fourth sublayer 3404 and a fifth sublayer 3405.

[0178] In some embodiments, the fourth sublayer 3404 includes a set of fourth metal traces 3410, and the fifth sublayer 3405 includes a set of fifth metal traces 3411. The materials of the first trace 3407, the second trace 3408, the third trace 3409, the fourth trace 3410, and the fifth trace 3411 may be aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), or other suitable electrically conductive materials.

[0179] In some implementations, refer to the appendix. Figure 34The semiconductor package 3300 further includes a molding material 3412 filled between the processor chip 3303 and the first sublayer 3401. In some embodiments, the semiconductor package 3300 further includes a set of metal vias 3406 connecting the redistribution structure 3302 and the processor chip 3303. In some embodiments, the processor chip 3303 further includes a set of metal pads 3413 connected to the set of metal vias 3406.

[0180] According to one embodiment, refer to the appendix. Figure 33 Appendix Figure 34 Appendix Figure 36 Appendix Figure 37 and appendix Figure 39 The semiconductor device 700 includes a redistribution structure 3302, a processor chip 3303, metal pillars 3307, a DRAM module 3315, a printed circuit board 3901, and a flash memory 3902. The metal pillars 3307 are disposed beside the processor chip 3303. The length of the metal pillars 3307 is greater than the thickness of the processor chip 3303. The processor chip 3303 has an active side 3304 and a back side 3305. The active side 3304 faces a first direction 3306. The active side 3304 of the processor chip 3303 is connected to the redistribution structure 3302.

[0181] The metal pillar 3307 has a first end 3308 and a second end 3309. The first end 3308 of the metal pillar 3307 is connected to the redistribution structure 3302. The first end 3308 faces a first direction 3306. The first end 3308 has a first width 3502. The second end 3309 has a second width 3503. The first width 3502 is greater than the second width 3503. The metal pillar 3307 has a side surface 3314. The side surface 3314 is curved inward.

[0182] The DRAM module 3315 is connected to the semiconductor package 3300 via a set of first solder bumps 3603. The printed circuit board 3901 is connected to the redistribution structure 3302 via a set of second solder bumps 3904. The flash memory 3902 is connected to the printed circuit board 3901 via a set of third solder bumps 3905.

[0183] In some embodiments, the first dimension of the first solder bump 3603 is smaller than the second dimension of the second solder bump 3904. In some embodiments, the first dimension of the first solder bump 3603 is smaller than the third dimension of the third solder bump 3905.

[0184] The first solder bump 3603, the second solder bump 3904, and the third solder bump 3905 can be made of any metal or conductive material, such as tin (Sn), lead (Pb), gold (Au), silver (Ag), copper (Cu), zinc (Zn), bismuth (Bi), and their alloys, and optionally a flux material. For example, the solder can be eutectic Sn / Pb, high-lead, or lead-free.

[0185] According to another embodiment, refer to the appendix. Figure 33 Appendix Figure 34 and appendix Figure 35 The semiconductor package 3300 includes a redistribution structure 3302, a processor chip 3303, and metal pillars 3307. The processor chip 3303 has an active side 3304 and a back side 3305. The active side 3304 faces a first direction 3306. The active side 3304 of the processor chip 3303 is connected to the redistribution structure 3302.

[0186] The metal column 3307 has a first end 3308, a second end 3309, and a waist portion 3310. The first end 3308 of the metal column 3307 is connected to the redistribution structure 3302. The first end 3308 faces a first direction 3306. The first end 3308 has a first width 3502. The second end 3309 has a second width 3503. The waist portion 3310 has a waist width 3501. The first width 3502 is smaller than the waist width 3501. The second width 3503 is smaller than the waist width 3501. The metal column 3307 has a side surface 3314. The side surface 3314 is curved outward.

[0187] See attached document Figure 35 In some embodiments, the metal pillar 3307 may be made of solder. The voids for accommodating the solder may be formed using laser apertures or lithography. In some embodiments, the metal pillar 3307 may be made of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), or other suitable electrically conductive materials.

[0188] The metal pillar 3307 in some embodiments of the semiconductor package 3300 has a large connection area at both ends. The metal pillar 3307 in some embodiments of the semiconductor package can be connected to the DRAM module 3315 via molding material 3312. The metal pillar 3307 in some embodiments of the semiconductor package 3300 has a large connection area at the end connected to the redistribution structure 3302.

[0189] Appendix Figure 40 This is a schematic diagram of a semiconductor device. (Attached) Figure 41A more detailed diagram of the redistribution structure is shown. (Attached) Figure 42 These are the top view and cross-sectional view of the conductive via. (Attached) Figure 43 These are the top view and cross-sectional view of the conductive via. (Attached) Figure 44 This is a cross-sectional view of multiple conductive vias. (Attached) Figure 45 This is a cross-sectional view of multiple conductive vias. (Attached) Figure 46 This is a top view of a conductive via. (Attached) Figure 47 This is a top view of a conductive via. (Attached) Figure 48 This is a top view of a conductive via. (Attached) Figure 49 This is a top view of a conductive via.

[0190] According to one embodiment, refer to the appendix. Figure 42 The conductive via 4106 includes a bottom 4201 and an annular flange 4203. The bottom 4201 is cup-shaped. The bottom 4201 has a flange 4202. The annular flange 4203 is connected to the flange 4202 of the bottom 4201. The annular flange 4203 has a first opening 4204.

[0191] In some embodiments, the conductive via 4106 further includes a second opening 4206. The first opening 4204 and the second opening 4206 are symmetrical with respect to the center point 4205 of the bottom 4201. In some embodiments, the conductive via 4106 is a copper via.

[0192] According to another embodiment, refer to the appendix. Figure 41 Appendix Figure 42 and appendix Figure 43 The redistribution structure 4100 includes a first sublayer 4101 and a second sublayer 4102. The first sublayer 4101 includes a first conductive via 4106.

[0193] The second sublayer 4102 is located on the first sublayer 4101. The second sublayer 4102 includes a second conductive via 4107. The shape and structure of the second conductive via 4107 are similar to those of the first conductive via 4106. The second conductive via 4107 includes a bottom 4201 and an annular flange 4203. The bottom 4201 is cup-shaped. The bottom has a flange 4202. The annular flange 4203 is connected to the flange 4202 of the bottom 4201. The annular flange 4203 has at least one opening 4204.

[0194] In some embodiments, the first conductive via 4106 includes a bottom 4201 and an annular flange 4203. The bottom 4201 is cup-shaped. The bottom has a flange 4202. The annular flange 4203 is connected to the flange 4202 of the bottom 4201. The annular flange 4203 has at least one opening 4204.

[0195] In some implementations, refer to the appendix. Figure 41 and attached Figure 42 The redistribution structure 4100 further includes a third sub-layer 4103. The third sub-layer 4103 includes a third conductive via 4108. Similar to the first conductive via 4106, the third conductive via 4108 includes a bottom 4201 and an annular flange 4203. The bottom 4201 is cup-shaped. The bottom 4201 has a flange 4202. The annular flange 4203 is connected to the flange 4202 of the bottom 4201. The annular flange 4203 has at least one opening 4204.

[0196] See attached document Figure 43 The first opening 4204 has a first inner edge 4207. The second opening has a second inner edge 4208. The first inner edge 4207 is along a first axis 4209. The second inner edge 4208 is along a second axis 4210. The conductive via 4106 has an inner edge distance 4211 between the first axis 4209 and the second axis 4210.

[0197] In some implementations, refer to the appendix. Figure 43 Appendix Figure 44 and appendix Figure 45 The first conductive via 4106 has a first inner edge distance 4211. The second conductive via 4107 has a second inner edge distance 4212. The third conductive via 4108 has a third inner edge distance 4213. In some embodiments, the first inner edge distance 4211 is smaller than the third inner edge distance 4213.

[0198] In some implementations, refer to the appendix. Figure 41 and attached Figure 42 The redistribution structure 4100 further includes a fourth sub-layer 4104. The fourth sub-layer 4104 includes a fourth conductive via 4109. The fourth conductive via 4109 is similar to the first conductive via 4106, and includes a bottom 4201 and an annular flange 4203. The bottom 4201 is cup-shaped. The bottom 4201 has a flange 4202. The annular flange 4203 is connected to the flange 4202 of the bottom 4201. The annular flange 4203 has at least one opening 4204.

[0199] In some implementations, refer to the appendix. Figure 41 and attached Figure 42The redistribution structure 4100 further includes a fifth sub-layer 4105. The fifth sub-layer 4105 includes a fifth conductive via 4110. The fifth conductive via 4110 is similar to the first conductive via 4106, including a bottom 4201 and an annular flange 4203. The bottom 4201 is cup-shaped. The bottom 4201 has a flange 4202. The annular flange 4203 is connected to the flange 4202 of the bottom 4201. The annular flange 4203 has at least one opening 4204.

[0200] In some implementations, refer to the appendix. Figure 43 Appendix Figure 44 and appendix Figure 45 The fourth conductive via 4109 has a fourth inner edge distance 4214. The fifth conductive via 4110 has a fifth inner edge distance 4215. In some embodiments, the first inner edge distance 4211 is smaller than the second inner edge distance 4212. In some embodiments, the second inner edge distance 4212 is smaller than the third inner edge distance 4213. In some embodiments, the third inner edge distance 4213 is smaller than the fourth inner edge distance 4214. In some embodiments, the fourth inner edge distance 4214 is smaller than the fifth inner edge distance 4215.

[0201] In some implementations, refer to the appendix. Figure 41 and attached Figure 46 At least one of the first conductive via 4106, the second conductive via 4107, the third conductive via 4108, the fourth conductive via 4109, and the fifth conductive via 4110 is a conductive via 4600. The conductive via 4600 has an opening 4601. The opening 4601 is symmetrical with respect to the center point 4602.

[0202] In some implementations, refer to the appendix. Figure 41 and attached Figure 47 Any one of the first conductive via 4106, the second conductive via 4107, the third conductive via 4108, the fourth conductive via 4109, and the fifth conductive via 4110 can be a conductive via 4700. The conductive via 4700 has an opening 4701. The opening 4701 is symmetrical with respect to a center point 4702. The opening 4702 is rectangular in shape.

[0203] In some embodiments, any one of the first conductive via 4106, the second conductive via 4107, the third conductive via 4108, the fourth conductive via 4109, and the fifth conductive via 4110 can be a conductive via 4800. The conductive via 4800 has an opening 4801 and an opening 4803. The openings 4801 and 4803 are symmetrical with respect to a center point 4802. The opening 4803 is rectangular in shape. The opening 4801 is trapezoidal in shape.

[0204] In some implementations, refer to the appendix. Figure 41 and attached Figure 49 Any one of the first conductive via 4106, the second conductive via 4107, the third conductive via 4108, the fourth conductive via 4109, and the fifth conductive via 4110 can be a conductive via 4900. The conductive via 4900 has an opening 4901 and an opening 4903. The openings 4901 and 4903 are symmetrical with respect to the center point 4902. The opening 4903 is rectangular in shape.

[0205] According to another embodiment, refer to the appendix. Figure 40 Appendix Figure 41 Appendix Figure 42 and appendix Figure 46 The semiconductor device 4000 includes a chip 4001, a redistribution structure 4100, metal pillars 4007, and a memory module 4010. The chip 4001 has an active side 4003 and a back side 4004.

[0206] The redistribution structure 4100 has a front side 4005 and a back side 4006. The front side 4005 of the redistribution structure 4100 is connected to the active side 4003 of the chip 4001 via a set of metal pillars 4301. The redistribution structure 4100 includes a conductive via 4600. The conductive via 4600 has at least one opening 4601.

[0207] The metal pillar 4007 has a first end 4008 and a second end 4009. The first end 4008 of the metal pillar 4007 is connected to the front side 4005 of the redistribution structure 4100. The storage module 4010 is connected to the metal pillar 4007 via solder bumps 4011.

[0208] In some implementations, refer to the appendix. Figure 47 Appendix Figure 48 and appendix Figure 49The redistribution structure 4100 includes a conductive via 4700. The conductive via 4700 has at least one opening 4701. In some embodiments, the redistribution structure 4100 includes a conductive via 4800. The conductive via 4800 has at least one opening 4801. In some embodiments, the redistribution structure 4100 includes a conductive via 4900. The conductive via 4900 has at least one opening 4901.

[0209] In some implementations, refer to the appendix. Figure 49 The opening 4901 has an inner end 4904 and an outer end 4905. The inner end 4904 has a first curvature. The outer end 4905 has a second curvature. The first curvature is greater than the second curvature.

[0210] In some embodiments, the opening 4801 is trapezoidal in shape. The opening 4801 has an inner side 4804 and an outer side 4805. The inner side 4804 has a first width. The outer side 4805 has a second width. The first width is smaller than the second width.

[0211] In some implementations, refer to the appendix. Figure 41 and attached Figure 46 The redistribution structure 4100 includes a first sublayer 4101. The conductive via 4600 is formed in the first sublayer 4101. In some embodiments, the first sublayer 4101 comprises polyimide, and the polyimide fills the opening 4601. In some embodiments, the redistribution structure 4100 further includes a second sublayer 4102. The conductive via 4600 is formed in the second sublayer 4102.

[0212] In some embodiments, the second sublayer 4102 comprises polyimide, and the polyimide fills the opening 4601. In some embodiments, the redistribution structure 4100 further includes a third sublayer 4103. The conductive via 4600 is formed in the third sublayer 4103. In some embodiments, the third sublayer 4103 comprises polyimide, and the polyimide fills the opening 4601.

[0213] In some embodiments, the redistribution structure 4100 further includes a fourth sublayer 4104. The conductive via 4600 is formed in the fourth sublayer 4104. In some embodiments, the fourth sublayer 4104 comprises polyimide, and the polyimide fills the opening 4601. In some embodiments, the redistribution structure 4100 further includes a fifth sublayer 4105. The conductive via 4600 is formed in the fifth sublayer 4105.

[0214] In some embodiments, the fifth sublayer 4105 comprises polyimide, and the polyimide fills the opening 4601. In some embodiments, the semiconductor device 4000 further includes an adhesive layer 4012 located on the back side 4004 of the chip 4001. In some embodiments, the semiconductor device 4000 further includes a molding material 4013 filling the space between the metal pillar 4007 and the chip 4001.

[0215] See attached document Figure 46 Appendix Figure 47 Appendix Figure 48 Appendix Figure 49 and appendix Figure 50 Any one of the openings 4601, 4701, 4801, 4803, 4901, 4903 and 5001 can be implemented as the first conductive through hole 4106, the second conductive through hole 4107, the third conductive through hole 4108, the fourth conductive through hole 4109 and the fifth conductive through hole 4110.

[0216] The materials of the first sublayer 4101, the second sublayer 4102, the third sublayer 4103, the fourth sublayer 4004, and the fifth sublayer 4005 may be polyimide, benzocyclobutene (BCB), polybenzodioxazole (PBO), or other materials with similar insulating properties.

[0217] The materials of the first conductive via 4106, the second conductive via 4107, the third conductive via 4108, the fourth conductive via 4109, and the fifth conductive via 4110 can be aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), or other suitable electrically conductive materials.

[0218] The metal pillar 4007 can be formed using a plating method. The material of the metal pillar 4007 can be Cu, Al, W, Au, solder, or other suitable electrically conductive materials. In some embodiments, the material in the metal pillar 4007 is uniformly distributed. That is, the metal pillar 4007 does not contain a non-uniform distribution formed by a mixture of two different metallic materials.

[0219] The first conductive via 4106, the second conductive via 4107, the third conductive via 4108, the fourth conductive via 4109, and the fifth conductive via 4110 can be formed by plating. The plating method can utilize Cu, Al, W, Au, solder, or other suitable electrically conductive materials.

[0220] In some embodiments, any one of the first sublayer 4101, the second sublayer 4102, the third sublayer 4103, the fourth sublayer 4104, and the fifth sublayer 4105 may include a conductive via 4700. The conductive via 4700 has an opening 4701. The opening 4701 is symmetrical with respect to a center point 4702. The opening 4701 is rectangular in shape. Polyimide fills the opening 4701. In some embodiments, benzocyclobutene (BCB), polybenzobisOxazole (PBO), or other materials with similar insulating properties may be used instead of polyimide.

[0221] In some embodiments, any one of the first sublayer 4101, the second sublayer 4102, the third sublayer 4103, the fourth sublayer 4104, and the fifth sublayer 4105 may include a conductive via 4800. The conductive via 4800 has openings 4801 and 4803. Openings 4801 and 4803 are symmetrical with respect to a center point 4802. Polyimide fills the openings 4801 and 4803. In some embodiments, benzocyclobutene (BCB), polybenzobisOxazole (PBO), or other materials with similar insulating properties may be used instead of polyimide.

[0222] In some embodiments, any one of the first sublayer 4101, the second sublayer 4102, the third sublayer 4103, the fourth sublayer 4104, and the fifth sublayer 4105 may include a conductive via 4900. The conductive via 4900 has openings 4901 and 4903. Openings 4901 and 4903 are symmetrical with respect to a center point 4902. Polyimide fills the openings 4901 and 4903. In some embodiments, benzocyclobutene (BCB), polybenzobisOxazole (PBO), or other materials with similar insulating properties may be used instead of polyimide.

[0223] In some implementations, refer to the appendix. Figure 50 Any one of the first conductive via 4106, the second conductive via 4107, the third conductive via 4108, the fourth conductive via 4109, and the fifth conductive via 4110 can be a conductive via 5000. The conductive via 5000 has an opening 5001. The opening 5001 is symmetrical with respect to the axis 5002. The opening 5001 has a segmental arc shape.

[0224] In some implementations, refer to the appendix. Figure 42 The conductive via 4106 includes a bottom 4201 and an annular flange 4203. The bottom 4201 is cup-shaped. The bottom 4201 has a flange 4202, an inclined wall 4216, and a bottom side 4217. The annular flange 4203 is connected to the flange 4202 of the bottom 4201. The annular flange 4203 has a first opening 4204. In some embodiments, the first thickness of the annular flange 4203 and the second thickness of the bottom side 4217 are substantially the same.

[0225] In some implementations, refer to the appendix. Figure 44 and attached Figure 45 The structures of conductive vias 4107, 4108, 4109, and 4110 are similar to those of conductive via 4106. Conductive via 4107 has an inclined wall 4218 and a bottom side 4219. Conductive via 4108 has an inclined wall 4220 and a bottom side 4221. Conductive via 4109 has an inclined wall 4222 and a bottom side 4223. Conductive via 4110 has an inclined wall 4224 and a bottom side 4225.

[0226] In some implementations, refer to the appendix. Figure 41 and attached Figure 44 The interior 4226 of the cup-shaped conductive via 4106 is filled with insulating material. The insulating material may be polyimide.

[0227] In some implementations, refer to the appendix. Figure 42 There may be stress on the bottom side 4217. The source of this stress may be the folded edge 4203 and the inclined wall 4216. This stress can be released through the openings 4204 and 4206 implemented herein. These openings can also be used to prevent stress-induced voids from forming. Similarly, refer to the appendix... Figure 46 Appendix Figure 47 Appendix Figure 48 Appendix Figure 49 and appendix Figure 50 The openings 4601, 4701, 4801, 4803, 4901, 4903, and 5001 can release stress from the corresponding flange and inclined sidewall. The openings 4601, 4701, 4801, 4803, 4901, 4903, and 5001 can prevent stress-induced voids from forming.

Claims

1. A semiconductor package, characterized in that, include: A redistribution structure having a front surface and a rear surface, the redistribution structure comprising at least three metal layers; A processor chip having an active side and a back side, the active side of the processor chip being connected to the front surface of the redistribution structure, and the active side of the processor chip having a passivation layer. An insulating layer is located between the passivation layer and the redistribution structure; A capacitor located on the rear surface of the redistribution structure, the capacitor being located within the vertical projection of the processor chip; A metal pillar is disposed next to the processor chip. The metal pillar has a first end, a second end, and a waist. The metal pillar is connected to the redistribution structure at the first end. The first end has a first width, the second end has a second width, and the waist has a waist width. The first width is greater than the waist width, and the second width is greater than the waist width. The metal pillar has a side surface that is curved inward. DRAM module; Non-volatile memory module; Printed circuit boards; A first solder bump, through which the redistribution structure is connected to the printed circuit board; The second solder bump connects the non-volatile memory module to the printed circuit board. as well as The third solder bump, through which the DRAM module is connected to the redistribution structure; A recess is formed between the redistribution structure and the processor chip, and there is a horizontal displacement between the chip edge of the processor chip and the outer edge of the insulating layer.

2. The semiconductor package according to claim 1, characterized in that, The middle metal layer of the three metal layers has multiple holes forming a mesh structure. The middle metal layer includes metal traces located between the multiple holes, and the width of the holes is greater than the width of the metal traces.

3. The semiconductor package according to claim 1, characterized in that, The redistribution structure includes multiple conductive vias, each of which includes a bottom and an annular folded edge.

4. An electronic device, characterized in that, include: A redistribution structure having a front surface and a rear surface, the redistribution structure comprising at least three metal layers, the middle metal layer of the three metal layers comprising a plurality of holes forming a mesh structure; A processor chip having an active side and a back side, the active side of the processor chip being connected to the front surface of the redistribution structure, and the active side of the processor chip having a passivation layer. An insulating layer is located between the passivation layer and the redistribution structure; A metal pillar is connected to the front surface of the redistribution structure and disposed next to the processor chip. The metal pillar has a first end, a second end, and a waist. The metal pillar is connected to the redistribution structure at the first end. The first end has a first width, the second end has a second width, and the waist has a waist width. The first width is greater than the waist width, and the second width is greater than the waist width. The metal pillar has a side surface that is curved inward. DRAM module; Non-volatile memory module; Printed circuit boards; A first solder bump, through which the redistribution structure is connected to the printed circuit board; The second solder bump connects the non-volatile memory module to the printed circuit board. as well as The third solder bump, through which the DRAM module is connected to the redistribution structure; Wherein, the area of ​​the redistributed structure is larger than the area of ​​the DRAM module; and A recess is formed between the redistribution structure and the processor chip, and there is a horizontal displacement between the chip edge of the processor chip and the outer edge of the insulating layer.

5. The electronic device according to claim 4, characterized in that, The redistribution structure includes multiple conductive vias, each of which includes a bottom and an annular folded edge.

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