Intelligent Memory Device Test Rack

Abstract

This application relates to a test rack for an intelligent memory device. A test rack includes two or more memory device test boards, where each memory device test board includes two or more memory device test resources. Each of the two or more memory device test boards includes a separate processing device for the memory device test resources assigned to the corresponding memory device test board. The processing device of the test board detects that a first memory subsystem has engaged with the first memory device test resource of the corresponding memory device test board. The processing device identifies a first test to be performed on the first memory device of the first memory subsystem, where the first test includes one or more first test instructions to be executed when performing the first test. The processing device causes the one or more first test instructions to be transmitted to the first memory subsystem, where the first test is performed by executing the one or more first test instructions at the first memory subsystem.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to memory subsystems, and more particularly, to intelligent memory device test racks. Background Art

[0002] A memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally speaking, a host system may utilize the memory subsystem to store data at and retrieve data from the memory devices. Summary of the Invention

[0003] One aspect of the present application relates to a test rack, comprising: a plurality of memory device test boards, wherein each of the plurality of memory device test boards includes a plurality of memory device test resources, and wherein each of the plurality of memory device test boards includes a separate processing device assigned to the plurality of memory device test resources of the corresponding memory device test board, and wherein the separate processing device of each of the plurality of memory device test boards will perform operations including: detecting that a first memory subsystem has engaged a first memory device test resource among the plurality of memory device test resources of the corresponding memory device test board; identifying a first test to be performed on a first memory device of the first memory subsystem, wherein the first test includes one or more first test instructions to be executed when performing the first test; and causing the one or more first test instructions to be transmitted to the first memory subsystem, wherein the first test is performed by executing the one or more first test instructions at the first memory subsystem.

[0004] Another aspect of the present application relates to a system, including: a memory device; and a processing device operatively coupled to the memory device, the processing device performing operations including: receiving, from a requester, a first request for a test to be performed on a memory device of a memory subsystem at a memory device test rack, wherein the memory device test rack includes a plurality of memory device test boards, each memory device test board includes a plurality of memory device test resources, and wherein each of the plurality of memory device test boards includes a separate processing device assigned to the memory device test resources of the corresponding memory device test board; transmitting a second request to each separate processing device to determine which of the memory device test resources of the corresponding memory device test board are available for performing the test on the memory device of the memory subsystem; receiving, from each separate processing device, a response, the response including an indication of whether each of the memory device test resources of the corresponding memory device test board is available for performing the test; determining, based on the responses received from each separate processing device, the available memory device test resources of the memory device test rack for performing the test; and transmitting an indication of the available memory device test resources to the requester.

[0005] Another aspect of the present application relates to a test rack, including: a first memory device test board including a first plurality of memory device test resources and a first processing device, wherein the first processing device is assigned to the first plurality of memory device test resources, and wherein the first processing device is configured to facilitate the execution of a test at a memory device of a memory subsystem coupled to a first memory device test resource of the first plurality of memory device test resources; and a second memory device test board including a second plurality of memory device test resources and a second processing device, wherein the second processing device is assigned to the second plurality of memory device test resources, and wherein the second processing device is configured to facilitate the execution of the test at the memory device of the memory subsystem coupled to a second memory device test resource of the second plurality of memory device test resources in response to the first processing device of the first memory device test board not being available to facilitate the execution of the test. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the following detailed description and the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example computing system including a memory subsystem is shown in accordance with some embodiments of the present disclosure.

[0008] Figure 2A test platform for performing tests on a memory device according to some embodiments of the present disclosure.

[0009] Figure 3 An example section of memory device test resources of a memory device test rack according to some embodiments of the present disclosure.

[0010] Figure 4 An example connection of a memory subsystem to memory device test resources according to some embodiments of the present disclosure.

[0011] Figure 5 A flowchart of an example method of an intelligent memory device test rack according to some embodiments of the present disclosure.

[0012] Figure 6 A flowchart of an example method of a memory subsystem engaged with memory device test resources of an intelligent memory device test rack according to some embodiments of the present disclosure.

[0013] Figure 7 A flowchart of an example method of a resource allocator for each processing device of a test board operatively coupled to a test rack according to some embodiments of the present disclosure.

[0014] Figure 8 A block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Description

[0015] Aspects of the present disclosure relate to an intelligent memory device test rack. The memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices and memory modules are described below in conjunction with Figure 1 Generally speaking, a host system may utilize a memory subsystem that includes one or more components (e.g., memory devices) for storing data. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

[0016] Memory devices used in a memory subsystem can be tested before being used for the memory subsystem. In a conventional testing process, a memory device can be placed in a chamber (e.g., an oven) that tests the memory device under various temperature conditions. For example, at a specific temperature, a chamber can be used to test multiple memory devices at once. The testing process can indicate various operations performed on the memory device at a specific temperature. These operations include but are not limited to read operations, write operations, and / or erase operations. When conducting the testing process, the performance and behavior of the memory device can be observed. For example, performance characteristics (e.g., read or write latency) and reliability of data stored on the memory device can be measured and recorded during and after the testing process. However, since the chamber can only subject the memory device to a single temperature at any given time, testing the memory device at many different temperatures can take a significant amount of time because the testing process needs to be executed for each target test temperature. Additionally, the chamber can only conduct a single testing process at a time. Therefore, if the testing process for the memory device to be tested has many different conditions, performing different tests on the memory device under different operating conditions (e.g., different temperatures) can take a substantial amount of time.

[0017] In some conventional memory device testing systems, a test component including a temperature control component can be used to test a memory device. The temperature control component is used to subject the memory device to specific temperature conditions. In some test components, only the temperature control component is included, and during the memory device testing, the memory device is not affected by any other conditions. A test rack can include multiple test components, where each test component of the test rack is coupled to a local test module. The local test module can facilitate testing each memory subsystem of the test components coupled to the test rack. For example, the local test module enables performing various operations on the memory device at one or more temperature conditions at multiple test components. Since the local test module facilitates testing each memory subsystem of the test components coupled to the test rack, when maintenance or a failure occurs in a single local test module, the entire test rack becomes unusable.

[0018] In some cases, each test rack can include hundreds of test components. The local test module can maintain a record of the multiple test components available for memory device testing. Since the record of the test components can include hundreds of entries (i.e., one entry for each test component), the local test module may need to use a relatively large amount of memory resources to maintain the record. The local test module can refer to the record of available test components in response to each request to perform a memory device test at the memory rack. Each reference to the record can increase the latency of the testing process at the test rack, thereby increasing the latency of the entire test system.

[0019] Aspects of the present disclosure address the above and other deficiencies by providing an intelligent memory device test rack. The distributed test platform may include a plurality of memory device test racks. Each test rack may include a plurality of segments of two or more memory device test resources. Each segment of the test rack may include a processing device. In one example, a segment of the test rack may be a test board of the test rack. The processing device may facilitate testing of a memory device included in a memory subsystem of the memory device test resources coupled to the segment of the test rack. Each test resource includes one or more test condition components, one or more test resource monitoring components, and a memory subsystem interface port. A memory subsystem including a memory device to be tested may be coupled to the test resources of the segment of the test rack by engaging the memory subsystem interface port. In response to detecting that the memory subsystem is coupled to the test resources, the processing device of the segment of the test rack may transmit test instructions including one or more operations to be performed at the memory device. A memory subsystem controller of the memory subsystem may cause the one or more operations to be performed at the memory device. The memory subsystem controller may generate a set of test results for the execution of each operation at the memory device. After the operations are performed at the memory subsystem, the memory subsystem controller transmits the set of test results to the processing device of the segment of the test rack.

[0020] Each test resource includes a test condition component. The test condition component may include at least one of a temperature controller or a voltage controller. The temperature controller is configured to control the temperature of the memory device during testing. The voltage controller is configured to control the voltage of a power signal provided to the memory subsystem during testing. The processing device of the segment of the test rack may cause one or more conditions to occur at the test resources. For example, at least one of the temperature controller or the voltage controller may cause a first condition to occur before initiating testing at the memory device. During testing of the memory device, the temperature controller and / or the voltage controller may cause a second condition to occur. In response to detecting that the second condition has occurred, the memory subsystem controller may generate a second set of test results, where the second set of test results is related to the execution of operations performed at the memory device operating under the second condition.

[0021] Advantages of the present disclosure include, but are not limited to, a reduction in the amount of time a test platform takes to perform tests on a memory device. Since many different tests can be performed at the test platform during the execution of many different operation sequences to test many different conditions (e.g., different temperatures, voltages of different power signals, etc.), the testing of the memory device can be considered more stable because the reliability and performance of the memory device can be tested by performing many different and parallel tests. Additionally, since the processing device of the memory test resources section of the test rack facilitates the testing of the memory device, in the case where the section is unavailable (e.g., for maintenance, etc.), one or more other sections of the test rack can be used for the testing of the memory device. Further, there is no need to maintain a record of available test resources for each test resource of the test rack, and thus no need to refer to the record in response to each request to test a memory device at a test resource of the test rack. Consequently, each test of each memory device can be performed in less time, thereby reducing the overall system latency. The reliability of the memory device is also increased because any possible defects can be identified and subsequently addressed when designing or manufacturing the memory device for customer use.

[0022] Figure 1 FIG. 4 illustrates an example computing system 100 that includes a memory subsystem 110 in accordance with some embodiments of the present disclosure. The memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such devices.

[0023] The memory subsystem 110 may be a storage device, a memory module, or a mixture of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0024] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, an automobile, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, an industrial device, or a networked commercial device), or such a computing device that includes memory and a processing device.

[0025] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is shown. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without an intermediate component), whether wired or wireless, including electrical, optical, magnetic, etc. connections.

[0026] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., NVDIMM controller), and a storage protocol controller (e.g., PCIe controller, SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0027] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include but are not limited to Serial Advanced Technology Attachment (SATA) interface, Peripheral Component Interconnect Express (PCIe) interface, Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), Double Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interface (e.g., DIMM socket interface supporting Double Data Rate (DDR)), etc. The physical host interface can be used to transfer data between the host system 120 and the memory subsystem 110. The host system 120 may further utilize the Non-Volatile Memory Express (NVMe) interface to access components (e.g., memory devices 130) when the memory subsystem 110 is coupled to the host system 120 via the PCIe interface. The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120. As an example, Figure 1 A memory subsystem 110 is shown. Generally, the host system 120 may access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0028] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. The volatile memory device (e.g., memory device 140) may be, but is not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0029] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memories and write-in-place memories, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. The non-volatile memory cross-point array can perform bit storage based on changes in bulk resistance in combination with a stackable cross-gridded data access array. Additionally, compared to many flash-based memories, cross-point non-volatile memory can perform in-situ write operations, where non-volatile memory cells can be programmed in a case where they have been previously erased. NAND-type flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0030] Each of the memory devices 130 can include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), can store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), and quad-level cells (QLC), can store multiple bits per cell. In some embodiments, each of the memory devices 130 can include one or more arrays of, for example, SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device can include an SLC portion, as well as an MLC portion, a TLC portion, or a QLC portion of memory cells. The memory cells of the memory device 130 can be grouped into pages, and a page can refer to a logical unit of the memory device for storing data. In some types of memories (e.g., NAND), pages can be grouped to form blocks.

[0031] Although non-volatile memory devices, such as 3D cross-point non-volatile memory cell arrays and NAND-type flash memories (e.g., 2D NAND, 3D NAND), are described, the memory device 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0032] The memory subsystem controller 115 (or simply referred to as the controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130 and other such operations. The memory subsystem controller 115 can include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-wired) logic to perform the operations described herein. The memory subsystem controller 115 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0033] The memory subsystem controller 115 can include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0034] In some embodiments, the local memory 119 can include memory registers for storing memory pointers, fetched data, etc. The local memory 119 can also include read only memory (ROM) for storing microcode. Although Figure 1 the illustrated memory subsystem 110 shows including the memory subsystem controller 115, in another embodiment of the present disclosure, the memory subsystem 110 does not include the memory subsystem controller 115 and instead can rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0035] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between the logical addresses (e.g., logical block address (LBA), namespace) and physical addresses (e.g., physical block address) associated with the memory device 130. The memory subsystem controller 115 can further include host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can convert commands received from the host system into command instructions for accessing the memory device 130 and convert responses associated with the memory device 130 into information for the host system 120.

[0036] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that can receive an address from the memory subsystem controller 115 and decode the address to access the memory device 130.

[0037] In some embodiments, the memory device 130 includes a local media controller 135 that, in conjunction with the memory subsystem controller 115, performs operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) may manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is an original memory device combined with a local controller (e.g., the local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0038] The memory subsystem 110 includes a test component 113 that performs tests on the memory devices of the subsystem 110 (e.g., the memory device 130). The memory subsystem 110 may be coupled to memory device test resources in a section of a test rack, such as Figure 3 memory device test resources 312A-N. In some embodiments, a section of the test rack may include a test board, such as Figure 2Test board 212. A section of the test rack may include a processing device assigned to facilitate memory device testing for each memory device test resource in the section of the test rack. The test component 113 receives one or more instructions to perform tests at the memory device 130 from the processing device in the section of the test rack. The test instructions may include one or more operations to be performed at the memory device 130, such as read operations, write operations, and / or erase operations. The test component 113 causes the one or more operations to be performed at the memory device 130. During the execution of the one or more operations, the test component 113 collects data related to the execution of the one or more operations. The test component 113 generates a first set of test results based on the data collected during the execution of the one or more operations. In some embodiments, the test component 113 detects that one or more conditions of the memory subsystem 110 have changed during the execution of the one or more operations at the memory device 130. For example, during the execution of the one or more operations, the temperature of the memory subsystem 110 may increase from a first temperature to a second temperature. In some embodiments, a test condition component of the test resources may change the one or more conditions of the memory subsystem 110. In such embodiments, the test component 113 generates a second set of test results based on the data collected during the execution of the one or more operations performed under the second conditions. After the test component 113 generates the first set of test results and / or the second set of test results, the test component 113 transmits each set of test results to the processing device in the section of the test rack.

[0039] Figure 2 FIG. shows a test platform 200 for performing tests on memory devices according to some embodiments of the present disclosure. The test platform 200 may include one or more test racks 210A, 210B, and 210N. Each of the test racks 210A, 210B, and 210N (referred to as test rack 210) may include a plurality of test boards 212, where each test board 212 includes one or more test resources 214 (i.e., test sockets). The test platform 200 may include any number of test racks 210, test boards 212, or test resources 214. As shown, the test board 212 may include one or more test resources 214. Although three test resources 214 are shown, the test board 212 may include any number of test resources 214. Each test resource 214 may include a memory subsystem that has been coupled to the corresponding test resource 214.

[0040] One or more tests may be performed on the memory devices of the memory subsystem in which test resources 214 have been embedded. Each test board 212 may include a separate dedicated processing device for facilitating testing of the memory devices at each test resource 214 of the test board 212. For example, each test board 212 may have a separate processing device instead of sharing one processing device per rack 210. The processing device may receive instructions to be executed when performing the tests. The instructions may include one or more operations to be performed at the memory devices of the memory subsystem. The instructions may also include one or more conditions to be applied to the memory subsystem during the tests.

[0041] The resource allocator component 222 may receive (e.g., from a user) instructions that include a series of one or more operations and / or conditions of tests to be performed on the memory devices of the memory subsystem. Each processing device may maintain a record of the available test resources 214 included in a section of the test rack 210. The resource allocator component 222 may query each processing device of each test rack 210 to determine the specific test resources 214 on different test racks 210 that are available for performing the tests. In some embodiments, the resource allocator component 222 may be provided by a server 220 connected to each processing device of the test board 212. In some embodiments, the server 220 is a computing device or system coupled to each processing device of each test resource 214 via a network.

[0042] In response to the memory subsystem being coupled to a specific test resource 214, the resource allocator component 222 may transmit the received instructions to the processing device of the test board 212 that includes the specific test resource 214. In some embodiments, the resource allocator component 222 may transmit the received instructions to the processing device before the memory subsystem is coupled to the test resource 214. After the tests have been performed on the memory devices of the memory subsystem, the processing device of the test board 212 may transmit data associated with the test results to the resource allocator component 222 for transmission and / or presentation to the requesting user. The data associated with the test results may include data associated with the execution of operations at the memory devices of the memory subsystem. In some embodiments, the data associated with the test results may further include data associated with one or more conditions of the test resources 214 during the test execution.

[0043] In some examples, the processing device of test board 212 may not be available to facilitate testing at test resources 214 of test board 212. For example, test board 212 may lose power, rendering the processing device and each test resource 214 of test board 212 unavailable. In another instance, an error may occur at the processing device of test board 212, thereby rendering each test resource 214 of test board 212 unavailable. Since each test board 212 of each test rack 210 includes a separate processing device assigned to test resources 214 of test board 212, in such a case, test resources 214 of another test board 212 can be used for testing. For example, the processing device of the first test board 212 is not available to facilitate testing of the memory device. A second test board 212 can be identified, where the second test board 212 includes a processing device that can be used to facilitate testing of the memory device. The memory device of the memory subsystem can be tested at test resources 214 of the second test board 212 until the processing device of the first test board 212 is available to facilitate testing.

[0044] Figure 3 is an example section of a memory device test resource 312 of a memory device test rack according to some embodiments of the present disclosure. For example, memory device test resources such as memory device test resources 312A, 312B, and / or 312N (referred to herein as test resources 312) can be Figure 2 an implementation of any of the memory device test resources 214 shown. Each test resource 312 can be included in a section of a test rack such as test rack 210. In some embodiments, the section of test rack 210 can be a test board, such as test board 212. The section of test rack 210 can include a processing device 310 and two or more test resources 312. Each test resource 312 can include one or more test condition components 314, one or more test resource monitoring components 316, and a memory subsystem interface port 318 (referred to herein as port 318).

[0045] As previously described, the processing device 310 can facilitate testing of the memory device 324 of the memory subsystem 320 coupled to test resource 312. The processing device 310 can receive one or more test instructions to be executed when performing a test of the memory device 324. The one or more test instructions can include one or more operations to be performed at the memory device 324. In some embodiments, the one or more test instructions can further include one or more conditions to be applied to the memory subsystem 320 during test execution.

[0046] The memory subsystem 320 may be coupled to the test resource 312 by engaging with the port 318. The port 318 may include a set of one or more serial input / output (IO) pins configured to couple to corresponding serial IO sockets of the memory subsystem 320. The port 318 may further include a set of one or more non-serial IO pins configured to couple to corresponding non-serial IO sockets of the memory subsystem 320. Other details regarding the port 318 are described with respect to Figure 4 described further.

[0047] In response to detecting that the memory subsystem 320 has been coupled to the port 318, the processing device 310 may provide a power signal to the memory subsystem 320 via the port 318 under a first voltage condition. In some embodiments, the power signal may include power. The processing device 310 may further transmit one or more test instructions to the memory subsystem 320 via the port 318, including one or more operations to be performed at the memory device 324.

[0048] In some embodiments, the processing device 310 may cause the memory subsystem 320 to initiate a restart process before performing a test at the memory device 324. In such embodiments, the processing device may transmit a signal to the memory subsystem controller 322 via the port 318, instructing the memory subsystem controller 322 to initiate a restart process. In response to receiving the signal, the memory subsystem controller 322 may initiate a restart process. The memory subsystem controller 322 may initiate a test after initiating the restart process. In other or similar embodiments, the processing device 310 does not transmit a signal to the memory subsystem controller 322 to initiate a restart process, but may transmit a signal to the memory subsystem controller 322 via the port 318, instructing the memory subsystem controller 322 to initiate a test at the memory device 324. The memory subsystem controller 322 may initiate a test at the memory device 324 in response to receiving the signal from the processing device 310 via the port 318.

[0049] Before initiating a test at the memory device 324, the processing device 310 may apply one or more conditions of the test resource 312 to the memory subsystem 320. In some embodiments, the processing device 310 may, according to a resource allocator (e.g., Figure 2The one or more test instructions received by the resource allocator component 222) apply the one or more test conditions to the memory subsystem 320. The test condition component 314 can generate the one or more test conditions. In some other embodiments, the test condition component 314 can include at least one of a temperature controller or a voltage controller. In some embodiments, the temperature controller can include one or more fans configured to cool the ambient air around the memory subsystem embedded in the test resources. In other or similar embodiments, the temperature controller can be a dual Peltier device (e.g., two Peltier devices) that uses the Peltier effect to apply a heating or cooling effect on the surface of the dual Peltier device coupled to the memory subsystem. In another example, voltage conditions can be applied to the memory subsystem 320 by the voltage controller. In some embodiments, the voltage controller can include one or more power supplies configured to provide different voltages to the memory subsystem 320 via the port 318.

[0050] In some embodiments, the one or more test instructions can include a first condition that will be applied to the memory subsystem during test execution. The first condition can be generated by the test condition component 314 before or during test execution at the memory device 324A. In some embodiments, the one or more test instructions can include at least a second condition that will be applied to the memory subsystem 320 during test execution at the memory device 324. The test condition component 314 can cause the first condition to become the second condition during the test of the memory device 324.

[0051] The test resource monitoring component 316 can monitor one or more conditions within the test resource 312. In some embodiments, the test resource monitoring component 316 can monitor the conditions generated by the test condition component 314. For example, the temperature monitoring component can measure the temperature of the test resource 312, where the temperature is generated by the temperature controller of the test resource 312. The test resource monitoring component 316 can include at least one of the following: a temperature monitoring component configured to monitor the temperature of the test resource 312, a voltage monitoring component configured to monitor the voltage of the power signal provided to the memory subsystem 320 via the port 318, a current monitoring component configured to monitor the current of the power signal provided to the memory subsystem 320 via the port 318, or a humidity monitoring component configured to monitor the humidity of the test resource 312.

[0052] As previously described, the memory subsystem controller 322 may receive from the processing device 310 one or more test instructions that include one or more operations to be performed at the memory device 324. In response to receiving an instruction from the processing device 310 to initiate a test at the memory device 324, the memory subsystem controller 322 may cause one or more operations of the received test instructions to be performed at the memory device 324. The memory subsystem controller 322 may generate one or more sets of test results associated with the execution of the one or more operations at the memory device 324. According to the previously described embodiments, the memory subsystem controller 322 may generate at least a first set of test results.

[0053] In some embodiments, the memory subsystem controller 322 may generate at least a second set of test results. When performing the one or more operations at the memory device 324, the memory subsystem controller 322 may detect a change from a first condition to a second condition, where according to the previously described embodiments, the test condition component 314 causes the first condition to become the second condition. In some embodiments, the memory subsystem controller 322 may detect the change in response to receiving a signal from the processing device 310. In other or similar embodiments, the memory subsystem controller 322 may detect the change in response to receiving a signal from a sensor of the memory subsystem 320 that the condition of the memory subsystem 320 has changed from the first condition to the second condition. In response to detecting that the first condition has become the second condition, the memory subsystem controller 322 may generate a second set of test results. The second set of test results may correspond to the execution of the one or more operations of the test instructions under the second condition.

[0054] In some embodiments, two or more memory subsystems 320 may be coupled to respective test resources 312 of a section of a test rack. For example, a first memory subsystem such as memory subsystem 320A may be coupled to a first test resource 312A, and a second memory subsystem 320B may be coupled to a second test resource 312B. A processing device 310 may identify a first test to be performed at a first memory device 324A of the memory subsystem 320A and a second test to be performed at a second memory device 324B of the memory subsystem 320B. In some embodiments, the operations included in the instructions of the first test may be the same as or similar to those included in the instructions of the second test. According to the previously described embodiments, the processing device 310 may transmit the instructions of the first test and the second test to the memory subsystem 320A and the memory subsystem 320B, respectively. In some embodiments, the processing device 310 may transmit a first signal to the first memory subsystem 320A and a second signal to the second memory subsystem 320B. The first memory subsystem controller 322A may cause the received instructions of the first test to be executed in response to receiving the first signal. Similarly, the second memory subsystem controller 322B may cause the received instructions of the second test to be executed in response to receiving the second signal. In some embodiments, the transmission of the first signal and the second signal may cause the instructions of the first test and the second test to be executed simultaneously at the first memory subsystem 320A and the second memory subsystem 320B. According to the previously described embodiments, one or more test results of the first test and the second test may be generated.

[0055] In response to completion of the test at the memory device 324, the memory subsystem controller 322 may transmit one or more sets of test results to the processing device 310. In response to receiving the one or more sets of test results, the processing device 310 may transmit each set of test results to another computing device, such as Figure 2 a server 220, for transmission and / or presentation to a user who requested the test of the memory device 324.

[0056] In some embodiments, the processing device 310 may include a memory component (not shown) configured to store data associated with one or more conditions of the test resources 312 during the execution of the test at the memory device 324. In such embodiments, the processing device 310 may transmit the data associated with the one or more conditions of the test resources 312 during the execution of the test at the memory device 324, as well as each set of test results.

[0057] Figure 4An example connection of a memory device test resource 312 to a memory subsystem 320 in accordance with some embodiments of the present disclosure. Port 318 can be configured to transmit a power signal to the memory subsystem 320. Port 318 can be further configured to transmit and / or receive instructions and data to / from the memory subsystem 320.

[0058] Port 318 can include a first set of pins 412 configured to couple to a first set of sockets 416 of the memory subsystem 320. Each of the first set of pins 412 can be configured to transmit a power signal (e.g., power) to the memory subsystem 320. The first set of sockets 416 can be configured to receive the power signal transmitted via port 318 from the test resource 312. In some embodiments, each of the first set of pins 412 can be a non-serial input / output (IO) pin. In other or similar embodiments, each of the first set of pins 412 can be a pin of a high-speed serial interface. For example, each of the first set of pins 412 can be configured to facilitate a Peripheral Component Interconnect Express (PCIe) protocol and / or a Serial ATA (SATA) protocol.

[0059] In some embodiments, the memory subsystem 320 can be enclosed in a protective cover 420. The protective cover 420 can have an opening 422 for exposing the first set of sockets 416 to the first set of pins 412 of the test resource 312. The first set of pins 412 can be configured to connect to the first set of sockets 416 via the opening 422 of the protective cover 420.

[0060] Port 318 can further include a second set of pins 414. Each of the second set of pins 414 can be configured to transmit instructions and data between the processing device 310 and the memory subsystem 320. In some embodiments, each of the second set of pins 414 can be a serial IO pin. In other or similar embodiments, each of the second set of pins 414 can be a pin of a low-speed serial interface. For example, each of the second set of pins 414 can be configured to facilitate a Universal Asynchronous Receiver / Transmitter (UART) protocol, a System Management Bus (SMB) protocol, or a Serial Wire Debug (SWD) protocol. The memory subsystem 320 can include a second set of sockets 418. In some embodiments, each of the second set of sockets 418 can be a serial IO socket. The second set of sockets 418 can be configured to receive data from and / or transmit data to the processing device 310. In some embodiments, the opening 422 of the protective cover 420 can expose the second set of sockets 418 to the second set of pins 414 of port 318. The second set of pins 414 can be configured to couple to the second set of sockets 418 via the opening 422 of the protective cover 420.

[0061] Figure 5FIG. 500 is a flow chart of an example method of an intelligent memory device test rack in accordance with some embodiments of the present disclosure. Method 500 may be executed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 500 is executed by a processing device of a section of the test rack (e.g., Figure 3 processing device 310). Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood as merely examples, and the illustrated processes may be executed in a different order, and some processes may be executed in parallel. Additionally, in various embodiments, one or more of the processes may be omitted. Accordingly, all of the processes are not required in every embodiment. Other process flows are possible.

[0062] At operation 510, the processing device 310 detects that a first memory subsystem has engaged a first memory device test resource of a section of the memory device test rack. For example, the first memory subsystem may be Figure 3 memory subsystem 320A. The first memory subsystem 320A may engage the first test resource 312A via a memory subsystem interface port (e.g., port 318A). Port 318A may include one or more non-serial input / output (IO) pins, such as Figure 4 a first set of pins 412, configured to couple to corresponding sockets of the first memory subsystem 320A, such as a first set of sockets 416. Each of the first set of pins 412 may be configured to transfer power from the first test resource 312A to the first memory subsystem 320A engaged with the first test resource 312A. Port 318A may further include one or more serial IO pins, such as a second set of pins 414, configured to couple to corresponding serial IO sockets of the first memory subsystem 320A, such as a second set of sockets 418. The one or more serial IO pins of the second set of pins 414 may be configured to transfer data and instructions between the processing device 310 and the first memory subsystem 320A engaged with the first test resource 312A.

[0063] In some embodiments, the first memory subsystem 320A may be enclosed within a protective cover, such as memory subsystem protective cover 420. The protective cover 420 may include an opening 422 configured to expose the first set of sockets 416 and the second set of sockets 418 of the first memory subsystem 320A to the first set of pins 412 and the second set of pins 414 of port 318A. The first set of pins 412 and the second set of pins 414 may be configured to couple to the first set of sockets 416 and the second set of sockets 418 via the opening 422 of the protective cover 420.

[0064] At operation 520, the processing device 310 identifies a first test to be performed on a first memory device (e.g., the first memory device 324A) of the first memory subsystem 320A, where the first test includes one or more first test instructions to be executed when performing the first test. The first memory subsystem 320A may include a first memory subsystem controller, such as the first memory subsystem controller 322A. The first memory subsystem controller 322A may be responsible for performing the test on the first memory device 324A. In some embodiments, the one or more first test instructions include one or more operations to be performed at the first memory device 324A, such as read operations, write operations, and / or erase operations. The test instructions may further include the conditions under which the test is to be performed, referred to as test conditions. For example, the test instructions may include one or more temperature conditions and / or one or more voltage conditions to be applied to the first memory subsystem 320A during the test execution. In some embodiments, the processing device 310 may further identify a second test to be performed on a second memory device (e.g., the memory device 324B of the memory subsystem 320B), where the second test includes one or more second test instructions to be executed when performing the second test.

[0065] Each test condition may be generated by a test condition component 314A of the first test resource 312A. For example, the memory subsystem 320A may be subjected to temperature conditions generated by a temperature controller. The test conditions may be monitored by one or more test resource monitoring components (e.g., the test resource monitoring component 316A) of the first test resource 312A. For example, a temperature monitoring component may monitor the temperature of the first memory subsystem 320A during the test. In another example, a voltage monitoring component may monitor the voltage provided to the first memory subsystem 320A via the port 318A. The test resource monitoring component 316A may further include a current monitoring component configured to monitor the current provided to the first memory subsystem 320A via the port 318A. In other or similar embodiments, the test resource monitoring component 316A may include a humidity monitoring component configured to monitor the humidity of the ambient air around the first memory subsystem 320A during the test.

[0066] At operation 530, processing device 310 causes the one or more first test instructions to be transmitted via port 318A to first memory subsystem 320A, where the first test is performed by executing the one or more first test instructions at first memory subsystem 320A. Memory subsystem controller 322A of first memory subsystem 320A may receive the one or more first test instructions and cause one or more operations of the first test to be performed at first memory device 324A. In some embodiments, processing device 310 causes an operation to be performed at first memory device 324A by transmitting a signal via port 318 to memory subsystem controller 322A that initiates execution of the operation at first memory device 324A. In other or similar embodiments, processing device 310 causes an operation to be performed at first memory device 324A by transmitting a signal that causes memory subsystem controller 322A to initiate a restart process. The one or more operations may be performed in response to first memory subsystem 320A initiating a restart process.

[0067] In some embodiments, according to the previously described embodiments, processing device 310 may transmit instructions for the first test and the second test to memory subsystem 320A and memory subsystem 320B, respectively. In some embodiments, processing device 310 may transmit a first signal to first memory subsystem 320A and a second signal to second memory subsystem 320B. First memory subsystem controller 322A may cause the received instructions of the first test to be executed in response to receiving the first signal. Similarly, second memory subsystem controller 322B may cause the received instructions of the second test to be executed in response to receiving the second signal. In some embodiments, the transmission of the first signal and the second signal may cause the instructions of the first test and the second test to be executed simultaneously at first memory subsystem 320A and second memory subsystem 320B. According to the previously described embodiments, one or more test results of the first test and the second test may be generated.

[0068] Processing device 310 may receive, via port 318, one or more sets of test results associated with the execution of the one or more operations at first memory device 324A. Each set of test results may include at least one of the performance characteristics or behaviors of first memory device 324A during the execution of the test process. The performance characteristics and / or behaviors of first memory device 324A may be observed by memory subsystem controller 322A while the one or more operations are being performed. In response to receiving the one or more sets of test results, processing device 310 may transmit the test results to a server associated with a customer that requested the memory device test, such as Figure 2Server 220. In some embodiments, the processing device 310 may transmit data associated with one or more conditions monitored by the test resource monitoring component 316A of the first test resource 312A, as well as test results. For example, the processing device 310 may transmit data associated with at least one of the following: the temperature of the first test resource 312A during the test of the first memory device 324A, the humidity of the first test resource 312A, the voltage of the power supply signal provided to the first memory subsystem 320A, or the current of the power supply signal provided to the first memory subsystem 320A.

[0069] Figure 6 is a flowchart of an example method 600 of a memory subsystem that engages with a memory device test resource of an intelligent memory device test rack according to some embodiments of the present disclosure. Method 600 may be executed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, the hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 600 is executed by Figure 1 test component 113. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Accordingly, the illustrated embodiments should be understood as merely examples, and the illustrated processes may be executed in a different order, and some processes may be executed in parallel. Additionally, in various embodiments, one or more processes may be omitted. Accordingly, not all processes are required in every embodiment. Other process flows are possible.

[0070] At operation 610, test component 113 detects that a memory subsystem (e.g., Figure 3 memory subsystem 320A) of has engaged with a first memory device test resource (e.g., test resource 312A) among two or more memory device test resources of a section of the memory device test rack. According to the previously described embodiments, memory subsystem 320A may engage with test resource 312A via a memory subsystem interface port (e.g., port 318A).

[0071] At operation 620, test component 113 receives, via port 318A, from a processing device (e.g., processing device 310) of a section of a memory device test rack, one or more test instructions for a test to be performed on a memory device (e.g., memory device 324A) of memory subsystem 320A. According to previously disclosed embodiments, the one or more test instructions may include operations to be performed at memory device 324A. Memory subsystem 320A may cause each operation of the one or more test instructions to be performed at memory device 324A. In some embodiments, memory subsystem 320A may cause each operation to be performed under various test conditions, temperature conditions, or voltage conditions. According to previously described embodiments, the temperature conditions and / or voltage conditions may be applied to memory subsystem 320A by a test condition component (e.g., test condition component 314A) of first test resource 312A.

[0072] At operation 630, test component 113 performs a test of memory device 324 by executing the one or more received test instructions. As previously described, a memory subsystem controller (e.g., memory subsystem controller 322A) may perform the test by causing the one or more operations of the received test instructions to be executed. In some embodiments, memory subsystem controller 322A may perform a test at memory device 324A in response to receiving a signal via port 318A from processing device 310 to initiate a test of memory device 324A. In other or similar embodiments, memory subsystem controller 322A may perform the test in response to initiating a restart process. According to previously described embodiments, memory subsystem controller 322A may initiate a restart process in response to receiving a signal from processing device 310.

[0073] At operation 640, test component 113 generates a first set of test results during test execution. As previously described, the one or more test instructions of the test may include the conditions under which memory subsystem 320A performs a test of the memory device. In some embodiments, the conditions may include at least a first test condition, such as a first temperature condition and / or a first voltage condition. The first set of test results may correspond to the execution of the test under the first test condition. Memory subsystem controller 322A may generate a second set of test results corresponding to the execution of the one or more operations of the test instructions under a second condition.

[0074] At operation 650, test component 113 transmits a first set of test results to processing device 310 via port 318. In some embodiments, according to the previously described embodiments, processing device 310 further transmits a second set of test results generated based on the execution of one or more operations under a second condition. According to the previously described embodiments, in response to receiving the first set of test results and / or the second set of test results, processing device 310 may transmit the received test results to a server, such as Figure 2 server 220 of

[0075] Figure 7 is a flowchart of an example method 700 of a resource allocator for each processing device of a test board operatively coupled to a test rack according to some embodiments of the present disclosure. Method 700 may be executed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 700 is executed by Figure 2 resource allocator 222 of

[0076] At operation 710, the processing logic receives a first request to perform a test on a memory device of a memory subsystem at a memory device test rack. In some embodiments, the memory subsystem may be Figure 3 memory subsystem 320 of Figure 2 and the memory device may be memory device 324. In some embodiments, the memory device test rack may be Figure 3 any one of test racks 210A, B, or C of

[0077] At operation 720, the processing logic transmits a second request to each individual processing device 310 of each test board 212 of the test rack 210 to determine which test resources 312 of the corresponding test board 212 are available for performing a test. At operation 730, the processing logic receives a response from each individual processing device 310, the response including an indication of whether each test resource 312 of the test board 212 is available for performing a test. In some embodiments, the response may include an indication of the test condition components 314 included in each test resource 312 of the test board 212. For example, the processing logic may receive a first response from the first processing device 310 indicating that the first test resource 312 of the first test board 212 is available and that the first test resource 312 includes a temperature controller and a voltage controller. The processing logic may also receive a second response from the second processing device 310 indicating that the second test resource 312 of the second test board 212 is available and that the second test resource 312 includes a temperature controller.

[0078] At operation 740, based on the responses received from each individual processing device, the processing logic determines the available test resources 312 of the test rack 212 for performing a test. In some embodiments, the available test resources 312 may be further determined based on an indication of whether the available test resources 312 include test condition components 314 configured to generate the test conditions included in the first request. According to the previous example, the first request may include one or more operations corresponding to the voltage of the power signal provided to the memory subsystem 320 by the available test resources 312. The processing logic may select the available test resources 312 for testing based on the indication in the first response that the first test resource 312 includes a voltage controller.

[0079] At operation 750, the processing logic transmits an indication of the available test resources 312. In response to receiving the indication of the available test resources 312, the memory subsystem may be coupled to the available test resources 312 for testing. For example, the processing logic may transmit an indication of the available test resources 312 to an operator of the test rack 210. In response to receiving the indication, the operator may couple the memory subsystem 320 to the available test resources 312 for testing.

[0080] In some embodiments, the processing logic may receive one or more operations to be performed during a test of a memory device. The operations may include test conditions generated by a test condition component 314 of the available test resources 312. In some embodiments, the test conditions may include the temperature of the ambient air around the memory subsystem 320 or the voltage of a power signal provided to the memory subsystem 320. The operations may further include one or more of a read operation, a write operation, or an erase operation to be performed at the memory device 324 during the test. In response to receiving the one or more operations, the processing logic may transmit one or more test instructions including the one or more operations to a processing device 310 assigned to the available test resources 312. In some embodiments, the one or more test instructions may be generated by the processing logic. In some embodiments, in response to receiving an indication that the memory subsystem 320 has been coupled to the available test resources 312 by a memory subsystem interface port of the available test resources 312 (e.g., port 318), the one or more test instructions are transmitted to the processing device 310. Figure 8 FIG. shows an example machine of a computer system 800 within which a set of instructions can be executed to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, the computer system 800 may correspond to a host system (e.g., Figure 1 host system 120), which includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 memory subsystem 110), or may be used to perform the operations of a controller (e.g., to execute an operating system to perform the operations corresponding to Figure 1 test component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0081] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a network appliance, a server, a network router, a switch or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Additionally, although a single machine is shown, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods discussed herein.

[0082] The example computer system 800 includes a processing device 802, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 818, which communicate with each other via a bus 830.

[0083] The processing device 802 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processing device 802 can also be one or more dedicated processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 802 is configured to execute instructions 826 for performing the operations and steps discussed herein. The computer system 800 can further include a network interface device 808 that communicates via a network 820.

[0084] The data storage system 818 can include a machine-readable storage medium 824 (also referred to as a computer-readable medium) on which is stored a set or sets of instructions 826 or software that embodies any one or more of the methods or functions described herein. The instructions 826 can also reside, completely or at least partially, within the main memory 804 and / or within the processing device 802 during execution by the computer system 800, the main memory 804, and the processing device 802, which also constitutes a machine-readable storage medium. The machine-readable storage medium 824, the data storage system 818, and / or the main memory 804 can correspond to Figure 1 the memory subsystem 110.

[0085] In one embodiment, the instructions 826 include instructions that implement the functionality corresponding to a test component (e.g., Figure 1 the test component 113). Although the machine-readable storage medium 824 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store a set or sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that is capable of storing or encoding a set of instructions for execution by a machine and that causes the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should therefore be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0086] Some of the foregoing detailed description has been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the most effective way for those skilled in the data processing arts to convey the substance of their work to others skilled in the art. Herein, and in general, an algorithm is conceived of as a self-consistent sequence of operations that produce a desired result. The operations are those requiring physical manipulation of physical quantities. Usually, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, and so forth.

[0087] However, it should be borne in mind that all such and similar terms are associated with appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the registers and memories of the computer system into other data similarly represented as physical quantities within the memory or registers of the computer system or other such information storage systems.

[0088] The present disclosure also relates to apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a computer readable storage medium, such as but not limited to any type of disk including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of media suitable for storing electronic instructions, which are respectively coupled to a computer system bus.

[0089] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the method. The structure for various of these systems will be presented from the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the present disclosure as described herein.

[0090] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium such as read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory components, and the like.

[0091] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A test rack, which comprises: A plurality of memory device test boards, each of which includes a plurality of memory device test resources, wherein each of the plurality of memory device test boards includes a separate processing device assigned to the plurality of memory device test resources of the corresponding memory device test board, and wherein each of the plurality of memory device test resources includes one or more separate test condition components, and wherein the separate processing device of each of the plurality of memory device test boards will perform operations including the following: Detect that one or more input / output (IO) components of a first memory subsystem have engaged with one or more corresponding IO components of a first memory device test resource among the plurality of memory device test resources of the corresponding memory device test board, wherein the first memory subsystem includes a first memory subsystem controller and a first memory device; Identify a first test to be performed on the first memory device of the first memory subsystem, wherein the first test includes a set of first test instructions to be executed when performing the first test, and wherein one or more of the set of first test instructions are for causing one or more first test condition components of the first memory device test resource to generate a first test condition to be applied to the first memory subsystem when the first test is executed at the first memory device; And Cause one or more of the set of first test instructions to be transmitted via the one or more of the IO components of the first memory device test resource to the first memory subsystem controller at the first memory subsystem, wherein the first memory subsystem controller will perform the first test by executing one or more of the set of first test instructions at the first memory device at the first memory subsystem.

2. The test rack according to claim 1, wherein the separate processing device of each of the plurality of memory device test boards will perform operations further including the following: Detect that a second memory subsystem has engaged with a second memory device test resource among the plurality of memory device test resources of the corresponding memory device test board, wherein the second memory subsystem includes a second memory subsystem controller and a second memory device; Identify a second test to be performed on the second memory device of the second memory subsystem, wherein the second test includes a set of second test instructions to be executed when performing the second test, and wherein one or more of the set of second test instructions correspond to causing one or more second test condition components of the second memory device test resource to generate a second test condition to be applied to the second memory subsystem during the execution of the first test; Cause one or more of the set of second test instructions to be transmitted from the second memory device test resource to the second memory subsystem controller at the second memory subsystem; And Transmit a first signal to the first memory subsystem controller and a second signal to the second memory subsystem controller, wherein the first signal and the second signal cause the first memory subsystem controller to execute one or more of the set of first test instructions while causing the second memory subsystem to execute one or more of the set of second test instructions.

3. The test rack according to claim 1, wherein the processing device of each of the plurality of memory device test boards will perform operations further comprising the following: Receive a first set of test results of the first test performed on the first memory device from the first memory subsystem.

4. The test rack according to claim 1, wherein the one or more IO components of the first memory device test resources comprise: A first set of serial input / output IO pins configured to be coupled to corresponding serial IO sockets of the first memory subsystem; And a second set of IO pins configured to be coupled to corresponding non-serial IO sockets of the first memory subsystem, and wherein one or more of the set of first test instructions are transmitted to the first memory subsystem controller via the first set of serial IO pins.

5. The test rack according to claim 1, wherein the processing device of each of the plurality of memory device test boards will perform operations further comprising the following: In response to the one or more first test condition components generating the first test condition during the execution of the first test, receive data associated with one or more conditions within the first memory device test resources from the test resource monitoring component of the first memory device test resources, wherein the one or more conditions correspond to the generated first test condition.

6. The test rack according to claim 5, wherein one or more additional instructions in the set of first test instructions are for causing the one or more first test condition components to generate a second test condition applied to the first memory subsystem when the first test is executed at the first memory device, and wherein the operation further comprises: In response to the one or more first test condition components generating the second test condition applied to the first memory subsystem during the execution of the first test, receive additional data associated with the one or more conditions within the first memory device test resources from the test resource monitoring component, wherein the one or more conditions correspond to the generated second test condition.

7. The test rack according to claim 5, wherein the one or more first test condition components include at least one of a temperature controller or a voltage controller, and the test resource monitoring component includes at least one of a temperature monitoring component, a voltage monitoring component, a current monitoring component, or a humidity monitoring component.

8. A system, which comprises: A memory device; And A processing device operatively coupled to the memory device, the processing device performing operations comprising the following: Receive a first request from a requesting party for a test performed at a memory device test rack on a memory subsystem, where a memory subsystem controller of the memory subsystem is configured to execute one or more instructions from a set of test instructions on the memory device when performing the test, and where the memory device test rack includes a plurality of memory device test boards, each memory device test board including a plurality of memory device test resources, and where each of the plurality of memory device test boards includes a separate processing device assigned to the memory device test resources of the corresponding memory device test board, and where each of the plurality of memory device test resources includes one or more separate test condition components; Transmit a second request to each separate processing device to determine which of the memory device test resources among the plurality of memory device test resources of the corresponding memory device test board are available to facilitate execution of the test on the memory subsystem; Receive a response from each separate processing device, the response including an indication of whether each of the plurality of memory device test resources of the corresponding memory device test board is available to facilitate execution of the test; Based on the responses received from each separate processing device, determine the available memory device test resources of the memory device test rack to facilitate execution of the test; Transmit an indication of the available memory device test resources to the requesting party; And In response to detecting that one or more input / output (IO) components of the memory subsystem have engaged with one or more corresponding IO components of the available memory device test resources, initiate execution of the test, where initiating execution of the test includes causing the one or more separate test condition components of the available memory device test resources to generate one or more test conditions applied to the memory subsystem when the test is executed at the memory device of the memory subsystem.

9. The system of claim 8, wherein the processing device will perform operations further including the following: Receive from the requesting party one or more operations to be performed during the test of the memory device of the memory subsystem; and Transmit the set of test instructions including the one or more operations to the separate processing device assigned to the available memory device test resources.

10. The system of claim 9, wherein the set of test instructions is transmitted to the separate processing device in response to detecting that the one or more IO components of the memory subsystem have engaged with the one or more corresponding IO components of the available memory device test resources.

11. The system of claim 9, wherein the one or more operations correspond to at least one of the test conditions generated by the one or more test condition components of the available memory device test resources during the test or one or more of a read operation, a write operation, or an erase operation performed at the memory device during the test.

12. The system according to claim 11, wherein the test conditions include at least one of a temperature of ambient air around the memory subsystem or a voltage of a power signal provided to the memory subsystem by the available memory device test resources.

13. The system according to claim 8, wherein the first request to perform the test on the memory device includes one or more operations corresponding to the test conditions to be applied to the memory subsystem during the test, and wherein the available memory device test resources are further determined based on an indication of whether the available memory device test resources include the test condition components configured to generate the test conditions during the test.

14. A test rack, which comprises: A first memory device test board, which includes a first plurality of memory device test resources and a first processing device, wherein the first processing device is assigned to the first plurality of memory device test resources, each of the first plurality of memory device test resources includes one or more individual test condition components, and wherein the first processing device is configured to, in response to detecting that one or more input / output (IO) components of the first memory test resource among the plurality of memory test resources have been engaged with one or more corresponding IO components of the memory subsystem, facilitate the execution of a test at the memory device of the memory subsystem by transmitting one or more instructions from a set of test instructions to a memory subsystem controller of the memory subsystem; and A second memory device test board, which includes a second plurality of memory device test resources and a second processing device, wherein the second processing device is assigned to the second plurality of memory device test resources, each of the second plurality of memory device test resources includes one or more additional individual test condition components, and wherein the second processing device is configured to facilitate the execution of the test at the memory device of the memory subsystem coupled to the second memory device test resource among the second plurality of memory device test resources in response to the first processing device of the first memory device test board being unavailable to facilitate the execution of the test.

15. The test rack according to claim 14, wherein the first processing device will perform operations including: Detecting that the one or more IO components of the first memory device test resource among the plurality of memory device test resources have been engaged with the one or more corresponding IO components of the memory subsystem; Identifying the test to be performed on the memory device of the memory subsystem, wherein the set of test instructions associated with the identified test includes one or more instructions for causing one or more first test condition components to generate a first condition to be applied to the memory device of the memory subsystem when the test is executed at the memory device; and Cause one or more instructions in the set of test instructions to be transmitted from the first memory device test resource to the memory subsystem controller via the one or more I / O components of the first memory device test resource, wherein the memory subsystem controller performs the test at the memory subsystem by executing the one or more instructions in the set of test instructions for the memory device.

16. The test rack according to claim 15, wherein the first processing device will perform operations further comprising: Receive a first set of test results of the test performed on the memory device from the memory subsystem controller.

17. The test rack according to claim 15, wherein the first processing device will perform operations further comprising: In response to the one or more first test condition components generating the first test condition during the execution of the test, receive data associated with one or more conditions within the first memory device test resource from the test resource monitoring component of the first memory device test resource, wherein the one or more conditions correspond to the generated first test condition.

18. The test rack according to claim 17, wherein the one or more first test condition components include at least one of a temperature controller or a voltage controller, and the test resource monitoring component includes at least one of a temperature monitoring component, a voltage monitoring component, a current monitoring component, or a humidity monitoring component.

19. The test rack according to claim 14, wherein the first processing device will perform operations comprising: Transmit a notification to the memory device test resource allocator that the first processing device is not available to facilitate the execution of the test at any of the first plurality of memory device test resources.

20. The test rack according to claim 19, wherein the second processing device will perform operations comprising: Receive a request to facilitate the execution of the test at the second memory device test resource among the second plurality of memory device test resources; Detect that the memory subsystem has engaged with the second memory device test resource; Identify the test to be performed on the memory device of the memory subsystem, wherein the set of test instructions associated with the identified test includes one or more instructions for causing one or more second test condition components to generate a second condition for the memory device of the memory subsystem that is applied when the test is performed at the memory device; And Cause one or more instructions in the set of test instructions to be transmitted from the second memory device test resource to the memory subsystem controller, wherein the memory subsystem controller performs the test at the memory subsystem by executing the one or more of the set of test instructions for the memory device.

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