A / D converters and electronic devices

Abstract

The A / D converter (10) according to the present invention is provided with a comparator circuit (21) for judging whether a pixel signal (S VSL ) of the excessive input and threshold voltage (V th ) comparison; and a first transistor (TR17), a control terminal of which receives the comparison result, and the first transistor forms a clamping circuit, wherein the clamping circuit (TR17) is turned on (or off) to make the currents flowing through a first predetermined position (CP1) and a second predetermined position (CP2) connected to each other through the first transistor (TR17) when clamping equal, or to make the voltages at the first predetermined position (CP1) and the second predetermined position (CP2) equal, thereby being able to suppress stripes when an excessive input is applied to the pixel signal line (TR13, TR14, R1) side.

Description

Technical Field

[0001] The present invention relates to an A / D converter and electronic equipment. Background Art

[0002] In recent years, for example, in digital cameras and smartphones, CMOS (Complementary Metal Oxide Semiconductor) image sensors and other imaging devices to which semiconductor microfabrication technology is applied have been widely used.

[0003] In these imaging devices, light incident from a subject is photoelectrically converted in a photodiode arranged in each pixel as a photoelectric conversion element, and then a voltage signal corresponding to the amount of charge obtained by this photoelectric conversion is read via an amplifying transistor and a vertical signal line, and the voltage signal is analog / digital (A / D) converted by an A / D converter having a comparator and output as imaging data.

[0004] When an image of a high-brightness object is captured by an imaging device using a CMOS or other imaging device, strip line noise (so-called streaks) extending in the left-right direction may be generated on the captured image due to power supply noise caused by simultaneous inversion in an A / D conversion section. A technology for suppressing the generation of streaks has been proposed (for example, refer to Patent Document 1).

[0005] [Citation List]

[0006] [Patent Document]

[0007] [Patent Document 1]

[0008] Japanese Patent Laid-Open No. 2005-252529 Summary of the invention

[0009] [Technical issues]

[0010] By the way, in the case of an imaging device using a CMOS or other imaging device to capture an image of a high-brightness subject using a sequential A / D converter, that is, when an excessive input is applied to the pixel signal line, significantly different currents will flow in the differential pair transistors in the preamplifier section included in the A / D conversion section.

[0011] Therefore, even when the low bit is transitioning, there are significantly different currents flowing in the differential pair transistors, and the comparison time of the comparator varies exponentially with respect to the input signal. As a result, the comparison time difference caused by this input differential may appear as stripes.

[0012] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an A / D converter and an electronic device capable of suppressing streaks when an excessive input is applied to a pixel signal line.

[0013] [Technical solution to the problem]

[0014] In order to achieve the above object, an A / D converter according to the present invention includes a comparator circuit and a first transistor. The comparator circuit performs a comparison between a pixel signal inputted with an excessive input and a threshold voltage to determine whether an input pixel signal is inputted. The first transistor has a control terminal and forms a clamp circuit, and the control terminal is configured to receive an input of a result of the comparison.

[0015] When the clamp circuit is turned on (off), the first transistor makes the current flowing in the first predetermined position and the second predetermined position equal, or makes the voltage at the first predetermined position and the second predetermined position equal, and the first predetermined position and the second predetermined position are connected to each other when clamping. Therefore, the generation of stripes can be suppressed.

[0016] [Beneficial effects of the present invention]

[0017] The present invention can suppress streaks by reducing the difference in voltage generated at the output of the differential amplifier. It should be noted that the above-mentioned beneficial effects are only exemplary and not restrictive. The present invention can provide any beneficial effects described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a block diagram showing a configuration example of a solid-state imaging device according to an embodiment.

[0019] Figure 2 It is a diagram showing a configuration example of an embodiment of an A / D converter to which the present technology is applied.

[0020] Figure 3 1 is an explanatory diagram of the relationship between the voltage of a pixel signal and the voltage of a threshold voltage signal in the case of using a 7-bit A / D converter.

[0021] Figure 4 is a diagram showing a detailed configuration of a preamplifier section according to the first embodiment.

[0022] Figure 5 : is a diagram showing a circuit configuration example of a threshold value determination circuit.

[0023] Figure 6 2 is a flowchart showing the processing executed by the threshold value determination circuit (threshold value determination path).

[0024] Figure 7 : is a diagram showing a detailed configuration of a preamplifier section according to a second modification of the first embodiment.

[0025] Figure 8 : is a diagram showing a detailed configuration of a preamplifier section according to a third modification example of the first embodiment.

[0026] Fig. 9 is a diagram showing a detailed configuration of a preamplifier section according to the second embodiment.

[0027] Fig.10 : is a diagram showing a detailed configuration of a preamplifier section according to a first modification example of the second embodiment.

[0028] Fig.11 is a diagram showing a detailed configuration of a preamplifier section according to a third embodiment.

[0029] Fig.12 : is a diagram showing a detailed configuration of a preamplifier section according to a first modification example of the third embodiment.

[0030] Fig.13 is a diagram showing an example of an initial voltage setting circuit.

[0031] Fig.14 is a block diagram showing a schematic configuration of a signal processing section according to a fourth embodiment.

[0032] Fig.15 is a block diagram showing an example of an indirect time-of-flight distance sensor to which the present technology is applied.

[0033] Fig.16 is a circuit diagram showing a configuration example of a pixel according to an embodiment of the present technology. DETAILED DESCRIPTION

[0034] Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that in the following description of the embodiments, the same elements are denoted by the same reference numerals and will not be described in detail.

[0035] (1) First Embodiment

[0036] [Structural Example of Solid-State Imaging Device]

[0037] Figure 1 is a block diagram showing a configuration example of a solid-state imaging device according to an embodiment.

[0038] The solid-state imaging device 1 includes a pixel array section 2 , a row scanning circuit 3 , a signal processing section 4 , a timing control section 5 , a column scanning circuit 6 , and an image processing section 7 .

[0039] In the above configuration, the pixel array section 2 includes a plurality of scanning lines and a plurality of signal lines. Pixel circuits are arranged at intersections between each scanning line and each signal line so that the plurality of pixel circuits are arranged in a two-dimensional matrix.

[0040] Under the control of the timing control section 5 , the row scanning circuit 3 enables any one of the plurality of scanning lines and outputs a pixel signal by driving a row of pixel circuits corresponding to the scanning line in the active state, wherein the pixel circuits constitute the pixel array section 2 .

[0041] The signal processing section 4 includes a plurality of A / D converters described later, and generates pixel data by performing A / D conversion or other signal processing on input pixel signals.

[0042] The timing control section 5 controls the timing of each operation of the row scanning circuit 3 , the signal processing section 4 , and the column scanning circuit 6 .

[0043] Under the control of the timing control unit 5, the column scanning circuit 6 operates synchronously with the operations of the row scanning circuit 3 and the signal processing unit 4, and the column scanning circuit 6 transmits the signals processed in the signal processing unit 4 for each signal line as pixel data sequentially to the image processing unit 7.

[0044] The image processing section 7 performs various types of image processing on image data including a plurality of pixel data.

[0045] In the image processing, for example, demosaic processing, white balance processing, and the like are performed.

[0046] Then, the image data after the image processing is sent to an external recording device such as an image memory.

[0047] The foregoing description assumes that the image processing section 7 is arranged in the solid-state imaging device 1. However, alternatively, the image processing section 7 may also be separately arranged outside the solid-state imaging device 1.

[0048] Furthermore, the circuits in the solid-state imaging device 1 may be respectively arranged on a single semiconductor substrate or may be dispersedly arranged on a plurality of stacked semiconductor substrates.

[0049] [Structural Example of A / D Converter]

[0050] Figure 2 It is a diagram showing a configuration example of an embodiment of an A / D converter to which the present technology is applied.

[0051] like Figure 2 As shown, the A / D converter 10 includes a local reference voltage generating section 11 , a D / A converting section 12 , a preamplifier section 13 , a comparator section 14 , a successive conversion logic section 15 , and a rotation logic section 16 .

[0052] A plurality of local reference voltage generating sections 11 are provided in the signal processing section 4. The local reference voltage generating sections 11 generate and output a plurality of types of local standard reference signals (local standard reference voltages) Sref to be used in the A / D converter 10 based on the standard reference signal (standard reference voltage) STref supplied from the reference voltage generating section 5A.

[0053] The D / A converter 12 uses the various types of local standard reference signals Sref generated by the local reference voltage generator 11 to convert the control data D under the control of the successive conversion logic and the rotation logic described later. CNT Perform digital / analog (D / A) conversion and output threshold voltage signal S th .

[0054] The preamplifier section 13 performs an operation on the threshold voltage signal S th and the pixel signal input terminal T from the pixel array section 2 VSL The input pixel signal S VSL Amplification is performed and differential signals OUTP and OUTN are output.

[0055] The comparator section 14 compares the differential signals OUTP and OUTN output from the preamplifier section and outputs a comparison result D CMP .

[0056] The successive conversion logic unit 15 converts the comparison result data D CMP Output is used to generate a threshold voltage signal S th In addition, the successive conversion logic unit 15 stores the input comparison result data D CMP , and based on the stored comparison result data D CMP From the output terminal TD OUT Output pixel data D VSL Pixel data D VSL Represents the pixel signal S VSL The result of analog / digital (A / D) conversion.

[0057] The rotation logic unit 16 generates a rotation signal based on the pseudo-random number data D provided from the pseudo-random number generating unit 4B provided in the signal processing unit 4. PN , generate data D ROT .

[0058] [Overview of A / D Converter Operation]

[0059] Next, the operation of the A / D converter 10 will be outlined.

[0060] The A / D converter 10 generates pixel data D representing the A / D conversion result. VSL The most significant bit to the least significant bit is compared successively to set the value of all bits to "1" or "0".

[0061] First, the successive conversion logic section 15 performs initial value setting by setting all bits to the center voltage (Vrc).

[0062] In parallel with the above operation, the pseudo-random number generator 4B generates the pseudo-random number data D PN Provided to the rotation logic 16.

[0063] The preamplifier section 13 amplifies the input pixel signal S VSL With the threshold voltage signal S th The differential signals OUTP and OUTN are generated by the difference between them, and the generated differential signals OUTP and OUTN are output to the comparator section 14.

[0064] The comparator section 14 compares the voltages of the differential signals OUTP and OUTN, and outputs the result as comparison result data D. CMP Output to the successive conversion logic unit 15.

[0065] The successive conversion logic unit 15 converts the comparison result data D CMP The result of the above operation generates the control data D for the D / A converter 12. SAR and D ROT , and store the comparison result data D CMP .

[0066] The D / A converter 12 uses the various local standard reference signals Sref generated by the local reference voltage generator 11 to convert the input control data D CNT Perform digital / analog (D / A) conversion and convert the threshold voltage signal S th The signal is output to the preamplifier section 13 .

[0067] Subsequently, in the same manner as described above, all bits from the most significant bit (MSB) to the least significant bit (LSB) are successively compared, and the successive conversion logic section 15 determines and stores the values ​​of all bits.

[0068] When the values ​​of all bits are determined, the stored data is output as A / D conversion result data from the output terminal TD OUT Output.

[0069] [Problems with conventional A / D converters]

[0070] The following is a detailed description of the problems of the conventional technology regarding the A / D converter.

[0071] Figure 3 : is an explanatory diagram of the relationship between the voltage of the pixel signal and the voltage of the threshold voltage signal in the case of using a 7-bit A / D converter as an example.

[0072] about Figure 3 The pixel signal S VSL , the lower side indicates a low voltage state (white side), and the upper side indicates a high voltage state (black side). The horizontal axis indicates time.

[0073] Reference Figure 3 , assuming that the xth bit at the time of A / D conversion is specified by (x). For example, the input signal at the time of MSB conversion corresponds to (7), and the input signal at the time of LSB conversion corresponds to (1).

[0074] Figure 3 (a) shows the pixel signal S at the beginning of the comparison VSL The voltage and threshold voltage signal S th The difference between the voltages is large but within the A / D conversion range. Figure 3 (b) shows the pixel signal S at the beginning of the comparison VSL The voltage and threshold voltage signal S th The difference between the voltages is small and within the A / D conversion range. Figure 3 (c) shows the pixel signal S VSL The voltage and threshold voltage signal S th The difference between the voltages is very large (excessive amplitude) and exceeds the A / D conversion range.

[0075] The successive conversion type A / D converter uses the comparison result of the comparator to generate a signal close to the pixel signal S VSL Therefore, when the pixel signal is in the range ( Figure 3 In the case of (a) and (b)), when LSB conversion (1) is performed, the pixel signal S VSL With the threshold voltage S th The difference between them is small and no greater than 1LSB.

[0076] In contrast, Figure 3 In the case of the example shown in (c), even when the LSB is converted (1), the pixel signal S VSL With the threshold voltage S th The difference between is also large and greater than 1 LSB. Since the comparison time of the comparator varies exponentially with respect to the input signal, the comparison time difference caused by this input differential appears as a stripe.

[0077] [Detailed Configuration of Comparator Section According to First Embodiment]

[0078] Figure 4is a diagram showing a detailed configuration of the preamplifier section 13 according to the first embodiment.

[0079] The preamplifier section 13 includes a P-channel MOS transistor TR11, a P-channel MOS transistor TR12, and a constant current source CC. The P-channel MOS transistor TR11 is configured to form a diode connection in a manner that a source terminal S is connected to a power line AVD and a gate terminal G is connected to a drain terminal D. The P-channel MOS transistor TR12 is configured in a manner that a source terminal S is connected to a power line AVD and a gate terminal G is connected to a gate terminal G of the P-channel MOS transistor TR11, so that the P-channel MOS transistor TR12 cooperates with the P-channel MOS transistor TR11 to function as a current mirror circuit. One end of the constant current source CC is connected to the drain terminal D of the P-channel MOS transistor TR11, and the other end is connected to the ground line AVS.

[0080] The preamplifier section 13 includes a P-channel MOS transistor TR13, a P-channel MOS transistor TR14, and a first load resistor R1. The P-channel MOS transistor TR13 outputs the pixel signal S VSL The first load resistor R1 is configured in such a manner that the source terminal S is connected to the drain terminal D of the P-channel MOS transistor TR12 and the source terminal S is connected to the drain terminal D of the P-channel MOS transistor TR12. The P-channel MOS transistor TR14 is configured in such a manner that the source terminal S is connected to the drain terminal D of the P-channel MOS transistor TR13 and the bias voltage BIAS is input to the gate terminal G, so that the P-channel MOS transistor TR14 functions as a cascode circuit. One end of the first load resistor R1 is connected to the drain terminal D of the P-channel MOS transistor TR14, and the other end is connected to the ground line AVS.

[0081] In addition, the preamplifier section 13 includes a P-channel MOS transistor TR15, a P-channel MOS transistor TR16, and a second load resistor R2. The P-channel MOS transistor TR15 is connected to the input terminal of the amplifier 13 by a threshold voltage signal S th The P-channel MOS transistor TR12 is configured in such a manner that the source terminal S is connected to the drain terminal D of the P-channel MOS transistor TR15 and the bias voltage BIAS is input to the gate terminal G, so that the P-channel MOS transistor TR16 functions as a cascode amplifier circuit. One end of the second load resistor R2 is connected to the drain terminal D of the P-channel MOS transistor TR16, and the other end is connected to the ground line AVS.

[0082] In addition, the preamplifier section 13 includes a threshold determination circuit 21. One input terminal of the threshold determination circuit 21 is connected to the drain terminal of the P-channel MOS transistor TR14 to receive an input of the first output signal OUTP. The other input terminal of the threshold determination circuit 21 is connected to the drain terminal of the P-channel MOS transistor TR16 to receive an input of the second output signal OUTN. The threshold determination circuit 21 compares the first output signal OUTP with the second output signal OUTN, and outputs a determination result signal S EV .

[0083] In addition, the preamplifier section 13 includes an N-channel MOS transistor TR17. The N-channel MOS transistor TR17 is configured in such a manner that a drain terminal D is connected to a connection point CP1 between a drain terminal D of a P-channel MOS transistor TR13 and a source terminal of a P-channel MOS transistor TR14, and a source terminal S is connected to a connection point CP2 between a drain terminal D of a P-channel MOS transistor TR15 and a source terminal of a P-channel MOS transistor TR16. When the discrimination result signal S output from the threshold judgment circuit 21 is EV When the voltage is input to the gate terminal G of the N-channel MOS transistor TR17, the N-channel MOS transistor TR17 functions as a switching element (switch) that short-circuits between the connection points CP1 and CP2.

[0084] In the above configuration, the N-channel MOS transistor TR17 forms a clamp circuit.

[0085] Furthermore, the P-channel MOS transistor TR13 , the P-channel MOS transistor TR14 , the P-channel MOS transistor TR15 , the P-channel MOS transistor TR16 , the first load resistor R1 , and the second load resistor R2 form a differential amplifier DA.

[0086] In the pixel signal S VSL When the pixel signal S is within the predetermined A / D conversion range, at the time of LSB conversion, VSL The voltage and threshold voltage signal S th Therefore, the difference between the first output signal OUTP and the second output signal OUTN output from the preamplifier section 13 is also small.

[0087] On the other hand, in the pixel signal S VSL In the case of an excessive input signal exceeding the predetermined A / D conversion range and the N-channel MOS transistor TR17 being turned off (put in an open state), the difference between the first output signal OUTP and the second output signal OUTN output from the preamplifier section 13 remains large even at the time of LSB conversion.

[0088] In the above case, when the N-channel MOS transistor TR17 is turned on (put in an off state), the currents flowing in the load resistors R1 and R2 can be made equal to each other so that the first output signal OUTP and the second output signal OUTN are at the same potential.

[0089] Therefore, the switching time of the comparator section 14 connected to the subsequent stage can be made the same. This makes it possible to reduce the degree of degradation due to streaks caused by the difference in switching speed of the comparator.

[0090] The following describes a method for determining an excessively large input signal.

[0091] Before the normal A / D conversion process, the threshold voltage S th Set to the excessive input judgment voltage V th , and then use the threshold determination circuit 21 to compare the pixel signal S VSL The voltage of the over-input judgment voltage V th The comparison result indicates that the pixel signal S VSL The voltage is lower than the excessive input judgment voltage V th (The excessive input judgment voltage V th When the pixel signal S VSL Out of A / D conversion range (pixel signal S VSL is an excessive input signal). Therefore, the N-channel MOS transistor TR17 is turned on (put in an off state).

[0092] On the other hand, in the pixel signal S VSL The voltage is higher than the excessive input judgment voltage V th (The excessive input judgment voltage V th In the case of a lower value, the pixel signal S VSL Therefore, the N-channel MOS transistor TR17 remains turned off (in an open state).

[0093] Subsequently, a normal A / D conversion process is performed.

[0094] [Circuit Configuration Example of Comparator Section]

[0095] Next, a circuit configuration example of the comparator section 14 will be described.

[0096] Figure 5 2 is a diagram showing a circuit configuration example of the comparator circuit 14 .

[0097] like Figure 5 As shown, the comparator section 14 is roughly divided into an amplifying section (amplifying stage) 14A and a latch section 14B.

[0098] The amplifying section 14A includes a P-channel MOS transistor TR21, an N-channel MOS transistor TR22, a P-channel MOS transistor TR23, an N-channel MOS transistor TR24, and an N-channel MOS transistor TR25. The P-channel MOS transistor TR21 is configured in such a manner that a source terminal S is connected to a digital power supply DVD and a gate terminal G is connected to a clock signal line CLK. The N-channel MOS transistor TR22 is configured in such a manner that a drain terminal D is connected to a drain terminal of the P-channel MOS transistor TR21 and a gate terminal G is connected to a positive input terminal INP. The P-channel MOS transistor TR23 is configured in such a manner that a source terminal S is connected to a digital power supply DVD and a gate terminal is connected to a clock signal line CLK. The N-channel MOS transistor TR24 is configured in such a manner that a drain terminal D is connected to a drain terminal D of the P-channel MOS transistor TR23 and a gate terminal G is connected to a negative input terminal INN. The N-channel MOS transistor TR25 is configured in such a manner that a drain terminal D is commonly connected to source terminals S of the N-channel MOS transistor TR22 and the N-channel MOS transistor TR24 , a gate terminal G is connected to the clock signal line CLK, and a source terminal S is connected to the digital ground DVS.

[0099] Furthermore, the amplifying section 14A includes inverters TR31 and TR32 and inverters TR33 and TR34. These inverters cooperate with each other to achieve signal amplification.

[0100] The latch section 14B includes a P-channel MOS transistor TR41, a P-channel MOS transistor TR42, an N-channel MOS transistor TR43, and an N-channel MOS transistor TR44. The P-channel MOS transistor TR41 is configured in such a manner that a source terminal S is connected to a digital power supply DVD and a gate terminal G is connected to a clock signal line CLK. The P-channel MOS transistor TR42 is configured in such a manner that a source terminal S is connected to a digital power supply DVD and a drain terminal D is connected to a drain terminal D of the P-channel MOS transistor TR41. The N-channel MOS transistor TR43 is configured in such a manner that a drain terminal D is connected to a drain terminal D of the P-channel MOS transistor TR41 and a drain terminal D of the P-channel MOS transistor TR42 and a gate terminal G is connected to a drain terminal D of the P-channel MOS transistor TR31 and a drain terminal D of the N-channel MOS transistor TR32. The N-channel MOS transistor TR44 is configured in such a manner that a drain terminal D is connected to a source terminal S of the N-channel MOS transistor TR43 , a source terminal S is connected to a digital ground DVS, and a gate terminal G is connected to a gate terminal G of the P-channel MOS transistor TR42 .

[0101] In addition, the latch section 14B includes a P-channel MOS transistor TR45, a P-channel MOS transistor TR46, an N-channel MOS transistor TR47, and an N-channel MOS transistor TR48. The P-channel MOS transistor TR45 is configured in such a manner that a source terminal S is connected to a digital power supply DVD and a gate terminal G is connected to a clock signal line CLK. The P-channel MOS transistor TR46 is configured in such a manner that a source terminal S is connected to a digital power supply DVD, a drain terminal D is connected to a drain terminal D of the P-channel MOS transistor TR45, and a gate terminal G is connected to a drain terminal D of the P-channel MOS transistor TR42 and a drain terminal D of the N-channel MOS transistor TR43. The N-channel MOS transistor TR47 is configured in such a manner that a drain terminal D is connected to a drain terminal D of the P-channel MOS transistor TR45 and a drain terminal D of the P-channel MOS transistor TR46, and a gate terminal G is connected to a drain terminal D of the P-channel MOS transistor TR33 and a drain terminal D of the N-channel MOS transistor TR34. The N-channel MOS transistor TR48 is constructed in such a manner that a drain terminal D is connected to a source terminal S of the N-channel MOS transistor TR47 , the source terminal S is connected to the digital ground DVS, and a gate terminal G is connected to a gate terminal G of the P-channel MOS transistor TR46 .

[0102] In the above configuration, the comparator section 14 outputs the comparator output OUTP according to the signals INP and INN input when the clock signal line CLK rises.

[0103] [Operation of Threshold Decision Circuit]

[0104] Figure 6 : is a flowchart showing the processing executed by the excessive input determination circuit (threshold value determination circuit).

[0105] First, the threshold voltage S th Set to the excessive input judgment voltage V for judging excessive input th (Step S11).

[0106] In the above example, voltage setting can be performed by expanding the function of the D / A conversion section 12 or by providing a separate setting circuit.

[0107] Next, the threshold determination circuit 21 is used to convert the pixel signal S VSL With the excessive input judgment voltage V th Compare and determine the pixel signal S VSL Is it lower than the excessive input judgment voltage V th (Pixel signal S VSL Is it an excessive input that exceeds the range of the A / D converter 10) (step S12). Alternatively, the threshold determination circuit may use the comparator section 14 for determination.

[0108] The determination result in step S12 indicates that the pixel signal S VSL When the excessive input (excessive voltage input) is higher than the excessive input judgment voltage (step S12 is No), the threshold judgment circuit 21 judges that the excessive input (excessive voltage input) is not applied to the gate terminal G (the gate terminal is one input terminal of the differential amplifier) ​​of the P-channel MOS transistor TR13, and outputs the judgment result signal S of the "L" level. EV The voltage is output to the gate terminal G of the N-channel MOS transistor TR17.

[0109] Therefore, the N-channel MOS transistor TR17 remains off (is placed in an on state) (step S14).

[0110] As a result, the differential amplifier DA maintains a normal operating state.

[0111] In contrast, the determination result in step S12 indicates that the pixel signal S VSL Lower than the excessive input judgment voltage V th (Pixel signal S VSL In the case where the excessive input (excessive voltage input) exceeds the range of the A / D converter 10) (step S12 is YES), the threshold value determination circuit 21 determines that the excessive input (excessive voltage input) is applied to the gate terminal G of the P-channel MOS transistor TR13 (the gate terminal is one input terminal of the differential amplifier DA), and generates the determination result signal S at the "H" level. EV The voltage is output to the gate terminal G of the N-channel MOS transistor TR17.

[0112] Therefore, the N-channel MOS transistor TR17 is turned on (put into an off state) (step S13).

[0113] As a result, a short circuit is formed between the connection points CP1 and CP2, so that the output voltages OUTP and OUTN are substantially equal to each other.

[0114] Therefore, even if an excessive input voltage is applied, the value of the voltage difference input to the comparator section 14 is extremely small. Therefore, even when an excessive input operation is performed, the input to the comparator section 14 can be reduced, so that the conversion speed can be made the same as the conversion speed of other pixel signals. Therefore, the degradation caused by streaks can be reduced.

[0115] [Advantageous Effects of the First Embodiment]

[0116] As described above, even when an excessive input is applied to the differential amplifier DA, the first embodiment can make the response time required for low-bit conversion the same as when no excessive input is applied to the differential amplifier DA. Therefore, degradation caused by streaks can be reduced.

[0117] [First Modification of the First Embodiment]

[0118] In the above configuration, it is assumed that the primary threshold voltage S th Set to excessive input judgment voltage V th , and outputs the determination result of the threshold determination circuit 21 directly to the gate terminal G of the N-channel MOS transistor TR17.

[0119] However, the threshold voltage S may not be th Set to the primary excessive input judgment voltage V th Instead, an alternative configuration may be adopted: A / D conversion is performed successively as a normal operation, and when the judgment result of the comparator section 14 for several consecutive high-order bits is "H", it is judged as an excessive input, and the NMOS transistor TR17 is turned on. By adopting the above-mentioned alternative configuration, it is not necessary to set the threshold voltage S th Set to excessive input judgment voltage V th And make an over-large input judgment. Therefore, the required A / D conversion time is only used for the actual A / D conversion, and no extra A / D conversion time is required. Therefore, the processing speed is improved.

[0120] When the above-described configuration is employed, the operation according to the first embodiment can be realized by simply changing the N-channel MOS transistor TR17 and the wiring from the successive conversion logic section 15 to the gate terminal G and changing the control program of the successive conversion logic section 15 .

[0121] [Second Modification of the First Embodiment]

[0122] Figure 7 : is a diagram showing a detailed configuration of a preamplifier section according to a second modification of the first embodiment.

[0123] exist Figure 7 In, with Figure 4 Elements which are identical to those shown are denoted by the same reference numerals as corresponding elements.

[0124] The preamplifier section 13A according to the second modification of the first embodiment is different from the preamplifier section 13 according to the first embodiment in that the former includes a comparison determination circuit 25 and an N-channel MOS transistor TR17A. The comparison determination circuit 25 converts the pixel signal S VSL The voltage is compared with the standard voltage V corresponding to the predetermined excessive input state th Compare and output the judgment result signal S EVAThe N-channel MOS transistor TR17A is constructed in such a manner that the drain terminal D is connected to the connection point CP11 between the drain terminal D of the P-channel MOS transistor TR14 and the resistor R1, and the source terminal S is connected to the connection point CP12 between the drain terminal D of the P-channel MOS transistor TR16 and the resistor R2. EVA When the voltage is input to the gate terminal G of the N-channel MOS transistor TR17A, the N-channel MOS transistor TR17A functions as a switch that short-circuits the connection points CP11 and CP12.

[0125] The second modification of the first embodiment is further configured such that in the pixel signal S VSL The voltage is lower than the standard comparison voltage V corresponding to the predetermined excessive input state th In the case of , the N-channel MOS transistor TR17A is turned on (off). Therefore, a short circuit is formed between the connection points CP11 and CP12, so that the voltages of the preamplifier outputs OUTP and OUTN are substantially equal to each other. Therefore, the voltage difference input to the comparator section 14 can be reduced.

[0126] [Third Modification of the First Embodiment]

[0127] Figure 8 : is a diagram showing a detailed configuration of a preamplifier section according to a third modification example of the first embodiment.

[0128] exist Figure 8 In, with Figure 4 Elements which are identical to those shown are denoted by the same reference numerals as corresponding elements.

[0129] The preamplifier section 13B according to the third modification of the first embodiment is different from the preamplifier section 13 according to the first embodiment in that the former includes VSL The voltage is compared with the standard voltage V corresponding to the predetermined excessive input state th Compare and output the judgment result signal S EVB The comparison determination circuit 25 is inputted, and the determination result of the comparison determination circuit 25 is inputted to the gate terminal G of the N-channel MOS transistor TR17B.

[0130] The third modification of the first embodiment is further configured such that in the pixel signal S VSL The voltage is lower than the standard comparison voltage V corresponding to the predetermined excessive input state th In the case of , the N-channel MOS transistor TR17B is turned on (off). Therefore, the voltages of the preamplifier outputs OUTP and OUTN are substantially equal to each other. Therefore, the voltage difference input to the comparator section 14 can be reduced.

[0131] [Fourth Modification of the First Embodiment]

[0132] In the foregoing description, it is assumed that the MOS transistor at the input stage of the preamplifier section 13B is configured as a P-channel MOS transistor. However, alternatively, the MOS transistor at the input stage of the preamplifier section 13B may also be configured as an N-channel MOS transistor.

[0133] (2) Second Embodiment

[0134] [Detailed Configuration of Comparator Section According to Second Embodiment]

[0135] Fig. 9 is a diagram showing a detailed configuration of a preamplifier section according to the second embodiment.

[0136] exist Fig. 9 In, with Figure 4 Elements identical to those of the illustrated first embodiment are denoted by the same reference numerals as corresponding elements.

[0137] The preamplifier section 13C according to the second embodiment is different from the preamplifier section 13 according to the first embodiment in that the former includes an N-channel MOS transistor TR51. The N-channel MOS transistor TR51 functions as a diode instead of the N-channel MOS transistor TR17 and the threshold value determination circuit 21.

[0138] In the above construction, the N-channel MOS transistor TR51 is constructed in the following manner: the drain terminal D is connected to the connection point CP11 between the drain terminal D of the P-channel MOS transistor TR14 and the resistor R1, the source terminal S is connected to the connection point CP12 between the drain terminal D of the P-channel MOS transistor TR16 and the resistor R2, and the gate terminal G is connected to the connection point CP11.

[0139] In the pixel signal S VSL The voltage and threshold voltage signal S th When the difference between the voltages of the first output signal OUTP and the second output signal OUTN is large and the difference between the first output signal OUTP and the second output signal OUTN is large, the N-channel MOS transistor TR51 is turned on (put into a conductor state). Therefore, the differential voltage between the first output signal OUTP and the second output signal OUTN can be reduced to the threshold voltage of the N-channel MOS transistor TR51 that acts as a diode. Compared with the first embodiment, the above method does not require an excessively large comparison time for input determination and a feedback signal provided from the successive conversion logic unit 15.

[0140] In addition, since only the pixel signal S VSLTherefore, another feature of the second embodiment is that the gate terminal G of the N-channel MOS transistor TR51, which functions as a diode, is connected to the pixel signal S VSL side.

[0141] However, in order to match the load capacity, it is also possible to configure an N-channel MOS transistor the same as TR51 in such a manner that the gate and the drain are connected to the CP12 side and the source is connected to the CP11 side.

[0142] [Detailed Configuration of Comparator Section According to First Modification of Second Embodiment]

[0143] Fig.10 : is a diagram showing a detailed configuration of a preamplifier section according to a first modification example of the second embodiment.

[0144] exist Fig.10 In, with Figure 4 Elements identical to those of the illustrated first embodiment are denoted by the same reference numerals as corresponding elements.

[0145] The preamplifier section 13D according to the first modification of the second embodiment is different from the preamplifier section 13 according to the first embodiment in that the former includes an N-channel MOS transistor TR52 functioning as a diode instead of the N-channel MOS transistor TR17 and the threshold value determination circuit 21 .

[0146] In the above-mentioned construction, the N-channel MOS transistor TR52 is constructed in the following manner: the drain terminal D is connected to the connection point CP1 between the drain terminal D of the P-channel MOS transistor TR13 and the source terminal S of the P-channel MOS transistor TR14, the source terminal S is connected to the connection point CP2 between the drain terminal D of the P-channel MOS transistor TR15 and the source terminal S of the P-channel MOS transistor TR16, and the gate terminal G is connected to the connection point CP1.

[0147] According to the above configuration, in the pixel signal S VSL The voltage and threshold voltage signal S th When the difference between the voltages of the first output signal OUTP and the second output signal OUTN is large and the difference between the first output signal OUTP and the second output signal OUTN is large, the N-channel MOS transistor TR52 is turned on (put into a conductor state). Therefore, the differential voltage between the first output signal OUTP and the second output signal OUTN can be reduced. Compared with the first embodiment, the above method does not require the comparison time of the threshold determination and the feedback signal provided from the successive conversion logic unit 15.

[0148] In the above case, as in the second embodiment, only the pixel signal S VSLTherefore, another feature of the first modification of the second embodiment is that the gate terminal G of the N-channel MOS transistor TR52, which functions as a diode, is connected to the pixel signal S VSL side.

[0149] However, in order to match the load capacity, it is also possible to configure an N-channel MOS transistor the same as TR52 in such a manner that the gate and the drain are connected to the CP12 side and the source is connected to the CP11 side.

[0150] [Second Modification of Second Embodiment]

[0151] In the foregoing description, it is assumed that the MOS transistor at the input stage of the preamplifier section 13C is configured as a P-channel MOS transistor. However, alternatively, the MOS transistor at the input stage of the preamplifier section 13C may also be configured as an N-channel MOS transistor.

[0152] (3) Third Embodiment

[0153] [Detailed Configuration of Comparator Section According to Third Embodiment]

[0154] Fig.11 is a diagram showing a detailed configuration of a preamplifier section according to a third embodiment.

[0155] exist Fig.11 In, with Figure 4 Elements identical to those of the illustrated first embodiment are denoted by the same reference numerals as corresponding elements.

[0156] The preamplifier section 13E according to the third embodiment is different from the preamplifier section 13 according to the first embodiment in that the former includes a P-channel MOS transistor TR53 instead of the N-channel MOS transistor TR17, and the P-channel MOS transistor TR53 is based on the determination result signal S output from the threshold determination circuit 21. EV , an initial voltage VSET corresponding to the case of standard pixel signal conversion is applied to the gate terminal G of the P-channel MOS transistor TR13.

[0157] In the above configuration, the P channel MOS transistor TR53 is configured in such a manner that the drain terminal D is connected to the gate terminal G of the P channel MOS transistor TR13 , and the gate terminal G is connected to the output terminal OUTP1 of the threshold value determination circuit 21 .

[0158] When the threshold value determination circuit 21 detects the pixel signal S VSL The voltage is lower than the standard comparison voltage V corresponding to the predetermined excessive input state thIn the case of , the third embodiment turns on (off) the P-channel MOS transistor TR53. Therefore, the initial voltage VSET is applied to the gate terminal G of the P-channel MOS transistor TR13 in the preamplifier section 13E, and a conversion similar to the standard pixel signal conversion is performed. Therefore, the influence on other columns is the same as when the standard pixel signal is converted. Therefore, the influence generated after CDS (Correlated Double Sampling: Correlated Double Sampling) is reduced. Thereby, the degradation of the stripe amount can be suppressed.

[0159] [Detailed Configuration of Preamplifier Section According to First Modification of Third Embodiment]

[0160] Fig.12 : is a diagram showing a detailed configuration of a preamplifier section according to a first modification example of the third embodiment.

[0161] exist Fig.12 In, with Fig.11 Elements identical to those of the illustrated third embodiment are denoted by the same reference numerals as corresponding elements.

[0162] The preamplifier section 13F according to the first modification of the third embodiment is different from the preamplifier section 13E according to the third embodiment in that the former includes a threshold value determination circuit 30. The threshold value determination circuit 30 converts the pixel signal S VSL The voltage is compared with the standard voltage V corresponding to the predetermined excessive input state th Compare and judge the result signal S EVF The voltage is output to the gate terminal G of the P-channel MOS transistor TR53.

[0163] Similarly, in the pixel signal S VSL The voltage is lower than the standard comparison voltage V corresponding to the predetermined excessive input state th In the case of , the first modification of the third embodiment also turns on (off) the P-channel MOS transistor TR53. Therefore, the initial voltage VSET is applied to the gate terminal G of the P-channel MOS transistor TR13 in the preamplifier section 13F, and a conversion similar to the standard pixel signal conversion is performed. Therefore, the influence on other columns is the same as when the standard pixel signal is converted. Therefore, the influence generated after CDS (Correlated Double Sampling: Correlated Double Sampling) is reduced. Thereby, the degradation of the streak amount can be suppressed.

[0164] The configuration of the initial voltage setting circuit used in the above embodiment will be briefly described below.

[0165] Fig.13 is a diagram showing an example of an initial voltage setting circuit.

[0166] The initial voltage setting circuit ensures the drain terminal-source terminal voltage Vds of the P-channel MOS transistor TR12 which functions as a current source when the voltage of the resistor R3 drops, and also defines and sets the initial value voltage V to be applied to the gate terminal G of the P-channel MOS transistor TR13 in the preamplifier section 13. SET .

[0167] (4) Fourth Embodiment

[0168] The foregoing embodiments have been described with respect to an A / D converter for processing one pixel. However, the fourth embodiment described below is an embodiment of a signal processing section including a plurality of A / D converters that sequentially perform A / D conversion processing on a plurality of pixels.

[0169] [Schematic Configuration of Signal Processing Section According to Fourth Embodiment]

[0170] Fig.14 is a block diagram showing a schematic configuration of a signal processing section according to a fourth embodiment.

[0171] Fig.14 The signal processing section 4A shown in FIG. 1 is an example showing a case where each A / D converter performs time-sharing processing on 8 pixels. For the sake of simplicity of explanation, although the signal processing section 4A includes 2n A / D converters, Fig.14 Only n A / D converters 10 - 1 to 10 - n (n is a natural number) are shown. Actually, the remaining n A / D converters are arranged on the upper side of the output signal lines extending upward from the pixels in the figure.

[0172] In the above case, the configuration of the A / D converters 10-1 to 10-n is the same as that of Figure 2 The A / D converters 10 shown have the same construction. Fig.14 A D / A converter section 12 , a preamplifier section 13 , a comparator section 14 , a successive conversion logic section 15 , and a rotation logic section 16 are shown.

[0173] exist Fig.14 In the illustrated case, eight pixels, ie, half of a total of 16 pixels including pixels PX1 to PX4, pixels PX11 to PX14, pixels PX21 to PX24, and pixels PX31 to PX34, are allocated to each A / D converter 10 - 1 .

[0174] More specifically, a total of eight pixels, ie, pixels PX1, PX3, PX11, PX13, PX21, PX23, PX31, and PX33 are allocated to the A / D converter 10-1 shown in the figure.

[0175] Similarly, a total of eight pixels, namely, pixels PX2, PX4, PX12, PX14, PX22, PX24, PX32, and PX34, are allocated to each of the A / D converters not shown.

[0176] (Basic Operation of Signal Processing Section According to Fourth Embodiment)

[0177] The basic operation of the signal processing section 4A according to the fourth embodiment will be described below.

[0178] The A / D converters 10-1 to 10-n and n A / D converters not shown included in the signal processing section 4A perform independent processing in synchronization with each other. Therefore, the basic operation of the A / D converter 10-1, for example, is described below.

[0179] For example, when the A / D converter 10 - 1 performs a single data read operation, the A / D converter 10 - 1 sequentially processes the pixel PX1 , the pixel PX3 , the pixel PX11 , the pixel PX13 , the pixel PX21 , the pixel PX23 , the pixel PX31 , and the pixel PX33 .

[0180] More specifically, at the first processing time of a single data reading operation, under the control of a successive conversion logic section and a rotation logic section described later, the D / A conversion section 12 of the A / D converter 10-1 uses a plurality of types of local standard reference signals Sref generated by the local reference voltage generation section 11 to convert the control data D CNT Perform digital / analog (D / A) conversion and convert the threshold voltage signal S th The signal is output to the preamplifier section 13 .

[0181] Therefore, the preamplifier section 13 performs an operation on the pixel signal S corresponding to the pixel PX1 input from the pixel signal input terminal TSL1. VSL and the threshold voltage signal S input from the D / A converter 12 th Amplification is performed, and the amplified signal is output to the comparator section 14 .

[0182] The comparator section 14 compares the above preamplifier outputs and outputs the comparison result data D CMP Output to the successive conversion logic unit 15.

[0183] The successive conversion logic unit 15 not only outputs the comparison result data D CMP The analog / digital conversion is performed successively by the control data D SAR , and also stores the input comparison result data DCMP , then, based on the stored comparison result data D CMP The successive conversion logic unit 15 outputs the signal from the output terminal TD OUTThe output represents the pixel signal S VSL The pixel data D of the analog / digital (A / D) conversion result VSL .

[0184] Subsequently, in the second processing timing to the eighth processing timing, the A / D converter 10-1 converts the pixel signals S corresponding to the respective pixels into VSL Analog / digital (A / D) conversion is similarly performed, and the signal is output from the output terminal TD OUT The conversion results are output, wherein the respective pixels are pixel PX3 input from pixel signal input terminal TSL2, pixel PX11 input from pixel signal input terminal TSL3, pixel PX13 input from pixel signal input terminal TSL4, pixel PX21 input from pixel signal input terminal TSL5, pixel PX23 input from pixel signal input terminal TSL6, pixel PX31 input from pixel signal input terminal TSL7, and pixel PX33 input from pixel signal input terminal TSL8.

[0185] In the above example, the A / D converters 10 - 2 to 10 - n and n A / D converters not shown also perform the same processing as above in a parallel manner.

[0186] As described above, the fourth embodiment provides additional beneficial effects in addition to the beneficial effects of the first embodiment. More specifically, the fourth embodiment can reduce the number of included A / D converters to about 1 / 8, compared to the case where the number of included A / D converters is the same as the number of pixels, thereby reducing the circuit area of ​​the signal processing unit 4A. Therefore, the installation area of ​​the solid-state imaging device can be reduced, and the size of the device incorporating the solid-state imaging device can be reduced.

[0187] (5) Fifth Embodiment

[0188] Fig.15 is a block diagram illustrating an example of an indirect time-of-flight distance sensor to which the present technology is applied.

[0189] The indirect-Time of Flight distance sensor 100 includes a sensor chip 101 and a circuit chip 102. The circuit chip 102 is stacked on the sensor chip 101.

[0190] The pixel array section 112 includes a plurality of pixels 111 arranged in a two-dimensional grid pattern on the sensor chip 101. Here, the pixel array section 112 may be arranged in a matrix manner and may include a plurality of column signal lines. The column signal lines are connected to the respective pixels.

[0191] A vertical driving circuit 113 , a column signal processing unit 114 , a timing adjustment circuit 115 , and an output circuit 116 are provided on the circuit chip 102 .

[0192] The vertical driving circuit 113 is configured to drive pixels and output pixel signals to the column signal processing section 114 .

[0193] The column signal processing section 114 performs A / D conversion processing on the input pixel signal, and outputs the pixel data after the A / D conversion to the output circuit 116 .

[0194] The output circuit 116 performs, for example, CDS (Correlated Double Sampling) processing on the pixel data from the column signal processing section 114 , and outputs the processed pixel data to a signal processing circuit at the next stage.

[0195] The timing adjustment circuit 115 is configured to control the respective driving timings of the vertical driving circuit 113. The column signal processing section 114 and the output circuit 116 operate in synchronization with the vertical synchronization signal output from the timing adjustment circuit 115.

[0196] The pixels 111 included in the pixel array section 112 will be described in detail below.

[0197] Fig.16 is a circuit diagram showing a configuration example of a pixel according to an embodiment of the present technology.

[0198] The pixel array section 112 includes a plurality of pixels 111 arranged in a two-dimensional grid pattern. Each pixel 111 is configured to be able to receive infrared light and photoelectrically convert the received infrared light into a pixel signal.

[0199] In addition, vertical signal lines VSL1 and VSL2 are arranged vertically for each column of pixels 111. When the total number of columns in the pixel array section 112 is M (M is an integer), a total of 2×M vertical signal lines are arranged. Each pixel has two taps. The vertical signal line VSL1 is connected to the tap A of each pixel 111, and the vertical signal line VSL2 is connected to the tap B of each pixel 111. In addition, the vertical signal line VSL1 transmits the pixel signal AINP1, and the vertical signal line VSL2 transmits the pixel signal AINP2.

[0200] The vertical driving circuit 113 sequentially selects and drives rows of the pixel array section 112 so that each row simultaneously outputs pixel signals AINP1 and AINP2 for each pixel block 221. That is, the vertical driving circuit 113 simultaneously drives the 2kth row and the (2k+1)th row of pixels 111.

[0201] The pixels 111 include a photodiode 121 , two transfer transistors 122 and 123 , two reset transistors 124 and 125 , two taps (floating diffusion layers 126 and 127 ), two amplification transistors 128 and 129 , and two selection transistors 130 and 131 , respectively.

[0202] The photodiode 121 performs photoelectric conversion on the received light and generates electric charge. The photodiode 121 is arranged on the back side of the semiconductor substrate, and the circuit is arranged on the front side of the semiconductor substrate. This type of solid-state imaging device is called a back-illuminated solid-state imaging device. Alternatively, instead of the back-illuminated structure, a front-illuminated structure can be adopted, in which the photodiode 121 is arranged on the front side of the semiconductor substrate.

[0203] The transfer transistor 122 and the transfer transistor 123 sequentially transfer charges from the photodiode 121 to the TAPA 126 and the TAPB 127 , respectively, according to a transfer signal TRG from the vertical drive circuit 113 .

[0204] The TAPA 126 and the TAPB 127 accumulate the transferred charges and generate a voltage corresponding to the amount of accumulated charges.

[0205] The overflow transistor 132 is a transistor that sequentially discharges the charges of the photodiode 121 to the high potential power supply VDD, and has a function of resetting the photodiode 121 .

[0206] The reset transistors 124 and 125 extract charges from the TAPA 126 and TAPB 127 , respectively, in accordance with the reset signal RSTp from the vertical drive circuit 113 to initialize the charge amounts.

[0207] The amplifier transistors 128 and 129 respectively amplify the voltages of TAPA 126 and TAPB 127. The selection transistors 130 and 131 output the amplified voltage signals as pixel signals to the column signal processing section 114 through two vertical signal lines (e.g., VSL1 and VSL2) according to the selection signal SELp from the vertical drive circuit 113. The vertical signal lines VSL1 and VSL2 are connected to the input of one A / D converter 10 in the column signal processing section 114.

[0208] It should be noted that the circuit configuration of the pixel 111 is not limited to Fig.15 The circuit configuration shown may be any configuration as long as it can generate a pixel signal through photoelectric conversion.

[0209] As in the case of the fourth embodiment, the fifth embodiment can reduce the installation area of ​​the solid-state imaging device and can reduce the size of the indirect time-of-flight distance sensor.

[0210] It should be noted that the beneficial effects described herein are exemplary only and not limiting. The present technology may provide beneficial effects other than those described herein.

[0211] It should be noted that the present technology can also adopt the following configurations. (1)

[0213] An A / D converter, comprising:

[0214] a comparator circuit that performs comparison of a pixel signal with a threshold voltage to determine whether an excessive input of the pixel signal has been input; and

[0215] A first transistor has a control terminal configured to receive an input of a result of the comparison and forms a clamp circuit. (2)

[0217] The A / D converter according to (1), wherein currents flowing in a first predetermined position and a second predetermined position are equalized, or voltages at the first predetermined position and the second predetermined position are equalized, the first predetermined position and the second predetermined position being connected to each other when clamped. (3)

[0219] The A / D converter according to (1) or (2), further comprising:

[0220] a pair of differential pair transistors forming an input current line and a reference current line; and

[0221] a pair of bias transistors that control a bias current flowing in the differential pair transistors,

[0222] The first transistor is arranged at an upstream side or a downstream side of the pair of bias transistors. (4)

[0224] The A / D converter according to any one of (1) to (3),

[0225] wherein the clamping circuit includes a threshold determination circuit for determining whether a signal having a value equal to or greater than a predetermined excessive input threshold value has been input as the pixel signal, and,

[0226] Based on the output of the threshold determination circuit, the first transistor forms a short circuit between a first predetermined position and a second predetermined position to which the first transistor is connected when clamped. (5)

[0228] An A / D converter, comprising:

[0229] a pair of differential pair transistors forming an input current line and a reference current line;

[0230] a pair of bias transistors that control bias current flowing in the differential pair transistors; and

[0231] A diode having an anode connected to a first predetermined location and a cathode connected to a second predetermined location, wherein the first predetermined location and the second predetermined location are connected when clamped. (6)

[0233] An electronic device, comprising:

[0234] a pixel array section including a plurality of pixels that perform photoelectric conversion and are arranged in an array; and

[0235] a signal processing unit that reads the analog pixel signal from the pixel array unit and performs signal processing,

[0236] The signal processing unit includes an A / D converter for performing analog / digital conversion on the analog pixel signal, and

[0237] The A / D converter comprises:

[0238] a comparator circuit that performs comparison of a pixel signal with a threshold voltage to determine whether an excessive input of the pixel signal has been input; and

[0239] A first transistor has a control terminal configured to receive an input of a result of the comparison and forms a clamp circuit. (7)

[0241] An electronic device, comprising:

[0242] a pixel array section including a plurality of pixels that perform photoelectric conversion and are arranged in an array; and

[0243] a signal processing unit that reads the analog pixel signal from the pixel array unit and performs signal processing,

[0244] The signal processing unit includes an A / D converter for performing analog / digital conversion on the analog pixel signal, and

[0245] The A / D converter comprises:

[0246] a pair of differential pair transistors forming an input current line and a reference current line;

[0247] a pair of bias transistors that control bias current flowing in the differential pair transistors; and

[0248] A diode having an anode connected to a first predetermined location and a cathode connected to a second predetermined location, wherein the first predetermined location and the second predetermined location are connected when clamped.

[0249] [reference numerals list]

[0250] 2: Pixel array section

[0251] 4: Signal processing unit

[0252] 10: A / D Converter

[0253] 11: Local reference voltage generation unit

[0254] 12: D / A conversion unit

[0255] 13, 13A to 13F: Preamplifier section

[0256] 14: Comparator section

[0257] 14A: Amplification

[0258] 14B: Latch unit

[0259] 15: Successive conversion logic

[0260] 16: Rotation logic unit

[0261] 21: Threshold determination circuit

[0262] CP1, CP11: connection point (first predetermined position)

[0263] CP2, CP12: connection point (second predetermined position)

[0264] TR17, TR17A, TR17B: N-channel MOS transistor (clamp circuit)

[0265] TR51, TR52: N-channel MOS transistor (clamping circuit)

[0266] TR53: P-channel MOS transistor (switching element)

[0267] DA: Differential Amplifier

[0268] S EV :Discrimination result signal

Claims

1. An A / D converter, comprising: a comparator circuit that performs a comparison between a pixel signal and a threshold voltage to determine whether an excessively large signal has been input as the pixel signal; a first transistor having a control terminal configured to receive an input of a result of the comparison and forming a clamp circuit; a pair of differential pair transistors forming an input current line and a reference current line; and a pair of bias transistors that control a bias current flowing in the differential pair transistors, The first end of the first transistor is connected to a first predetermined position, and the second end of the first transistor is connected to a second predetermined position. When the comparator circuit determines that an excessively large signal is input to the pixel signal, a short circuit is formed between the first predetermined position and the second predetermined position to which the first transistor is connected when clamping. The first transistor is arranged at an upstream side or a downstream side of the two bias transistors of the pair of bias transistors.

2. The A / D converter according to claim 1, wherein: When the clamp circuit is turned on, the first transistor makes currents flowing in the first predetermined position and the second predetermined position equal, or makes voltages at the first predetermined position and the second predetermined position equal.

3. The A / D converter according to claim 1, in, The comparator circuit includes a threshold determination circuit for determining whether a signal having a voltage equal to or greater than the threshold voltage has been input as the pixel signal, and, Based on the output of the threshold determination circuit, the first transistor forms a short circuit between a first predetermined position and a second predetermined position to which the first transistor is connected when clamped.

4. An A / D converter comprising: a pair of differential pair transistors forming an input current line and a reference current line; a pair of bias transistors that control bias current flowing in the differential pair of transistors; a comparator circuit that performs a comparison between a pixel signal and a threshold voltage to determine whether an excessively large signal has been input as the pixel signal; and A diode, an anode of the diode is connected to a first predetermined position, and a cathode of the diode is connected to a second predetermined position, the first predetermined position is located at a connection point between a first differential pair transistor in the pair of differential pair transistors and a first bias transistor of the pair of bias transistors, and the second predetermined position is located at a connection point between a second differential pair transistor in the pair of differential pair transistors and a second bias transistor of the pair of bias transistors, and when the comparator circuit determines that an excessively large signal is input to the pixel signal, the first predetermined position and the second predetermined position are connected to form a short circuit when clamping.

5. An electronic device, comprising: a pixel array section including a plurality of pixels that perform photoelectric conversion and are arranged in an array; and a signal processing unit that reads the analog pixel signal from the pixel array unit and performs signal processing, The signal processing unit includes an A / D converter for performing analog / digital conversion on the analog pixel signal, and the A / D converter is an A / D converter according to any one of claims 1 to 4.

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