Image sensor and method for manufacturing the same

Abstract

An image sensor includes: a substrate having a first surface and an opposite second surface, and including unit pixels each having a photoelectric conversion region; a semiconductor pattern disposed in a first trench defining the unit pixel, the semiconductor pattern including a first semiconductor layer disposed on an inner surface of the first trench and a second semiconductor layer disposed on the first semiconductor layer; and a first contact portion disposed on the second surface and connected to the semiconductor pattern. A height of the first semiconductor layer from a bottom surface of the first trench is less than a height of the second semiconductor layer from the bottom surface of the first trench.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to Korean Patent Application No. 10-2019-0171635 and No. 10-2020-0042280 filed on December 20, 2019 and April 7, 2020, respectively, in the Korean Intellectual Property Office, the common subject matter of which is incorporated herein by reference. Technical Field

[0003] The inventive concept relates to image sensors, and in particular, to complementary metal oxide semiconductor (CMOS) image sensors. Background Art

[0004] Image sensors are electronic devices that convert electromagnetic energy (e.g., incident light) into corresponding electrical signals. With the recent developments in the computer and communications industries, there has been a demand for high-performance image sensors in various applications such as digital cameras, camcorders, personal communication systems, game consoles, security cameras, medical miniature cameras, robots, etc.

[0005] Generally, image sensors can be classified into charge coupled devices (CCDs) and complementary metal oxide semiconductor (CMOS) image sensors. Since CMOS image sensors have a relatively simple operation method and can be manufactured on a single semiconductor chip together with a signal processing circuit, the size of many products incorporating CMOS image sensors can be reduced. In addition, since CMOS image sensors operate with relatively low power consumption, they can be easily incorporated into battery-powered electronic devices. In addition, CMOS image sensors can be manufactured using well-known CMOS manufacturing technology, and therefore, manufacturing costs can be reduced. In addition, CMOS image sensors provide high-resolution images. Therefore, the use of CMOS image sensors is growing rapidly. Summary of the invention

[0006] Embodiments of the inventive concept provide an image sensor having improved reliability.

[0007] According to an embodiment conceived in the present invention, an image sensor may include: a substrate having a first surface and an opposite second surface, and including unit pixels respectively having photoelectric conversion regions; a semiconductor pattern arranged in a first groove defining the unit pixel, the semiconductor pattern including a first semiconductor layer arranged on an inner surface of the first groove and a second semiconductor layer arranged on the first semiconductor layer; and a first contact portion arranged on the second surface and connected to the semiconductor pattern, wherein a height of the first semiconductor layer from a bottom surface of the first groove is less than a height of the second semiconductor layer from the bottom surface of the first groove.

[0008] According to an embodiment of the present inventive concept, an image sensor may include: a substrate having a first surface and an opposite second surface and including a plurality of unit pixels; a color filter and a microlens disposed on the second surface of the substrate; a pixel isolation pattern disposed in a first groove defining the unit pixel and penetrating the substrate, the pixel isolation pattern including a first oxide layer covering an inner surface of the first groove, a first semiconductor layer, and a second semiconductor layer; and a first contact portion connected to the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer has a first side surface and an opposite second side surface, and

[0009] A distance between the first side surface and the second side surface in a horizontal direction increases as a distance from the first surface of the substrate decreases.

[0010] According to an embodiment of the inventive concept, an image sensor may include: a substrate having a first surface and an opposite second surface, and including a pixel region having a plurality of unit pixels, an optical black region, and a pad region; a pixel isolation pattern filling a first trench of the substrate and defining the unit pixel, the pixel isolation pattern including a first oxide layer covering an inner surface of the first trench, a first semiconductor layer, and a second semiconductor layer; a color filter disposed on the second surface of the substrate; a microlens disposed on the color filter; a transfer transistor and a logic transistor disposed on the first surface; a device isolation pattern disposed adjacent to the first surface to fill the second trench of the substrate; an interlayer insulating layer disposed on the first surface; an interconnection line disposed in the interlayer insulating layer and electrically connected to the transfer transistor and the logic transistor; a first light blocking pattern and a first contact portion disposed on the optical black region; and a second light blocking pattern and a second contact portion disposed on the pad region. The first contact portion is connected to the first light blocking pattern and the first semiconductor layer and the second semiconductor layer.

[0011] According to an embodiment of the inventive concept, a method for manufacturing an image sensor may include: preparing a substrate having a first surface and an opposite second surface and including a pixel region, an optical black region, and a pad region; performing an etching process on the substrate to form a first trench; and forming a pixel isolation pattern to fill an inner space of the first trench. The formation of the pixel isolation pattern may include: depositing a first oxide layer to cover an inner surface of the first trench; depositing a first preliminary semiconductor layer to cover the first oxide layer; performing a first etching process on the first preliminary semiconductor layer to form a first semiconductor layer; and depositing a second semiconductor layer to fill the inner space of the first trench.

[0012] According to an embodiment conceived in the present invention, an image sensor may include: a substrate having a first surface and an opposite second surface, and including a unit pixel having a plurality of photoelectric conversion regions; a pixel isolation pattern disposed in a first groove defining the unit pixel, the pixel isolation pattern including a first oxide layer covering an inner surface of the first groove, a first semiconductor layer, and a second semiconductor layer; and a device isolation pattern disposed adjacent to the first surface of the substrate, wherein the second semiconductor layer includes a first portion and a second portion and extends vertically toward the second surface of the substrate, the second portion being separated from the first oxide layer by the first semiconductor layer interposed therebetween, and the first semiconductor layer and the second semiconductor layer include polycrystalline silicon. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Example embodiments may be more clearly understood by considering the following brief description taken in conjunction with the accompanying drawings.The accompanying drawings illustrate non-limiting example embodiments described herein.

[0014] Figure 1 is a block diagram illustrating an image sensor according to an embodiment of the inventive concept.

[0015] Figure 2 is a circuit diagram of an active pixel sensor array of an image sensor according to an embodiment of the inventive concept.

[0016] Figure 3 is a plan view illustrating an image sensor according to an embodiment of the inventive concept.

[0017] Figure 4 is along Figure 3 A cross-sectional view taken along line II'.

[0018] Figure 5 It further shows Figure 4 An enlarged cross-sectional view of area "A" is shown.

[0019] Figure 6 It further shows Figure 5 An enlarged cross-sectional view of area "B" is shown.

[0020] Figure 7 and Figure 8 It further shows Figure 5 ” and conceptually illustrates an enlarged cross-sectional view of a region “C” shown in FIG. 1 and a grain of the first and second semiconductor layers.

[0021] Fig. 9 is a cross-sectional view illustrating an image sensor according to an embodiment of the inventive concept.

[0022] Fig.10 is a cross-sectional view illustrating an image sensor according to an embodiment of the inventive concept.

[0023] Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 and Fig.19 is along Figure 3 1 and 2 , and illustrate a method of manufacturing an image sensor according to an embodiment of the inventive concept in one example.

[0024] Fig. 20 is a plan view illustrating an image sensor according to an embodiment of the inventive concept.

[0025] Fig.21 is along Fig. 20 A cross-sectional view taken along line II-II'.

[0026] In this article, it should be noted that these figures are intended to illustrate the general characteristics of the methods, structures and / or materials used in certain example embodiments and to supplement the written description provided below. However, the drawings are not drawn to scale and do not reflect the precise structure or performance characteristics of a particular embodiment, and should not be interpreted as defining or limiting the range of values ​​or characteristics contained in the example embodiments. For example, for clarity, the relative thickness and positioning of material layers, regions and / or structural elements in the drawings may be reduced or exaggerated. In all written descriptions and drawings, similar reference numerals and labels are used to represent similar or similar elements and / or features. Throughout the written description, specific geometric terms may be used to emphasize specific relative relationships between elements, components and / or features for a particular embodiment of the present invention. Those skilled in the art will recognize that such geometric terms are inherently relative, arbitrary in describing relationships and / or relate to aspects of the embodiments shown. Geometric terms may include, for example: height / width; vertical / horizontal; closer / further; close / far away; above / below; below / above; upper / lower; top / bottom; center / edge; around; perimeter; overlap / below; beside; parallel, etc. DETAILED DESCRIPTION

[0027] Figure 1 is a block diagram illustrating an image sensor according to an embodiment of the inventive concept.

[0028] refer to Figure 1 The image sensor may include: an active pixel sensor array 1, a row decoder 2, a row driver 3, a column decoder 4, a timing generator 5, a correlated double sampler (CDS) 6, an analog-to-digital converter (ADC) 7 and an input / output buffer 8.

[0029] The active pixel sensor array 1 may include a plurality of unit pixels arranged two-dimensionally, and may convert an optical signal into an electrical signal. The active pixel sensor array 1 may be driven by a plurality of driving signals (such as a pixel selection signal, a reset signal, and a charge transfer signal) sent from a row driver 3. In addition, the converted electrical signal may be provided to a correlated double sampler 6.

[0030] The row driver 3 may provide a driving signal for driving a plurality of unit pixels to the active pixel sensor array 1 based on the result decoded by the row decoder 2. When the unit pixels are arranged in a matrix form (ie, in rows and columns), a driving signal may be provided for a corresponding row.

[0031] The timing generator 5 may provide timing and control signals to the row decoder 2 and the column decoder 4 .

[0032] The CDS 6 may receive the electrical signal generated by the active pixel sensor array 1 and may perform a holding and sampling operation on the received electrical signal. For example, in the CDS 6, a double sampling operation may be performed on a specific noise level and a signal level of the electrical signal to output a difference level corresponding to the difference between the noise level and the signal level.

[0033] The ADC 7 may convert an analog signal corresponding to the difference level output from the CDS 6 into a digital signal, and may output the converted digital signal.

[0034] The input / output buffer 8 may latch the digital signal, and may sequentially output the latched digital signal to an image signal processing section (not shown) based on the result of decoding by the column decoder 4 .

[0035] Figure 2 is a circuit diagram illustrating, in one example, an active pixel sensor array of an image sensor according to an embodiment of the inventive concept.

[0036] refer to Figure 1 and Figure 2 , the active pixel sensor array 1 may include a plurality of unit pixels PX, and the unit pixels PX may be arranged in a matrix shape. Each unit pixel PX may include a transfer transistor TX and logic transistors RX, SX, and DX. The logic transistor may include a reset transistor RX, a selection transistor SX, and a drive transistor DX. The transfer transistor TX may include a transfer gate TG. Each unit pixel PX may also include a photoelectric conversion device PD and a floating diffusion region FD.

[0037] The photoelectric conversion device PD can generate and store photoelectric charges proportional to the amount of light incident from the outside. The photoelectric conversion device PD may include a photodiode, a phototransistor, a photogate, a pinned photodiode, or any combination thereof. The transfer transistor TX may transfer the charge generated in the photoelectric conversion device PD to the floating diffusion region FD. The charge generated in the photoelectric conversion device PD may be transferred to and accumulated in the floating diffusion region FD. The drive transistor DX may be controlled by the amount of photoelectric charges stored in the floating diffusion region FD.

[0038] The reset transistor RX may periodically release the photocharge stored in the floating diffusion region FD. The reset transistor RX may have a drain electrode connected to the floating diffusion region FD and a source electrode connected to the power supply voltage VDD. When the reset transistor RX is turned on, the power supply voltage VDD connected to the source of the reset transistor RX may be applied to the floating diffusion region FD. Therefore, if the reset transistor RX is turned on, the charge stored in the floating diffusion region FD may be released by the reset transistor RX, whereby the floating diffusion region FD may be reset.

[0039] The drive transistor DX may function as a source follower buffer amplifier. The drive transistor DX may amplify a potential change of the floating diffusion region FD and may output the amplified signal to the output line Vout.

[0040] The selection transistor SX may select a row of the unit pixel P to be read. If the selection transistor SX is turned on, the power supply voltage VDD may be applied to the drain electrode of the driving transistor DX.

[0041] Figure 3 is a plan view showing an image sensor according to an embodiment of the inventive concept, and Figure 4 is along Figure 3 A cross-sectional view taken along line II′.

[0042] refer to Figure 3 and Figure 4 , an image sensor according to an embodiment of the inventive concept may include a photoelectric conversion layer 10, an interconnection layer 20, and an optically transparent layer 30. When viewed in a vertical cross-sectional view, the photoelectric conversion layer 10 may be disposed between the interconnection layer 20 and the optically transparent layer 30. The photoelectric conversion layer 10 may include a substrate 100, a pixel isolation pattern 150 disposed in the substrate 100, a device isolation pattern 103, and a photoelectric conversion region 110. In the photoelectric conversion region 110, incident light may be converted into an electrical signal.

[0043] The substrate 100 may have a first or front surface 100a and an opposing second or rear surface 100b. The interconnect layer 20 may be disposed on the first surface 100a of the substrate 100, and the optically transparent layer 30 may be disposed on the second surface 100b of the substrate 100.

[0044] The interconnection layer 20 may include a transfer transistor TX, logic transistors RX, SX, and DX, insulating layers 222 and 223, and interconnection lines 212 and 213. The transfer transistor TX may be electrically connected to the photoelectric conversion region 110. The interconnection lines 212 and 213 may be vertically connected to the transfer transistor TX and the logic transistors RX, SX, and DX through the via VI. The electrical signal converted in the photoelectric conversion layer 110 may be processed in the interconnection layer 20. The interconnection lines 212 and 213 may be disposed in the interlayer insulating layers 222 and 223 stacked on the first surface 100a of the substrate 100. In an embodiment, the interconnection lines 212 and 213 may be arranged independently of the arrangement of the photoelectric conversion region 110. For example, the interconnection lines 212 and 213 may be arranged to cross the photoelectric conversion region 110.

[0045] The optical transparent layer 30 may include a color filter 303 and a micro lens 307. The optical transparent layer 30 may perform operations of converging and filtering light incident from the outside, and may provide the light to the photoelectric conversion layer 10.

[0046] The substrate 100 may include a bulk silicon wafer and an epitaxial layer formed on the bulk silicon wafer, and in an embodiment, the bulk silicon wafer and the epitaxial layer may have a first conductivity type (e.g., P-type). Here, according to the process of manufacturing the image sensor, the bulk silicon wafer may be removed from the substrate 100, and only the P-type epitaxial layer may be left. In addition, the substrate 100 may be a bulk semiconductor wafer in which a well region of the first conductivity type is provided. In some embodiments, various substrates (e.g., an N-type epitaxial layer, a bulk silicon wafer, and a silicon on insulator (SOI) wafer) may be used as the substrate 100.

[0047] The substrate 100 may include unit pixels PX defined by a pixel isolation pattern 150. The unit pixels PX may be arranged along a first direction D1 and a second direction D2 that intersect each other or in a matrix pattern. The pixel isolation pattern 150 may prevent photocharges generated in response to light incident into each unit pixel PX from entering adjacent unit pixels PX by random drift. In other words, the pixel isolation pattern 150 may prevent a crosstalk phenomenon from occurring between the unit pixels PX.

[0048] When viewed in a plan view, the pixel isolation pattern 150 may have a lattice or grid structure. When viewed in a plan view, the pixel isolation pattern 150 may be arranged to completely surround each unit pixel PX. For example, the pixel isolation pattern 150 may include a first portion P1 extending in the second direction D2 and spaced apart in the first direction D1, and a second portion P2 extending in the first direction D1 and spaced apart in the second direction D2. Each unit pixel PX may be defined by a pair of first portions P1 and a pair of second portions P2. In other words, each unit pixel PX may be surrounded by a pair of first portions P1 and a pair of second portions P2.

[0049] As shown in the cross-sectional view taken along the second direction D2 and the third direction D3, the pixel isolation pattern 150 may extend from the first surface 100a of the substrate 100 to the second surface 100b. In an embodiment, the pixel isolation pattern 150 may be arranged to penetrate the substrate 100. For example, the vertical height of the pixel isolation structure 150 may be substantially the same as the vertical thickness of the substrate 100. As an example, the width of the pixel isolation pattern 150 may gradually decrease in the direction from the first surface 100a of the substrate 100 to the second surface 100b. Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 The pixel isolation pattern 150 is described in additional detail.

[0050] The photoelectric conversion regions 110 may be respectively disposed in the unit pixels PX. The photoelectric conversion regions 110 may be doped to have a conductivity type different from that of the substrate 100 (e.g., a second conductivity type or an N-type). The photoelectric conversion regions 110 may be adjacent to the first surface 100a of the substrate 100. The photoelectric conversion regions 110 may be disposed closer to the first surface 100a than the second surface 100b.

[0051] Each photoelectric conversion region 110 may include a first region adjacent to the first surface 100a and a second region adjacent to the second surface 100b. There may be a difference in impurity concentration between the first region and the second region of the photoelectric conversion region 110. This may result in a non-vanishing potential gradient in the photoelectric conversion region 110 between the first surface 100a and the second surface 100b of the substrate 100.

[0052] The substrate 100 and the photoelectric conversion region 110 may constitute a photodiode. For example, the first conductive type substrate 100 and the second conductive type photoelectric conversion region 110 may constitute a PN junction to serve as a photodiode. The photoelectric conversion region 110 constituting the photodiode may generate and / or accumulate charges in proportion to the intensity of incident light.

[0053] The device isolation pattern 103 may be disposed on the first surface 100a of the substrate 100 to define a first active pattern ACT1, a second active pattern ACT2, and a third active pattern ACT3. The width of the device isolation pattern 103 may be gradually reduced in a direction from the first surface 100a of the substrate 100 to the second surface 100b. The bottom surface of the device isolation pattern 103 may be vertically spaced apart from the photoelectric conversion region 110. The level of the bottom surface of the device isolation pattern 103 may be a first level lv1. The depth of the device isolation pattern 103 may be less than the depth of the pixel isolation pattern 150. The pixel isolation pattern 150 may overlap a portion of the device isolation pattern 103.

[0054] Each unit pixel PX may include a first active pattern ACT1 defined by a device isolation pattern 103. For example, when viewed in a plan view, the first active pattern ACT1 may be disposed in a central region of each unit pixel PX. The first active pattern ACT1 may have an “L”-shaped planar shape. Each unit pixel PX may include a second active pattern ACT2 or a third active pattern ACT3. The second active pattern ACT2 and the third active pattern ACT3 may be defined by the device isolation pattern 103. When viewed in a plan view, each of the second active pattern ACT2 and the third active pattern ACT3 may be disposed in an edge region of each unit pixel PX. Each of the second active pattern ACT2 and the third active pattern ACT3 may have a line shape extending in the second direction D2. However, the planar shapes of the first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3 may not be limited to. Figure 3 Examples are shown and various changes may be made.

[0055] Alternatively, each unit pixel PX may include a first active pattern ACT1, a second active pattern ACT2, and a third active pattern ACT3. The first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3 may be arranged to be spaced apart from each other. The first active pattern ACT1, the second active pattern ACT2, and the third active pattern ACT3 may have different sizes. The first active pattern ACT1 may be disposed between the second active pattern ACT2 and the third active pattern ACT3.

[0056] Previous references Figure 2The described transfer transistor TX and logic transistors RX, SX, and DX may be disposed on the first surface 100a of the substrate 100. The transfer transistor TX may be disposed on the first active pattern ACT1 of each unit pixel PX. The transfer transistor TX may be electrically connected to the photoelectric conversion region 110. The transfer transistor TX may include a transfer gate TG disposed on the first active pattern ACT1, and a floating diffusion region FD. The transfer gate TG may include a lower portion inserted into the substrate 100 and an upper portion connected to the lower portion and formed to protrude above the first surface 100a of the substrate 100. A gate dielectric layer GI may be inserted between the transfer gate TG and the substrate 100. The floating diffusion region FD may be formed in a region of the first active pattern ACT1 located at one side of the transfer gate TG. The floating diffusion region FD may be doped to have a second conductivity type (e.g., N-type) different from the conductivity type of the substrate 100.

[0057] A driving transistor DX and a selection transistor SX may be disposed on the second active pattern ACT2 of each unit pixel PX. The driving transistor DX may include a driving gate SFG disposed on the second active pattern ACT2, and the selection transistor SX may include a selection gate SG. A reset transistor RX may be disposed on the third active pattern ACT3 of each unit pixel PX. The reset transistor RX may include a reset gate RG disposed on the third active pattern ACT3. A gate dielectric layer GI may be interposed between each of the driving gate SFG, the selection gate SG, and the reset gate RG and the substrate 100.

[0058] The interconnection layer 20 may include a first interlayer insulating layer 221, a second interlayer insulating layer 222, and a third interlayer insulating layer 223, and a first interconnection line 212 and a second interconnection line 213. The first interlayer insulating layer 221 may be disposed on the first surface 100a of the substrate 100 to cover the transmission transistor TX and the logic transistors RX, SX, and DX. The first interconnection line 212 and the second interconnection line 213 may be disposed in the second interlayer insulating layer 222 and the third interlayer insulating layer 223 stacked on the first interlayer insulating layer 221, respectively.

[0059] The first interconnection line 212 and the second interconnection line 213 may be electrically connected to the transfer transistor TX and the logic transistors RX, SX, and DX through a contact portion BCP disposed to penetrate the first interlayer insulating layer 221. In an embodiment, the first interconnection line 212 and the second interconnection line 213 may be disposed regardless of the arrangement of the photoelectric conversion region 110. When viewed in a plan view, the first interconnection line 212 and the second interconnection line 213 may be disposed to cross the photoelectric conversion region 110.

[0060] The optical transparent layer 30 may include color filters 303a, 303b, and 303c and a microlens 307. The optical transparent layer 30 may collect and filter externally incident light, and may then provide the light to the photoelectric conversion layer 10.

[0061] That is, the color filter 303 and the microlens 307 may be disposed on the second surface 100b of the substrate 100. The color filters 303a, 303b, and 303c may be disposed on the unit pixel PX, respectively. The microlens 307 may be disposed on the color filters 303a, 303b, and 303c, respectively. The anti-reflection layer 132 and the first insulating layer 134 and the second insulating layer 136 may be disposed between the second surface 100b of the substrate 100 and the color filters 303a, 303b, and 303c. The anti-reflection layer 132 may be configured to prevent the light incident into the second surface 100b of the substrate 100 from being reflected, and this may allow the incident light to be effectively incident into the photoelectric conversion region 110. The third insulating layer 305 may be disposed between the color filter 303 and the microlens 307.

[0062] Color filters 303a, 303b and 303c may include a first color filter 303a, a second color filter 303b and a third color filter 303c. The first color filter 303a, the second color filter 303b and the third color filter 303c may include primary color filters. As an example, the first color filter 303a, the second color filter 303b and the third color filter 303c may include green, red and blue color filters. In an embodiment, the first color filter 303a, the second color filter 303b and the third color filter 303c may be arranged in a Bayer pattern. In an embodiment, the first color filter 303a, the second color filter 303b and the third color filter 303c may include color filters of other colors (e.g., cyan, magenta or yellow).

[0063] Each of the micro lenses 307 may have a convex shape capable of focusing incident light onto the unit pixel PX. When viewed in a plane, the micro lenses 307 may overlap the photoelectric conversion regions 110 , respectively.

[0064] Figure 5 It further shows Figure 4 An enlarged cross-sectional view of area "A" is shown, Figure 6 It further shows Figure 5 An enlarged cross-sectional view of region "B" is shown. Hereinafter, the pixel isolation pattern 150 will be described in some additional details.

[0065] Combination Figure 4 refer to Figure 5 and Figure 6, the first trench TR1 may be provided to penetrate the substrate 100 and define a unit pixel PX. When viewed in a plan view, the first trench TR1 may have a lattice or mesh structure. The pixel isolation pattern 150 may be provided in the trench TR1 to fill the inner space of the first trench TR1. The pixel isolation pattern 150 may be provided to penetrate the device isolation pattern 103.

[0066] The pixel isolation pattern 150 may include a first oxide layer 151, a semiconductor pattern CP, and a capping pattern 157. The semiconductor pattern CP may include a first semiconductor layer 153 and a second semiconductor layer 155. The first oxide layer 151 may cover the inner side surface of the first trench TR1. The semiconductor pattern CP and the capping pattern 157 may fill the first trench TR1. For example, the capping pattern 157 may fill the upper region of the first trench TR1. The semiconductor pattern CP may fill the remaining region of the first trench TR1 except the upper region of the first trench TR1.

[0067] The first oxide layer 151 may be disposed on the inner side surface of the first trench TR1. The first oxide layer 151 may conformally cover the inner side surface of the first trench TR1. A thickness w3 of the first oxide layer 151 in the second direction D2 may be substantially uniform. For example, the thickness w3 may be to . When viewed in a cross-sectional view, the first oxide layer 151 may have a first inner side surface 151a and an opposite second inner side surface 151b. The first inner side surface 151a and the second inner side surface 151b may be parallel to the inner side surface of the first trench TR1. The first oxide layer 151 may extend from the first surface 100a of the substrate 100 to the second surface 100b. When viewed in a plan view, the first oxide layer 151 may be provided to surround each photoelectric conversion region 110. The first oxide layer 151 may be inserted between the semiconductor pattern CP and the substrate 100. Although not shown, a plurality of oxide layers may be further provided on the first oxide layer 151. The semiconductor pattern CP may be spaced apart from the substrate 100 by the first oxide layer 151. The semiconductor pattern CP may be electrically disconnected from the substrate 100 by the first oxide layer 151. The first oxide layer 151 may be formed of or include a non-conductive material. For example, the first oxide layer 151 may be formed of or include at least one of silicon oxide, silicon oxynitride, or silicon nitride.

[0068] The semiconductor pattern CP may include a first semiconductor layer 153 and a second semiconductor layer 155. The first semiconductor layer 153 may be disposed on the first oxide layer 151. The first semiconductor layer 153 may conformally cover a portion of the first oxide layer 151. The first semiconductor layer 153 may not cover the upper portion of the first oxide layer 151. Therefore, the upper portion of the first oxide layer 151 may be exposed through the first semiconductor layer 153. The level of the uppermost portion of the first semiconductor layer 153 may be a third level lv3. The vertical distance from the first surface 100a of the substrate 100 to the first semiconductor layer 153 may be in the range of 50nm to 2000nm. The vertical distance from the first surface 100a of the substrate 100 to the first semiconductor layer 153 may refer to the vertical distance from the first surface 100a to the third level lv3. The vertical distance from the first surface 100a of the substrate 100 to the second semiconductor layer 155 may refer to the vertical distance from the first surface 100a to the second level lv2. The vertical distance from the first surface 100a of the substrate 100 to the first semiconductor layer 153 may be greater than the vertical distance from the first surface 100a of the substrate 100 to the second semiconductor layer 155. The first semiconductor layer 153 and the second semiconductor layer 155 may be formed of polycrystalline silicon or include polycrystalline silicon. As an example, the first semiconductor layer 153 and the second semiconductor layer 155 may be formed of doped polycrystalline silicon or include doped polycrystalline silicon. The first semiconductor layer 153 may be formed of (or include) N-type and / or P-type doped polycrystalline silicon. As another example, the first semiconductor layer 153 and the second semiconductor layer 155 may be formed of undoped polycrystalline silicon or include undoped polycrystalline silicon. The first semiconductor layer 153 may have a first side surface 153a and a second side surface 153b facing each other. The first side surface 153a and the second side surface 153b may be an interface between the first semiconductor layer 153 and the second semiconductor layer 155.

[0069] like Figure 6 As shown, the first semiconductor layer 153 may include a first portion 153U and a second portion 153B. The first portion 153U may be connected to the second portion 153B and may be disposed on the first oxide layer 151. The first portion 153U may be closer to the first surface 100a than the second portion 153B. The first portion 153U may be an upper portion of the first semiconductor layer 153. The thickness w1 of the first portion 153U in the second direction D2 does not have to be uniform. That is, the thickness w1 of the first portion 153U in the second direction D2 may decrease as the distance from the first surface 100a decreases. For example, the thickness w1 of the first portion 153U of the first semiconductor layer 153 may be less near the first surface 100a of the substrate 100 than near the second surface 100b of the substrate 100. For example, the thickness w1 may be about to about The thickness w1 in the second direction D2 may be a distance between the first inner surface 151a of the first oxide layer 151 and the first side surface 153a of the first semiconductor layer 153 in the second direction D2. Therefore, the interfaces 153a and 153b of the first portion 153U may not be parallel to the inner surfaces 151a and 151b of the first oxide layer 151.

[0070] The second portion 153B may be connected to the first portion 153U and may be disposed on the first oxide layer 151. The second portion 153B may be closer to the second surface 100b than the first portion 153U. The second portion 153B may extend toward the second surface 100b. Therefore, the bottom surface of the second portion 153B may be coplanar with the second surface 100b of the substrate 100. The second portion 153B may be a lower portion of the first semiconductor layer 153. The second portion 153B may have a substantially uniform thickness (e.g., w2) in the second direction D2. That is, as the distance to the first surface 100a or the second surface 100b decreases, the thickness w2 may become substantially uniform. For example, the thickness w2 may be approximately to about The thickness w2 in the second direction D2 may be a distance measured in the second direction D2 between the first inner side surface 151a of the first oxide layer 151 and the first side surface 153a of the first semiconductor layer 153. Therefore, the interfaces 153a and 153b of the second portion 153B may be parallel to the interface 151b of the first oxide layer 151.

[0071] The second semiconductor layer 155 may be disposed on the first semiconductor layer 153 and the first oxide layer 151. The second semiconductor layer 155 may cover the first surface 153a and the second surface 153b of the first semiconductor layer 153 and the upper portion of the first oxide layer 151 exposed by the first semiconductor layer 153. The second semiconductor layer 155 may be formed of (or include) N-type and / or P-type doped polysilicon. The second semiconductor layer 155 may be formed of or include the same material as the first semiconductor layer 153. The second semiconductor layer 155 may be inserted between the first side surface 153a and the second side surface 153b of the first semiconductor layer 153 to fill the internal space of the first trench TR1. The second semiconductor layer 155 may extend toward the second surface 100b of the substrate 100. The bottom surface of the second semiconductor layer 155 may be coplanar with the second surface 100b of the substrate 100 and the bottom surface of the first semiconductor layer 153.

[0072] The level of the top surface 155a of the second semiconductor layer 155 may be a second level lv2. The top surface 155a of the second semiconductor layer 155 may be located at a level between the bottom surface of the device isolation pattern 103 and the second surface 100b of the substrate 100. The thickness w4 of the second semiconductor layer 155 in the second direction D2 may increase as the distance from the first surface 100a of the substrate 100 decreases. In other words, the thickness w4 of the second semiconductor layer 155 adjacent to the first surface 100a of the substrate 100 may be greater than the thickness w4 of the second semiconductor layer 155 adjacent to the second surface 100b of the substrate 100. Therefore, the distance between the first side surface 153a and the second side surface 153b of the first semiconductor layer 153 in the second direction D2 may increase as the distance from the first surface 100a of the substrate 100 decreases. In an embodiment, the thickness w4 may be about 1000 mm / s. to about within the range.

[0073] like Figure 6 As shown, the second semiconductor layer 155 may include a first portion 155U and a second portion 155B. The first portion 155U may be connected to the second portion 155B. The first portion 155U may be closer to the capping pattern 157 than the second portion 155B. The first portion 155U may contact the capping pattern 137. The first portion 155U may be an upper portion of the second semiconductor layer 155. The first portion 155U may have a uniform thickness in the second direction D2. The second portion 155B may be connected to the first portion 155U and may extend vertically toward the second surface 100b of the substrate 100. The second portion 155B may be closer to the second surface 100b of the substrate 100 than the first portion 155U. The bottom surface of the second portion 155B may be coplanar with the second surface 100b of the substrate 100. The second portion 155B may be a lower portion of the second semiconductor layer 155. The thickness of the second portion 155B in the second direction D2 does not have to be uniform. For example, the thickness of the second portion 155B in the second direction D2 may decrease as the distance from the second surface 100 b decreases.

[0074] The capping pattern 157 may be disposed on the top surface 155a of the second semiconductor layer 155. The capping pattern 157 may be disposed adjacent to the first surface 100a of the substrate 100. The top surface 157a of the capping pattern 157 may be coplanar with the first surface 100a of the substrate 100. The bottom surface of the capping pattern 157 may be substantially the same as the top surface 155a of the second semiconductor layer 155. The capping pattern 157 may be formed of or include a non-conductive material. For example, the capping pattern 157 may be formed of or include at least one of silicon oxide, silicon oxynitride, or silicon nitride.

[0075] In an embodiment, the first height H1 of the first semiconductor layer 153 may be less than the second height H2 of the second semiconductor layer 155. That is, the first height H1 may be the height of the first semiconductor layer 153 from the second surface 100b of the substrate 100. The first height H1 may be the height of the first semiconductor layer 153 from the bottom surface of the first trench TR1. The first height H1 may be the vertical distance from the second surface 100b of the substrate 100 to the third level lv3. The second height H2 may be the height of the second semiconductor layer 155 from the second surface 100b of the substrate 100. The second height H2 may be the height of the second semiconductor layer 155 from the bottom surface of the first trench TR1. The second height H2 may be the vertical distance from the second surface 100b of the substrate 100 to the second level lv2. Each of the first height H1 and the second height H2 may be in the range of about 3 μm to about 8 μm. The third height H3 may be the difference between the first height H1 and the second height H2. The third height H3 may be the vertical distance from the top surface 155a of the second semiconductor layer 155 to the third level lv3. For example, the third height H3 may be in the range of about 150 nm to about 1500 nm. In an embodiment, the second level lv2 and the third level lv3 may be positioned at a level lower than the bottom surface (e.g., the first level lv1) of the device isolation pattern 103. For example, the top surface 155a of the second semiconductor layer 155 and the uppermost portion of the first semiconductor layer 153 may be located at a level lower than the bottom surface of the device isolation pattern 103. The ratio of the vertical height H1 of the first semiconductor layer 153 to the vertical height of the pixel isolation pattern 150 may be in the range of about 3 / 4 to about 5 / 6. Here, the vertical height of the pixel isolation pattern 150 may be, for example, a vertical distance from the second surface 100b of the substrate 100 to the first surface 100a.

[0076] Figure 7 and Figure 8 It is conceptually shown Figure 5 The area "C" shown in FIG. 1 further illustrates an enlarged cross-sectional view of the grain structure of the first and second semiconductor layers.

[0077] refer to Figure 7 and Figure 8 , the first semiconductor layer 153 may include first grains GR1, and the second semiconductor layer 155 may include second grains GR2. The first semiconductor layer 153 and the second semiconductor layer 155 may be formed by a process of depositing polysilicon. The first grains GR1 and the second grains GR2 may have different average grain sizes from each other according to process conditions in the deposition process.

[0078] like Figure 8As shown, the image sensor may further include an oxide pattern 156 inserted between the first semiconductor layer 153 and the second semiconductor layer 155. The oxide pattern 156 may be formed of silicon oxide or include silicon oxide. That is, the oxide pattern 156 may be formed by oxidizing the surface of the first semiconductor layer 153. In an embodiment, the oxide pattern 156 may partially cover the first side surface 153a and the second side surface 153b of the first semiconductor layer 153. Alternatively, the oxide pattern 156 may conformally cover the first semiconductor layer 153. In an embodiment, a plurality of oxide patterns 156 may be provided. The oxide patterns 156 may be vertically spaced apart from each other. In an embodiment, the boundary between the first semiconductor layer 153 and the second semiconductor layer 155 may be distinguished by the oxide pattern 156.

[0079] A conductive line may be disposed on a peripheral region of the second surface 100b of the substrate 100. The conductive line may be electrically connected to the semiconductor pattern CP of the pixel isolation pattern 150. In an embodiment, the conductive line may directly contact a bottom surface CPb of the semiconductor pattern CP.

[0080] A negative voltage may be applied to the wire. As an example, the wire may be electrically connected to a charge pump, and thus, a negative voltage from the charge pump may be applied to the wire. The negative voltage may be a constant voltage. The negative voltage may be applied to the semiconductor pattern CP through the wire. Positive charges generated in the unit pixel PX may be removed by the semiconductor pattern CP surrounding the unit pixel PX. Therefore, the dark current characteristics of the image sensor may be improved.

[0081] A second trench TR2 may be provided to define a first active pattern ACT1, a second active pattern ACT2, and a third active pattern ACT3 of each unit pixel PX. The second trench TR2 may extend from the first surface 100a to the second surface 100b. The second trench TR2 may be shallower than the first trench TR1. The device isolation pattern 103 may fill the second trench TR2. The bottom surface of the pixel isolation pattern 150 may be closer to the second surface 100b of the substrate 100 than to the bottom surface of the device isolation pattern 103.

[0082] Fig. 9 is a cross-sectional view illustrating an image sensor according to an embodiment of the inventive concept.

[0083] refer to Fig. 9 , a first trench TR1′ may be provided to partially penetrate the substrate 100 and define a unit pixel PX. The first trench TR1′ may extend from the second surface 100b of the substrate 100 to the first surface 100a of the substrate 100. A bottom surface TR1b of the first trench TR1′ may be placed between the first surface 100a and the second surface 100b of the substrate 100.

[0084] The pixel isolation pattern 150' may be disposed in the first trench TR1' to fill the inner space of the first trench TR1'. The pixel isolation pattern 150' may include a first oxide layer 151 and a semiconductor pattern CP. When viewed in a cross-sectional view parallel to the second direction D2 and the third direction D3, the pixel isolation pattern 150' may extend from the second surface 100b of the substrate 100 to the first surface 100a of the substrate 100. The pixel isolation pattern 150' may be disposed to partially penetrate the substrate 100. Therefore, the vertical height of the pixel isolation pattern 150' may be less than the vertical thickness of the substrate 100. In an embodiment, the width of the pixel isolation pattern 150 in the second direction D2 may gradually decrease in a direction from the second surface 100b of the substrate 100 to the first surface 100a. The top surface 155a of the second semiconductor layer 155 may be coplanar with the second surface 100b of the substrate 100.

[0085] Fig.10 is a cross-sectional view illustrating an image sensor according to an embodiment of the inventive concept.

[0086] refer to Fig.10 The image sensor according to the present embodiment may include a first pixel isolation pattern 150 and a second pixel isolation pattern 150 ″ that penetrate the substrate 100 . The second pixel isolation pattern 150 ″ may be electrically disconnected from the first pixel isolation pattern 150 .

[0087] The transfer gate TG may be disposed on the first surface 100a of the substrate 100. The first floating diffusion region FD1 may be disposed in the substrate 100, adjacent to the transfer gate TG. The first device isolation pattern 103 and the second device isolation pattern 105 may be disposed in the substrate 100. The second floating diffusion region FD2 may be disposed in the substrate 100, and the second floating diffusion region FD2 may be spaced apart from the first floating diffusion region FD1 by the second device isolation pattern 105 in the substrate 100. In the unit pixel PX, the first photoelectric conversion region 110a may be disposed in the substrate 100. The first photoelectric conversion region 110a may be a region of the doped second conductivity type.

[0088] The first insulating layer 134 may be disposed on the second surface 100b of the substrate 100. The color filters 303a and 303c may be formed on the first insulating layer 134 and may be respectively disposed in the unit pixel PX. The light blocking pattern 133a may be formed on the first insulating layer 134 and between the color filters 303a and 303c. The side surfaces and top surfaces of the color filters 303a and 303c and the top surface of the light blocking pattern 133a may be covered with a second insulating layer 136. The space (or gap) between the color filters 303a and 303c may be filled with a low refraction pattern 133b.

[0089] The third insulating layer 138 may be disposed on the second insulating layer 136 and the low refraction pattern 133b. The third insulating layer 138 may be a silicon oxide layer or a silicon nitride layer. The pixel electrode 142 may be disposed on the third insulating layer 138 and in each unit pixel PX. The insulating pattern 148 may be inserted between the pixel electrodes 142. The insulating pattern 148 may be a silicon oxide layer or a silicon nitride layer. The second photoelectric conversion layer 110b may be disposed on the pixel electrode 142. The common electrode 144 may be disposed on the second photoelectric conversion layer 110b. The passivation layer 139 may be disposed on the common electrode 144. The microlens 307 may be disposed on the passivation layer 139.

[0090] The pixel electrode 142 and the common electrode 144 may be formed of or include at least one of the following: indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) and / or an organic transparent conductive material. The second photoelectric conversion layer 110b may be, for example, an organic photoelectric conversion layer. The second photoelectric conversion layer 110b may include a P-type organic semiconductor material and an N-type organic semiconductor material, and the P-type and / or N-type organic semiconductor material may form a PN junction. Alternatively, the second photoelectric conversion layer 110b may include quantum dots or chalcogenides.

[0091] The pixel electrode 142 can be electrically connected to the second pixel isolation pattern 150". That is, the pixel electrode 142 can be electrically connected to the semiconductor pattern CP' of the second pixel isolation pattern 150". The semiconductor pattern CP' can be formed of or include at least one of the following: for example, doped polysilicon, metal nitride (e.g., titanium nitride), metal material (e.g., tungsten, titanium and copper) or transparent conductive material (e.g., ITO). The through-hole plug 146 can penetrate the third insulating layer 138, the low-refractive pattern 133b, the second insulating layer 136, the light blocking pattern 133a and the first insulating layer 134, and can contact the second pixel isolation pattern 150". The side surface of the through-hole plug 146 can be covered with a through-hole insulating layer 147. The semiconductor pattern CP' can be electrically connected to the second floating diffusion region FD2 through the interconnect structure 212 and BCP2.

[0092] Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 and Fig.19 (hereinafter collectively referred to as “ Figures 11 to 19 ”) is along Figure 3 1 and 2 , and illustrate a method of manufacturing an image sensor according to an embodiment of the inventive concept in one example. Fig. 20 is a plan view illustrating an image sensor according to an embodiment of the inventive concept.

[0093] A method for manufacturing an image sensor according to an embodiment of the present invention may generally include: preparing a substrate including a pixel area, an optical black area, and a pad area, and having two opposing main surfaces (e.g., a first surface and a second surface); forming a pixel isolation pattern extending from the first surface to the second surface; forming an interlayer insulating layer on the first surface; and forming interconnection lines in the interlayer insulating layer.

[0094] refer to Fig.11 and Fig. 20 , a substrate 100 having a first surface 100a and an opposite second surface 100b may be prepared. The substrate 100 may include a pixel region AR, an optical black region OB, and a pad region PR. The substrate 100 may contain impurities of a first conductivity type (e.g., P-type). As an example, the substrate 100 may be a substrate in which an epitaxial layer of a first conductivity type is formed on a bulk silicon wafer of the first conductivity type. As another example, the substrate 100 may be a bulk wafer including a well of the first conductivity type.

[0095] The second trench TR2 may be formed on the first surface 100a of the substrate 100. The formation of the second trench TR2 may include: forming a mask pattern MK on the first surface 100a of the substrate 100; and performing an etching process on the first surface 100a using the mask pattern MK.

[0096] refer to Fig.12 , the first trench TR1 may be formed on the first surface 100a of the substrate 100. Before forming the first trench TR1, a second preliminary pixel isolation pattern 103p may be formed on the first surface 100a of the substrate 100. The second preliminary pixel isolation pattern 103p may be formed by performing a deposition process on the first surface 100a of the substrate 100. The second preliminary pixel isolation pattern 103p may be formed to completely fill the second trench TR2 and cover the mask pattern MK. The top surface of the second preliminary pixel isolation pattern 103p may be formed at a level higher than the first surface 100a of the substrate 100. The first trench TR1 may be formed by forming a mask (not shown) on the second preliminary pixel isolation pattern 103p and anisotropically etching the second preliminary pixel isolation pattern 103p and the substrate 100 using the mask. The bottom surface of the first trench TR1 may be located at a level higher than the second surface 100b of the substrate 100. The second preliminary pixel isolation pattern 103p may be formed of, for example, at least one of silicon oxide, silicon nitride, or silicon oxynitride or include at least one thereof.

[0097] refer to Fig.13, the first preliminary oxide layer 151P may be formed to conformally cover the inner side surface of the first trench TR1. The first preliminary oxide layer 151P may cover the inner surface of the first trench TR1 and the top surface of the second preliminary pixel isolation pattern 103p. The first preliminary oxide layer 151P may be formed by depositing an insulating material on the substrate 100 provided with the first trench TR1. The first preliminary oxide layer 151P may be formed of, for example, at least one of silicon oxide, silicon nitride, and / or silicon oxynitride or include at least one thereof.

[0098] refer to Fig.14 , a first preliminary semiconductor layer 153P may be formed on the first preliminary oxide layer 151P. The first preliminary semiconductor layer 153P may be formed by performing a first deposition process on the substrate 100 provided with the first preliminary oxide layer 151P. The first preliminary semiconductor layer 153P may cover the first preliminary oxide layer 151P on the inner side surface of the first trench TR1, and may cover the top surface of the second preliminary pixel isolation pattern 103p. The first preliminary semiconductor layer 153P may be formed of or include, for example, polycrystalline silicon.

[0099] refer to Fig.15 , a first etching process may be performed to remove the upper portion of the first preliminary semiconductor layer 153P, and as a result, the first semiconductor layer 153 may be formed. Therefore, a portion of the first preliminary oxide layer 151P may be exposed to the outside. The etching process may be performed until the first semiconductor layer 153 is located at a level lower than the bottom surface of the second preliminary pixel isolation pattern 103p. Although not shown, the first etching process may be omitted. According to an embodiment, after the etching process, a doping process may be performed on the first semiconductor layer 153. The doping process may be, for example, a beam line ion implantation process or a plasma doping (PLAD) process. In the case of a plasma doping process, a source material in a gaseous state may be supplied into a process chamber. The source material may be ionized using plasma, and then the ionized source material may be injected into the first semiconductor layer 153 by applying a high voltage bias to an electrostatic chuck (not shown) loaded with the substrate 100. By using a plasma doping process, a uniform doping profile may be achieved at a relatively deep depth, and the processing speed of the doping process may be increased. In the case of a beam-line ion implantation process, it may be difficult to uniformly dope the first semiconductor layer 153 in the vertical direction because the first trench TR1 is relatively deep and narrow. Therefore, if the doping process is performed by the beam-line ion implantation process, the impurity concentration of the first semiconductor layer 153 may vary in the vertical direction. For example, the impurity concentration of the upper portion of the first semiconductor layer 153 may be higher than the impurity concentration of the lower portion of the first semiconductor layer 153.

[0100] In some embodiments, a doping process may be performed on the first preliminary oxide layer 151P before forming the first semiconductor layer 153. Therefore, the first preliminary oxide layer 151P may include impurities of the second conductivity type. In the present embodiment, a heat treatment process may be performed after forming the first semiconductor layer 153 and the second semiconductor layer 155. As a result of the heat treatment process, impurities in the first preliminary oxide layer 151P may diffuse into the first semiconductor layer 153 and the second semiconductor layer 155. Therefore, the impurity concentrations of the first semiconductor layer 153 and the second semiconductor layer 155 may be different. For example, the impurity concentration of the first semiconductor layer 153 may be higher than the impurity concentration of the second semiconductor layer 155.

[0101] refer to Fig.16 , a second preliminary semiconductor layer 155P may be formed on the first preliminary oxide layer 151P and the first semiconductor layer 153. The second preliminary semiconductor layer 155P may cover the first semiconductor layer 153 and the first preliminary oxide layer 151P. The second preliminary semiconductor layer 155P may be formed by performing a second deposition process on the first semiconductor layer 153 and the first preliminary oxide layer 151P. The second preliminary semiconductor layer 155P may be formed to completely fill the remaining area of ​​the first trench TR1. The second preliminary semiconductor layer 155P may be formed of or include polysilicon.

[0102] In the image sensor device, if a negative voltage is applied to the semiconductor pattern CP filling the first trench TR1, the dark current characteristics of the image sensor can be improved. In the case where the first trench TR1 is not densely filled with the semiconductor pattern CP and there is a void in the first trench TR1, the dark current characteristics may deteriorate. Therefore, when the semiconductor pattern CP is formed in the first trench TR1, it is necessary to prevent the formation of a void in the first trench TR1. In an embodiment, an etching process may be further performed between the first deposition process and the second deposition process to remove the upper portion of the first semiconductor layer 153. In this case, the area of ​​the top opening through which the subsequent second deposition process will be performed can be increased, and this can make it possible to effectively supply the deposition material to the deeper area (e.g., the bottom surface) of the first trench TR1. Therefore, the formation of a void in the semiconductor pattern CP can be prevented, so that an image sensor with improved reliability can be realized.

[0103] The second semiconductor layer 155 may be formed by performing a second etching process on the second preliminary semiconductor layer 155P. The second etching process may be, for example, an anisotropic etching process or an isotropic etching process. The isotropic etching process may be performed using a wet etching process. For example, in the case where the second preliminary semiconductor layer 155P includes polycrystalline silicon, the second preliminary semiconductor layer 155P may be etched using a wet etching solution in which hydrofluoric acid (HF), nitric acid (HNO), and the like are mixed. 3 ) and acetic acid (CH 3 COOH).

[0104] refer to Fig.17 , the preliminary capping layer 157P may be formed to cover the entire top surface of the substrate 100 and fill the upper portion of the first trench TR1. The formation of the preliminary capping layer 157P may include performing a deposition process on the first surface 100a of the substrate 100. The preliminary capping layer 157P may be formed of or include at least one of silicon oxide, silicon nitride, and / or silicon oxynitride.

[0105] refer to Fig.18 , a capping pattern 157 and a device isolation pattern 103 may be formed. The formation of the capping pattern 157 and the device isolation pattern 103 may include performing a planarization process on the first surface 100a of the substrate 100. In an embodiment, the mask pattern MK may be removed after the planarization process, and in this case, the first surface 100a of the substrate 100 may be prevented from being damaged. The photoelectric conversion region 110 may be formed by doping impurities into the unit pixel PX. The photoelectric conversion region 110 may have a second conductivity type (e.g., N type) different from the first conductivity type (e.g., P type).

[0106] refer to Fig.19 , a thinning process may be performed to remove a portion of the substrate 100 or reduce the vertical thickness of the semiconductor substrate 100. The thinning process may include grinding and / or polishing the second surface 100b of the substrate 100, and performing an anisotropic or isotropic etching process. The substrate 100 may be vertically inverted for the thinning process. A portion of the substrate 100 may be removed by a grinding or polishing process, after which an anisotropic or isotropic etching process may be performed to remove surface defects from the surface of the substrate 100.

[0107] A thinning process may be performed on the second surface 100b of the substrate 100 to expose surfaces of the semiconductor pattern CP and the first oxide layer 151. The semiconductor pattern CP and the first oxide layer 151 may have bottom surfaces located at substantially the same level as the second surface 100b of the substrate 100.

[0108] Thereafter, a transfer transistor TX may be formed on the first active pattern ACT1 of each unit pixel PX, a drive transistor DX and a selection transistor SX may be formed on the second active pattern ACT2 , and a reset transistor RX may be formed on the third active pattern ACT3 .

[0109] That is, the formation of the transfer transistor TX may include: doping the first active pattern ACT1 with impurities to form a floating diffusion region FD; and forming a transfer gate TG on the first active pattern ACT1. The formation of the drive transistor DX and the select transistor SX may include: doping the second active pattern ACT2 with impurities to form an impurity region DR, and forming a drive gate SFG and a select gate SG on the second active pattern ACT2. The formation of the reset transistor RX may include: doping the third active pattern ACT3 with impurities to form an impurity region DR; and forming a reset gate RG on the third active pattern ACT3.

[0110] The first interlayer insulating layer 221 may be formed on the first surface 100a of the substrate 100. The first interlayer insulating layer 221 may be formed to cover the transfer transistor TX and the logic transistors RX, SX, and DX formed on the first surface 100a of the substrate 100.

[0111] The second interlayer insulating layer 222 and the third interlayer insulating layer 223 may be sequentially formed on the first interlayer insulating layer 221. The first interconnection line 212 and the second interconnection line 213 may be formed in the second interlayer insulating layer 222 and the third interlayer insulating layer 223, respectively.

[0112] Return to reference Figure 4 , an anti-reflection layer 132, a first insulating layer 134, and a second insulating layer 136 may be sequentially formed on the second surface 100b of the substrate 100. Color filters 303a and 303c may be formed on the unit pixels PX, respectively. Micro lenses 307 may be formed on the color filters 303a and 303c, respectively.

[0113] Fig.21 is along Fig. 20 A cross-sectional view taken along line II-II'.

[0114] refer to Fig. 20 and Fig.21 , an image sensor according to an embodiment of the inventive concept may include: a substrate 100 having a pixel region AR, an optical black region OB, and a pad region PR, an interconnection layer 20 on a first surface 100a of the substrate 100, and a base substrate 40 on the interconnection layer 20. The interconnection layer 20 may include an upper interconnection layer 21 and a lower interconnection layer 23. The pixel region AR may include a plurality of unit pixels PX. The pixel region AR may be a substrate having a plurality of unit pixels PX and a plurality of unit pixels PX. Figures 3 to 8Features described are essentially the same features.

[0115] In the optical black area OB, a first connection structure 50, a first contact part 81, and a body color filter 90 may be disposed on the substrate 100. The first connection structure 50 may include a first light blocking pattern 51, an insulating pattern 53, and a first capping pattern 55.

[0116] Combination Figure 4 refer to Fig.21 , the first light blocking pattern 51 may be disposed on the second surface 100b of the substrate 100. That is, the first light blocking pattern 51 may cover the second insulating layer 136 on the second surface 100b, and specifically, may conformally cover the inner surfaces of the third trench TR3 and the fourth trench TR4. The first light blocking pattern 51 may be disposed to penetrate the photoelectric conversion layer 10 and the upper interconnection layer 21, and connect the photoelectric conversion layer 10 to the interconnection layer 20. That is, the first light blocking pattern 51 may contact the interconnection lines disposed in the upper interconnection layer 21 and the lower interconnection layer 23 and the pixel isolation pattern 150 disposed in the photoelectric conversion layer 10. Therefore, the first connection structure 50 may be electrically connected to the interconnection lines in the interconnection layer 20. The first light blocking pattern 51 may be formed of or include at least one of metal materials (e.g., tungsten). The first light blocking pattern 51 may block light incident into the optical black area OB.

[0117] The first contact portion 81 may be disposed in an inner region of the third trench TR3 to fill the remaining region of the third trench TR3. The first contact portion 81 may be formed of or include at least one of metal materials (e.g., aluminum). The first contact portion 81 may be electrically connected to the semiconductor pattern CP. Therefore, a bias may be applied to the semiconductor pattern CP through the first contact portion 81. The insulating pattern 53 may fill the remaining region of the fourth trench TR4. The insulating pattern 53 may be disposed to completely or partially penetrate the photoelectric conversion layer 10 and the interconnection layer 20. The first cap pattern 55 may be disposed on the top surface of the insulating pattern 53. The first cap pattern 55 may be disposed on the insulating pattern 53. The first cap pattern 55 may be formed by Figure 4 The capping pattern 157 is formed of the same material as or includes the material.

[0118] The body color filter 90 may be disposed on the first contact part 81, the first light blocking pattern 51, and the first capping pattern 55. The body color filter 90 may cover the first contact part 81, the first light blocking pattern 51, and the first capping pattern 55. The first protection layer 71 may be disposed on the body color filter 90 to hermetically seal the body color filter 90.

[0119] The photoelectric conversion region 110' and the dummy region 111 may be disposed on the optical black region OB of the substrate 100. The photoelectric conversion region 110' may be doped to have a second conductivity type different from the first conductivity type. The second conductivity type may be, for example, N-type. The pixel array AP may include a plurality of unit pixels PX. The photoelectric conversion region 110' on the optical black region OB may have a structure similar to the photoelectric conversion region 110 on the pixel region AR, but may not be used to perform the same operation as the photoelectric conversion region 110 on the pixel region AR (e.g., generating an electrical signal by incident light). The dummy region 111 may not be doped with impurities. In an embodiment, the signal generated in the dummy region 111 may be used as information to remove process noise.

[0120] The second connection structure 60, the second contact part 83, and the second protection layer 73 may be disposed on the pad region PR of the substrate 100. The second connection structure 60 may include a second light blocking pattern 61, an insulating pattern 63, and a second capping pattern 65.

[0121] The second light-blocking pattern 61 may be disposed on the second surface 100b of the substrate 100. That is, the second light-blocking pattern 61 may cover the second insulating layer 136 on the second surface 100b, and may conformally cover the inner surfaces of the fifth trench TR5 and the sixth trench TR6. The second light-blocking pattern 61 may be disposed to penetrate the photoelectric conversion layer 10 and the upper interconnection layer 21 and connect the photoelectric conversion layer 10 and the interconnection layer 20 to each other. That is, the second light-blocking pattern 61 may contact the interconnection line in the lower interconnection layer 23. Therefore, the second connection structure 60 may be electrically connected to the interconnection line in the interconnection layer 20. The second light-blocking pattern 61 may be formed of or include at least one of a metal material (e.g., tungsten).

[0122] The second contact portion 83 may be provided in the fifth trench TR5 to fill the remaining area of ​​the fifth trench TR5. The second contact portion 83 may be formed of or include at least one of metal materials (e.g., aluminum). The second contact portion 83 may be used as a conductive path for electrical connection with an external device. The insulating pattern 63 may fill the remaining area of ​​the sixth trench TR6. The insulating pattern 63 may be provided to completely or partially penetrate the photoelectric conversion layer 10 and the interconnection layer 20. The second capping pattern 65 may be provided on the insulating pattern 63. The second capping pattern 65 may be provided by Figure 4 The second protection layer 73 may cover a portion of the second light blocking pattern 61 and the second capping pattern 65 .

[0123] The current applied through the second contact portion 83 may be supplied to the pixel isolation pattern 150 through the second light blocking pattern 61, the interconnection line in the interconnection layer 20, and the first light blocking pattern 51. The electrical signals generated in the photoelectric conversion regions 110 and 110' and the dummy region 111 may be transmitted to the outside through the interconnection line in the interconnection layer 20, the second light blocking pattern 61, and the second contact portion 83.

[0124] According to an embodiment of the inventive concept, an image sensor may include a pixel isolation pattern including a first semiconductor layer and a second semiconductor layer. Therefore, a void may be removed from an inner space of a trench formed in a substrate, and this may improve the reliability of the image sensor.

[0125] While example embodiments of the inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An image sensor, comprising: a substrate having a first surface and an opposite second surface and including unit pixels each having a photoelectric conversion region; a semiconductor pattern disposed in a first trench defining the unit pixel, the semiconductor pattern comprising a first semiconductor layer disposed on an inner surface of the first trench and a second semiconductor layer disposed on the first semiconductor layer; as well as a first contact portion disposed on the second surface and connected to the semiconductor pattern, The height of the first semiconductor layer from the bottom surface of the first trench is smaller than the height of the second semiconductor layer from the bottom surface of the first trench. 2 . The image sensor according to claim 1 , wherein a bottom surface of the semiconductor pattern is coplanar with the second surface of the substrate.

3. The image sensor according to claim 1, further comprising: A device isolation pattern is disposed adjacent to the first surface to fill the second trench of the substrate, wherein a top surface of the second semiconductor layer is disposed at a level between a bottom surface of the device isolation pattern and the second surface of the substrate.

4. The image sensor according to claim 1, wherein: A first width of the second semiconductor layer adjacent to the first surface is greater than a second width of the second semiconductor layer adjacent to the second surface.

5. The image sensor according to claim 1, wherein: The first semiconductor layer and the second semiconductor layer include polysilicon doped with first conductivity type impurities, and The first conductivity type is one of N type and P type.

6. The image sensor according to claim 1, wherein: A vertical distance from the first surface of the substrate to the first semiconductor layer is in the range of 50 nm to 2000 nm.

7. The image sensor according to claim 1, further comprising: An oxide pattern is disposed between the first semiconductor layer and the second semiconductor layer to at least partially cover an interface between the first semiconductor layer and the second semiconductor layer.

8. The image sensor according to claim 1, further comprising: A first light blocking pattern covers an inner surface of the third trench of the substrate and is connected to the first contact portion, wherein the first contact portion fills an inner space of the third trench.

9. The image sensor according to claim 1, further comprising: a microlens disposed on the second surface, The first trench extends from the second surface to the first surface, a bottom surface of the first trench is disposed at a level between the first surface and the second surface, and the first semiconductor layer covers the bottom surface of the first trench.

10. An image sensor, comprising: a substrate having a first surface and an opposite second surface and including a plurality of unit pixels; A color filter and a microlens are disposed on the second surface of the substrate; a pixel isolation pattern disposed in a first trench defining the unit pixel and penetrating the substrate, the pixel isolation pattern comprising a first oxide layer covering an inner surface of the first trench, a first semiconductor layer, and a second semiconductor layer; as well as a first contact portion connected to the first semiconductor layer and the second semiconductor layer, The first semiconductor layer has a first side surface and an opposite second side surface, and A distance between the first side surface and the second side surface in a horizontal direction increases as a distance from the first surface of the substrate decreases.

11. The image sensor according to claim 10, wherein: A first height of the first semiconductor layer from the second surface is smaller than a second height of the second semiconductor layer from the second surface.

12. The image sensor according to claim 10, wherein: The second semiconductor layer is disposed between the first side surface and the second side surface of the first semiconductor layer.

13. The image sensor according to claim 10, wherein: The second semiconductor layer includes a first portion and a second portion, and extends vertically toward the second surface of the substrate, The first portion contacts the first oxide layer, and The second portion is spaced apart from the first oxide layer by the first semiconductor layer interposed therebetween.

14. The image sensor according to claim 10, wherein: A thickness of the first semiconductor layer adjacent to the first surface of the substrate is smaller than a thickness of the second semiconductor layer adjacent to the second surface of the substrate.

15. The image sensor according to claim 10, wherein: A vertical distance from the first surface of the substrate to the first semiconductor layer is greater than a vertical distance from the first surface to the second semiconductor layer.

16. The image sensor according to claim 10, wherein: A ratio between a vertical height of the first semiconductor layer and a vertical height of the pixel isolation pattern is in a range of 3 / 4 to 5 / 6. 17 . The image sensor of claim 10 , further comprising an oxide pattern, wherein the oxide pattern is disposed between the first semiconductor layer and the second semiconductor layer.

18. The image sensor according to claim 10, wherein: The substrate includes a pixel region, a pad region, and an optical black region between the pixel region and the pad region. The first contact portion is disposed in the optical black region, and A first light blocking pattern is disposed between the first contact portion and the substrate, and is connected to the first semiconductor layer and the second semiconductor layer.

19. The image sensor according to claim 10, wherein: The first semiconductor layer and the second semiconductor layer include polysilicon doped with first conductivity type impurities, and The concentration of the first conductive type impurity in the first semiconductor layer is higher than that in the second semiconductor layer.

20. An image sensor, comprising: A substrate having a first surface and an opposite second surface, and including a pixel region having a plurality of unit pixels, an optical black region, and a pad region; a pixel isolation pattern filling the first trench of the substrate and defining the unit pixel, the pixel isolation pattern comprising a first oxide layer covering an inner surface of the first trench, a first semiconductor layer, and a second semiconductor layer; A color filter is disposed on the second surface of the substrate; A microlens, disposed on the color filter; A transmission transistor and a logic transistor are disposed on the first surface; a device isolation pattern disposed adjacent to the first surface to fill the second trench of the substrate; An interlayer insulating layer, disposed on the first surface; an interconnection line disposed in the interlayer insulating layer and electrically connected to the transfer transistor and the logic transistor; A first light blocking pattern and a first contact portion disposed on the optical black area; and a second light blocking pattern and a second contact portion, disposed on the pad region; The first contact portion is connected to the first light blocking pattern and the first and second semiconductor layers.

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