Mixer circuit system

Abstract

The present invention relates to a mixer circuit system. A differential mixer circuit system comprises: a first input voltage node and a second input voltage node and a first input current node and a second input current node; a passive impedance network connected between the first input voltage node and the second input voltage node and the first input current node and the second input current node and configured to convert the first input voltage signal and the second input voltage signal into the first input current signal and the second input current signal, the first input voltage signal and the second input voltage signal defining a differential input voltage signal having an input frequency, and the first input current signal and the second input current signal defining a differential input current signal; and a mixing stage configured to mix the differential input current signal with at least one mixing signal having a corresponding mixing frequency and output a differential output signal having an output frequency depending on the input frequency and each mixing frequency.

Description

Technical Field

[0001] The present invention relates to mixer circuitry, which is referred to herein as hybrid circuitry. In particular, the present invention relates to differential hybrid circuitry. Background Art

[0002] In such a mixer circuit system, an input signal having an input frequency (e.g., a radio frequency (RF)) can be received, and an output signal having an output frequency (e.g., a baseband (BB) or an intermediate frequency (IF)) can be generated based on the input signal and the mixed signal (having the mixed frequency) in a process known as heterodyning or mixing. Such a circuit system can be implemented as an integrated circuit system, for example, on an IC chip. In the case of an integrated circuit system, as is generally known, a transistor can be used as a mixing device.

[0003] It will be appreciated that the output frequency may be lower in frequency than the input frequency (as in the example above) or higher in frequency than the input frequency.Such circuitry may, for example, be used in a receiver circuit such as a radio receiver circuit or a transmitter circuit such as a radio transmitter circuit.

[0004] It would be desirable to provide improved mixer circuitry, particularly mixer circuitry for implementation as an integrated circuit system, such as on an IC chip. Summary of the invention

[0005] According to an embodiment of the first aspect of the present invention, a differential mixer circuit system is provided, which includes: a first input voltage node and a second input voltage node and a first input current node and a second input current node; a passive impedance network, which is connected between the first input voltage node and the second input voltage node and the first input current node and the second input current node, and is configured to convert the first input voltage signal and the second input voltage signal received at the first input voltage node and the second input voltage node, respectively, into a first input current signal and a second input current signal, the first input current signal and the second input current signal are provided at the first input current node and the second input current node, respectively, the first input voltage signal and the second input voltage signal define a differential input voltage signal having an input frequency, and the first input current signal and the second input current signal define a differential input current signal; and a mixing stage, which is configured to mix the differential input current signal with at least one mixing signal having a corresponding mixing frequency, and output a differential output signal having an output frequency depending on the input frequency and each mixing frequency.

[0006] The mixing stage can be viewed as mixing the differential input current signal with at least one mixing signal.

[0007] Such a differential hybrid circuit system enables the frequency of a signal to be changed to a lower or higher frequency. That is, the output frequency can be higher or lower than the input frequency. The passive impedance network enables the differential input voltage signal to be converted into a differential input current signal without using, for example, one or more switches (transistors). The passive impedance network can provide the required matching between the differential mixer circuit system and the previous stage circuit system. Compared with other technologies, this passive voltage to current conversion can result in increased speed and / or increased linearity and / or increased dynamic range.

[0008] The passive impedance network may include: a tail node for connecting to a voltage source; a first tail side impedance connected between a first input voltage node and the tail node and a first mixer side impedance connected between the first input voltage node and a first input current node; and a second tail side impedance connected between a second input voltage node and the tail node and a second mixer side impedance connected between the second input voltage node and a second input current node.

[0009] The first tail side impedance and the second tail side impedance and the first mixer side impedance and the second mixer side impedance may be resistors. In this case, the passive impedance network may be referred to as a resistor network.

[0010] The passive impedance network may include: a tail node for connecting to a voltage source; a first tail side impedance connected between a first input current node and the tail node and a first input side impedance connected between the first input current node and a first input voltage node; and a second tail side impedance connected between a second input current node and the tail node and a second input side impedance connected between the second input current node and a second input voltage node.

[0011] The first tail side impedance and the second tail side impedance may be inductors. The first input side impedance and the second input side impedance may be resistors.

[0012] The tail node may be connected to a voltage source via a current source. The current source may be configured to control or adjust a bias current flowing through the tail node.

[0013] The impedance of the passive impedance network may be or may include a resistor and / or an inductor.

[0014] The differential mixer circuit system may include a first output current node and a second output current node. The mixing stage may be connected between the first input current node and the second input current node and the first output current node and the second output current node. The mixing stage may be configured to mix the first input current signal and the second input current signal with at least one mixing signal to generate a first output current signal and a second output current signal at the first output current node and the second output current node, respectively, and the first output current signal and the second output current signal define a differential output signal.

[0015] The passive impedance network may be viewed as forming a voltage-to-current conversion stage of the differential mixer circuit system. The differential mixer circuit system may include a current-to-voltage conversion stage connected to the output current nodes and configured to convert first and second output current signals provided at the first and second output current nodes, respectively, into first and second output voltage signals, the first and second output voltage signals also being provided at the first and second output current nodes, respectively.

[0016] The mixing stage may include at least a first mixer substage, wherein X≥2. The first mixer substage may include a first switch array and a second switch array, each of the first switch array and the second switch array including X switches, X upstream nodes and X downstream nodes, and the switches of each array are respectively connected between the upstream node and the downstream node of the array along a corresponding current path. The upstream node of the first array of the first mixer substage may be connected to a first input current node, and the upstream node of the second array of the first mixer substage may be connected to a second input current node. The downstream node of the first array of the first mixer substage and the downstream node of the second array of the first mixer substage may be connected to an output current node along the following current path: the current path is arranged so that the first output current signal and the second output current signal are provided at the first output current node and the second output current node, respectively. In the first operating mode of the differential mixer circuit system, at least one mixing signal may include at least a first substage mixing signal, the first substage mixing signal is an X-phase mixing signal, and the switches of each array may be configured to be controlled by respective phases of the first substage mixing signal.

[0017] X may be ≥3, or X may be ≥4, or X may be ≥8.

[0018] The mixing stage may include at least a second mixer substage, the second mixer substage including a plurality of switch arrays, each of the plurality of switch arrays including Y switches, Y upstream nodes and Y downstream nodes, wherein Y ≥ 2, and the switches of each array are respectively connected between the upstream node and the downstream node of the array along a corresponding current path. The downstream node of the first array of the first mixer substage and the downstream node of the second array of the first mixer substage may be connected to the output current node along the following current path, and the current path is arranged to pass through the switches of the array of the second mixer substage so as to provide a first output current signal and a second output current signal at the first output current node and the second output current node, respectively. In the first operating mode, at least one mixing signal may include at least a second substage mixing signal, the second substage mixing signal being a Y-phase mixing signal, and the switches of each array of the second mixer substage may be configured to be controlled by the respective phases of the second substage mixing signal.

[0019] In a second operating mode of the differential mixer circuit system (which may replace the first operating mode): the X switches of each array of the first mixer substage can be configured to be controlled by the respective phases of the first substage mixing signal, and the Y switches of each array of the second mixer substage can be configured to be controlled by the respective control signals so that some of the Y switches (remain) turned on (ON) and some of the Y switches (remain) turned off (OFF); or the Y switches of each array of the second mixer substage can be configured to be controlled by the respective phases of the second substage mixing signal, and the X switches of each array of the first mixer substage can be configured to be controlled by the respective control signals so that some of the X switches (remain) turned on (ON) and some of the X switches (remain) turned off (OFF).

[0020] The first operating mode or the second operating mode may be simply referred to as a specific operating mode or a given operating mode. The circuit system may selectively operate in the first operating mode or the second operating mode. The circuit system may operate only in one of the first operating mode and the second operating mode. Y may be ≥3, or Y may be ≥4, or Y may be ≥8. X may be equal to Y. X and / or Y may be an even number and may be equal to 2 N , where N is a positive integer.

[0021] The switch of the first mixer substage and the switch of the second mixer substage may be transistors, for example field effect transistors.

[0022] According to an embodiment of the second aspect of the present invention, there is provided a differential mixer circuit system, the differential mixer circuit system comprising: a first input current node and a second input current node, which are configured to receive a first input current signal and a second input current signal, respectively, the first input current signal and the second input current signal defining a differential input current signal having an input frequency; a first output current node and a second output current node, which are configured to output a first output current signal and a second output current signal, respectively, the first output current signal and the second output current signal defining a differential output current signal; and a mixing stage, which is connected between the first input current node and the second input current node and the first output current node and the second output current node, and is configured to mix a differential input current signal with at least one mixing signal having a corresponding mixing frequency to generate a differential output current signal having an output frequency that depends on the input frequency and each mixing frequency, wherein: the mixing stage includes a first mixer substage and a second mixer substage; and wherein: the first mixer substage is configured to perform at least a portion of the mixing using a first substage mixing signal, the first substage mixing signal being an X-phase mixing signal having a first mixing frequency, wherein X≥4 (or X≥2 or X≥3); and / or the second mixer substage is configured to perform at least a portion of the mixing using a second substage mixing signal, the second substage mixing signal being a Y-phase mixing signal having a second mixing frequency, wherein Y≥4 (or Y≥2 or Y≥3).

[0023] The first mixer sub-stage may include a first switch array and a second switch array, each of which includes X switches, X upstream nodes and X downstream nodes, and the switches of each of these arrays are respectively connected between the upstream node and the downstream node of the array. The second mixer sub-stage may include a plurality of switch arrays, each of which includes Y switches, Y upstream nodes and Y downstream nodes, and the switches of each of these arrays are respectively connected between the upstream node and the downstream node of the array. A series of current paths may connect the input current node to the output current node, each of which current paths from one of the input current nodes from the upstream node of the switch of the first mixer sub-stage through the switch of the first mixer sub-stage to the downstream node of the switch of the first mixer sub-stage, from the upstream node of the switch of the second mixer sub-stage through the switch of the second mixer sub-stage to the downstream node of the switch of the second mixer sub-stage and then to one of the output current nodes. The X switches of each array of the first mixer sub-stage may be configured to be controlled by each phase of the first sub-stage mixing signal. The Y switches of each array of the second mixer sub-stage may be configured to be controlled by respective phases of the second sub-stage mixing signal.

[0024] According to an embodiment of a third aspect of the present invention, a differential mixer circuit system is provided, the differential mixer circuit system comprising: a first input current node and a second input current node, which are configured to receive a first input current signal and a second input current signal, respectively, the first input current signal and the second input current signal defining a differential input current signal having an input frequency; a first output current node and a second output current node, which are configured to output a first output current signal and a second output current signal, respectively, the first output current signal and the second output current signal defining a differential output current signal; and a mixing stage, which is connected between the first input current node and the second input current node and the first output current node and the second output current node, and is configured to mix the differential input current signal with at least one mixing signal having a corresponding mixing frequency to generate a differential output current signal having an output frequency depending on the input frequency and each mixing frequency, wherein the mixing stage comprises a first mixer sub-stage and a second mixer sub-stage, the first mixer sub-stage comprises a first switch array and a second switch array, each of the first switch array and the second switch array comprises X switches, X upstream nodes and X downstream nodes, wherein X≥4 (or X≥2 or X≥3), and these arrays The switches of each array in the first mixer substage are respectively connected between the upstream node and the downstream node of the array, the second mixer substage includes a plurality of switch arrays, each of the plurality of switch arrays includes Y switches, Y upstream nodes and Y downstream nodes, where Y≥4 (or Y≥2 or Y≥3), the switches of each array in the arrays are respectively connected between the upstream node and the downstream node of the array; and a series of current paths connecting the input current node to the output current node, each current path in the current paths runs from one of the input current nodes from the upstream node of the switch of the first mixer substage through the switch of the first mixer substage to The invention relates to a method of controlling an output current node of an amplifier comprising: providing an output current node of the amplifier to a downstream node of the switches of the first mixer substage, from an upstream node of the switches of the second mixer substage through the switches of the second mixer substage to a downstream node of the switches of the second mixer substage and then to one of the output current nodes, and wherein the X switches of each array of the first mixer substage are configured to be controlled by respective phases of a first substage mixing signal, the first substage mixing signal being an X-phase mixing signal having a first mixing frequency, and / or the Y switches of each array of the second mixer substage are configured to be controlled by respective phases of a second substage mixing signal, the second substage mixing signal being a Y-phase mixing signal having a second mixing frequency.

[0025] Optional features in relation to the aforementioned second and / or third aspects of the present invention may be provided as follows.

[0026] The mixing stage can be considered as mixing the differential input current signal with at least one mixing signal.

[0027] Such a differential hybrid circuit system enables the frequency of a signal to be changed to a lower or higher frequency. That is, the output frequency can be higher or lower than the input frequency.

[0028] In a first operating mode of the differential mixer circuitry, the X switches of each array of the first mixer substage may be configured to be controlled by a respective phase of the first substage mixing signal, and the Y switches of each array of the second mixer substage may be configured to be controlled by a respective phase of the second substage mixing signal.

[0029] In the second operation mode of the differential mixer circuit system: the X switches of each array of the first mixer substage can be configured to be controlled by the respective phases of the first substage mixing signal, and the Y switches of each array of the second mixer substage can be configured to be controlled by the respective control signals so that some of the Y switches (remain) turned on and some of the Y switches (remain) turned off; or the Y switches of each array of the second mixer substage can be configured to be controlled by the respective phases of the second substage mixing signal, and the X switches of each array of the first mixer substage can be configured to be controlled by the respective control signals so that some of the X switches (remain) turned on and some of the X switches (remain) turned off.

[0030] An upstream node of the first array of first mixer substages may be connected to the first input current node, and an upstream node of the second array of first mixer substages may be connected to the second input current node.

[0031] The series of current paths can be configured so that the differential mixer circuit system is configured as a single-balanced or double-balanced or triple-balanced differential mixer circuit system in the first operating mode and / or the second operating mode. This has the following advantages: undesired components at the frequency of the input signal (first sub-stage mixing signal and / or second sub-stage mixing signal and / or input voltage signal) are eliminated at the output.

[0032] A downstream node of the first array of the first mixer substage and a downstream node of the second array of the first mixer substage may be connected to an output current node along current paths arranged to pass through switches of the array of the second mixer substage such that in a first operating mode, between the first mixer substage and the second mixer substage and between the second mixer substage and the output node, current paths carrying signals having the same phase are superimposed together to provide a first output current signal and a second output current signal at the first output current node and the second output current node, respectively. In other words, the differential mixer circuitry may be balanced (i.e., double-balanced and / or triple-balanced) with respect to the first substage mixing signal and the second substage mixing signal.

[0033] A downstream node of the first array of the first mixer substage and a downstream node of the second array of the first mixer substage may be connected to an output current node along current paths arranged to pass through switches of the array of the second mixer substage such that in a second operating mode, current paths carrying signals having the same phase are superimposed together between the first mixer substage and the second mixer substage and / or between the second mixer substage and the output node to provide a first output current signal and a second output current signal at the first output current node and the second output current node, respectively. In other words, the differential mixer circuitry may be balanced (i.e., double-balanced and / or triple-balanced) with respect to the first substage mixing signal and / or the second substage mixing signal.

[0034] The downstream node of the first array of the first mixer substage and the downstream node of the second array of the first mixer substage can be connected to the output current node so that the current path from the downstream node of the first array is superimposed with the current path from the downstream node of the second array, respectively. In other words, the differential mixer circuit system can be balanced with respect to the differential input voltage signal.

[0035] A downstream node of the first array of the first mixer substage and a downstream node of the second array of the first mixer substage can be connected to the output current node such that current paths from downstream nodes of the first mixer substage connected to switches controlled by opposite phases of the first substage mixing signal add together. In other words, the differential mixer circuitry can be balanced relative to the first substage mixing signal.

[0036] The downstream nodes of the array of the second mixer sub-stage can be connected to the output current node so that the current paths from the downstream nodes of the second mixer sub-stage connected to the switches controlled by the opposite phase of the second sub-stage mixing signal add together. In other words, the differential mixer circuit system can be balanced with respect to the second sub-stage mixing signal.

[0037] The downstream nodes of the array of second mixer sub-stages may be connected to the output current nodes such that current paths from the downstream nodes of the second mixer sub-stages connected to switches respectively controlled by the Y phases of the second sub-stage clock signal are superimposed together. That is, the first output current signal and the second output current signal may each have contributions from all Y phases of the second sub-stage mixing signal.

[0038] X may be ≥3, or X may be ≥4, or X may be ≥8. Y may be ≥3, or Y may be ≥4, or Y may be ≥8. X may be ≥4 and Y may be ≥2. X may be equal to Y. X and / or Y may be even and may be equal to 2 N , where N is a positive integer.

[0039] When X=4, the four phases of the first sub-stage mixed signal may be orthogonal phases. When Y=4, the four phases of the second sub-stage mixed signal may be orthogonal phases.

[0040] The differential mixer circuit system may include a third output current node and a fourth output current node; and the downstream node of the first array of the first mixer sub-stage and the downstream node of the second array can be connected to the output current nodes along a current path through the switches of the array of the second mixer sub-stage, so that the first output current signal to the fourth output current signal with phase orthogonality are respectively provided at the first output current node to the fourth output current node.

[0041] The second mixer sub-stage may comprise at least four of said switch arrays, each of said switch arrays comprising Y switches.

[0042] X may be ≥4 and Y may be ≥2, and the second mixer substage may include at least four of the switch arrays, each of which includes Y switches. X may be ≥2 and Y may be ≥4, and the second mixer substage may include at least two of the switch arrays, each of which includes Y switches. X may be ≥4 and Y may be ≥4, and the second mixer substage may include at least two of the switch arrays, each of which includes Y switches. X may be ≥4 and Y may be ≥4, and the second mixer substage may include at least four of the switch arrays, each of which includes Y switches. X may be ≥8 and Y may be ≥8, and the second mixer substage may include at least two of the switch arrays, each of which includes Y switches.

[0043] In the second operation mode, the control signal may be configured to control the switches such that some of the switches are (remained) turned on to connect the downstream node to the output current node, thereby providing an output current signal at the output current node.

[0044] In a second operating mode, the control signal can be configured to control the individual switches so that some of these switches (remain) turned on to connect the downstream node to the output current node, so that (at each of these switches) current paths carrying signals with different phases from each other are superimposed.

[0045] The switch of the first mixer substage and the switch of the second mixer substage may be transistors, for example field effect transistors.

[0046] The differential mixer circuit system may include: a first input voltage node and a second input voltage node and a first input current node and a second input current node; and a passive impedance network, which is connected between the first input voltage node and the second input voltage node and the first input current node and the second input current node, and is configured to convert the first input voltage signal and the second input voltage signal received at the first input voltage node and the second input voltage node, respectively, into a first input current signal and a second input current signal, the first input current signal and the second input current signal are provided at the first input current node and the second input current node, respectively, and the first input voltage signal and the second input voltage signal define a differential input voltage signal having the input frequency.

[0047] The passive impedance network enables the differential input voltage signal to be converted into a differential input current signal without using, for example, one or more switches (transistors). The passive impedance network can provide the required matching between the differential mixer circuit system and the preceding stage circuit system. Such passive voltage-to-current conversion can result in increased speed and / or increased linearity and / or higher dynamic range compared to other techniques.

[0048] The passive impedance network may include: a tail node for connecting to a voltage source; a first tail side impedance connected between a first input voltage node and the tail node and a first mixer side impedance connected between the first input voltage node and a first input current node; and a second tail side impedance connected between a second input voltage node and the tail node and a second mixer side impedance connected between the second input voltage node and a second input current node.

[0049] The passive impedance network may include: a tail node for connecting to a voltage source; a first tail side impedance connected between a first input current node and the tail node and a first input side impedance connected between the first input current node and a first input voltage node; and a second tail side impedance connected between a second input current node and the tail node and a second input side impedance connected between the second input current node and a second input voltage node.

[0050] The differential mixer circuit system (of any of the aforementioned aspects) may include a pair of auxiliary transistors whose source terminals are connected to corresponding auxiliary voltage sources via corresponding impedances, whose drain terminals are connected to corresponding nodes at corresponding positions on a pair of said current paths respectively carrying current signals with opposite phases, and whose gate terminals are connected to each other's drain terminals.

[0051] The differential mixer circuit system (of any of the aforementioned aspects) may include a pair of auxiliary transistors whose source terminals are connected to corresponding auxiliary voltage sources via corresponding impedances, whose drain terminals are respectively connected to the second input current node and the first input current node, and whose gate terminals are respectively connected to the first input current node and the second input current node.

[0052] The differential mixer circuit system (of any of the aforementioned aspects) may include a pair of auxiliary transistors whose source terminals are connected to corresponding auxiliary voltage sources via corresponding impedances, whose drain terminals are respectively connected to the second output current node and the first output current node, and whose gate terminals are respectively connected to the first output current node and the second output current node.

[0053] The differential mixer circuit system (of any of the aforementioned aspects) may include a pair of auxiliary transistors whose source terminals are connected to corresponding auxiliary voltage sources via corresponding impedances, whose drain terminals are respectively connected to the fourth output current node and the third output current node, and whose gate terminals are respectively connected to the third output current node and the fourth output current node.

[0054] Such an auxiliary transistor may provide a gain “boost” to the differential mixer circuitry (eg, at high frequencies compared to at DC). That is, the gain of the differential mixer circuitry may be boosted or increased by the auxiliary transistor.

[0055] For each pair of auxiliary transistors, the auxiliary voltage sources may have the same voltage level as each other or different voltage levels from each other.

[0056] According to an embodiment of a fourth aspect of the present invention, there is provided an analog-to-digital converter circuit system, which includes a differential mixer circuit system and a (e.g., current mode) analog-to-digital converter, wherein the differential mixer circuit system is configured to: receive an analog differential input current signal having an input frequency; mix the differential input current signal with a first sub-stage mixing signal and a second sub-stage mixing signal having a first mixing frequency and a second mixing frequency, respectively; and output an analog differential output current signal having an output frequency depending on the input frequency and the first mixing frequency and the second mixing frequency, wherein the analog-to-digital converter is configured to convert the analog differential output current signal into a digital signal, wherein the differential mixer circuit system includes a first mixer sub-stage and a second mixer sub-stage, the first mixer sub-stage being configured to be controlled by X phases of the first sub-stage mixing signal, and the second mixer sub-stage being configured to be controlled by Y phases of the second sub-stage mixing signal, wherein X≥4 (or X≥2 or X≥3) and Y≥4 (or Y≥2 or Y≥3).

[0057] According to an embodiment of a fifth aspect of the present invention, there is provided an analog-to-digital converter circuit system, the analog-to-digital converter circuit system comprising the circuit system of any one of the first to third aspects described above.

[0058] As appropriate, the differential output current signal or the differential output voltage signal may be an analog differential output signal, and the analog-to-digital converter circuitry may include an analog-to-digital converter configured to convert the analog differential output signal into a digital (differential output) signal.

[0059] According to an embodiment of a sixth aspect of the present invention, there is provided an integrated circuit system such as an IC chip and / or an ADC circuit system, the integrated circuit system comprising the circuit system of any one of the first to fifth aspects.

[0060] Features of any of the above aspects may be applied to any of the other above aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] By way of example, reference will now be made to the accompanying drawings, in which:

[0062] Figure 1A is a schematic diagram of a mixer circuit system as a comparative example;

[0063] Figure 1B It is used to understand Figure 1A A schematic diagram of a circuit system;

[0064] Figure 2 is a schematic diagram of a modified mixer circuit system as a comparative example;

[0065] Figure 3 is a schematic diagram of a first example arrangement of mixer circuitry;

[0066] Figure 4 is a schematic diagram of a modified first example arrangement of mixer circuitry;

[0067] Figure 5 It is used to understand Figure 4 A schematic diagram of a circuit system;

[0068] Figure 6 It is used to understand Figure 3 and Figure 4 A graph of a circuit system;

[0069] Figure 7 is a schematic diagram of another modified first example arrangement of mixer circuitry;

[0070] Fig. 8A and Figure 8B It is used to understand Figure 3 , Figure 4 and Figure 7 A graph of a circuit system;

[0071] Fig. 9 is a schematic diagram of another modified first example arrangement of mixer circuitry;

[0072] Fig.10 It is used to understand Fig. 9 A schematic diagram of a circuit system;

[0073] Fig.11 is a schematic diagram of another modified first example arrangement of mixer circuitry;

[0074] Fig.12 is a schematic diagram of a second example arrangement of mixer circuitry;

[0075] Fig.13 It is used to understand Fig.12 A graph of a circuit system;

[0076] Fig.14 It is used to understand Fig.12 A graph of a circuit system;

[0077] Fig.15 is a schematic diagram of a modified second example arrangement of mixer circuitry;

[0078] Fig.16 is a schematic diagram of another modified second example arrangement of mixer circuitry;

[0079] Fig.17 It is used to understand Fig.16 A graph of a circuit system;

[0080] Fig.18 It is used to understand Fig.16 A graph of a circuit system;

[0081] Fig.19 It is used to understand Fig.12 , Fig.15 and Fig.16 A graph of a circuit system;

[0082] Fig. 20 is a schematic diagram of another modified second example arrangement of mixer circuitry;

[0083] Fig.21 It is used to understand Fig. 20 A graph of a circuit system;

[0084] Fig. 22 It is used to understand Fig. 20 A graph of a circuit system;

[0085] Fig.23 is a schematic diagram of another modified second example arrangement of mixer circuitry;

[0086] Fig.24A is a schematic diagram of an ADC circuit system; and

[0087] Fig. 24B It is a schematic diagram of an integrated circuit. DETAILED DESCRIPTION

[0088] Figure 1A is a schematic diagram of a mixer circuit system 100 as a comparative example.

[0089] The mixer circuit system 100 includes a circuit configured to receive an input voltage signal V RF The input voltage node 101 is connected to the switch 111 so that the input voltage signal controls the switch 111. The switch 111 is connected to a high voltage reference (or source) V H The mixer circuit system 100 includes a first mixer switch 131 connected between the input current node 121 and a first current output node 171, and a second mixer switch 132 connected between the input current node 121 and a second current output node 172. In this example, the switches 111, 131 and 132 are field effect transistors, in particular PMOS MOSFETs. The mixer circuit system 100 also includes a first mixer switch 131 connected between the input current node 121 and a first current output node 171, and a second mixer switch 132 connected between the input current node 121 and a second current output node 172. In this example, the switches 111, 131 and 132 are field effect transistors, in particular PMOS MOSFETs. The mixer circuit system 100 also includes a first mixer switch 131 connected between the first current output node 171 and a low voltage reference (which is lower than the high voltage reference V H ), and a second resistor 192 connected between the second current output node 172 and a low voltage reference (or source) having a voltage lower than the high voltage reference V H .

[0090] The switch 111 converts the input voltage signal V RF is converted into an input current signal, which is provided at the input current node 121. Based on the mixed signal V LO The input current signal (RF current) is directed downward through one or the other of the first mixer switch 131 and the second mixer switch 132 by controlling the first mixer switch 131 and the second mixer switch 132 with opposite phases (where LO can be considered to represent a local oscillator). For example, the first mixer switch 131 is connected to be composed of a mixed signal V with a phase of 0 degrees. LO The second hybrid switch 132 is connected to a hybrid signal with a phase of 180 degrees (ie, -V LO) control. It should be understood that, depending on the mixed signal, there may be a time period during which the RF current is distributed between the first mixer switch 131 and the second mixer switch 132. The first mixer switch 131 and the second mixer switch 132 are configured to mix the input current signal with the mixed signal to output a current output signal, which is provided at the current output node 171 and the current output node 172. The first resistor 191 and the second resistor 192 are configured to convert the current signals output by the first mixer switch and the second mixer switch, respectively, into voltage signals to provide a voltage output signal V between the first output node 181 and the second output node 182. IF .

[0091] In general, the mixer circuit system 100 is configured to convert the input voltage signal V RF Convert the input current signal into an input current signal; combine the input current signal with the mixed signal V LO Mixing; and output voltage output signal V IF . Voltage output signal V IF It depends on the input voltage signal (V RF ) frequency (input frequency f IN ) and mixed signal V LO The frequency (mixing frequency f MIX ) frequency (output frequency). In particular, the voltage output signal V IF The included frequency is (f IN ±f MIX )’s weight.

[0092] Capacitor 103 represents the sum of the parasitic capacitance seen at the drain of switch 111. Capacitor 103 has a capacitance value C1 given by:

[0093] C1=C DB1 +C GS2 +C GS3 +C SB2 +C SB3 (1)

[0094] Among them, C DB1 is the drain-to-body capacitance of the switch 111, C GS2 and C GS3 are the gate-source capacitance of the first hybrid switch 131 and the gate-source capacitance of the second hybrid switch 132, and C SB2 and C SB3 are the source-bulk capacitance of the first hybrid switch 131 and the source-bulk capacitance of the second hybrid switch 132 , respectively.

[0095] Figure 1B It is used to understand Figure 1ASchematic diagram of a mixer circuit system 100. Figure 1B is a small signal AC model of the mixer circuit system 100, and its elements correspond to the elements in the mixer circuit system 100, which is referred to herein as the model circuit system 100S. That is, the current source 111S represents the transfer switch 111, the node 121S represents the input current node 121, the current source 131S represents the first mixer switch 131, the node 171S represents the current output node 171, the resistor 191S represents the first resistor 191, and the capacitor 103S represents the capacitor 103 (i.e., the sum of the parasitic capacitances seen at the drain of the transfer switch 111) and has the capacitance value C1 in equation 1. That is, in Figure 1B In the present invention, only one "side" of the mixer circuit system 100 is considered, it being understood that equivalent considerations apply to the other side.

[0096] according to Figure 2 , the gain of the circuit (in the s-domain) can be calculated as follows:

[0097] G1=(2 / π)×R L ×g mRF ×g mLO / (C1s+g mLO ) (2)

[0098] Among them, g mRF is the small signal transconductance of the switch 111, R L is the resistance value of resistor 191, and g mLO is the transconductance of each of the first hybrid switch 131 and the second hybrid switch 132. Due to the down-conversion gain of the first hybrid switch 131 and the second hybrid switch 132 (which together may be referred to as a hybrid stage), a factor of (2 / π) is added to the equation.

[0099] Two important aspects of the mixer circuit system 100 can be derived from Equation 2 as follows. First, the main pole of the circuit is:

[0100] ω p =g mLO / C1 (3)

[0101] Equation 3 mainly determines the maximum speed of the mixer. The second conclusion is the accuracy (linearity) of the mixer, which is mainly due to the following two terms in Equation 2: The transconductance g of the switch 111 mRF And in the two conductance g mLO The current sharing that occurs between C1 (i.e., the term 1 / (C1s+g mLO )). When the input voltage signal V RF When the amplitude increases, the amount g mRFand g mLO Both change, which will produce nonlinear behavior, which will be reflected in the mixer's P 1dB (1dB compression point or P_1dB) or IP3 (third order intercept point).

[0102] Figure 2 2 is a schematic diagram of a modified mixer circuit system 200, also as a comparative example. The modified mixer circuit system 200 is an implementation of the mixer circuit system 100 that has been modified to be double-balanced.

[0103] It should be understood that the mixer circuit system 200 receives a differential input voltage signal V RF As input, two arrays 231 and 232 of switches 231A / 231B and switches 232A / 232B are used to combine the differential input voltage signal with the mixed signal V LO Mix and output a differential voltage signal V IF .

[0104] In detail, the modified mixer circuit system 200 includes first and second input voltage nodes 201 and 202, first and second transfer switches 211 and 212, first and second input current nodes 221 and 222, first and second switch arrays 231 and 232, first and second current output nodes 271 and 272, first and second resistors 291 and 292, and first and second output nodes 281 and 282. The first and second current output nodes 271 and 272, the first and second resistors 291 and 292, and the first and second output nodes 281 and 282 are configured in the same manner as the corresponding elements (171, 172, 191, 192, 181, and 182, respectively) of the mixer circuit system 100.

[0105] The first input voltage node 201 and the second input voltage node 202 are configured to receive the voltages therebetween, which are shown as having positive components V RF+ and negative component V RF- The differential input voltage signal V RF The first switch array 231 includes a first switch 231A and a second switch 231B, which are configured to receive an input current signal from the node 221 and to be configured to be output from the mixed signal V LOThe opposite phase control of the first switch 131 and the second switch 132 of the mixer circuit system 100 is similar. Similarly, the second switch array 232 includes a first switch 232A and a second switch 232B, which are configured to receive the input current signal from the node 222 and are configured to be controlled by the mixed signal V LO In this example, the switches 211, 212, 231A, 231B, 232A, 232B are field effect transistors, in particular PMOS MOSFETs.

[0106] See also Figure 2 It should be understood that each of the output nodes 271 and 272 carries a double balanced signal because any V LO Chain through -V LO The chain is balanced, and similarly any V RF+ Chain through V RF- Chain Balance. Taking output node 271 as an example, the chain from transistor 231A is balanced by the chain from transistor 232B, and the chain from transistor 211 is balanced by the chain from transistor 212.

[0107] Equations 1 to 3 are equally applicable to the modified mixer circuit system 200 as they are to the mixer circuit system 100. As discussed above, the two conclusions drawn from Equation 2 (the speed limitation of the mixer circuit system 100 and the modified mixer circuit system 200, and the nonlinearity of the mixer circuit system 100 and the modified mixer circuit system 200) are disadvantageous. To overcome these disadvantages (and other disadvantages), two example arrangements are disclosed herein.

[0108] Figure 3 is a schematic diagram of a first example arrangement 300 of mixer circuitry embodying the present invention.

[0109] The mixer circuit system 300 is a differential mixer circuit system and includes a first input voltage node 301 and a second input voltage node 302, a current source 308, a passive impedance network 310 (which can be referred to as a passive network or a passive matching network), a first input current node 321 and a second input current node 322, a first array 331 of first switches 331A and a second switch 331B, a second array 332 of first switches 332A and a second switch 332B, a first output current node 371 and a second output current node 372, a first output voltage node 381 and a second output voltage node 382, ​​and a first resistor 391 and a second resistor 392.

[0110] The first input voltage node 301 and the second input voltage node 302 are configured to receive a first input voltage signal V RF+ and the second input voltage signal V RF- , the first input voltage signal V RF+ and the second input voltage signal V RF- Define the input frequency as f IN The differential input voltage signal V RF The passive network 310 is connected between the first input voltage node 301 and the second input voltage node 302 and is connected between the current source 308 (which in turn is connected to a high voltage reference or power supply V H ) and the first input current node 321 and the second input current node 322. The current source 308 is configured to control or adjust the bias current provided to the passive network 310, that is, so that the bias current is actually a DC (that is, ideally, constant) current. The passive network 310 is configured to convert the first input voltage signal V RF+ and the second input voltage signal V RF- The first input current signal and the second input current signal are respectively converted into a first input current signal and a second input current signal, and the first input current signal and the second input current signal are respectively provided at a first input current node 321 and a second input current node 322. The passive network 310 makes the first input current signal and the second input current signal have corresponding (respectively represented by V RF+ and V RF- The passive network 310 operates as a voltage-to-current conversion stage 310. The first input current signal and the second input current signal define a voltage having an input frequency f IN The differential input current signal.

[0111] The first array 331 and the second array 332 may be collectively referred to as a mixing stage 350. The mixing stage 350 is configured to mix a differential input current signal with a mixing frequency f MIX Mixed signal V LO mixed, and the output has a frequency that depends on the input frequency f IN and the mixing frequency f MIX The output frequency f OUT In particular, the differential output signal contains a frequency (f IN ±f MIX ) weight. Specifically, Figure 3 In the example shown, the mixing stage 350 is configured to generate first and second output current signals at first and second output current nodes 371 and 372 , respectively, and the first and second output current signals define a differential output signal, which is a differential output current signal.

[0112] The first switch 331A and the second switch 331B of the first array 331 are each connected to receive a first input current signal at the first input current node 321, and the first switch 332A and the second switch 332B of the second array 332 are each connected to receive a second input current signal at the second input current node 322. The first switches 331A and 332A are connected to receive a mixed signal V having a first phase (e.g., 0 degrees). LO The outputs of the first switches 331A and 332A are connected to the first output current node 371 and the second output current node 372, respectively. The second switches 331B and 332B are connected to be connected to the mixed signal V having a second phase (e.g., 180 degrees) opposite to the first phase. LO (exist Figure 3 In the "-V LO ” shown) control, and the outputs of the second switches 331B and 332B are connected to the second output current node 372 and the first output current node 371, respectively.

[0113] To better understand this embodiment and the subsequent embodiments disclosed herein, it may be useful to note the following: the current signal output from the first switch 331A of the first array 331 and the current signal output from the second switch 332B of the second array 332 can be considered to have the same phase as each other. This is because the input current signals received by the two switches 331A and 332B have opposite phases, and the mixed signal that controls the two switches also has opposite phases (and because the phase of the input current signal and the phase of the mixed signal are added at the output of each switch of the first array 331 and the second array 332). Then, the current signal output from the first switch 331A of the first array 331 and the current signal output from the second switch 332B of the second array 332 are added at the output current node 371. A similar description applies to the current signal output from the second switch 331B of the first array 331 and the current signal output from the first switch 332A of the second array 332 being added at the output current node 372.

[0114] Using a differential input voltage signal and a differential mixing signal, and "crossing" the current paths between the mixing stage 350 and the output current nodes 371 and 372 so that the current signals from the switches of the first array 331 are summed with the current signals from the switches of the second array 332 as shown, provides a double balanced arrangement as previously mentioned. For example, any V LO Chain through -V LO The chain is balanced, and similarly any V RF+ Chain through V RF-The differential signaling also provides common-mode rejection.

[0115] The first resistor 391 and the second resistor 392 (as an example implementation of impedance) can be collectively referred to as a current-to-voltage conversion stage 390. The first resistor 391 and the second resistor 392 are connected to the first current output node 371 and the second current output node 372, respectively, and are configured to convert the first output current signal and the second output current signal into a first output voltage signal and a second output voltage signal, which are provided at the first output voltage node 381 and the second output voltage node 382, ​​respectively. The first output voltage signal and the second output voltage signal define a differential output voltage signal having an output frequency. The differential output signal can be a differential output current signal or a differential output voltage signal. The first resistor and the second resistor are connected to the first current output node 371 and the second current output node 372, respectively, with their voltage levels at the high reference voltage V H between a low voltage reference (or source) (e.g., ground GND) and a voltage level below that.

[0116] When implemented in other circuit systems (e.g., analog-to-digital converters, ADCs), the passive network 310 provides the required matching between the mixer circuit system 300 and the preceding stage (e.g., low noise amplifiers, LNAs). For example, if the LNA is designed off-chip, the passive network 310 can be designed to provide the required characteristic impedance (e.g., 50Ω) seen from the input port of the mixer circuit system 300 to eliminate the effect. In addition, the passive network 310 linearly converts the voltage to a current (i.e., converts the differential input voltage signal to a differential input current signal). Further, the passive network 310 can be designed to provide the desired RF filtering to remove the RF image.

[0117] Figure 4 is a modification 300 - 1 of the first example arrangement 300 of mixer circuitry embodying the present invention.

[0118] The mixer circuit system 300-1 includes a passive network 310-1, which includes impedances 311 to 314 and a tail node 309 as an implementation of the passive network 310. Other elements of the mixer circuit system 300-1 are similar to Figure 3 The elements of the mixer circuit system 300 shown are the same and have the same reference numerals. Duplicated descriptions are omitted.

[0119] Referring to the mixer circuit system 300-1, the passive network 310-1 includes a tail node 309, a first tail side impedance 311 and a second tail side impedance 312, and a first mixer side impedance 313 and a second mixer side impedance 314. The tail node 309 is connected to the current source 308 to receive the current from the current source 308. The first tail side impedance 311 is connected between the first input voltage node 301 and the tail node 309, the first mixer side impedance 313 is connected between the first input voltage node 301 and the first input current node 321, the second tail side impedance 312 is connected between the second input voltage node 302 and the tail node 309, and the second mixer side impedance 314 is connected between the second input voltage node 302 and the second input current node 322.

[0120] Figure 4 A more specific implementation 310' of the passive network 310 is also shown, in which the impedances 311 to 314 are implemented as resistors 311 to 314. In this case, the passive network may be referred to as a resistive network 310'.

[0121] Figure 5 It is used to understand Figure 4 Schematic diagram of mixer circuit system 300-1. Figure 5 is a small signal AC model of mixer circuit system 300-1, and its elements correspond to the elements in mixer circuit system 300-1, which is referred to herein as model circuit system 300-1S. That is, node 301S represents the first input node 301, impedance 311S represents the first tail side impedance 311, impedance 313S represents the first mixer side impedance 313, node 321S represents the first input current node 321, current source 331S represents one of the switches of the first switch array 331, node 371S represents the first output current node 371, and resistor 391S represents the first resistor 391. Capacitance 303S represents the sum of the parasitic capacitances seen at the sources of the switches of the first array 331. That is, in Figure 5 In the example, only one "side" of the mixer circuit system 300-1 is considered, with the understanding that equivalent considerations apply to the other side. That is, the model circuit system 300-1S is a half-circuit model that gives the same gain results as the corresponding full circuit (i.e., the mixer circuit system 300-1).

[0122] based on Figure 4 and Figure 5 It is obvious that the input impedance seen from the first input voltage node 301 can be calculated as

[0123] Z in =(Z1+1 / g mLO )||Z2 (4)

[0124] Wherein, Z1 is the impedance value of the first mixer-side impedance 313, Z2 is the impedance value of the first tail-side impedance 311, and g mLO is the transconductance of one of the switches of the first array 331. Of course, a similar calculation can be made for the input impedance seen from the second input voltage node 302.

[0125] according to Figure 5 , the gain of the mixer circuit system 300-1 can be calculated as

[0126] G2=(2 / π)×R L ×g mLO ×Y1 / (g mLO +sC1+Y1) (5)

[0127] Where Y1=1 / Z1, and C1 is the capacitance value of capacitor 301S (ie, the parasitic capacitance seen at the source of the switches of the first array 331):

[0128] C1=C GS2 +C GS3 +C SB2 +C SB3 (6)

[0129] Among them, C GS2 and C GS3 are the gate-source capacitance of switch 331B and the gate-source capacitance of switch 331A, respectively, and C SB2 and C SB3 They are the source-to-bulk capacitance of switch 331B and the source-to-bulk capacitance of switch 331A, respectively.

[0130] Comparing mixer circuit system 300-1 with mixer circuit system 100 or mixer circuit system 200, it will be appreciated that because mixer circuit system 300-1 does not include a "switch" (e.g., switch 111), the drain-body capacitance of switch 111 is removed from the parasitic capacitance value C1, which makes C1 smaller.

[0131] Refer again Figure 4 , a specific implementation 310 ′ of the passive network 310 includes resistors 311 to 314 as impedances 311 to 314 , and as mentioned above may be referred to as a resistor network 310 ′.

[0132] Assuming that the passive network 310 includes resistors as in the resistive network 310', the following calculations are simplified. Of course, similar considerations apply (and corresponding advantages are obtained), however, in practice the impedances 311 to 314 are implemented. Looking at the resistive network 310', the gain calculated in Equation 5 can be calculated as

[0133] G2=(2 / π)×R L ×g mLO ×g1 / (g mLO +sC1+g1) (7)

[0134] Where g1=1 / R1, and R1 is the resistance value of either the first mixer side resistor or the second mixer side resistor assuming the circuit is balanced. Similar to Equation 3, the dominant pole of the mixer circuit system 300-1 can be calculated as:

[0135] ω p =(g mLO +g1) / C1 (8)

[0136] Comparing Equation 8 with Equation 3, it should be appreciated that the dominant pole of the mixer circuit system 300-1 increases to (1+g1 / g mLO ) times. This means that the passive network can be designed so that a higher bandwidth is achieved compared to mixer circuitry 100 or 200 (in fact, mixer circuitry 300-1 is faster than mixer circuitry 100 or 200). It should be understood that similar considerations apply to mixer circuitry 300 because, compared to mixer circuitry 100 or 200, there is no "transfer switch" (i.e., transfer switch 111), but instead a passive network is used for voltage to current conversion.

[0137] Figure 6 is a graph for understanding the mixer circuit systems 300 and 300 - 1 . Figure 6 The graph in FIG. 1 shows the normalized gain of mixer circuit system 200 and mixer circuit system 300 - 1 (with resistor network 310 ′) versus normalized input frequency (RF in this case). Simulations are performed to obtain Figure 6 291, 292, 391, and 392), and test bench conditions. RF The single tone signal (single tone) is used as the input voltage signal V RF And the mixed signal V LO The mixing frequency is set to f LO So that f LO =f RF+100 MHz. A 100 MHz tone amplitude is detected at the output of each of mixer circuitry 200 and mixer circuitry 300-1. Figure 6 The frequency response with respect to the normalized input frequency f is shown for the mixer circuit system 200 (shown by the curve with crosses) and the mixer circuit system 300-1 (shown by the curve with circles). RF / f T The normalized mixer gain G / G0 is obtained by dividing the input frequency f RF Normalized to f T The generated T is the cutoff frequency of the switches of the first array 331 and the second array 332 and the two arrays 231 and 232. The normalized mixer gain is generated by normalizing the mixer gain G to G0, i.e., the mixer gain at DC. It can be seen that the bandwidth of the mixer circuit system 200 (i.e., the input frequency corresponding to the normalized gain of -3dB) is about 0.38f T , where f T is the cut-off frequency as defined above. The bandwidth of mixer circuitry 300-1 (input frequency corresponding to a normalized gain of -3 dB) is approximately 0.76f T , which is significantly higher than the bandwidth of the mixer circuit system 200.

[0138] In the generation Figure 6 In the example simulation of the graph in FIG. 1 , the resistance value and the transconductance value are as follows: R1=40Ω, R2=150Ω, where R1 is the resistance value of each of the mixer side resistors 313 and 314, and R2 is the resistance value of each of the tail side resistors 311 and 312, and 1 / g mLO =35Ω. According to equation 8, the bandwidth of mixer circuit system 300-1 should be increased to (1+35 / 40)=1.875 times compared to the bandwidth of mixer circuit system 200. This is almost the same as Figure 6 The bandwidth improvement shown in the curve graph is consistent.

[0139] One source of nonlinearity in mixer circuitry 100 and mixer circuitry 200 is the transconductance of switch 111 (and 121), i.e., g mRF , the switch 111 (and 121) acts as a V / I converter. Ignoring the frequency response of the mixing stage 350, using Equation 2 to calculate the gain change of the mixer circuit system 100 or 200 based on the change in the transconductance of the switch 111 or 121 yields:

[0140] ΔG1=(2 / π)×R L ×Δg mRF (9)

[0141] Normalize the change in mixer gain to the mixer gain:

[0142] ΔG1 / G1=Δg mRF / g mRF (10)

[0143] Considering the mixer circuit system 300-1 (with the resistor network 310') and ignoring the high frequency response, the gain change of the mixer circuit system 300-1 can be calculated according to Equation 7:

[0144] ΔG2 / G2=Δg mLO / (g mLO ×(1+g mLO / g1)) (11)

[0145] Assume that the large signal variation of the transconductance of the switching switches in the mixer circuit systems 100 and 200 is about the same level as the large signal variation of the transconductance of the switches of the first array 331 and the second array 332 of the mixer circuit system 300-1, that is:

[0146] Δg mLO ~Δg mRF (12)

[0147] Then a comparison of the gain changes in (10) and (11) yields:

[0148] (ΔG2 / G2) / (ΔG1 / G1)=1 / (1+g mLO / g1) (13)

[0149] That is, the gain variation in mixer circuitry 300-1 is smaller than the gain variation in mixer circuitry 100 and 200. This means that mixer circuitry 300-1 (and therefore mixer circuitry 300 due to the absence of switching switches 111 / 211 / 212) exhibits better large signal behavior (in terms of linearity, P_1dB, and IP3) than mixer circuitry 100 and mixer circuitry 200.

[0150] Figure 7 is a schematic diagram of another modification 300-2 of the first example arrangement of mixer circuitry embodying the present invention.

[0151] The mixer circuit system 300-2 includes a passive network 310-2 including impedances 315 to 318 and a tail node 309 as an implementation of the passive network 310. Other elements of the mixer circuit system 300-2 are similar to Figure 3 The elements of the mixer circuit system 300 shown are the same and have the same reference numerals. Duplicated descriptions are omitted.

[0152] Referring to the mixer circuit system 300-2, the passive network 310-2 includes a tail node 309, a first tail impedance 315 and a second tail impedance 316, and a first input impedance 317 and a second input impedance 318. The first tail impedance 315 is connected between the first input current node 321 and the tail node 309, the first input impedance 317 is connected between the first input current node 321 and the first input voltage node 301, the second tail impedance 316 is connected between the second input current node 322 and the tail node 309, and the second input impedance 318 is connected between the second input current node 322 and the second input voltage node 302. The first tail impedance 315 and the second tail impedance 316 are implemented as inductors, and the first input impedance 317 and the second input impedance 318 are implemented as resistors. This is not required.

[0153] Fig. 8A and Figure 8B is a graph useful for understanding the mixer circuit systems 300, 300-1, and 300-2. A simulation is performed to obtain Fig. 8A and Figure 8B In addition to using and comparing mixer circuit system 300-2 and mixer circuit system 200, the simulation is performed to obtain Figure 6 The simulation of the curve graph in has the same settings. In addition, the following example design parameters are used in the simulation: VDD = 0.9V, f RF =39.9GHz, f LO =40GHz. In addition, the input RF amplitude (input voltage signal V RF The amplitude is swept from -50dBm to -10dBm.

[0154] Fig. 8A The graph in FIG. 1 shows the input RF power in dBm (i.e., the input voltage signal V ) for the mixer circuit system 200 (shown by the curve with crosses), the mixer circuit system 300-2 (shown by the curve with circles), and the ideal mixer (shown by the curve with squares). RF The output IF power of the detected tone in dBm (i.e., the output voltage signal V IF output power). Figure 8B The graph in FIG. 1 shows the input RF power in dBm (i.e., the input voltage signal V ) for the mixer circuit system 200 (shown by the curve with crosses), the mixer circuit system 300-2 (shown by the curve with circles), and the ideal mixer (shown by the curve with squares). RF The normalized value of the output IF power of the ideal mixer (i.e., the output voltage signal V IFoutput power).

[0155] according to Fig. 8A and Figure 8B The results shown in FIG. 2 show that the mixer circuit system 200 shows a 1 dB compression point, P 1dB =-16.9 dBm, while the mixer circuit system 300-2 shows a 1 dB compression point, P 1dB =-15.1 dBm, which is about 1.8 dB higher than the 1 dB compression point of mixer circuitry 200. Thus, linearity is improved in mixer circuitry 300-2 compared to mixer circuitry 200 (and the same considerations apply to mixer circuitry 300 and mixer circuitry 300-1 as to 300-2). In this design example, the hybrid conversion gain is about 18.4 dB.

[0156] Fig. 9 is a schematic diagram of another modification 300-3 of the first example arrangement of mixer circuitry embodying the present invention.

[0157] The mixer circuit system 300-3 includes a boost (gain boost) network 340. The other components of the mixer circuit system 300-3 are similar to Figure 4 The elements of the mixer circuit system 300-1 are shown to be the same and have the same reference numerals. Repeated descriptions are omitted. Of course, the boosting network 340 may be similarly included in any of the mixer circuit systems 300, 300-1 and 300-2.

[0158] Referring to mixer circuitry 300-2, boost network (or circuitry) 340 includes first and second auxiliary transistors 343 and 344 and first and second auxiliary impedances 341 and 342. In this example, first and second auxiliary transistors 343 and 344 are field effect transistors, specifically PMOS MOSFETs.

[0159] The first auxiliary transistor 343 is connected to a first auxiliary power supply (ie, connected to a high voltage reference or source V H The second auxiliary transistor 344 is connected between the second auxiliary power supply (i.e., connected to the high voltage reference or source V H between a high voltage reference or source (the same and / or the same as the first auxiliary power supply) and the first input current node 321.

[0160] The first auxiliary transistor 343 and the second auxiliary transistor 344 are connected to the first auxiliary power supply and the second auxiliary power supply via the first auxiliary impedance 341 and the second auxiliary impedance 342, respectively. The first auxiliary impedance 341 includes a resistor 341A and a capacitor 341B connected in parallel between the first auxiliary power supply and the first auxiliary transistor 343. The second auxiliary impedance 342 includes a resistor 342A and a capacitor 342B connected in parallel between the second auxiliary power supply and the second auxiliary transistor 344. The gate terminal of the first auxiliary transistor 343 and the gate terminal of the second auxiliary transistor 344 are connected to the first input current node 321 and the second input current node 322, respectively, so that the first auxiliary transistor 343 and the second auxiliary transistor 344 are controlled by the first input current signal and the second input current signal, respectively.

[0161] The operation of the boost network 340 is as follows. When the input signal V RF When the amplitude of becomes higher, the current through the first mixer side impedance 313 increases, while the current through the second mixer side impedance 314 decreases. In this case, the gate voltage of the first auxiliary transistor 343 increases and the gate voltage of the second auxiliary transistor 344 decreases. This causes more current to flow through the second auxiliary transistor 344 and less current to flow through the first auxiliary transistor 343. When the input signal V RF The corresponding considerations apply when the amplitude of becomes low. This action increases the amount of RF current through the switch of the mixing stage 350 (i.e., the amplitude of the input current signal), and thereby increases the conversion gain of the mixer circuit system 300-3. Resistors 341A and 342A are included to linearize the first auxiliary transistor 343 and the second auxiliary transistor 344, and also when the input stage is in a balanced state (i.e., when V RF+ =V RF- The resistors 341A and 342A are actually shunted by the capacitors 341B and 342B at RF frequencies to increase the AC gain of the boost network 340. This provides a good AC / DC performance ratio for the entire mixer circuit system 300-3.

[0162] Fig.10 It is used to understand Fig. 9 Schematic diagram of mixer circuit system 300-3. Fig.10is a small signal AC model of mixer circuit system 300-3, and its elements correspond to the elements of mixer circuit system 300-3, which is referred to as model circuit system 300-3S in this article. Similar to the previous examples of small signal AC models disclosed herein, the elements of model circuit system 300-3S corresponding to the elements of mixer circuit system 300-3 have the same reference numerals as those of mixer circuit system 300-3, but with "S" attached to the end thereof. For example, nodes 301S and 302S represent the first input node 301 and the second input node 302, respectively. Accordingly, the correspondence between the other elements of model circuit system 300-3S and the other elements of mixer circuit system 300-3 should be understood. In addition, it should be noted that in model circuit system 300-3S, the intrinsic capacitance and parasitic capacitance of the switches of auxiliary transistors 343 and 344 and mixing stage 350 are ignored (i.e., for the calculation of low-frequency gain). Furthermore, it is assumed that resistors 341A and 342A are completely shunted by capacitors 341B and 342B.

[0163] Taking the above into account, according to the model circuit system 300-3S, the gain of the mixer circuit system 300-3 can be calculated as:

[0164] G3=(2 / π)×R L ×g mLO ×Y1 / (g mLO +Y1-g mA1，2 ) (14)

[0165] Among them, g mA1,2 is the transconductance of each of the first auxiliary transistor 343 and the second auxiliary transistor 344, and the other quantities have the same meanings as in the previous equations.

[0166] Comparing Equation 14 with Equation 5 at low frequency (i.e., so that s ≈ 0) yields:

[0167] G3>G2 (15)

[0168] That is, the gain of mixer circuitry 300-3 is higher than the gain of mixer circuitry 300-1. As described above, it should be understood that the addition of boosting network 340 is not limited to mixer circuitry 300-1. The boosting network may be added to any of mixer circuitry 300, 300-1, and 300-2.

[0169] Furthermore, instead of or in addition to adding the boosting network 340 between the passive network 310 and the hybrid stage 350 , the boosting network 340 may be added between the hybrid stage 350 and the current-to-voltage conversion stage 390 .

[0170] Fig.11is a schematic diagram of another modification 400 of the first example arrangement of mixer circuitry embodying the present invention.

[0171] The mixer circuit system 400 includes a voltage-to-current conversion stage 410 (i.e., a passive / resistive network), a mixing stage 450, a current-to-voltage stage 490, a first boosting network 440 connected between the voltage-to-current conversion stage 410 and the mixing stage 450, and a second boosting network 440′ connected between the mixing stage 450 and the current-to-voltage stage 490. The voltage-to-current conversion stage 410, the mixing stage 450, and the current-to-voltage stage 490 may correspond to those stages of the mixer circuit system 300, 300-1, or 300-2. In addition, the first boosting network 440 corresponds to Fig. 9 , and its elements have been given the same reference numerals, but these reference numerals begin with 400 instead of 300. The connection of the first boosting network 440 to the mixer circuitry 400 is the same as the connection of the boosting network 340 to the mixer circuitry 300-3.

[0172] The second boost network 440' includes a third auxiliary transistor 447 and a fourth auxiliary transistor 448 and a third auxiliary impedance 445 and a fourth auxiliary impedance 446. The third auxiliary transistor 447 is connected to a third auxiliary power source (ie, connected to a high voltage reference V H The fourth auxiliary transistor 448 is connected between the fourth auxiliary power supply (i.e., connected to a high voltage reference or source that can be connected to the high voltage reference V H between a high voltage reference or source (the same and / or the same as the third auxiliary power supply and / or the same as any of the first auxiliary power supply and the second auxiliary power supply) and the first output current node 471. In this example, the third auxiliary transistor 447 and the fourth auxiliary transistor 448 are field effect transistors, in particular PMOS MOSFETs.

[0173] The third auxiliary transistor 447 and the fourth auxiliary transistor 448 are connected to the third auxiliary power supply and the fourth auxiliary power supply via the third auxiliary impedance 445 and the fourth auxiliary impedance 446, respectively. Although not shown, the third auxiliary impedance 445 includes a resistor 445A and a capacitor 445B connected in parallel between the third auxiliary power supply and the third auxiliary transistor 447, and the fourth auxiliary impedance 446 includes a resistor 446A and a capacitor 446B connected in parallel between the fourth auxiliary power supply and the fourth auxiliary transistor 448. The gate terminal of the third auxiliary transistor 447 and the gate terminal of the fourth auxiliary transistor 448 are connected to the first output current node 471 and the second output current node 472, respectively, so that the third auxiliary transistor 447 and the fourth auxiliary transistor 448 are controlled by the first output current signal and the second output current signal, respectively. Of course, including two such boost networks 440 and 440' in the mixer circuit system (e.g., 300) will produce higher gain (especially at high frequencies), which may be desirable.

[0174] Note that the gain of the mixer circuit system (e.g., 300) can be increased by using higher resistance values ​​for resistors 391 and 392, but this increase is limited by voltage headroom and imposes additional voltage headroom limitations on the stack (a set of components of the mixer circuit system (e.g., 300)) connected between the higher voltage reference source and the lower voltage reference source. IN In terms of noise in the RF front end, it is better to increase the gain near the RF front end (i.e., near the input voltage node) rather than increasing the gain near the IF (or baseband) back end (i.e., near the output current node or output voltage node). This can be achieved by including the above-described and Fig.11 The first boost network 440 and the second boost network 440' shown in Fig. 4 are implemented. Including two such boost networks 440 and 440' in the mixer circuit system (e.g., 300) provides a distributed gain boost capability for the mixer circuit system (e.g., 300) without imposing additional voltage headroom restrictions on the stack (imposing additional voltage headroom restrictions on the stack is the case when the higher resistance values ​​of resistors 391 and 392 are used to boost the gain).

[0175] Fig.12 is a schematic diagram of a second example arrangement 500 of mixer circuitry embodying the present invention. The following description of the operation of the mixer circuitry 500 is in accordance with a first (or given) mode of operation.

[0176] The mixer circuit system 500 is a differential mixer circuit system and includes a first input current node 521 and a second input current node 522, a mixing stage 550, and a first output current node 571 and a second output current node 572. The mixing stage 550 includes a first mixer sub-stage 530 and a second mixer sub-stage 560. The first mixer sub-stage 530 includes a first array 531 and a second array 532, each of which includes X switches, X upstream nodes, and X downstream nodes. In particular, the first array 531 and the second array 532 each include four switches, four upstream nodes, and four downstream nodes (i.e., X=4). The second mixer sub-stage 560 includes a first array 561 and a second array 562, each of which includes Y switches, Y upstream nodes, and Y downstream nodes. In particular, the first array 561 and the second array 562 each include four switches, four upstream nodes, and four downstream nodes (i.e., Y=4). In the present example, the switches of the hybrid stage 550 are field effect transistors, specifically PMOS MOSFETs (and similar considerations apply to the other hybrid stages shown herein).

[0177] The switches of the first mixer sub-stage 530 are connected to be controlled by the respective phases of the first sub-stage mixed signal. The switches of the first array 531 are connected to be controlled by the phases A, B, C and D of the first sub-stage mixed signal, respectively, and the switches of the second array 532 are also connected to be controlled by the phases A, B, C and D of the first sub-stage mixed signal, respectively. The signal having four phases A, B, C and D and corresponding to the first sub-stage mixed signal is a time-interleaved clock signal. Similarly, the switches of the second mixer sub-stage 560 are connected to be controlled by the respective phases of the second sub-stage mixed signal. The switches of the first array 561 are connected to be controlled by the phases A, B, C and D of the second sub-stage mixed signal, respectively, and the switches of the second array 562 are also connected to be controlled by the phases A, B, C and D of the second sub-stage mixed signal, respectively. The signal having four phases A, B, C and D and corresponding to the second sub-stage mixed signal is a time-interleaved clock signal. The phase of the signal controlling each switch of the mixing stage 550 is indicated by the letter A, B, C, or D next to each switch (at its gate).

[0178] The switches of each array 531 and 532 are connected to the upstream node and the downstream node of the array (or connected between the upstream node and the downstream node of the array) along the corresponding current path. The switches of each array 561 and 562 are connected to the upstream node and the downstream node of the array along the corresponding current path.

[0179] The switch (i.e., the channel of each transistor) forms part of its corresponding current path. Fig.12531D2. The current path 531D is shown in more detail in FIG. The current path 531D includes a switch 531D1 connected between an upstream node 531D0 and a downstream node 531D2, such that a source terminal of the switch 531D1 is connected to the upstream node 531D0 and a drain terminal of the switch 531D1 is connected to the downstream node 531D2. The switch 531D1 is connected to be controlled by the phase D (at its gate terminal) of the first sub-stage mixed signal.

[0180] Other switches, upstream nodes, and downstream nodes have corresponding reference numerals, but these reference numerals are not included to avoid confusion. Fig.12 Overly complicated. For example, switch 531B1 (a switch of the first array 531 having the letter B next to its gate terminal) is connected along current path 531B between upstream node 531B0 and downstream node 531B2, and is connected to be controlled by phase B of the first sub-stage mixing signal. In addition, switch 532C1 (a switch of the second array 532 having the letter C next to its gate terminal) is connected along current path 532C between upstream node 532C0 and downstream node 532C2, and is connected to be controlled by phase C of the first sub-stage mixing signal. In addition, switch 561A1 (a switch of the first array 561 of the second mixer sub-stage 560 having the letter A next to its gate terminal) is connected along current path 561A between upstream node 561A0 and downstream node 561A2, and is connected to be controlled by phase A of the second sub-stage mixing signal. In addition, switch 562B1 (a switch of the second array 562 of the second mixer sub-stage 560 having the letter B next to its gate terminal) is connected between the upstream node 562B0 and the downstream node 562B2 along the current path 562B, and is connected to be controlled by the phase B of the second sub-stage mixing signal. The other switches of the mixing stage 550 are similarly connected to their respective upstream and downstream nodes, and repeated descriptions are omitted.

[0181] The first input current node 521 and the second input current node 522 are configured to receive a first input current signal and a second input current signal, respectively, and the first input current signal and the second input current signal define a differential input current signal having an input frequency. The first mixer sub-stage 530 is configured to mix the differential input current signal with a first sub-stage mixed signal. The first sub-stage mixed signal has a first mixing frequency. The second mixer sub-stage 560 is configured to mix the output of the first mixer sub-stage 530 with the second sub-stage mixed signal and output a differential output current signal. The second sub-stage mixed signal has a second mixing frequency.

[0182] The differential output current signal thus has an output frequency that depends on the input frequency and the first mixing frequency and the second mixing frequency. As mentioned in the description of the first example arrangement of the mixer circuit system and its modified examples, when two signals are mixed, the resulting signal contains components with different frequencies. It should be understood that the output frequency in the mixer circuit system 500 can have multiple components, in fact f OUT =(f IN ±f1±f2), where f OUT is the output frequency, f IN is the input frequency, and f1 and f2 are the first mixed frequency and the second mixed frequency (and others, such as harmonics), respectively. Of course, various methods / techniques (e.g., suitable filtering) can be used to obtain only one or some of these components as the output current signal, for example, f IN -f1-f2. In the specific example of the context, f IN =40 GHz (ie, RF), f1 =32 GHz (ie, RF), f2 =8 GHz (ie, IF), so that the baseband frequency (centered around DC, i.e., 0 Hz) can be obtained as the output frequency.

[0183] The mixer circuit system 500 also includes a current-to-voltage conversion stage 590 and a first output voltage node 581 and a second output voltage node 582. The first output voltage node 581 and the second output voltage node 582 are configured to output a first output voltage signal and a second output voltage signal defining a differential output voltage signal, the differential output voltage signal having an output frequency and corresponding to the differential output current signal. The current-to-voltage conversion stage 590 includes: a first resistor 591 and a second resistor 592, which are respectively connected between the first output current node 571 and the second output current node 572 and a low voltage reference or source (e.g., ground GND), the voltage level of the low voltage reference or source being between the high voltage reference or source V H below the voltage level; a first current source 593 and a second current source 594, which are respectively connected between the first output current node 571 and the second output current node 572 and a low voltage reference or source (e.g., ground GND); and a first capacitor 595 and a second capacitor 596, which are respectively connected between the first output current node 571 and the second output current node 572 and a low voltage reference or source (e.g., ground GND).

[0184] The current-to-voltage conversion stage 590 may include only a first resistor 591 and a second resistor 592. The first capacitor 595 and the second capacitor 596 are used to filter out high frequency noise and mixed interference or mixer interference (i.e., filter out undesired frequency components) from the output voltage signal. The first current source 593 and the second current source 594 are used to reduce the output common mode voltage. This provides sufficient drain-source voltage margin for the switches of the second mixer sub-stage 560 (because these switches operate in the saturation region).

[0185] The mixer circuit system 500 also includes a voltage-to-current conversion stage 510 and a first input voltage node 501 and a second input voltage node 502. The first input voltage node 501 and the second input voltage node 502 are configured to receive a first input voltage signal VINP and a second input voltage signal VINM, respectively, and the first input voltage signal VINP and the second input voltage signal VINM define a differential input voltage signal having an input frequency. The voltage-to-current conversion stage 510 is configured to convert the first input voltage signal VINP and the second input voltage signal VINM into a first input current signal and a second input current signal, and the first input current signal and the second input current signal are provided at a first input current node 521 and a second input current node 522. The voltage-to-current conversion stage 510 is the same as the passive (resistance) network 310' of the mixer circuit system 300-1, and repeated descriptions are omitted. Of course, any passive network disclosed herein can be used, and any other circuit system for converting the first input voltage signal VINP and the second input voltage signal VINM into a first input current signal and a second input current signal can also be used. Furthermore, the mixer circuit system 500 may operate based on a differential input current signal, and thus the voltage-to-current conversion stage 510 may not be included in some implementations of the mixer circuit system 500 .

[0186] The four phases of the first sub-level mixed signal are orthogonal. For example, the phases of the four phases A, B, C and D of the first sub-level mixed signal are 0 degrees, 90 degrees, 180 degrees and 270 degrees, respectively. Similarly, the four phases of the second sub-level mixed signal are orthogonal. For example, the phases of the four phases A, B, C and D of the second sub-level mixed signal are 0 degrees, 90 degrees, 180 degrees and 270 degrees, respectively. It should be understood that other phases are also possible in theory (for example, A, B, C and D can be 5 degrees, 95 degrees, 185 degrees and 275 degrees, respectively).

[0187] The downstream nodes of the first array 531 of the first mixer sub-stage 530 and the downstream nodes of the second array 532 of the first mixer sub-stage 530 are connected to the output current node 571 and the current node 572 along the current paths arranged to pass through the switches of the array 561 of the second mixer sub-stage 560 and the switches of the array 562 of the second mixer sub-stage 560 so as to provide the first output current signal and the second output current signal at the first output current node 571 and the second output current node 572, respectively. In particular, between the first mixer sub-stage 530 and the second mixer sub-stage 560 and between the second mixer sub-stage 560 and the output current node 571 and the output current node 572, the current paths carrying signals having the same phase are connected to be superimposed together to provide the first output current signal and the second output current signal at the first output current node 571 and the second output current node 572, respectively.

[0188] For example, considering current path 531D, the phase of the current signal output at the downstream node 531D2 will be 270 degrees (the phase of the first input current signal (0 degrees) + the phase D (270 degrees) of the first sub-stage mixed signal, because the current signal at the upstream node 531D0 is rotated 270 degrees by switch 531D1). Considering current path 532B, the phase of the current signal output at the downstream node 532B2 will be 270 degrees (the phase of the second input current signal (180 degrees) + the phase B (90 degrees) of the first sub-stage mixed signal). The two current signals output at the downstream nodes 531D2 and 532B2 therefore have the same phase (270 degrees), and the current paths carrying these signals between the first mixer sub-stage 530 and the second mixer sub-stage 560 are superimposed together, as shown in FIG. Fig.12 shown.

[0189] As another example, considering current path 532C, the phase of the current signal output at downstream node 532C2 will be 0 degrees (phase of the second input current signal (180 degrees) + phase C (180 degrees) of the first sub-stage mixed signal). Considering current path 531A, the phase of the current signal output at downstream node 531A2 will be 0 degrees (phase of the first input current signal (0 degrees) + phase A (0 degrees) of the first sub-stage mixed signal). The two current signals output at downstream nodes 532C2 and 531A2 therefore have the same phase (0 degrees), and the current paths carrying these signals between the first mixer sub-stage 530 and the second mixer sub-stage 560 are superimposed together, as shown in FIG. Fig.12 shown.

[0190] As yet another example, considering current path 561A, the phase of the current signal output at downstream node 561A2 will be 0 degrees (the phase of the current signal output from downstream nodes 531A2 and 532C2 (described as 0 degrees above) + the phase A (0 degrees) of the second sub-stage mixed signal). Considering current path 561D, the phase of the current signal output at downstream node 561D2 will be 0 degrees (the phase of the current signal output from downstream nodes 531B2 and 532D2 (90 degrees) + the phase D (270 degrees) of the second sub-stage mixed signal). The two current signals output at downstream nodes 561A2 and 561D2 therefore have the same phase (0 degrees), and the current paths carrying these signals between the second mixer sub-stage 560 and the output current nodes 571 and 572 are superimposed together, as shown in FIG. Fig.12 The two current signals output at the downstream nodes 561A2 and 561D2 are also added together with the two current signals output at the downstream nodes 562C2 and 562B2 which are also 0 degrees in phase, as shown in FIG. Fig.12 It should be understood that other current paths are similar to Fig.12 The methods shown in the figure are combined and repeated description is omitted.

[0191] It should be understood that the downstream nodes of the first array 531 of the first mixer sub-stage 530 and the downstream nodes of the second array 532 of the first mixer sub-stage 530 are connected to the output current nodes 571 and 572, so that the current paths from the downstream nodes of the first array 531 are superimposed with the current paths from the downstream nodes of the second array 532, respectively. In addition, it should be understood that the downstream nodes of the first array 531 of the first mixer sub-stage 530 and the downstream nodes of the second array 532 of the first mixer sub-stage 530 are connected to the output current nodes 571 and 572, so that the current paths from the downstream nodes of the first mixer sub-stage 530 connected to the switches controlled by the opposite phases (e.g., A and C, or B and D) of the first sub-stage mixing signals are superimposed together. In addition, it should be understood that the downstream nodes of the array 561 of the second mixer sub-stage 560 and the downstream nodes of the array 562 of the second mixer sub-stage 560 are connected to the output current nodes 571 and 572, so that the current paths starting from the downstream nodes of the second mixer sub-stage 560 connected to the switches controlled by the opposite phases of the second sub-stage mixing signals (for example, A and C, or B and D) are superimposed together.

[0192] Technicians will recognize Fig.12The combination of current paths in the result is a balanced (e.g., double balanced) topology or architecture, where the currents combine at the nodes to appropriately have contributions (e.g., through chains or leakage) from both the first sub-stage mixed signal and / or the second sub-stage mixed signal in opposite phase and of course from both the first input voltage signal VINP and the second input voltage signal VINM (which also have opposite phases). Effectively, undesirable components at the frequencies of the input signals (the first sub-stage mixed signal, the second sub-stage mixed signal, and the input voltage signal) are cancelled at the output. In fact, given the balance associated with each of the first sub-stage mixed signal, the second sub-stage mixed signal, and the input voltage signal, Fig.12 The topology can be called triple-balanced.

[0193] It should be understood that the downstream nodes of the array 561 of the second mixer sub-stage 560 and the downstream nodes of the array 562 of the second mixer sub-stage 560 are connected to the output current nodes 571 and 572, so that the current paths from the downstream nodes of the second mixer sub-stage 560 connected to the switches respectively controlled by the Y (four) phases of the second sub-stage clock signal are superimposed. That is, the first output current signal and the second output current signal each have contributions from all Y (four) phases of the second sub-stage mixing signal. In addition, from Fig.12 It is evident that the first output current signal and the second output current signal each have contributions from all X (four) phases of the first sub-stage mixed signal. Thus, the balance involves all phases of the first sub-stage mixed signal, the second sub-stage mixed signal and the input voltage signal.

[0194] The time-interleaved signals constituting the phases of the first sub-stage mixing signal and the second sub-stage mixing signal may be generated by a voltage controlled oscillator (VCO), ie, a local oscillator. Fig.12 The left side of can be called the "right track", and Fig.12 The right side of can be called the "negative rail".

[0195] Fig.13 and Fig.14 is a graph useful for understanding the mixer circuit system 500 . Fig.13 and Fig.14 The graph in shows a differential input voltage signal (labeled as VIN), one of the mixed current signals output from the first mixer sub-stage 530 at the node where the current paths converge, i.e., one of the current signals input to the second mixer sub-stage 560 (labeled as IOUT_RF), one of the mixed current signals output from the second mixer sub-stage 560 at the node where the current paths converge, i.e., the current signal at node 571 or node 572 (labeled as IOUT_IF), and a differential voltage output signal output between a first voltage output node 581 and a second voltage output node 582, each of which is relative to time. Fig.13 and Fig.14 The graph in shows the same signal, but Fig.14 The signal is shown on a smaller time scale to get more information. A simulation is performed to obtain Fig.13 and Fig.14 The simulation was done in 16 nanometer FinFet technology. In the simulation, an RF AM (amplitude modulation) signal with a carrier frequency of 40 GHz was used as the input signal VIN, which carried a 100 MHz baseband single tone signal with a power of -8 dBm (100% modulation was used in the simulation). The simulation shows that a conversion gain of about 5.5 dB is achieved for the mixer circuit system 500.

[0196] The mixer circuit system 500 can operate using only two phases A and C of the first sub-stage mixed signal and the second sub-stage mixed signal. However, the four phases A to D are used to increase the conversion gain of the mixer. In addition, although four phases (X=Y=4) are used in the mixer circuit system 500, the technology can be generalized to an n-phase solution (where the integer n≥2). That is, other numbers of phases can be used in similar mixer circuit systems.

[0197] Fig.15 is a schematic diagram of a modification 600 of a second example arrangement of mixer circuitry embodying the present invention.

[0198] Mixer circuit system 600 is a differential mixer circuit system and has a similar structure to mixer circuit system 500. Elements in mixer circuit system 600 corresponding to elements in mixer circuit system 500 are given similar reference numerals (but starting with 600 instead of 500), and repeated descriptions are omitted. The difference between mixer circuit system 600 and mixer circuit system 500 is that mixer circuit system 600 uses eight phases A to H of the first sub-stage mixing signal and eight phases A to H of the second sub-stage mixing signal.

[0199] Thus, the first array 631 and the second array 632 of the first mixer sub-stage 630 and the first array 661 and the second array 662 of the second mixer sub-stage 660 each include eight switches, eight upstream nodes and eight downstream nodes, i.e., X=8 and Y=8. The corresponding eight phases A to H are spaced 45 degrees apart. For example, the eight phases A to H are 0 degrees, 45 degrees, 90 degrees, 135 degrees, 180 degrees, 225 degrees, 270 degrees and 315 degrees, respectively. The operation of the mixer circuit system 600 (in the first operating mode) is similar to the operation of the mixer circuit system 500 in how the current paths carrying signals with the same phase are superimposed between the first mixing sub-stage 630 and the second mixing sub-stage 660 and again between the second mixing sub-stage 660 and the first output current node 671 and the second output current node 672.

[0200] from Fig.15 It can be seen that the specific combination forms a similar balanced (ie, triple balanced as mentioned above) topology as before. Similar to the mixer circuit system 500, see Fig.15 The following will be understood. The current paths from the downstream nodes of the first array 631 are superimposed with the current paths from the downstream nodes of the second array 632, respectively. The current paths from the downstream nodes of the first mixer sub-stage 630 connected to the switches controlled by the opposite phases of the first sub-stage mixing signal (e.g., A and E, B and F, C and G, or D and H) are superimposed together. The current paths from the downstream nodes of the second mixer sub-stage 660 connected to the switches controlled by the opposite phases of the second sub-stage mixing signal (e.g., A and E, B and F, C and G, or D and H) are superimposed together. The current paths from the downstream nodes of the second mixer sub-stage 660 connected to the switches controlled by the eight (Y=8) phases of the second sub-stage clock signal are superimposed together, that is, the first output current signal and the second output current signal each have contributions from all eight (Y=8) phases of the second sub-stage mixing signal. In addition, the first output current signal and the second output current signal each have contributions from all eight (X=8) phases of the first sub-stage mixing signal. Therefore, it should be appreciated that similar considerations as described in conjunction with mixer circuitry 500 apply to mixer circuitry 600 .

[0201] Fig.16 is a schematic diagram of another modification 700 of the second example arrangement of mixer circuitry embodying the present invention.

[0202] The mixer circuit system 700 is a differential mixer circuit system and has a similar structure to the mixer circuit system 500. Elements in the mixer circuit system 700 corresponding to elements in the mixer circuit system 500 are given similar reference numerals (but starting with 700 instead of 500), and repeated descriptions are omitted. The difference between the mixer circuit system 700 and the mixer circuit system 500 is that the mixer circuit system 700 is configured to provide orthogonal first output current signals to fourth output current signals and orthogonal corresponding first output voltage signals to fourth output voltage signals (i.e., with phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees).

[0203] The mixer circuit system 700 includes first to fourth output current nodes 771, 772, 773, and 774 for respectively outputting first to fourth output current signals and first to fourth output voltage nodes 781, 782, 783, and 784 for respectively outputting first to fourth output voltage signals. The first output voltage node 781 and the second output voltage node 782 are configured to output first and second output voltage signals having opposite phases (e.g., 0 degrees and 180 degrees) to each other, and the first and second output voltage signals define a first differential output voltage signal ( Fig.16 V OUTI The third output voltage node 783 and the fourth output voltage node 784 are configured to output a third output voltage signal and a fourth output voltage signal having opposite phases (e.g., 90 degrees and 270 degrees) to each other, and the third output voltage signal and the fourth output voltage signal define a second differential output voltage signal ( Fig.16 V OUTQ ). The mixer circuit system 700 may therefore be referred to as an IQ mixer.

[0204] Another difference between the mixer circuit system 700 and the mixer circuit system 500 is that the mixer circuit system 700 includes four arrays 761, 762, 763, and 764 in the second mixing sub-stage 760, instead of the two arrays 561 and 562 in the second mixing sub-stage 560 in the mixer circuit system 500. Another difference between the mixer circuit system 700 and the mixer circuit system 500 is that the mixer circuit system 700 includes first to fourth resistors 791, 792, 793, and 794. Although not shown, the mixer circuit system 700 may include first to fourth capacitors and first to fourth current sources similar to the first capacitor 595 and the second capacitor 596 and the first current source 593 and the second current source 594 of the current-to-voltage conversion stage 590 in the mixer circuit system 500 as part of the current-to-voltage conversion stage 790.

[0205] The operation of the mixer circuit system 700 (in the first operating mode) is similar to the operation of the mixer circuit system 500 in how the current paths carrying signals with the same phase are superimposed between the first mixing sub-stage 730 and the second mixing sub-stage 760 and again between the second mixing sub-stage 760 and the first output current node 771 to the fourth output current node 774.

[0206] from Fig.16 It can be seen that the specific combination forms a similar balanced (ie, triple balanced as mentioned above) topology as before. Similar to the mixer circuit system 500, see Fig.16 The following will be understood. The current paths from the downstream nodes of the first array 731 are superimposed with the current paths from the downstream nodes of the second array 732, respectively. The current paths from the downstream nodes of the first mixer sub-stage 730 connected to the switches controlled by the opposite phases of the first sub-stage mixing signal (e.g., A and C or B and D) are superimposed together. The current paths from the downstream nodes of the second mixer sub-stage 760 connected to the switches controlled by the opposite phases of the second sub-stage mixing signal (e.g., A and C or B and D) are superimposed together. The current paths from the downstream nodes of the second mixer sub-stage 760 connected to the switches controlled by the four (Y=4) phases of the second sub-stage clock signal are superimposed together, that is, the first output current signal to the fourth output current signal each have contributions from all four (Y=4) phases of the second sub-stage mixing signal. In addition, the first output current signal to the fourth output current signal each have contributions from all four (X=4) phases of the first sub-stage mixing signal. Therefore, it should be appreciated that similar considerations apply to mixer circuitry 700 as described in conjunction with mixer circuitry 500 .

[0207] Fig.17 and Fig.18 is a graph useful for understanding the mixer circuit system 700 . Fig.17 and Fig.18The graph in shows a differential input voltage signal (labeled as VIN(I+Q)), one of the mixed current signals output from the first mixer sub-stage 730 at the node where the current paths converge, i.e., one of the current signals input to the second mixer sub-stage 760 and corresponding to the "I" output signal (labeled as IOUT_RF_I), one of the mixed current signals output from the first mixer sub-stage 730 at the node where the current paths converge, i.e., one of the current signals input to the second mixer sub-stage 760 and corresponding to the "Q" output signal (labeled as IOUT_RF_Q), a mixed current signal at node 771 or 772 (labeled as IOUT_IF_I), a mixed current signal at node 773 or 774 (labeled as IOUT_IF_Q), a differential voltage output signal (labeled as VOUTI) output between the first voltage output node 781 and the second voltage output node 782, and a differential voltage output signal (labeled as VOUTQ) output between the third voltage output node 783 and the fourth voltage output node 784, each of these signals relative to time. Fig.17 and Fig.18 The graph in shows the same signal, but Fig.18 The signals on a smaller time frame are shown to give more information.

[0208] In addition to using the mixer circuit system 700, performing and being performed to obtain Fig.13 and Fig.14 A similar simulation is performed to obtain the curves in Fig.17 and Fig.18 In the simulation, the use of and is performed to obtain Fig.13 and Fig.14 The input signals and mixed signals used in the simulations of the graphs are the same, except for Fig.17 and Fig.18 The input signal in the graph has two carriers that are modulated with their corresponding baseband tone signals. That is, in the simulation, the mixer circuit system 700 is down-converted (i.e., to a lower frequency) and detects two single tones of 100 MHz on the "I channel" (i.e., in the output signal VOUTI) and 110 MHz on the "Q channel" (i.e., in the output signal VOUTQ).

[0209] Fig.19 is a schematic diagram useful for understanding mixer circuit systems 500, 600, and 700. Fig.101, consider circuitry 500S, which corresponds to a portion of mixer circuitry 500. Elements of circuitry 500S that correspond to elements of mixer circuitry 500 are given the same reference numerals as elements of mixer circuitry 500, but with S appended to the end thereof. Of course, circuitry 500S also represents mixer circuitry 600 and 700, and the following considerations apply to mixer circuitry 500, 600, and 700.

[0210] The input current (i.e., the input current signal) is obtained by taking each input voltage node 501 and 502 (at Fig.19 The "input impedance" Z seen by 501S) is considered in in The result of the voltage-to-current conversion is shown in Figure 1. Ignoring high-frequency capacitive / inductive effects, the impedance seen by the source of the switch of the first mixer sub-stage is almost equal to 1 / g m , where g m is the transconductance of each of these switches. In this case, the input current can be estimated as:

[0211] I in =V in / (R1+1 / g m ) (16)

[0212] Where R1 is the resistance of impedance (resistor) 513S (corresponding to resistor 513 in mixer circuit system 500). This current is mixed with the first and second mixer sub-stages (e.g., 530 and 560 in mixer circuit system 500) in a double balanced configuration (as described above). Since the input current passes through the first and second mixer sub-stages and is ultimately injected into the load resistor R L (i.e., resistor 591 or 592 in mixer circuit system 500), so the output voltage (the voltage of the differential output voltage signal)) can be estimated as:

[0213] V out =(2 / π)×(2 / π)×I in ×R L (17)

[0214] According to Equation 17, the conversion gain of the proposed mixer architecture can be calculated as:

[0215] G4=V out / V in =4×R L / (π 2 ×(R1+1 / gm)) (18)

[0216] Fig. 20800 is another modification of the second example arrangement of mixer circuitry embodying the present invention. Mixer circuitry 800 is a differential mixer circuitry. Mixer circuitry 800 is identical to mixer circuitry 500 except that instead of the Y-phase signal used to control the switches of the second mixer sub-stage 860, the switches are controlled by binary signals. Thus, mixer circuitry 800 illustrates a second mode of operation of mixer circuitry 500.

[0217] The operation of mixer circuit system 800 is the same as that of mixer circuit system 500 except for the binary signal used to control the switch of second mixer sub-stage 860, and a repeated description is omitted. By using the binary signal to control the switch of second mixer sub-stage 860, mixer circuit system 500 can be converted into mixer circuit system 800, which actually uses only one mixing stage, namely the first mixing sub-stage. When operating in this manner, the mixer circuit system can be referred to as a "direct" mixer circuit system. Fig. 20 , next to the gate of each switch of the second mixer sub-stage 860 is a "1" or a "0". A "1" indicates that the binary signal controlling the switch (e.g., a logic high, such as VDD) is controlling the switch "off", i.e., current is not allowed to flow through the switch. A "0" indicates that the binary signal controlling the switch (e.g., a logic low, such as GND) is controlling the switch "on", i.e., current is allowed to flow through the switch. The switches of the second mixer sub-stage 860 are controlled in this manner so that each switch is always on or off in the second operating mode. From Fig. 20 It should be understood that the first output current signal and the second output current signal having opposite phases are provided at the first output node 871 and the second output node 872 .

[0218] It should be understood that any of the mixer circuit systems 500, 600, or 700 may be operated in the manner in which the mixer circuit system 800 is operated (by using a binary signal to control the switches of the second mixing sub-stage). That is, any of the mixer circuit systems 500, 600, or 700 may be operated according to a first operating mode (whereby the switches of the second mixing sub-stage are controlled by the phase of the second sub-stage mixing signal to achieve mixing, as described above with reference to Fig.12 , Fig.15 and Fig.16 The second mixing sub-stage may be operated in accordance with the second operating mode (described above) or in accordance with the second operating mode (whereby the switches of the second mixing sub-stage are controlled by a binary signal to in effect convert the mixer circuitry into a "straight" mixer). This applies to other implementations / modifications of the second example arrangement of the mixer circuitry considered in the present application. Of course, it is also possible to apply such a binary signal to the first mixing sub-stage instead of the second mixing sub-stage.

[0219] The advantage of the second operating mode is that, since there is only one "mixing stage" in which the mixing is performed, the conversion gain is increased to the conversion gain calculated in equation 7. It is advantageous for the mixer circuit system to be able to operate with two mixing stages (first operating mode) or one mixing stage (second operating mode) to accommodate different situations. An advantage of the first operating mode is that, since the input frequency is reduced by a factor of two (i.e., by two mixer sub-stages), the first mixing frequency and the second mixing frequency can be lower than the frequency of a single mixing signal with restrictions on the available mixing signals. In some scenarios, it may be difficult or undesirable to generate a clock signal with a sufficiently high frequency for the second operating mode.

[0220] Although the mixer circuitry according to the second example arrangement and modifications thereof has been described as having a particular number of switches (i.e., numbers X and Y) in each array of the first mixer sub-stage and each array of the second mixer sub-stage, there are many other example implementations where X and Y have different numbers.

[0221] In short, as an example, there is a first set of example implementations where X=4 and Y=2, as well as many other implementations, including implementations where both X and Y are greater than eight. In addition, in the described examples and modifications, there are two (or four in the case of orthogonal output signals) arrays in the second mixer substage. There are many other example implementations where there are more than two arrays in the second mixer substage. In short, as an example, there is a second set of example implementations where X=4, Y=2 and the second mixer substage includes four of the switch arrays; X=2, Y=4 and the second mixer substage includes two of the switch arrays; X=4, Y=4 and the second mixer substage includes two of the switch arrays; and of course many other example implementations such as those where X and Y are greater than eight. The second set of example implementations are particularly suitable for providing orthogonal output signals, but of course they can be used to provide a single differential output signal instead of two differential output signals (I and Q).

[0222] Fig.21 and Fig. 22 is a graph useful for understanding the mixer circuit system 800 (ie, useful for understanding the second operation mode). Fig.21 and Fig. 22The graph in shows a differential input voltage signal (labeled as VIN), one of the mixed current signals output from the first mixer sub-stage 830 at the node where the current paths converge, i.e., one of the current signals input to the second mixer sub-stage 860 (labeled as IOUT_RF), a mixed current signal output from the second mixer sub-stage 860 at node 871 or 872 (labeled as IOUT_IF), and a differential voltage output signal (labeled as VOUT) output between the first voltage output node 881 and the second voltage output node 882, each of which is relative to time. Fig.21 and Fig. 22 The graph in shows the same signal, but Fig. 22 The signals on a smaller time frame are shown to get more information.

[0223] In addition to using the mixer circuit system 800 (ie, the second mode of operation), performing and being performed to obtain Fig.13 and Fig.14 A similar simulation is performed to obtain the curves in Fig.21 and Fig. 22 In addition, the input frequency used is 20 GHz, and the first mixing frequency (and indeed the only mixing frequency in this case) is also 20 GHz. Fig.21 and Fig. 22 As can be seen in FIG. 8 , the conversion gain of the mixer circuit system 800 is about 7.1 dB, which is 1.6 dB higher than the conversion in the simulation of the mixer circuit system 500, the results of the simulation of the mixer circuit system 500 are about 7.1 dB. Fig.13 and Fig.14 Shown in.

[0224] As discussed above, since there is only one mixer sub-stage controlled by the mixing signal in mixer circuit system 800, there is only one 2 / π factor in the output voltage (i.e., in the equation equivalent to equation 17 but for mixer circuit system 800). Therefore, the gain of 800 should be 3.9 dB higher than the gain of mixer circuit system 500 (=20×log10(π / 2)). However, the simulation results (i.e., Fig.21 and Fig. 22) shows a gain of about 1.6 dB higher than the gain of mixer circuit system 500. The lost gain (i.e., 3.9 dB - 1.6 dB) is due to the fact that the currents output at the downstream nodes of the second mixer sub-stage 860 of mixer circuit system 800 are added together without the currents having opposite phases. For example, at output node 871, a current having phase A is added together with a current having phase B, which are 90 degrees out of phase with each other. The gain of mixer circuit system 800 is still higher than the gain of mixer circuit system 500 (i.e., 1.6 dB higher).

[0225] Fig.23 is a schematic diagram of a mixer circuit system 900 embodying the present invention.

[0226] Mixer circuit system 900 is a differential mixer circuit system, and includes RF mixer 930, VCO 923, IF mixer 960, analog to digital converter (ADC) 924, baseband digital circuit system 925, and calibration circuit system 926. RF mixer 930 corresponds to the first mixer sub-stage in mixer circuit systems 500, 600, 700, and 800, and IF mixer 960 corresponds to the second mixer sub-stage in mixer circuit systems 500, 600, 700, and 800, and their operations are described above. Of course, the frequency of the signal used at each stage is not limited to, for example, RF, IF, and baseband.

[0227] The VCO 923 is configured to generate the phase of the first sub-stage mixing signal (and the second sub-stage mixing signal used in the first operating mode, although not shown). The RF mixer 930 receives an RF analog differential input current signal I having an input frequency. IN As its input, and configured to mix the RF analog differential input current signal with each phase of the RF mixer mixing signal having a first mixing frequency (corresponding to the first sub-stage mixing signal of the circuit system 500, 600, 700 or 800), and output the current signal in the IF band to the IF mixer 960. The current signal output from the RF mixer is combined as described above, for example, with reference to the mixer circuit system 500 before being input to the IF mixer 960. The IF mixer 960 is configured to mix the current signal from the RF mixer 930 with the IF mixer mixing signal having a second mixing frequency (corresponding to the second sub-stage mixing signal), and output the output current signal in the baseband, which is an analog signal having an output frequency in the baseband. In the same manner as described above, the output frequency depends on the input frequency and the first mixing frequency and the second mixing frequency.

[0228] In this example, ADC 924 is a baseband ADC and is configured to convert the baseband analog output current signal from IF mixer 960 into a digital signal (which may be highly parallel where ADC 924 uses multiple sub-ADC units) and send the digital signal to baseband digital circuitry 925. Baseband digital circuitry 925 performs digital (e.g., parallel to serial) processing and outputs a baseband digital output signal. Calibration circuitry 926 may analyze the digital signal output by ADC 924 and / or baseband digital circuitry 925 and calibrate the operation of any other units as indicated based on the analysis.

[0229] Of course, the RF analog differential input current signal I IN The analog output current signal may have any frequency and is not limited to RF signals, and the first mixing frequency and the second mixing frequency are also not limited. In addition, the analog output current signal may have any frequency (depending on the input frequency and the first mixing frequency and the second mixing frequency) and is not limited to baseband signals. It should be understood that the mixer circuit system 900 may operate according to the second operating mode described above with reference to the mixer circuit system 800.

[0230] Advantageously, the mixer circuit system 900 has the same Fig. 9 The circuit system disclosed in this article has a similar structure to that disclosed in EP2211468. The similarity of the hybrid level of the circuit system disclosed in this article also extends to that of EP2211468. Fig.10 , and thus the circuit system can be modified to be used as the mixer circuit system 900. Therefore, the speed and calibration benefits described in EP2211468 can be enjoyed in the mixer circuit system 900.

[0231] The mixer circuit systems 500 to 900 are particularly suitable for narrowband RF applications for the following reasons. At least when operating according to the first operating mode, there are two mixing stages in the mixer circuit systems 500, 600, 700 and 900 (at the first mixer sub-stage and the second mixer sub-stage). Therefore, as described above, in order to convert the input signal from RF to baseband, the mixing frequency does not need to be as high as if there is only one mixing stage. In addition, the passive network can be tuned for impedance matching at the narrowband frequency of interest (e.g., at 50Ω) and can also be configured for noise filtering.

[0232] See in particular Fig.23There are methods to feed the RF analog differential input current signal directly to the ADC 924, however, this requires an ultra-wideband ADC to directly process the RF input. Therefore, the present invention provides a method by which a baseband ADC can be used (so that the ADC can consume less power, have higher resolution and be easier to manufacture) and the passive network described above can be tuned to filter out undesired frequency components to produce a low noise output.

[0233] Back to Fig.11 , it should be understood that one or both of the boost networks 440 and 440' may be added to any of the mixer circuit systems 500, 600, 700, 800 and 900 and the mixer circuit systems 300, 300-1 or 300-2 described above. That is, the voltage-to-current conversion stage 410, the mixing stage 450 and the current-to-voltage stage 490 may correspond to the corresponding stages of the mixer circuit systems 500, 600, 700, 800 and 900. It should be understood that in the case of the mixer circuit system 700, two boost networks 440' and 440" may be provided between the output current nodes 771 to 774, the boost network 440' being connected between the first output current node 771 and the second output current node 772, and the boost network 440" being connected between the third output current node 773 and the fourth output current node 774. In addition, additional boosting networks may be added between current path pairs carrying current signals having opposite phases (i.e., anti-phase), for example, between a first sub-mixer stage and a second sub-mixer stage in any of the mixer circuit systems 500, 600, 700, 800, and 900.

[0234] As mentioned above, the switches of the mixer circuit systems 300, 300-1, 300-2, 300-3, 400, 500, 600, 700, 800, 900 are shown in the figures as PMOS transistors. The upstream node of the array of the first mixer sub-stage is the source terminal of each switch of the array of the first mixer sub-stage, and the downstream node of the array of the first mixer sub-stage is the drain terminal of each switch of the array of the first mixer sub-stage. The upstream node of the array of the second mixer sub-stage is the source terminal of each switch of the array of the second mixer sub-stage, and the downstream node of the array of the first mixer sub-stage is the drain terminal of each switch of the array of the second mixer sub-stage. Of course, these switches can be replaced by suitable hybrid devices such as BJT transistors. In addition, N-channel devices can be used instead of P-channel devices, that is, by providing "other ways" for the circuit system.

[0235] The current-to-voltage conversion stage 390, 490, 590, 690, 790, or 890 is not required, and any associated mixer circuit system disclosed herein may provide a current-based output instead. In addition, the current-to-voltage conversion stage 390, 490, 590, 690, 790, or 890 may include any circuit system suitable for converting a current signal into a voltage signal and is not limited to the circuit system shown in the drawings.

[0236] As described with reference to mixer circuit system 500, in mixer circuit system 600, 700, 800, or 900, any passive network disclosed herein may be used, and any other circuit system for converting first input voltage signal VINP and second input voltage signal VINP into first input current signal and second input current signal may also be used. In addition, mixer circuit system 600, 700, 800, or 900 may operate based on differential input current signals, and therefore may not include an associated voltage-to-current conversion stage in mixer circuit system 600, 700, 800, or 900.

[0237] It should be understood that labels such as RF, IF and LO are only examples and the frequency of the signal marked with such labels is not limited. That is, for example, the input voltage signal V RF is not limited to RF signals having a radio frequency and may be any signal having any frequency (wherein the same considerations apply to the output voltage signal V IF ).

[0238] It will be appreciated that the mixer circuitry 300, 300-1, 300-2, 300-3, 400, 500, 600, 700, 800, 900 may be provided together with mixed signal circuitry such as ADC circuitry (or, in some arrangements, DAC circuitry), which ADC circuitry may be implemented as current mode circuitry (e.g., as described in EP2211468 with respect to its Fig. 9 and Fig.10 as described). Fig.24A As shown in , for example, the mixer circuit systems 300 , 300 - 1 , 300 - 2 , 300 - 3 , 400 , 500 , 600 , 700 , 800 , 900 disclosed herein may be provided together with the ADC circuit system 1 or as a part of the ADC circuit system 1 .

[0239] For example, the circuit system of the present invention may be implemented as an integrated circuit system on an IC chip such as a flip chip. Fig. 24Bis a schematic diagram of an integrated circuit 2 comprising ADC circuitry 1. Integrated circuits comprising mixer circuitry 300, 300-1, 300-2, 300-3, 400, 500, 600, 700, 800, 900 may also be provided.

[0240] The present invention extends to integrated circuit systems and IC chips as mentioned above, circuit boards including such IC chips, and communication networks (e.g., Internet fiber optic networks and wireless networks) and network devices of such networks, which network devices include such circuit boards. The circuit system of the present invention can also be implemented with discrete components arranged on a circuit board. The circuit system of the present invention can be implemented alone (as an independent circuit) or together with other circuit systems.

[0241] In any of the above method aspects (e.g., the operation change between the first operation mode and the second operation mode), various features can be appropriately implemented in hardware or as software modules running on one or more processors. Features of one aspect can be applicable to any other aspect.

[0242] The present invention also provides a computer program or computer program product for executing any method described herein, and a computer readable medium having a program for executing any method described herein stored thereon. The computer program implementing the present invention may be stored on a computer readable medium, or it may be in the form of a signal, such as a downloadable data signal provided from a website on the Internet, or it may be in any other form.

[0243] Additional embodiments may be provided within the spirit and scope of the invention as disclosed herein.

Claims

1. A differential mixer circuit system, comprising: first and second input voltage nodes and first and second input current nodes; a passive impedance network connecting the first input voltage node and the second input voltage node to the first input current node and the second input current node and configured to convert first and second input voltage signals received at the first and second input voltage nodes, respectively, into first and second input current signals, the first and second input current signals being provided at the first and second input current nodes, respectively, the first and second input voltage signals defining a differential input voltage signal having an input frequency, and the first and second input current signals defining a differential input current signal; as well as a mixing stage comprising a plurality of switches each connected at the first input current node, and a plurality of switches each connected at the second input current node, and configured to mix the differential input current signal with at least one mixing signal having a corresponding mixing frequency, and output a differential output signal having an output frequency depending on the input frequency and each mixing frequency, Wherein, the passive impedance network comprises: A tail node for connection to a voltage source; a first tail-side impedance connected between the first input voltage node and the tail node and a first mixer-side impedance connected between the first input voltage node and the first input current node; and a second tail-side impedance connected between the second input voltage node and the tail node and a second mixer-side impedance connected between the second input voltage node and the second input current node.

2. The differential mixer circuit system of claim 1 , comprising a first output current node and a second output current node, wherein: The mixing stage is connected between the first input current node and the second input current node and the first output current node and the second output current node, and is configured to mix the first input current signal and the second input current signal with the at least one mixing signal to generate a first output current signal and a second output current signal at the first output current node and the second output current node, respectively, and the first output current signal and the second output current signal define the differential output signal.

3. The differential mixer circuit system of claim 2, wherein: The passive impedance network forms a voltage-to-current conversion stage of the differential mixer circuitry; and / or The differential mixer circuit system includes a current-to-voltage conversion stage, which is connected to the output current node and is configured to convert the first output current signal and the second output current signal provided at the first output current node and the second output current node, respectively, into a first output voltage signal and a second output voltage signal, and the first output voltage signal and the second output voltage signal are also provided at the first output current node and the second output current node, respectively.

4. The differential mixer circuit system according to claim 2 or 3, wherein: The mixing stage comprises at least a first mixer sub-stage, and the first mixer sub-stage comprises: a first switch array and a second switch array, each of the first switch array and the second switch array comprises X switches, X upstream nodes and X downstream nodes, wherein X≥2, and the switches of each array are respectively connected between the upstream node and the downstream node of the array along the corresponding current path, in: An upstream node of the first switch array of the first mixer substage is connected to the first input current node, and an upstream node of the second switch array of the first mixer substage is connected to the second input current node; a downstream node of the first switch array of the first mixer substage and a downstream node of the second switch array of the first mixer substage are connected to the output current node along current paths arranged such that the first output current signal and the second output current signal are provided at the first output current node and the second output current node, respectively; and In a first operating mode of the differential mixer circuit system, the at least one mixing signal includes at least a first sub-stage mixing signal, the first sub-stage mixing signal is an X-phase mixing signal, and the switches of each array are configured to be controlled by a respective phase of the first sub-stage mixing signal.

5. The differential mixer circuit system of claim 4, wherein: The mixing stage comprises at least a second mixer substage, the second mixer substage comprises a plurality of switch arrays, each of the plurality of switch arrays comprises Y switches, Y upstream nodes and Y downstream nodes, wherein Y ≥ 2, the switches of each array are respectively connected between the upstream node and the downstream node of the array along a corresponding current path; a downstream node of the first switch array of the first mixer substage and a downstream node of the second switch array of the first mixer substage are connected to the output current node along a current path arranged to pass through switches of the array of the second mixer substage such that the first output current signal and the second output current signal are provided at the first output current node and the second output current node, respectively; and In the first operating mode, the at least one mixing signal includes at least a second sub-stage mixing signal, the second sub-stage mixing signal is a Y-phase mixing signal, and the switches of each array of the second mixer sub-stage are configured to be controlled by the respective phases of the second sub-stage mixing signal. 6 . An integrated circuit system, comprising the circuit system according to claim 1 .

7. The integrated circuit system according to claim 6, wherein: The integrated circuit system is an IC chip and / or an ADC circuit system.

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