Voltage regulation method and electronic device

Abstract

The present application discloses a voltage regulation method and an electronic device, which relates to the field of electronic technology, to ensure that the processor can achieve power consumption reduction and performance improvement under both light and heavy load conditions. The method is applied to an electronic device having a processor and a power supply for supplying power to the processor. The method comprises: the processor sends power supply regulation information to the power supply according to the main frequency of the next period; the power supply determines the power supply voltage V used to supply power to the processor according to the power supply regulation information out The supply voltage V out As the load current of the power supply increases, V min ≤V out ≤V,V min is the minimum supply voltage of the processor's main frequency in the next period, and V is the set supply voltage of the processor's main frequency in the next period.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a voltage regulation method and an electronic device. Background Art

[0002] Moore's Law of Circuits is a law that reveals the speed of progress in information technology. It states that when the price remains unchanged, the number of components that can be accommodated on an integrated circuit will double approximately every 18-24 months, and the performance will also double. In other words, the performance of a computer that can be purchased with one dollar will more than double every 18-24 months.

[0003] In recent years, with the continuous improvement of the operating frequency and integration of integrated circuits, the power consumption of integrated circuits has increased rapidly, making it difficult for integrated circuits to continue to apply Moore's Law of circuits, resulting in the inability to improve processor performance and integration, and increased cooling costs.

[0004] In order to solve the above problems, the dynamic voltage and frequency scaling (DVFS) technology is generally used to adjust the power supply voltage of the power supply to the processor, so as to reduce the processor main frequency and power supply voltage when the processor load is light; when the processor load is heavy, the processor main frequency and power supply voltage are increased, thereby reducing the power consumption of the processor. However, when the processor is heavily loaded, the DVFS technology cannot reduce the power supply voltage of the processor. Therefore, the effect of the DVFS technology in reducing power consumption is not obvious. Summary of the invention

[0005] The present application provides a voltage regulation method and an electronic device to ensure that a processor can achieve reduced power consumption and improved performance under both light and heavy load conditions.

[0006] In order to solve the above technical problems, the embodiments of the present application provide the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a voltage regulation method, which is applied to an electronic device having a processor and a power supply for supplying power to the processor. The method comprises: the processor sends power supply regulation information to the power supply according to the main frequency of the next period, the power supply regulation information includes a set power supply voltage V of the main frequency of the next period, and the main frequency of the next period refers to the main frequency predicted according to the current main frequency; the power supply provides a power supply voltage V to the processor according to the set power supply voltage V of the main frequency of the next period and the set voltage slope R of the main frequency of the next period. out The voltage slope refers to the change in the supply voltage V as the load current of the power supply increases. out The supply voltage V out As the load current increases, it decreases. V min ≤Vout ≤V,V min It is the minimum supply voltage for normal operation of the processor when the processor runs at the main frequency in the next period and the load current increases.

[0008] In the method provided in the present application, the main frequency of the next period refers to the main frequency predicted according to the current main frequency, and the power supply voltage V provided to the processor by the power supply according to the set supply voltage V of the main frequency of the next period and the set voltage slope R of the main frequency of the next period out Adapt to the main frequency of the processor in the next period. In addition, since the load current has the characteristic of periodically increasing from the minimum value to the maximum load current, when the power supply in the prior art outputs the load terminal voltage in a constant voltage manner, the load terminal voltage passively decreases during the process of increasing the load current. The method provided in this application actively controls the supply voltage V output by the power supply. out As the load current increases, it decreases, so that when the load current starts to increase, the supply voltage V out Actively decreases as the load current increases. At this time, the supply voltage V out Less than the set supply voltage V of the processor at the next period of main frequency and greater than or equal to the minimum supply voltage V for normal operation when the processor is running at the next period of main frequency and the load current increases. min It can be seen that compared with the prior art, the power supply voltage V ou It is possible to reduce the power consumption of the processor while ensuring the normal operation of the processor, thereby improving the performance of the processor. Moreover, since the higher the main frequency of the processor, the higher the load of the processor, the method provided by the present application can ensure that no matter how high or low the load of the processor is, the power supply can supply power to the processor in a manner lower than the power supply voltage set at the current main frequency when the load current increases, so that the processor has lower power consumption while operating normally.

[0009] In some possible implementations, before the processor sends the power supply adjustment information to the power supply according to the main frequency of the next period, the method further includes: the processor predicts the load of the next period according to the current load, and determines the main frequency of the next period according to the load of the next period. For example, a corresponding relationship table between the load and the main frequency is stored in the built-in memory of the motherboard or the processor, and the main frequency of the next period is queried in the corresponding relationship table between the load and the main frequency according to the predicted load of the next period.

[0010] In some possible implementations, the method further includes: when the processor determines that the main frequency of the next time period is not equal to the current main frequency, setting the current main frequency equal to the main frequency of the next time period. In view of the interdependent relationship between power supply voltage regulation and main frequency regulation, when the processor determines that the main frequency of the next time period is not equal to the current main frequency, setting the current main frequency equal to the main frequency of the next time period includes: when the processor determines that the main frequency of the next time period is less than the current main frequency, the processor sets the current main frequency equal to the main frequency of the next time period before sending power supply adjustment information to the power supply according to the main frequency of the next time period; when the processor determines that the main frequency of the next time period is greater than the current main frequency, the power supply provides the processor with a power supply voltage V according to the set power supply voltage V of the main frequency of the next time period and the set voltage slope R of the main frequency of the next time period. out After that, the processor sets the current main frequency to be equal to the main frequency of the next period.

[0011] In some possible implementations, the supply voltage V out =VI*R, I is the load current of the power supply, which is determined by the supply voltage V out It can be seen from the calculation formula that the supply voltage V out It is determined by the set voltage slope R of the processor in the next period, the set power supply voltage V in the next period, and the load current I. Since the voltage slope refers to the speed at which the power supply voltage decreases as the load current of the power supply increases, the product of the set voltage slope R of the main frequency in the next period and the load current I is essentially: the active decrease of the power supply voltage when the load current of the power supply increases. As long as the active decrease is greater than or equal to the passive maximum decrease of the load terminal voltage when the load current increases in the prior art, the power supply voltage V out Always greater than or equal to the minimum supply voltage V for normal operation of the processor when the load current increases during the next period of operation. min .

[0012] In some possible implementations, the set supply voltage V of the main frequency of the next period can be provided by the processor, and the set voltage slope R of the main frequency of the next period can exist in the power supply, or can be provided by the processor. When the processor only provides the set supply voltage V of the main frequency of the next period to the power supply, the processor does not need to use the communication interface between the processor and the power supply to dynamically set the set voltage slope R of the main frequency of the next period in the power supply, thereby effectively reducing the communication delay and voltage regulation delay, and improving the voltage regulation speed.

[0013] In some possible implementations, the processor sends power supply adjustment information to the power supply according to the main frequency of the next time period, including: the processor searches for the set power supply voltage V of the main frequency of the next time period from the target correspondence relationship according to the main frequency of the next time period, and sends the set power supply voltage V of the main frequency of the next time period to the power supply. The target correspondence relationship here is the correspondence between the main frequency of the processor, the set power supply voltage, and the set voltage slope. Of course, the target correspondence relationship can also be the correspondence between the main frequency of the processor and the set power supply voltage. At this time, the processor only needs to query the set power supply voltage of the main frequency of the next time period from the target correspondence relationship, and send the set power supply voltage of the main frequency of the next time period to the power supply, which can reduce communication delay and voltage regulation delay, and shorten the voltage regulation time.

[0014] In some possible implementations, when the processor only provides the power supply with the set supply voltage V of the main frequency of the next period, the set voltage slope R of the main frequency of the next period may exist in the power supply in the form of a constant voltage slope. The existence mode may be a storage mode. The constant voltage slope is the minimum voltage slope R allowed by the processor at the set supply voltage of each main frequency. min , R min >0. Due to R min >0, it can ensure that when the processor is working at any load or main frequency, the power supply can always provide the processor with a power supply voltage less than or equal to the set power supply voltage, so that the processor has lower energy consumption. In addition, since the constant voltage slope is the minimum value R of the measured voltage slope of the processor at each main frequency min Therefore, when the constant voltage slope is used as the set voltage slope R of the main frequency of the next period, the product of the set voltage slope of the main frequency of the next period and the load current can be controlled to make the processor run normally and avoid the situation that when the constant voltage slope is large, the processor will be in a state of power supply voltage V when the load current increases. out Failure to operate normally occurs.

[0015] In some possible implementations, when the set voltage slope R of the main frequency in the next period is provided by a processor, the power supply adjustment information includes not only the set supply voltage V of the main frequency in the next period, but also the set voltage slope R of the main frequency in the next period.

[0016] In some possible implementations, when the set voltage slope R of the main frequency of the next period is provided by the processor, the processor sends the power supply adjustment information to the power supply according to the main frequency of the next period, including: the processor searches for the set power supply voltage V of the main frequency of the next period and the set voltage slope R of the main frequency of the next period from the target corresponding relationship according to the main frequency of the next period, and sends the set power supply voltage V of the main frequency of the next period and the set voltage slope R of the main frequency of the next period to the power supply. The target corresponding relationship is the corresponding relationship between the main frequency of the processor, the set power supply voltage, and the set voltage slope.

[0017] In a possible implementation, the set voltage slope of the processor at each main frequency is the voltage slope allowed by the set power supply voltage of the processor at each main frequency. In other words, the set voltage slope of each main frequency in the above target correspondence is the voltage slope allowed by the set power supply voltage of the processor at each main frequency. At this time, the set power supply voltage V of the next period has a good match with the set voltage slope R of the next period, so that the power supply voltage V provided by the power supply to the processor is out Ensure that the processor's power consumption is optimized while ensuring normal processor operation.

[0018] In a possible implementation, the set voltage slope of the processor at all main frequencies is equal to the constant voltage slope. The constant voltage slope is the minimum voltage slope R allowed by the set supply voltage of the processor at each main frequency. min , R min >0. In other words, the set voltage slopes of all main frequencies in the above target correspondence are equal to the constant voltage slope. When the processor sends the set supply voltage V of the main frequency of the next period and the set voltage slope R of the main frequency of the next period to the power supply for the first time, the power supply can save the set voltage slope R of the main frequency of the next period in the form of a constant voltage slope. Since the set voltage slopes of all main frequencies in the target correspondence are equal to the constant voltage slope, the power supply actually saves the set voltage slopes of all main frequencies in the target correspondence in the form of a constant voltage slope. When the power supply needs to adjust the power supply voltage V provided to the processor again out When the processor only needs to query the set supply voltage R of the next period of main frequency from the target correspondence, and send the set supply voltage V of the next period of main frequency to the power supply, so that the power supply adjusts the reference voltage according to the set supply voltage V of the next period of main frequency. In this process, the processor only needs to dynamically set the reference voltage in the power supply through the bus interface according to the main frequency of the next period of time to reduce communication delay and voltage adjustment delay, so as to shorten the voltage adjustment time. In addition, since the constant voltage slope is the minimum voltage slope R allowed by the processor at the set supply voltage of each main frequency min , R min > 0, which can ensure that the power supply voltage V provided by the power supply to the processor is sufficient when the processor is working at any load or main frequency. out Always meet V min ≤V out ≤V, so that the processor has lower energy consumption while operating normally.

[0019] In some possible implementations, the voltage slope R allowed by the processor at each main frequency setting supply voltage is (i) =R max(i) -ΔR (i) , R max(i)ΔR is the maximum voltage slope of the processor's supply voltage at each clock frequency. (i) is the voltage slope margin of the processor at each main frequency. At this time, due to R max(i) The maximum voltage slope of the power supply voltage set for the processor at each main frequency. Therefore, when the load current increases, the power supply voltage V provided by the power supply to the processor out As close as possible to V min , thereby ensuring that the processor runs at lower power consumption. And, when R (i) =R max(i) When the load current increases, it is easy to cause the supply voltage V out Slightly lower than V min , making the processor unable to operate normally. Based on this, in R max(i) The voltage slope margin is subtracted from the value of , thereby ensuring that the processor operates normally with lower power consumption.

[0020] In a possible implementation, the set supply voltage of each main frequency in the above processor is V (i) That is, the set supply voltage of each main frequency in the above target correspondence is V (i) . V (i) =V min(i) +ΔV (i) , V min(i) ΔV is the minimum supply voltage for normal operation of the processor when the load current increases at each main frequency. (i) is the supply voltage margin of the processor at each main frequency. At this time, the set supply voltage V of the main frequency in the next period found by the processor is lower than the minimum supply voltage V of normal operation when the processor is running at the main frequency in the next period and the load current increases. min Slightly larger, so that the power supply voltage V out It can ensure that the processor runs normally at lower power consumption.

[0021] In a possible implementation, before the processor sends power supply adjustment information to the power supply according to the main frequency of the next time period, the method further includes: the processor calibrates the target correspondence according to the performance difference information, so that the calibrated target correspondence matches the processor included in the electronic device, thereby improving the reliability and accuracy of voltage adjustment, and these performance difference information can be detected by a critical path detection (critical path monitor, abbreviated as CPM) circuit built into the processor. The CPM circuit is used to simulate the timing critical path of the benchmark processor. The delay level (such as delay time) or oscillation frequency determined by the CPM circuit is the performance difference information. When the processor has different delay levels or oscillation frequencies in different environments, the minimum power supply voltage of the processor will also be different at a given main frequency.

[0022] In a possible implementation, in order to cooperate with the processor to calibrate the target correspondence according to the performance difference information, the correspondence between the performance differences of multiple processors without considering the influence of temperature and the difference in the minimum power supply voltage, or the correspondence between the performance differences of multiple processors at multiple temperature levels considering the influence of temperature and the difference in the minimum power supply voltage should also be pre-stored. For example: when the target correspondence is the target correspondence of the benchmark processor, the performance difference of each processor can be expressed by the delay level (such as delay time) or oscillation frequency of the processor, or can be indirectly expressed by the delay difference or oscillation frequency difference between the processor and the benchmark processor at the same voltage. The minimum power supply voltage difference corresponding to the performance difference of each processor refers to the minimum power supply voltage difference between the processor and the benchmark processor at the same main frequency. The benchmark processor refers to the processor with the worst performance among multiple processors. That is, the benchmark processor is the processor with the largest minimum power supply voltage at the same main frequency among multiple processors.

[0023] When the temperature influence is not considered, the performance difference information detected by the CPM circuit, the processor calibrates the target correspondence according to the performance difference information, so that the target correspondence matches the processor included in the electronic device, including: the processor searches for the lowest power supply voltage difference from the correspondence between the performance differences of multiple processors and the lowest power supply voltage difference according to the performance difference information, and calibrates the set power supply voltage corresponding to each main frequency in the target correspondence according to the lowest power supply voltage difference, so that the calibrated target correspondence matches the processor included in the electronic device.

[0024] When the temperature influence is taken into consideration, the performance difference information detected by the CPM circuit, and the processor calibrating the target correspondence according to the performance difference information so that the target correspondence matches the processor included in the electronic device, including: the processor searching for the correspondence between the performance difference and the minimum power supply voltage difference of multiple processors at the temperature level where the current temperature is located from the correspondence between the performance difference and the minimum power supply voltage difference of multiple processors at multiple temperature levels according to the current temperature, searching for the minimum power supply voltage difference that matches the current performance difference information from the correspondence between the performance difference and the minimum power supply voltage difference of multiple processors at the temperature level where the current temperature is located according to the performance difference information, and calibrating the set power supply voltage corresponding to each main frequency in the target correspondence according to the minimum power supply voltage difference that matches the performance difference information, so that the calibrated target correspondence matches the processor included in the electronic device.

[0025] In one possible implementation, the electronic device contains a storage medium. The storage medium may exist independently of the processor, or may be built into the processor. The target correspondence relationship may be directly or indirectly stored in the storage medium in a variety of forms. Of course, the storage medium may also store the correspondence between the performance differences of multiple processors and the minimum power supply voltage differences, or the correspondence between the performance differences of multiple processors at multiple temperature levels and the minimum power supply voltage differences. For example, the correspondence between the performance differences of multiple processors and the minimum power supply voltage differences may be stored in the storage medium in the form of a relationship table or a functional relationship. The correspondence between the performance differences of multiple processors at multiple temperature levels and the minimum power supply voltage differences is stored in the storage medium in the form of a relationship table or a functional relationship.

[0026] In a possible implementation, the above-mentioned target correspondence is stored in the above-mentioned storage medium. The target correspondence is a target correspondence for a benchmark processor. The benchmark processor is a processor with the largest minimum power supply voltage at the same main frequency among multiple processors, that is, the benchmark processor is the processor with the worst performance among multiple processors. At this time, the set power supply voltage and set voltage slope corresponding to each main frequency in the target correspondence can meet the voltage regulation of multiple processors. Therefore, the target correspondence of the benchmark processor has wide applicability. It should be understood that multiple processors can be distinguished according to production process, aging degree, etc. Regardless of whether the production process is different or the aging degree is different, it will eventually be reflected in the form of performance difference information. For example: for processors of the same model, processors of different batches have slight differences in production process, resulting in different batches of processors of the same model belonging to different categories.

[0027] In a possible implementation, the target correspondence relationship is stored in a storage medium. The target correspondence relationship is a target correspondence relationship of a processor included in the electronic device where the storage medium is located. The target correspondence relationship can be tested and stored in the storage medium after the electronic device leaves the factory.

[0028] In a possible implementation, the electronic device further includes a storage medium. The storage medium stores target correspondences of the reference processor at multiple temperature levels. The definition of the reference processor is referred to above and will not be described in detail here. At this time, before the processor sends power supply adjustment information to the power supply according to the main frequency of the next time period, the method further includes: the processor searches for a target correspondence from the target correspondence of the reference processor at multiple temperature levels according to the current temperature. The target correspondence is a target correspondence of the reference processor at the temperature level where the current temperature is located. At this time, if the searched target correspondence is calibrated, the calibrated target correspondence can be made to better match the processor.

[0029] In a possible implementation, without considering the influence of temperature, the electronic device is powered on, the CPM circuit detects the performance difference information, and before the processor sends the power supply adjustment information to the power supply according to the main frequency of the next period, the method further includes: the processor searches for a target correspondence relationship matching the processor included in the electronic device from the target correspondence relationship of multiple processors according to the performance difference information. The difference information of the processor corresponding to the target correspondence relationship matches the difference information tested by the CPM circuit better.

[0030] When the influence of temperature is taken into consideration, when the electronic device is powered on, the CPM circuit detects performance difference information, and before the processor sends power supply adjustment information to the power supply according to the main frequency of the next time period, the method further includes: the processor searches for target correspondences of multiple processors at the temperature level where the current temperature is located from target correspondences of multiple processors at multiple temperature levels according to the current temperature; and searches for a target correspondence that matches the processor included in the electronic device from the target correspondences of multiple processors at the temperature level where the current temperature is located according to the performance difference information.

[0031] In a possible implementation, in order to cooperate with the processor to find a target correspondence relationship that matches the processor included in the electronic device, the above-mentioned electronic device includes a storage medium. Without considering the influence of temperature, the above-mentioned electronic device also includes a storage medium, and the performance difference information of multiple processors and the target correspondence relationship of multiple processors can be measured by a CPM circuit before leaving the factory, and the relationship between the two can be established, and the performance difference information of multiple processors and the target correspondence relationship of multiple processors can be stored in the storage medium. Under the premise of considering the influence of temperature, the performance difference information of multiple processors at multiple temperature levels and the target correspondence relationship of multiple processors at multiple temperature levels can be measured by a CPM circuit before leaving the factory, and the mutual dependence relationship between the performance difference information of multiple processors at multiple temperature levels and the target correspondence relationship of multiple processors at multiple temperature levels can be established, and then the performance difference information of multiple processors at multiple temperature levels and the target correspondence relationship of multiple processors at multiple temperature levels can be stored in the storage medium.

[0032] In a second aspect, the present application provides an electronic device. The electronic device includes: a processor, which is used to send power supply adjustment information to a power supply according to the main frequency of the next period; the power supply adjustment information includes a set power supply voltage V of the main frequency of the next period, and the main frequency of the next period refers to the main frequency predicted according to the current main frequency; the power supply is used to provide a power supply voltage V to the processor according to the set power supply voltage V of the main frequency of the next period and the set voltage slope R of the main frequency of the next period out The voltage slope refers to the change in the supply voltage V as the load current of the power supply increases. out The rate of decline of the supply voltage V out As the load current of the power supply increases, it decreases; V min ≤V out ≤V,V min It is the minimum supply voltage for normal operation of the processor when the processor runs at the main frequency in the next period and the load current increases.

[0033] In a possible implementation, the processor is further configured to predict the load in the next period based on the current load and determine the main frequency in the next period based on the load before sending power supply adjustment information to the power supply based on the main frequency in the next period.

[0034] In some possible implementations, the processor is further configured to set the current main frequency equal to the main frequency of the next period when the processor determines that the main frequency of the next period is not equal to the current main frequency. For example, the processor is further configured to determine that the main frequency of the next period is less than the current main frequency, and before sending power supply adjustment information to the power supply according to the main frequency of the next period, the current main frequency is set equal to the main frequency of the next period. The power supply is configured to provide the processor with a power supply voltage V according to the set power supply voltage V of the main frequency of the next period and the set voltage slope R of the main frequency of the next period. outAfter that, the processor is specifically used to determine that the main frequency of the next time period is greater than the current main frequency, and set the current main frequency equal to the main frequency of the next time period.

[0035] In a possible implementation, the supply voltage V out =VI*R, I is the load current of the power supply.

[0036] In a possible implementation, the processor is specifically used to search the set power supply voltage V of the main frequency of the next period from the target correspondence according to the main frequency of the next period, and send the set power supply voltage V of the main frequency of the next period to the power supply. The target correspondence is a correspondence between the main frequency of the processor, the set power supply voltage, and the set voltage slope, or a correspondence between the main frequency of the processor and the set power supply voltage.

[0037] In a possible implementation, the set voltage slope of the main frequency of the next period exists in the power supply in the form of a constant voltage slope. The constant voltage slope is the minimum voltage slope allowed by the processor at each main frequency set supply voltage R min , R min >0.

[0038] In a possible implementation, the power supply adjustment information further includes a set voltage slope R of the main frequency in the next time period.

[0039] In a possible implementation, the processor is specifically used to search the set power supply voltage V of the main frequency of the next period and the set voltage slope R of the main frequency of the next period from the target corresponding relationship according to the main frequency of the next period, and send the set power supply voltage V of the main frequency of the next period and the set voltage slope R of the main frequency of the next period to the power supply. The target corresponding relationship is the corresponding relationship between the main frequency of the processor, the set power supply voltage, and the set voltage slope.

[0040] In a possible implementation, the set voltage slope of the processor at each main frequency is the voltage slope allowed by the set power supply voltage of the processor at each main frequency.

[0041] In a possible implementation, the set voltage slope of the processor at all main frequencies is equal to the constant voltage slope. The constant voltage slope is the minimum voltage slope R allowed by the set supply voltage of the processor at each main frequency. min , R min >0.

[0042] In a possible implementation, the voltage slope allowed by the processor at each main frequency setting supply voltage is R (i) , R (i) =R max(i) -ΔR (i) , R max(i)is the maximum voltage slope of the processor at each set supply voltage frequency, ΔR (i) It is the voltage slope margin of the processor at each main frequency.

[0043] In a possible implementation, the processor sets a power supply voltage V at each main frequency. (i) =V min(i) +ΔV (i) , V min(i) ΔV is the minimum supply voltage for normal operation of the processor when the load current increases at each main frequency. (i) The supply voltage margin for the processor at each clock frequency.

[0044] In a possible implementation, the processor is further used to calibrate the target correspondence according to the performance difference information before sending power supply adjustment information to the power supply according to the main frequency of the next time period, so that the calibrated target correspondence matches the processor included in the electronic device.

[0045] In one possible implementation, without considering the influence of temperature, the above-mentioned processor is specifically used to find the minimum power supply voltage difference from the correspondence between the performance differences of multiple processors and the minimum power supply voltage difference according to the performance difference information, and calibrate the set power supply voltage corresponding to each main frequency in the target correspondence according to the minimum power supply voltage difference, so that the calibrated target correspondence matches the processor included in the electronic device.

[0046] Under the premise of considering the influence of temperature, the above-mentioned processor is specifically used to find the correspondence between the performance difference and the minimum power supply voltage difference of multiple processors at the temperature level where the current temperature is located from the correspondence between the performance difference and the minimum power supply voltage difference of multiple processors at multiple temperature levels according to the current temperature, find the minimum power supply voltage difference that matches the current performance difference information from the correspondence between the performance difference and the minimum power supply voltage difference of multiple processors at the temperature level where the current temperature is located according to the performance difference information, and calibrate the set power supply voltage corresponding to each main frequency in the target correspondence according to the minimum power supply voltage difference that matches the performance difference information, so that the calibrated target correspondence matches the processor included in the electronic device.

[0047] In one possible implementation, the electronic device contains a storage medium. The storage medium may exist independently of the processor, or may be built into the processor. The target correspondence relationship may be directly or indirectly stored in the storage medium in a variety of forms. Of course, the storage medium may also store the correspondence between the performance differences of multiple processors and the minimum power supply voltage differences, or the correspondence between the performance differences of multiple processors at multiple temperature levels and the minimum power supply voltage differences. For example, the correspondence between the performance differences of multiple processors and the minimum power supply voltage differences may be stored in the storage medium in the form of a relationship table or a functional relationship. The correspondence between the performance differences of multiple processors at multiple temperature levels and the minimum power supply voltage differences is stored in the storage medium in the form of a relationship table or a functional relationship.

[0048] In a possible implementation, the target correspondence relationship is stored in a storage medium, and the target correspondence relationship is a target correspondence relationship of a reference processor. The reference processor is a processor with the largest minimum power supply voltage among multiple processors at the same main frequency.

[0049] In a possible implementation, the target correspondence relationship is stored in a storage medium. The target correspondence relationship is a target correspondence relationship of a processor included in the electronic device where the storage medium is located. The target correspondence relationship can be tested and stored in the storage medium after the electronic device leaves the factory.

[0050] In a possible implementation, the electronic device further includes a storage medium. The storage medium stores target correspondences of the reference processor at multiple temperature levels. The reference processor is a processor with the largest minimum power supply voltage at the same main frequency among multiple processors. The processor is also used to search for a target correspondence from the target correspondences of the reference processor at multiple temperature levels according to the current temperature before sending power supply adjustment information to the power supply according to the main frequency of the next time period. The target correspondence is the target correspondence of the reference processor at the temperature level where the current temperature is located.

[0051] In a possible implementation, without considering the influence of temperature, the processor is further used to search for a target correspondence that matches the processor included in the electronic device from the target correspondences of multiple processors based on the performance difference information before sending the power supply adjustment information to the power supply according to the main frequency of the next time period. Under the premise of considering the influence of temperature, the processor is further used to search for a target correspondence that matches the processor included in the electronic device from the target correspondences of multiple processors at multiple temperature levels based on the current temperature before sending the power supply adjustment information to the power supply according to the main frequency of the next time period; and search for a target correspondence that matches the processor included in the electronic device from the target correspondences of multiple processors at the temperature level where the current temperature is located based on the performance difference information.

[0052] In a possible implementation, the electronic device includes a storage medium. Without considering the influence of temperature, the storage medium stores performance difference information of multiple processors and target correspondences of multiple processors, and the performance difference information of multiple processors and the target correspondences of multiple processors are mutually dependent. Considering the influence of temperature, the performance difference information of multiple processors at multiple temperature levels and the target correspondences of multiple processors at multiple temperature levels are stored in the storage medium, and the performance difference information of multiple processors at multiple temperature levels and the target correspondences of multiple processors at multiple temperature levels are mutually dependent.

[0053] In a third aspect, the present application further provides a processor, which includes one or more modules for implementing the steps executed by the processor in the first aspect, and the one or more modules may correspond to the steps executed by the processor in the method of the first aspect.

[0054] In a fourth aspect, the present application provides a power supply, which includes one or more modules for implementing the steps performed by the power supply in the first aspect, and the one or more modules may correspond to the steps performed by the power supply in the method of the first aspect.

[0055] In a fifth aspect, the present application provides a terminal device. The terminal device includes a processor and a power supply. The processor is used to execute the steps performed by the processor as described in the first aspect or any possible implementation of the first aspect, and the power supply is used to execute the steps performed by the power supply as described in the first aspect or any possible implementation of the first aspect.

[0056] In some possible implementations, the terminal device further includes a storage medium for storing the correspondence between the computer program and the target.

[0057] In a sixth aspect, the present application provides a communication device, comprising a processor and a power supply, wherein the processor is used to execute the steps performed by the processor as described in the first aspect or any possible implementation of the first aspect, and the power supply is used to execute the steps performed by the power supply as described in the first aspect or any possible implementation of the first aspect.

[0058] In some possible implementations, the above-mentioned communication device also includes a storage medium for storing the correspondence between the computer program and the target.

[0059] In a seventh aspect, the present application further provides a chip. The chip includes a processor and a communication interface coupled to the communication interface. The processor is used to run a computer program or instruction to implement the steps performed by the processor as described in the first aspect or any possible implementation of the first aspect.

[0060] In a possible implementation, the chip further includes a memory for storing computer programs or instructions and target correspondences.

[0061] In an eighth aspect, the present application further provides a chip. The chip includes a processor and a communication interface coupled to the communication interface. The processor is used to run a computer program or instruction to implement the steps performed by the power supply as described in the first aspect or any possible implementation of the first aspect.

[0062] In a possible implementation, the chip further includes a memory for storing computer programs.

[0063] Any of the above-mentioned devices, computer storage media, computer program products, chips, or communication systems are used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can be referred to the beneficial effects of the corresponding schemes in the corresponding methods provided above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0065] Figure 2 This is a schematic diagram of the connection structure between the processor and the power supply in the embodiment of the present application;

[0066] Figure 3 A system architecture diagram of a vehicle communication system provided in an embodiment of the present application;

[0067] Figure 4 Schematic diagram of the voltage regulation method provided in the embodiment of the present application Figure 1 ;

[0068] Figure 5 Schematic diagram of the process of the voltage regulation method provided in the embodiment of the present application Figure 2 ;

[0069] Figure 6 It is a schematic diagram of the transient process of power supply load;

[0070] Figure 7 This is a schematic diagram of the power supply loadline characteristics;

[0071] Figure 8 Schematic diagram of the mechanism of DVFS technology to reduce power consumption;

[0072] Fig. 9 A comparison chart of the power supply method of this application, DVFS technology, and fixed voltage method;

[0073] Fig.10 It is the main frequency and voltage slope curve of the processor;

[0074] Fig.11 Schematic diagram of the process of the voltage regulation method provided in the embodiment of the present application Figure 3 ;

[0075] Fig.12 Schematic diagram of the process of the voltage regulation method provided in the embodiment of the present application Figure 4 ;

[0076] Fig.13 Schematic diagram of the process of the voltage regulation method provided in the embodiment of the present application Figure 5 ;

[0077] Fig.14 It is the voltage slope diagram of the power supply voltage in the rated mode;

[0078] Fig.15 It is the voltage slope diagram under different power consumption modes;

[0079] Fig.16 A schematic diagram of the structure of a device provided in an embodiment of the present application;

[0080] Fig.17 A schematic diagram of the structure of a voltage regulating device provided in an embodiment of the present application;

[0081] Fig.18 A schematic diagram of the structure of another voltage regulating device provided in an embodiment of the present application;

[0082] Fig.19 A schematic diagram of the structure of another voltage regulating device provided in an embodiment of the present application;

[0083] Fig. 20 A schematic diagram of the structure of the chip provided in the embodiment of the present application. DETAILED DESCRIPTION

[0084] Before introducing the embodiments of the present application, the following definitions are given for the relevant terms involved in the embodiments of the present application:

[0085] Dynamic Voltage and Frequency Scaling (DVFS) technology refers to dynamically adjusting the operating frequency and voltage of the chip according to the different computing power requirements of the applications running on the chip (for the same chip, the higher the frequency, the higher the voltage required), so as to achieve energy saving. Specifically, when the processor load is light, the processor main frequency and power supply voltage are reduced; when the processor load is heavy, the processor main frequency and power supply voltage are increased, thereby reducing the power consumption of the processor.

[0086] Intel Turbo Boost Technology is also known as Turbo Boost Technology, or Turbo Technology for short. Turbo Technology is an automatic overclocking (OC) technology for multi-core CPUs. When the CPU core does not reach the temperature, current, and power consumption specification thresholds, Turbo Technology will automatically allow some active cores of the CPU to run beyond the rated main frequency, improving processor performance and coping with peak loads.

[0087] The Basic Input Output System (BIOS) is a set of programs that are fixed to a read-only memory image chip on the motherboard of the computer. It stores the computer's most important basic input and output programs, self-test programs after power-on, and system self-startup programs.

[0088] Adaptive voltage scaling (AVS) is a real-time, closed-loop control power management technology that continuously adjusts the supply voltage. AVS can be implemented through a critical path monitor (CPM) circuit. The CPM circuit is used to simulate the timing critical path of the benchmark processor, and then determine the performance difference information such as the delay level or oscillation frequency, so as to adaptively adjust the circuit power supply level according to the performance difference information to ensure that the delay level or oscillation frequency meets the system requirements and the voltage is reduced as much as possible.

[0089] Voltage Identification (VID), also known as VID code, refers to a code representing a voltage value, which is actually a digitized voltage value.

[0090] The voltage regulator module (VRM) is a device that provides a suitable power supply voltage for the microprocessor, also known as a VRM power supply. The VRM power supply can identify the VID code and adjust the output constant voltage supply voltage so that the output constant voltage supply voltage is consistent with the voltage value represented by the VID code. Specifically, the VRM power supply has an 8-bit VID code integrated inside, which represents 256 voltage values. The processor sends an 8-bit VID code to the VRM power supply, and the VRM power supply can use the integrated 8-bit VID code to identify the VID code sent by the processor to determine the supply voltage.

[0091] The load line, also known as Loadline, refers to the characteristic curve of the power supply voltage output by the VRM power supply, which decreases linearly as the load current increases.

[0092] The voltage drop slope is referred to as the voltage slope or Loadline value, which indicates the linear drop speed of the power supply voltage as the load current of the VRM power supply increases. When the Loadline value is larger, it means that the power supply voltage output by the VRM power supply drops linearly faster as the load current increases. When the Loadline value is smaller, it means that the power supply voltage output by the VRM power supply drops linearly slower as the load current increases.

[0093] Phase Locked Loop (PLL) is also called phase-locked loop. It is a typical feedback control circuit that uses an external reference signal to control the frequency and phase of the oscillation signal inside the loop, and realizes automatic tracking of the output signal frequency to the input signal frequency. It is generally used in closed-loop tracking circuits.

[0094] A digital to analog converter (DAC) is a device that converts a digital signal into an analog signal (in the form of current, voltage, or charge).

[0095] The Power Management Bus (PMBus) is a bus that supports an open standard digital power management protocol. The open standard digital power management protocol facilitates communication with a power converter or other device by defining the transmission and physical interface and command language.

[0096] In order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and their order is not limited. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

[0097] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0098] In the present application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.

[0099] The method provided in the embodiment of the present application is applied to an electronic device. The electronic device can be applied to a terminal or a communication device. The terminal can be a vehicle-mounted terminal, a mobile phone, a computer, a server, or other terminal devices. The communication device can be a base station, a satellite, or other communication devices.

[0100] Figure 1 A schematic diagram of the structure of an electronic device provided by an embodiment of the present application is shown. Figure 1 As shown, the electronic device 100 includes a processor 101, a power supply 102 and a storage medium 103. The processor 101 and the power supply 102 can be integrated together or exist independently. The processor 101 can cover various general-purpose processors of terminals and data center equipment, and of course it can also be a vehicle-mounted processor, but it is not limited to the ones listed here. The processor 101 may include one or more CPUs. The storage medium 103 is coupled to the processor, and can store computer-executable instructions and data for executing the scheme of the present application, and the execution is controlled by the processor 101. The processor 101 is used to execute computer-executable instructions stored in the storage medium, thereby implementing the method provided in the following embodiments of the present application. Optionally, the computer-executable instructions in the embodiments of the present application may also be referred to as application code, which is not specifically limited in the embodiments of the present application.

[0101] like Figure 1 As shown, the storage medium 103 may exist independently of the processor 101, or may be built into the processor 101. For example, the storage medium 103 may be a built-in memory in the processor 101, or may be a BIOS memory on the motherboard.

[0102] like Figure 1As shown, the processor 101 can be a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an ASIC, a field-programmable gate array (FPGA), or other programmable logic devices, discrete gates or transistor logic devices, or discrete hardware components. The memory can be a random access memory (RAM), or can include a non-volatile memory, such as a disk memory, a flash memory, etc., which are not listed one by one. Specifically, the memory can be an external memory such as a memory on a motherboard (such as a BIOS memory), or can be a built-in memory of a processor. For example: when the processor 101 is a CPU, the storage medium 103 can be a built-in memory inside the CPU.

[0103] like Figure 1 As shown, the storage medium 103 can be a random access memory (RAM), a flash memory, a read only memory (ROM), an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM), a register, a hard disk, a mobile hard disk, a read-only compact disk (CD-ROM) or any other form of storage medium known in the art.

[0104] Figure 2 FIG. 2 shows a schematic diagram of the connection structure between the processor and the power supply in an embodiment of the present application. Figure 2 As shown, the processor 101 includes a processor core 1011 and a phase-locked loop 1013. The phase-locked loop 1013 adjusts or sets the main frequency of the processor under the control of the processor core 1011. And when the processor 101 also includes a built-in memory 1012, the built-in memory 1012 can realize the function of the above-mentioned storage medium 103, thereby reducing unnecessary hardware in the electronic device, so that the integration of the electronic device is relatively high.

[0105] In one example, if Figure 2 As shown, the processor 101 further includes a CPM circuit 1015 , and the CPM circuit 1015 is electrically connected to the processor core 1011 .

[0106] Figure 1 The power supply 102 shown may be any power supply with a voltage regulation function, and may provide a supply voltage to the processor 101 . Figure 2The power supply 102 shown is a schematic diagram of a structure taking a VRM power supply as an example. Figure 2 As shown, the power supply 102 includes a VRM chip 1021, a logic control circuit 1022 and a buck converter 1023. The VRM chip 1021 is connected to the signal input end of the logic control circuit 1022, and the signal output end of the logic control circuit 1022 is electrically connected to the buck converter 1023, so that the VRM chip 1021 provides a signal carrying information to the logic control circuit 1022. Of course, the power supply 102 may also include a register 1024 or other device with a storage function, which can store information for the VRM chip 1021 to retrieve. In some cases, the buck converter 1023 may also be independent of the power supply 102 and be provided between the power supply 102 and the processor 101.

[0107] For example, Figure 2 As shown, the buck converter 1023 includes a grounding capacitor C and a plurality of inductors L connected in parallel, the first ends of the plurality of inductors L connected in parallel are connected to the signal output end of the logic control circuit 1022, and the second ends of the plurality of inductors L connected in parallel are also grounded through the grounding capacitor C. It can be seen that the connection relationship of the buck converter 1023 is a multi-channel staggered parallel quasi-square wave (quasisquare-wave, abbreviated as QSW) topology, which has a good ripple mutual cancellation effect, and the more the number of inductors connected in parallel, the better the ripple mutual cancellation effect. As for the number of inductors L connected in parallel, it is set according to actual needs. But the number of these inductors L is at least 2. For example: when the number of inductors connected in parallel in the buck converter 1023 is 4, at this time, when the duty cycle of the multi-channel staggered parallel QSW topology is 0.25, 0.5 or 0.75, the ripple of the supply voltage output by the power supply 102 can be completely cancelled. If the duty cycle is not equal to the above value, only partial ripple cancellation can be achieved.

[0108] like Figure 2 As shown, the processor 101 and the power supply 102 can communicate with each other. In practical applications, the processor 101 includes a communication interface 1014. The power supply 102 includes a communication interface 1025 to realize communication between the processor 101 and the power supply 102. For example, the processor 101 and the power supply 102 are connected through a bus or a power line. The bus can be a power management bus (Power Management Bus, abbreviated as PMBus bus), which is an I2C (Inter-Integrated Circuit) bus. For example, the processor 101 communicates with the power supply 102 through the PMBus bus. At this time, the communication interface of the processor 101 and the communication interface of the power supply 102 are both PMBus interfaces.

[0109] The method provided in the embodiment of the present application can be implemented by any general purpose processor or application specific circuit (ASIC), etc. The following description is based on the application scenario of the vehicle-mounted processor applied to a vehicle. The following description is for understanding only and is not intended to be limiting.

[0110] Figure 3 1 is a system architecture diagram of a vehicle communication system provided by an embodiment of the present application. Figure 3 In the present invention, similar symbols identify similar components unless the context indicates otherwise. The illustrative system and method embodiments described herein are not intended to be limiting. It can be readily appreciated that certain aspects of the disclosed systems and methods can be arranged and combined in a variety of different configurations, all of which are contemplated herein.

[0111] like Figure 3 As shown, the vehicle communication system 10 includes a vehicle 12, one or more wireless carrier systems 14, a ground network 16, a computer 18, and a call center 20. It should be understood that the disclosed method can be used with any number of different systems and is not specifically limited to the operating environment shown here. Similarly, the architecture, construction, setup and operation of the communication system 10 and its individual components are generally known in the prior art. Therefore, the following paragraphs simply provide an overview of an example communication system 10, and other systems not shown herein can also use the disclosed method.

[0112] The vehicle 12 may be an unmanned vehicle or a manned vehicle. The vehicle 12 may be implemented on or in the form of an automobile. However, the example system may also be implemented on or in the form of other vehicles, such as cars, trucks, motorcycles, buses, boats, airplanes, helicopters, lawn mowers, snowplows, RVs, amusement park vehicles, agricultural equipment, construction equipment, trams, golf carts, trains, and trams. In addition, robotic devices may also be used to perform the methods and systems described herein.

[0113] exist Figure 32 shows some vehicle hardware 28. These vehicle hardware 28 include an information communication unit 30, a microphone 32, one or more buttons or other control inputs 34, an audio system 36, a visual display 38, and a GPS (Global Position System) module 40 and multiple VM modules 42 (Vehicle Security Module, abbreviated as VM here to distinguish from the VSM power supply in the previous text, and the Chinese name is the vehicle security unit). Some of these devices can be directly connected to the information communication unit, such as the microphone 32 and the button 34, while others use one or more network connections to achieve indirect connection, such as a communication bus 44 or an entertainment bus 46. Examples of suitable network connections include CAN (Controller Area Network), MOST (Media Oriented Systems Transport), LIN (Local Interconnect Network), LAN (Local Area Network), and other suitable connections, such as Ethernet or other connections that comply with known ISO (International Organization for Standardization), SAE (Society of Automotive Engineers) and IEEE (Institute of Electrical and Electronics Engineers) standards and regulations, to name just a few.

[0114] like Figure 3As shown, the information communication unit 30 can be an OEM (Original Equipment Manufacturer) installed (embedded) or aftermarket device that is installed in the vehicle and is capable of wireless voice and / or data communications over the wireless carrier system 14 and via wireless networking. This enables the vehicle to communicate with the call center 20, other vehicles enabled with information communication, or some other entity or device. The information communication unit preferably uses radio broadcasting to establish a communication channel (a voice channel and / or a data channel) with the wireless carrier system 14 so that voice and / or data transmissions can be sent and received over the channel. By providing voice and data communications, the information communication unit 30 enables the vehicle to provide a variety of different services, including those associated with navigation, telephone, emergency assistance, diagnostics, infotainment, etc. Data can be sent via a data connection (e.g., via packet data transmission on a data channel, or via a voice channel using techniques known in the art). For combined services including both voice communications (e.g., having a live advisor or voice response unit at the call center 20) and data communications (e.g., providing GPS location data or vehicle diagnostic data to the call center 20), the system can utilize a single call on a voice channel and switch between voice and data transmission on the voice channel as needed, which can be accomplished using techniques known to those skilled in the art. In addition, data can be sent and received using a short message service SMS (e.g., PDP (Packet Data Protocol)); the information communication unit can be configured as mobile terminated and / or originated, or configured as application terminated and / or originated.

[0115] The information communication unit 30 described above utilizes cellular communication according to the GSM (Global System for Mobile Communication) or CDMA (Code Division Multiple Access) standards, and therefore includes a cellular chipset 50 (standard cellular chipset) for voice communication (e.g., hands-free calling), a wireless modem for data transmission, a processing device 52, one or more digital memories 54, and dual antennas 56. It should be understood that the modem can be implemented by software stored in the information communication unit and executed by the processing device 52, or it can be a separate hardware component located inside or outside the information communication unit 30. The modem can operate using any number of different standards or protocols (e.g., EVDO (CDMA20001xEV-DO, EVDO), CDMA, GPRS (General Packet Radio Service, General Packet Radio Service Technology) and EDGE (Enhanced Data Rate for GSMEvolution, Enhanced Data Rate GSM Evolution Technology)). Wireless networking between vehicles and other networked devices can also be performed using the information communication unit 30. To this end, the information communication unit 30 can be configured to communicate wirelessly according to one or more wireless protocols (e.g., any of the IEEE 802.11 protocols, WiMAX (Worldwide Interoperability for Microwave Access), or Bluetooth). When used for packet-switched data communications such as TCP / IP (Transmission Control Protocol / Internet Protocol), the information communication unit can be configured with a static IP address, or can be set to automatically receive an assigned IP address from another device on the network (e.g., a router) or from a network address server.

[0116] The above-mentioned processing device 52 is an on-board processor. The processing device 52 can be any type of device capable of processing electronic instructions, including a microprocessor, a microcontroller, a main processor, a controller, a vehicle communication processor, and an ASIC (Application Specific Integrated Circuit). It can be a dedicated processor used only for the information communication unit 30 or can be shared with other vehicle systems. The processing device 52 executes various types of digital storage instructions, such as software or firmware programs stored in the memory 54, which enables the information communication unit to provide a wider variety of services. Specifically, the processing device 52 can execute programs or process data to execute at least a portion of the method discussed herein. The processing device 52 can be an electronic device to which the method of the present application is applied.

[0117] The information communication unit 30 described above can be used to provide a different range of vehicle services, including wireless communications with other parts of the vehicle. Such services include: turn-by-turn direct 1ns and other navigation-related services provided in conjunction with the GPS-based vehicle navigation module 40; airbag deployment notifications and other emergency or roadside assistance-related services provided in conjunction with one or more collision sensor interface modules (such as the main body control module (not shown)). Diagnostic reports using one or more diagnostic modules. And information entertainment-related services, in which music, web pages, movies, television programs, video games and / or other information are downloaded by the information entertainment module and stored for current or later playback. The services listed above are by no means an exhaustive list of all capabilities of the information communication unit 30, but are merely an enumeration of some of the services that the information communication unit can provide. In addition, it should be understood that at least some of the above modules can be implemented in the form of software instructions stored inside or outside the information communication unit 30, they can be hardware components located inside or outside the information communication unit 30, or they can be integrated and / or shared with each other, or with other systems located throughout the vehicle, which only lists a few possibilities. When the VM modules 42 are located outside the telematics unit 30 and are in operation, they can exchange data and commands with the telematics unit 30 using the vehicle bus 44 .

[0118] The GPS module 40 receives radio signals from GPS satellites 60. From these signals, the GPS module 40 can determine the location of the vehicle, which is used to provide navigation and other location-related services to the vehicle driver. Navigation information can be presented on the display 38 (or other displays in the vehicle) or can be presented in words, such as when providing turn-by-turn navigation. Navigation services can be provided using a navigation module in a dedicated vehicle (which can be a part of the GPS module 40), or some or all of the navigation services can be completed via the information communication unit 30, where the location information is sent to a remote location to provide navigation maps, map annotations (points of interest, restaurants, etc.), route calculations, etc. for the vehicle. The location information can be provided to the call center 20 or other remote computer systems, such as computer 18, for other purposes, such as fleet management. And, new or updated map data can be downloaded to the GPS module 40 from the call center 20 via the information communication unit 30.

[0119] In addition to the audio system 36 and the GPS module 40, the vehicle 12 can include other vehicle safety modules in the form of electronic hardware components, namely VM modules 42, which are located throughout the vehicle, typically receive input from one or more sensors, and use the sensed input to perform diagnostics, monitoring, control, reporting and / or other functions. Each of the VM modules 42 is preferably connected to the VM module 42 via a communication bus 44, is also connected to the information communication unit 30, and can be programmed to run vehicle system and subsystem diagnostic tests. For example, one VM module 42 can be an ECM (Engine Control Module) that controls various aspects of engine operation (e.g., fuel ignition and ignition timing), another VM module 42 can be a powertrain control module that regulates the operation of one or more components of the vehicle's powertrain, and another VM module 42 can be a body control module that manages various electrical components located throughout the vehicle (such as the vehicle's power door locks and headlights). According to one embodiment, the engine control module is equipped with an OBD (On Board Diagnostics) feature that provides a large amount of real-time data, such as data received from various sensors (including vehicle emission sensors), and provides a standardized series of diagnostic trouble codes that allow technicians to quickly identify and repair faults within the vehicle. As those skilled in the art will appreciate, the VM modules mentioned above are only examples of some modules that can be used within the vehicle 12, and many other modules are possible.

[0120] The vehicle hardware 28 (also referred to as vehicle electronics) also includes a plurality of vehicle user interfaces that provide a means for providing and / or receiving information to the vehicle driver and passenger, including a microphone 32, a button 34, an audio system 36, and a visual display 38. As used herein, the term "vehicle user interface" broadly includes any suitable form of electronic equipment, including hardware and software components, that is located on the vehicle and enables the vehicle user to communicate with or through the components of the vehicle. The microphone 32 provides audio input to the information communication unit to enable the driver or other driver and passenger to provide voice commands and perform hands-free calls via the wireless carrier system 14. For this purpose, it can be connected to an onboard automated voice processing unit that utilizes HMI (Human Machine Interface) technology known in the art. The button 34 allows manual user input to the information communication unit 30 to initiate a wireless telephone call and provide other data, response or control input. Separate buttons can be used to initiate emergency calls and conventional service assistance calls to the call center 20. The audio system 36 provides audio output to the vehicle occupants and can be a dedicated stand-alone system or part of the main vehicle audio system. According to the specific embodiment shown here, the audio system 36 is operably connected to the vehicle bus 44 and the entertainment bus 46 and can provide AM (Amplitude Modulation), FM (Frequency Modulation) and satellite radio, DVD (Digital Versatile Disc) and other multimedia functions. This functionality can be provided in conjunction with the infotainment module described above or provided independently. The visual display 38 is preferably a graphical display, such as a touch screen on the instrument panel or a heads-up display reflected from the windshield, and can be used to provide a variety of input and output functions. Various other vehicle user interfaces can also be utilized, as Figure 3 The interface in is just an example of a specific implementation.

[0121] Wireless carrier system 14 is preferably a cellular telephone system, including a plurality of cell towers 70 (only one is shown), one or more MSCs (Mobile Switching Centers) 72, and any other networking components required to connect wireless carrier system 14 to land network 16. Each cell tower 70 includes transmit and receive antennas and a base station, with base stations from different cell towers connected to MSC 72 directly or via an intermediate device (e.g., a base station controller). Wireless carrier system 14 may implement any suitable communication technology, including, for example, analog technology (e.g., AMPS (Advanced Mobile Phone System)) or newer digital technology (e.g., CDMA (e.g., CDMA2000) or GSM / GPRS). As will be appreciated by those skilled in the art, a variety of cell tower / base station / MSC arrangements are possible and may be used with wireless carrier system 14. For example, the base stations and cell towers can be co-located in the same location, or they can be located remotely from each other, each base station can respond to a single cell tower or a single base station can serve each cell tower, and each base station can be connected to a single MSC, to name just a few of the possible arrangements.

[0122] In addition to using wireless carrier system 14, different wireless carrier systems in the form of satellite communications can be used to provide one-way or two-way communications with the vehicle. This can be accomplished using one or more communication satellites 62 and uplink transmission stations 64. One-way communications can be, for example, a satellite broadcast service, where program content (news, music, etc.) is received by transmission station 64, packaged for upload, and then sent to satellite 62, which broadcasts the programs to users. Two-way communications can be, for example, a satellite telephone service that uses satellite 62 to relay telephone communications between vehicle 12 and station 64. If used, such a satellite phone can be added to wireless carrier system 14 or used in place of wireless carrier system 14.

[0123] The ground network 16 may be a conventional land-based radio communication network that is connected to one or more fixed telephones and connects the wireless carrier system 14 to the call center 20. For example, the ground network 16 may include a PSTN (Public Switched Telephone Network), such as a PSTN used to provide wired telephones, packet-switched data communications, and Internet infrastructure. One or more parts of the ground network 16 can be implemented using standard wired networks, optical fibers or other optical networks, cable networks, power lines, other wireless networks (e.g., WLAN (Wireless Local Area Networks), or networks that provide BWA (Broadband Wireless Access) and any combination thereof. The ground network 16 may also include one or more SMSCs (Short Message Service Centers) for storing, uploading, converting, and / or transmitting SMS (Short Message Service) between senders and receivers. For example, the SMSC may receive SMS messages from the call center 20 or a content provider (e.g., an external short message entity or ESME), and the SMSC may transmit the SMS messages to the vehicle 12 (e.g., a mobile terminal device). SMSCs and their functions are known to those skilled in the art. In addition, call center 20 need not be connected via land network 16, but may include wireless telephone equipment so that it can communicate directly with a wireless network (eg, wireless carrier system 14).

[0124] Computer 18 can be one of a plurality of computers, and these plurality of computers can be accessed via a private or public network (such as the Internet). Each such computer 18 can be used for one or more purposes, such as a vehicle can access a web server via an information communication unit 30 and a wireless carrier system 14. Other such accessible computers 18 can be, for example: a service center computer, where diagnostic information and other vehicle data can be uploaded from the vehicle via an information communication unit 30; a client computer used by a vehicle owner or other user for purposes such as: accessing or receiving vehicle data, or setting or configuring user parameters, or controlling the functions of the vehicle; or a third party library, whether by communicating with the vehicle 12 or the call center 20, or communicating with both, vehicle data or other information is provided to or from the third party library. Computer 18 can also be used to provide an Internet connection, such as a DNS (Domain Name Server, domain name server) service, or as a network address server that uses DHCP (Dynamic host configuration protocol, dynamic host configuration protocol) or other suitable protocols to assign IP addresses to the vehicle 12.

[0125] The call center 20 is designed to provide a variety of different system back-end functions to the vehicle hardware 28, and according to the exemplary embodiment shown here, the call center 20 generally includes one or more switches 80, servers 82, databases 84, live advisors 86, and VRS (Automatic voice response system) 88, all of which are known in the art. These various call center components are preferably connected to each other via a wired or wireless local area network 90. ​​The switch 80 can be a PBX (Private branch exchange) that routes incoming signals so that voice transmissions are typically sent to the live advisor 86 via a regular telephone or to the automatic voice response system 88 using VoIP. The live advisor phone can also use VoIP (Voice over Internet Phone, network voice phone service), such as Figure 380 and the network 90. ​​The VoIP and other data communications through the switch 80 are implemented via a modem (not shown) connected between the switch 80 and the network 90. ​​The data transmission is passed to the server 82 and / or the database 84 via the modem. The database 84 can store account information, such as user authentication information, vehicle identifiers, profile records, behavior patterns, and other relevant user information. The data transmission can also be performed by a wireless system, such as 802.11x, GPRS, etc. In addition, the short message service (SMS) can be used to send and / or receive data (e.g., PDP); and the call center 20 can be configured to be mobile terminated and / or originated, or configured to be application terminated and / or originated. Although the illustrated embodiment has been described as it will be used with a manned call center 20 using a live advisor 86, it will be understood that the call center can instead use VRS 88 as an automated advisor, or a combination of VRS 88 and live advisor 86 can be used.

[0126] At present, for unmanned vehicles, the processing equipment is required to have high computing power and high reliability. The vehicle-mounted ambient temperature of unmanned vehicles is high (for example, the internal ambient temperature of the car center console can reach 85 degrees), and the high computing power and high power consumption of the autonomous driving processor itself generate heat, and the processor core temperature rises sharply, limiting the further improvement of the processor computing power. In order to ensure that the core temperature of the processor in the processing equipment is not too high under high computing power operation, in addition to improving the cooling system capacity, it is more important to effectively reduce the power consumption of the processor through power reduction technology. The relevant technology can only reduce power consumption when the processor is under low load. When the processor load is relatively high, in order to ensure the processing speed of the processor, the power consumption of the processor is still difficult to reduce. Therefore, the chip integration of the processor in the relevant technology cannot be further improved, and the further application of Turbo technology in the processor is limited, resulting in the inability to further improve the performance of the processor. Not only that, because when the processor load is relatively high, the processor generates a lot of heat when it runs, and the cooling system is required to cool the processor, which further increases the cooling cost of the processor. For example: when the energy consumption of the data center increases, a cooling system with relatively high cooling performance is required to cool the data center. Another example: Due to high energy consumption, the standby time of terminal equipment is reduced and it cannot work for a long time.

[0127] In order to solve the above situation, an embodiment of the present application provides a voltage regulation method. The steps performed by the processor in the method provided in the embodiment of the present application can also be performed by a chip applied to the processor, and the steps performed by the power supply can also be performed by a chip applied to the power supply. The following embodiments take the processor and the power supply as the execution subjects respectively as examples.

[0128] Figure 4FIG. 1 is a flow chart of a voltage regulation method provided in an embodiment of the present application. Figure 4 As shown, an embodiment of the present application provides a voltage regulation method. The method is applied to an electronic device having a processor and a power supply. The power supply can supply power to the processor. The method includes:

[0129] Step 101: The processor sends power supply adjustment information to the power supply according to the main frequency of the next period. The power supply adjustment information includes the set power supply voltage V of the main frequency of the next period, which is defined as the set power supply voltage determined by the processor according to the main frequency of the next period when the processor runs at a certain main frequency. Generally, a single DVFS technology can be used to determine it. That is, based on the main frequency of the next period, the set power supply voltage corresponding to the main frequency of the next period is found from the correspondence between the main frequency of the processor and the set power supply voltage.

[0130] The duration of the next time period can be in minutes according to actual conditions. Exemplarily, the duration of the next time period is 10ms to 50ms. For example, the duration of the next time period is 50ms. In practical applications, the main frequency of the next time period refers to the main frequency predicted based on the current main frequency. That is, before step 101, step 100 should also be included: the processor predicts the main frequency of the next time period based on the current load.

[0131] Exemplarily, the processor collects the current load in real time, predicts the load of the next period based on the collected current load, and determines the main frequency of the next period based on the load of the next period. The current load can be processor occupancy, application execution volume or task volume, etc.

[0132] For example, a corresponding relationship table between load and main frequency is stored in the built-in memory of the motherboard or processor. In the corresponding relationship table between load and main frequency, a load corresponding to a certain interval of the same main frequency can be set. At this time, according to the predicted load of the next period, the load interval of the predicted load of the next period is first determined in the corresponding relationship table between load and main frequency, and then the main frequency of the next period is determined according to the load interval.

[0133] Another example: the main frequency switching information is stored in the built-in memory of the motherboard or processor. The preset main frequency is determined according to the predicted load of the next time period, and the main frequency of the next time period is found from the main frequency switching information according to the preset main frequency. In actual applications, the main frequency switching information includes multiple main frequency points, and the smallest main frequency point is selected from one or more main frequency points greater than the preset main frequency as the main frequency of the next time period. For example: the main frequency switching information includes multiple frequency points of 1.0GHz, 1.5GHz, and 2.0GHz. When the main frequency of the next time period is 1.3GHz, it means that the main frequency of the next time period should be switched to 1.5GHz. When the main frequency of the next time period is 1.7GHz, it means that the main frequency of the next time period should be switched to 2.0GHz.

[0134] Step 102: The power supply receives the power supply adjustment information sent by the processor. For example, if the processor and the power supply communicate via the PMBus bus, the power supply receives the power supply adjustment information via the PMBus interface.

[0135] Step 103: The power supply provides a power supply voltage V to the processor according to the set power supply voltage V of the main frequency of the next period and the set voltage slope R of the main frequency of the next period. out The voltage slope here refers to the supply voltage V as the load current of the power supply increases. out The rate of decrease is also called loadline value, which is measured in units of resistance. out As the load current of the power supply increases, it decreases. V min ≤V out ≤V,V min It is the minimum supply voltage for normal operation when the load current increases during the next period of main frequency operation. For example: V min It refers to the minimum supply voltage provided by the power supply to the processor when the load current increases to the maximum value. This minimum supply voltage allows the processor to operate normally.

[0136] In order to cooperate with the power supply constant voltage adjustment, the above method also includes: when the processor determines that the main frequency of the next time period is not equal to the current main frequency, the current main frequency is set equal to the main frequency of the next time period. The main frequency of the processor is actually the product of the external frequency and the multiplier. For example, the external frequency of a CPU is 100MHz, the multiplier is 8.5, and the main frequency of the CPU = external frequency × multiplier = 100MHz × 8.5 = 850MHz. It can be seen that the processor's main frequency can be adjusted by changing the processor's multiplier or external frequency. In addition, the method of adjusting the processor's main frequency should also be determined in combination with the processor model. For example: if the processor is an Intel CPU, since the Intel CPU prevents the modification of the multiplier, the main frequency of the Intel CPU can only be modified by modifying the external frequency. For another example: the CPU of Advanced Micro Devices, Inc. (AMD) can modify the multiplier, but modifying the multiplier does not improve the CPU performance as well as the external frequency.

[0137] For example, when switching the processor main frequency, the PLL inside the processor is used to adjust the clock multiplier so that the current main frequency of the processor is equal to the main frequency of the next period determined by the processor core.

[0138] When switching the processor main frequency, the timing of switching the processor main frequency needs to be determined according to the relationship between the current main frequency and the main frequency of the next period. Figure 5 As shown, when the processor determines that the main frequency of the next time period is not equal to the current main frequency, setting the current main frequency equal to the main frequency of the next time period includes:

[0139] Step 100a: The processor determines that the main frequency of the next time period is less than the current main frequency, sets the current main frequency equal to the main frequency of the next time period, and executes step 101.

[0140] Step 100b: the processor determines that the main frequency of the next time period is greater than the current main frequency, and executes step 101.

[0141] When the processor determines that the main frequency of the next time period is greater than the current main frequency, after step 103, the method further includes: step 104: the processor sets the current main frequency to be equal to the main frequency of the next time period.

[0142] In the method provided in the embodiment of the present application, the main frequency of the next period refers to the main frequency predicted according to the current main frequency, and the power supply voltage V provided to the processor by the power supply according to the set supply voltage V of the main frequency of the next period and the set voltage slope R of the main frequency of the next period out Adapt to the main frequency of the processor in the next period. In addition, since the load current has the characteristic of periodically increasing from the minimum load current to the maximum load current, when the power supply in the prior art outputs the load terminal voltage in a constant voltage manner, the load terminal voltage passively decreases during the process of increasing the load current. The method provided in the embodiment of the present application actively controls the supply voltage V output by the power supply out As the load current increases, it decreases, so that when the load current starts to increase, the supply voltage V out Actively decreases as the load current increases. At this time, the supply voltage V out Less than the set supply voltage V of the processor's main frequency in the next period and greater than or equal to the maximum load current. When the processor is running at the main frequency in the next period, the minimum supply voltage V for normal operation when the load current increases. min It can be seen that compared with the prior art, the power supply voltage V out The processor power consumption can be reduced while ensuring normal operation of the processor, thereby improving the processor performance. Moreover, since the higher the processor's main frequency, the higher the processor's load, the method provided in the embodiment of the present application can ensure that no matter how high or low the processor's load is, the power supply can supply power to the processor in a manner lower than the current main frequency setting supply voltage when the load current increases, thereby ensuring that the processor has low power consumption while operating normally.

[0143] It can be seen from the above that compared with the single DVFS technology to reduce the power consumption of the processor, the method provided in the embodiment of the present application can ensure the normal operation of the processor, and can not only reduce the power consumption of the processor when the load is light, but also reduce the power consumption of the processor when the load is heavy, thereby achieving global power consumption reduction, and then reducing the heat generation of the processor. Moreover, when the processor is under a relatively high load, the heat generation of the processor is relatively low. Therefore, the use of Turbo technology can further increase the main frequency and alleviate the application limitation problem of Turbo technology caused by the relatively high heat generation of the processor.

[0144] As a possible implementation, based on the fact that the power supply voltage output by the VRM power supply has the characteristic of linearly decreasing as the load current of the load line increases, the power supply voltage V out =VI*R, I is the load current of the power supply. It can be seen from the formula that the method of the embodiment of the present application is based on the DVFS technology in the prior art to reduce power consumption. Based on the characteristic that the voltage slope decreases as the load current increases, the product of the set voltage slope and the load current is used to fine-tune the power supply voltage determined by the DVFS technology, thereby achieving global power consumption reduction.

[0145] In addition, the above supply voltage V out It is determined by the set voltage slope R of the processor in the next period, the set power supply voltage V in the next period, and the load current I. Since the voltage slope refers to the speed at which the power supply voltage decreases as the load current of the power supply increases, the product of the set voltage slope R of the main frequency in the next period and the load current I is essentially: the active decrease of the power supply voltage when the load current of the power supply increases. As long as the active decrease is greater than or equal to the passive maximum decrease of the load terminal voltage when the load current increases in the prior art, the power supply voltage V out Always greater than or equal to the minimum supply voltage V for normal operation of the processor when the load current increases during the next period of operation. min .

[0146] When the power supply includes a VRM chip, a logic control circuit and a buck converter. The VRM chip can determine the reference voltage according to the set supply voltage V of the main frequency of the next period, and determine the voltage slope of the reference voltage according to the set voltage slope R of the main frequency of the next period. The VRM chip transmits the reference voltage and the voltage slope of the reference voltage to the logic control circuit. The logic control circuit outputs a variable voltage according to the reference voltage and the voltage slope of the reference voltage, and changes the voltage through the buck converter to output a supply voltage V that meets the processor operation requirements. out .

[0147] Figure 6 A schematic diagram of the power supply load transient process is shown. Figure 7A schematic diagram of the power supply loadline characteristics is shown. Figure 6 Medium V min The minimum supply voltage for the processor. max is the maximum value of the load current. Figure 6 and Figure 7 The principle that the power supply voltage of the present application method ensures the normal operation of the processor at a lower voltage is analyzed.

[0148] like Figure 6 As shown by the straight line a in , when the Loadline value = 0, it means that the power supply provides the power supply voltage to the processor in the form of a DC voltage, and the power supply voltage is not reduced, that is, the power supply voltage V0 does not change with the load current. Figure 7 Curve a in is the transient curve of load current. Figure 7 Curve b in the figure represents the transient response curve of the power supply voltage when Loadline value = 0. Figure 7 As shown in curves a and b in the figure, under the impact of load current, due to the insufficient capacitance at the output end of the buck converter, the power supply voltage provided by the power supply drops passively. The drop process lasts from several μs to tens of μs, and then gradually recovers to the DC voltage.

[0149] Specific, combined Figure 7 From the curves a and b in the figure, we can see that when the load current is at its minimum value, the supply voltage is V0 and remains constant. When the load current rises from the minimum value to the maximum value, the supply voltage passively drops from V0 to the minimum value V min , and then gradually rises. When the load current drops from the maximum value to the minimum value, the supply voltage quickly rises to the maximum value V max , and then gradually decreases until the supply voltage equals V0. During the whole process, the difference between the minimum and maximum supply voltage can reach V max -V min And, when the supply voltage drops passively from V0 to the minimum value V min The processor can still operate normally, so the passive maximum drop voltage of the supply voltage ΔV max =V0-V min .

[0150] like Figure 6 As shown by the oblique line b in the figure, when the Loadline value is greater than 0, it means that the DC voltage is actively and linearly reduced when the load current increases, and the voltage reduction slope is equal to the Loadline value. Figure 7 c in the figure is the transient response curve when the power supply voltage is at Loadline value > 0. Figure 7As shown in curve c in the figure, under the impact of load current, the power supply actively controls the supply voltage to drop. As long as the supply voltage drop amplitude ΔV is not lower than the passive maximum drop voltage ΔV of curve b, max , the processor can be guaranteed to work normally. It can be seen that the method provided by the embodiment of the present application can ensure the normal operation of the processor. If the supply voltage drop amplitude ΔV is less than the passive maximum drop voltage of curve b, the processor cannot work normally.

[0151] As can be seen from the above, in the method provided in the embodiment of the present application, as long as the load current is equal to the minimum value, the supply voltage V out =Equal to the set supply voltage V of the main frequency of the next period. When the load current increases, always keep R*I less than or equal to the passive maximum drop voltage of the set supply voltage V of the main frequency of the next period, so as to ensure that the supply voltage V out The minimum supply voltage greater than or equal to the main frequency of the next period.

[0152] In order to verify that the method provided in the embodiment of the present application can reduce the power consumption of the processor under heavy load, the following analysis is conducted in combination with the DVFS technology.

[0153] DVFS technology is a dynamic voltage and frequency adjustment technology that can reduce power consumption to a certain extent. It can reduce power consumption by reducing the operating voltage and operating frequency of the chip.

[0154] Take the chip as an example: the power consumption calculation formula of the chip is is the dynamic power consumption of the chip, V cc I LEAK is the static power consumption of the chip, V cc is the working voltage of the chip, f is the working frequency of the chip, I LEAK is the leakage current of the chip, α is the average flip rate of the circuit at the current operating frequency of the chip, and C is the capacitance of the load capacitor. It should be understood that the power consumption calculation formula of the chip is also applicable to processors or integrated circuits with information processing functions.

[0155] It can be seen from the power consumption calculation formula of the chip that the dynamic power consumption of the chip is related to the working voltage V cc The dynamic power consumption is in a quadratic relationship with the chip's operating frequency f, and when the chip's operating voltage V cc The higher the chip's operating frequency f, the higher the chip's dynamic power consumption. Therefore, DVFS technology can reduce power consumption by lowering the chip's supply voltage and operating frequency.

[0156] Figure 8 FIG. 4 is a schematic diagram showing the mechanism by which DVFS technology reduces power consumption. Figure 8 The timing a in is the voltage timing diagram; Figure 8The timing b in the figure is the main frequency timing diagram. Figure 8 As shown in FIG. 1 , when the processor load is light, the processor's main frequency and supply voltage are relatively low. When the processor load is heavy, the processor's main frequency and supply voltage are relatively high and at rated values.

[0157] Fig. 9 A comparison diagram of the method of the present application, the DVFS technology, and the fixed voltage method for power supply is shown, wherein the horizontal axis is the load current (which can be regarded as the maximum load current) and the vertical axis is the supply voltage. Fig. 9 The straight line a in FIG. 1 is a voltage variation diagram of the fixed voltage method. It can be seen from the straight line a that no matter how the main frequency of the processor changes, the power supply voltage of the processor is a fixed rated power supply voltage. Fig. 9 The broken line b in the figure is the voltage variation diagram when a single DVFS power supply is used. It can be seen from the broken line b that: in the low power consumption mode, the CPU main frequency is F1, and the CPU supply voltage is V11; in the rated mode, the CPU main frequency is F2, and the CPU supply voltage is V12; in the first overclocking mode, the CPU main frequency is F3, and the CPU supply voltage is V13; in the second overclocking mode, the CPU main frequency is F4, and the CPU supply voltage is supply voltage V14. Fig. 9 The broken line c in the figure is a voltage variation diagram of the power supply using the method of the present application. It can be seen from the broken line c that: in the low power consumption mode, the main frequency of the CPU is F1, and the power supply voltage of the CPU is V21; in the rated mode, the main frequency of the CPU is F2, and the power supply voltage of the CPU is V22; in the first overclocking mode, the main frequency of the CPU is F3, and the power supply voltage of the CPU is V23; in the second overclocking mode, the main frequency of the CPU is F4, and the power supply voltage of the CPU is V24. It should be understood that as the power consumption increases, the main frequency of the CPU also increases, so F1<F2<F3<F4.

[0158] Depend on Fig. 9 It can be seen that when a single DVFS power supply is used, V11<V12<V13<V14, and the CPU power supply voltage increases in a step-by-step manner as the main frequency and power consumption increase until it is equal to the power supply voltage V14. Fig. 9 The first shaded area P1 in the figure is the power consumption benefit area of ​​DVFS technology compared with the fixed voltage method. It can be seen that when the CPU main frequency is high, DVFS technology cannot reduce the power consumption of the CPU processor. It can be seen that DVFS technology can reduce the power consumption when the processor load is relatively light, but DVFS technology cannot reduce the power consumption when the processor load is relatively heavy.

[0159] When power is supplied using the method of the embodiment of the present application, V21<V22<V23<V24. Although the power supply voltage of the CPU increases in a step-by-step manner with the increase of the main frequency and power consumption, the power supply voltage in each power consumption mode is lower than the power supply voltage using the DVFS technology. Fig. 9 The second shaded area P2 in the figure is the power consumption benefit area compared with the DVFS technology. It has been verified that compared with the DVFS technology, the method of the embodiment of the present application can ensure that the overall power consumption benefit of the CPU is more than 10%.

[0160] It can be seen from the above that the method of the present application can further reduce the power consumption of the processor regardless of the main frequency. Therefore, compared with the DVFS technology, the method provided in the embodiment of the present application can not only further reduce the power consumption of the processor, but also enable the processor to operate normally at the lowest supply voltage in multiple power consumption modes such as low power consumption mode, rated mode, overclocking mode (first overclocking mode, second overclocking mode), thereby achieving full-domain power consumption reduction of the processor, thereby reducing the degree of processor heating under heavy load conditions, enabling the processor to operate at a higher main frequency or even overclocked, and improving processor performance.

[0161] As a possible implementation, the set supply voltage V of the main frequency in the next period may be provided by a processor, and the set voltage slope R of the main frequency in the next period may exist in the power supply or be provided by a processor.

[0162] When the processor only provides the power supply with a set supply voltage V of the main frequency for the next period, in practical applications, the stored set voltage slope may be stored in a storage medium of the electronic device or in a storage medium of the power supply.

[0163] Exemplarily, the above-mentioned set voltage slope exists in the power supply in the form of a constant voltage slope. The processor does not need to use the communication interface between the processor and the power supply to dynamically set the set voltage slope R of the main frequency of the next period in the power supply, thereby effectively reducing the communication delay and voltage regulation delay and improving the voltage regulation speed. For example, the above-mentioned processor sends power supply adjustment information to the power supply according to the main frequency of the next period, including:

[0164] Step 1011A: The processor searches for the set supply voltage V of the main frequency of the next time period from the target corresponding relationship according to the main frequency of the next time period.

[0165] Step 1012A: The processor sends the set supply voltage V of the main frequency of the next time period to the power supply.

[0166] After the processor queries the set supply voltage of the main frequency of the next period from the target corresponding relationship according to the main frequency of the next period, it is sent to the power supply through the PMBus interface of the processor, and the PMBus interface of the power supply receives the set supply voltage of the main frequency of the next period.

[0167] The above target corresponding relationship may be the corresponding relationship between the processor's main frequency, the set power supply voltage and the voltage slope. Of course, the target corresponding relationship may also be the corresponding relationship between the processor's main frequency and the set power supply voltage determined by using the DVFS technology.

[0168] In practical applications, the power supply stores the set voltage slope R of the main frequency in the next period in the form of a constant voltage slope. The constant voltage slope is the minimum voltage slope R allowed by the processor at each main frequency set supply voltage. min , R min >0. Due to R min >0, it can ensure that when the processor is working at any load or main frequency, the power supply can always provide the processor with a power supply voltage less than or equal to the set power supply voltage, so that the processor has lower energy consumption. In addition, when the constant voltage slope is the set voltage slope R of the main frequency of the next period, the product of the set voltage slope of the main frequency of the next period and the load current can be controlled to ensure the normal operation of the processor, and avoid the situation that when the constant voltage slope is large, the processor will not be able to operate normally under the power supply voltage V when the load current increases. out Failure to operate normally occurs.

[0169] When the processor provides the power supply with the set supply voltage V of the main frequency of the next period and the set voltage slope R of the main frequency of the next period, the power supply adjustment information also includes the set voltage slope R of the main frequency of the next period. At this time, the processor sends the power supply adjustment information to the power supply according to the main frequency of the next period, including:

[0170] Step 1011B: the processor searches for the set supply voltage V of the main frequency of the next period and the set voltage slope R of the main frequency of the next period from the target corresponding relationship according to the main frequency of the next period.

[0171] Step 1012B: the processor sends the set supply voltage V of the main frequency for the next period and the set voltage slope R of the main frequency for the next period to the power supply.

[0172] After the processor queries the set supply voltage of the main frequency of the next period and the set voltage slope of the main frequency of the next period from the target correspondence according to the main frequency of the next period, it sends them to the power supply through the PMBus interface of the processor, and the PMBus interface of the power supply receives the set supply voltage of the main frequency of the next period and the set voltage slope of the main frequency of the next period.

[0173] In actual applications, the processor sends the set supply voltage of the main frequency of the next period to the power supply in the form of VID code, uses 8 to 16 bits of data as the set voltage slope of the next period, and sends the set supply voltage of the main frequency of the next period and the set voltage slope of the next period to the power supply. For VID code, it can be directly transmitted in the VID code used in DVFS technology. For 8 to 16 bits of data, after the power supply receives 8 to 16 bits of data, it can obtain the set voltage slope of the next period after simple data processing. For example: when the power supply includes a VRM chip, a logic control circuit and a buck converter, the VRM chip can determine the set supply voltage V of the main frequency of the next period and the set voltage slope R of the main frequency of the next period according to the VID code and 8 to 16 bits of data. At this time, the set supply voltage V of the main frequency of the next period is used as the reference voltage, and the set voltage slope R of the main frequency of the next period is used as the voltage slope of the reference voltage. The VRM chip sends the reference voltage and the voltage slope of the reference voltage to the logic control circuit. The logic control circuit adjusts the voltage according to the reference voltage and the voltage slope of the reference voltage, and converts the voltage through the buck converter to obtain the supply voltage V out , and then use the power interface of the power supply to supply power to the processor.

[0174] The above target correspondence is the correspondence between the processor's main frequency, the set power supply voltage and the set voltage slope, wherein the set voltage slopes of all main frequencies may be completely different, or may be partially equal or completely equal.

[0175] When the set voltage slopes of all main frequencies are completely different or partially equal, the set voltage slope of the processor at each main frequency is the voltage slope allowed by the set power supply voltage of the processor at each main frequency. At this time, the set voltage slope of each main frequency in the above target correspondence is the voltage slope allowed by the set power supply voltage of the processor at each main frequency. The power supply voltage V determined by the power supply out Under the condition that the normal operation of the processor is satisfied, the power consumption of the processor is optimized. Table 1 shows the target correspondence when the voltage slope of the CPU is equal at some main frequencies. It should be understood that the power consumption mode shown in Table 1 is only an example, and in actual applications, there may be other various power consumption modes.

[0176] Table 1 Target correspondence of equal voltage slopes for some main frequencies

[0177]

[0178] As shown in Table 1, when the main frequency of the CPU in the next period is 1.5GHz, the set supply voltage V of the main frequency in the next period that the CPU searches for is 1.1V, and the set operating voltage slope R of the main frequency in the next period is 0.1mOhm. At this time, the CPU sets the reference voltage in the power supply to 1.0V through communication interfaces such as PMBus, and the voltage slope of the reference voltage is 0.1mohm. When the main frequency of the CPU in the next period is 2.5GHz, the set supply voltage V of the main frequency in the next period that the CPU searches for is 1.2V, and the set operating voltage slope R of the main frequency in the next period is 0.2mOhm. At this time, the CPU sets the reference voltage in the power supply to 1.2V through communication interfaces such as PMBus, and the voltage slope of the reference voltage is 0.2mOhm.

[0179] When the set voltage slopes of all main frequencies are completely equal, the set voltage slope needs to be applicable to the supply voltage regulation at all main frequencies. In other words, the set voltage slopes of the processor at all main frequencies are equal to the constant voltage slope. At this time, the set voltage slopes corresponding to all main frequencies in the above target correspondence are equal to the constant voltage slope. The constant voltage slope is applicable to the supply voltage regulation of various main frequencies, which is the minimum voltage slope R allowed by the processor at each main frequency. min , R min >0. For example: R selected from Table 1 min =0.1mOhm. When all the set voltage slopes in Table 1 are set to 0.1mOhm, the target corresponding relationship of equal set voltage slopes of all main frequencies shown in Table 2 can be obtained. It should be understood that the power consumption modes shown in Table 2 are only examples, and in actual applications, there may be various other power consumption modes.

[0180] Table 2 Target correspondence of equal voltage slopes for all main frequencies

[0181]

[0182] The set voltage slope in Table 2 can be saved in advance in the register of the power supply of the electronic device. At this time, the power supply adjustment information provided by the processor may only contain the set supply voltage V of the main frequency of the next time period. Of course, if the set voltage slope is not saved in advance in the register of the power supply of the electronic device, then after the processor provides the set supply voltage V of the main frequency of the next time period and the set voltage slope R of the main frequency of the next time period to the power supply for the first time, the power supply can save the set voltage slope R of the main frequency of the next time period in the storage medium of the electronic device or in the register of the power supply in the form of a constant voltage slope. For example: statically configure the set voltage slope R of the main frequency of the next time period to the register at one time. Since the set voltage slopes of all main frequencies in the target correspondence are equal to the constant voltage slope, the power supply actually saves the set voltage slopes of all main frequencies in the target correspondence in the form of a constant voltage slope.

[0183] After this, the power supply needs to regulate the supply voltage V to the processor again. out When the power supply is in operation, the processor only needs to dynamically set the reference voltage inside the power supply through the communication interface, thereby reducing the communication delay and the voltage regulation delay, and shortening the voltage regulation time. For example: when the voltage slope set in Table 2 is not saved in the power supply, when the CPU's main frequency in the next period is 1.5GHz, the set supply voltage of the main frequency in the next period determined by the CPU is 1.1V, and the set operating voltage slope R of the main frequency in the next period is 0.1mOhm. The CPU sets the reference voltage in the power supply to 1.0V and the voltage slope of the reference voltage to 0.1mohm through communication interfaces such as PMBus. When the power supply saves the set voltage slope in Table 2 in the form of a constant voltage slope, the CPU only needs to query the set supply voltage V of the main frequency in the next period to 1.1V from the target correspondence shown in Table 2 according to the main frequency in the next period, and set the reference voltage in the power supply to 1.1V through communication interfaces such as PMBus, and the power supply provides the processor with a power supply voltage V according to the set voltage slope of 0.1mohm and the reference voltage of 1.1V. out .

[0184] Another example: When the voltage slope set in Table 2 is not saved in the power supply, and the main frequency of the CPU in the next period is 2.5GHz, the set supply voltage V of the main frequency in the next period found by the CPU is 1.2V, and the set operating voltage slope R of the main frequency in the next period is 0.1mOhm. The CPU sets the reference voltage in the power supply to 1.2V through communication interfaces such as PMBus, and the voltage slope of the reference voltage is 0.1mohm. In the case where the power supply saves the voltage slope set in Table 2 in the form of a constant voltage slope, the CPU only needs to determine that the set supply voltage V of the main frequency in the next period is 1.2V, and set the reference voltage in the power supply to 1.2V through communication interfaces such as PMBus, and the power supply provides the processor with a power supply voltage V according to the set voltage slope of 0.1mohm and the reference voltage of 1.2V. out .

[0185] It should be noted that when the set voltage slope R of the main frequency in the next period exists in the power supply in the form of a constant voltage slope, the target correspondence relationship may be the target correspondence relationship shown in Table 1 and Table 2, or the correspondence relationship between the main frequency and the set supply voltage shown in Table 3. It should be understood that the power consumption mode shown in Table 3 is only an example, and in actual applications, there may be other various power consumption modes.

[0186] Table 3 Correspondence between main frequency and set supply voltage

[0187] model Main frequency (GHz) Set the supply voltage (unit: V) Low Power Mode 0.5 0.9 Rated mode 1.5 1.1 First overclocking mode 2.5 1.2 Second overclocking mode 3.0 1.3

[0188] The correspondence between the main frequency and the set power supply voltage shown in Table 3 can directly refer to the correspondence between the main frequency and the set power supply voltage of the processor used in the DVFS technology in the prior art. Of course, it can also be reconstructed by the user.

[0189] It should be noted that when the above target correspondence is the correspondence between the processor's main frequency, the set power supply voltage, and the set voltage slope, regardless of whether the set voltage slope in the target correspondence is completely equal, it is stored in a storage medium in one of the following ways. The storage medium includes but is not limited to the BIOS memory of the motherboard or the built-in memory of the processor.

[0190] The first storage method: the target correspondence is stored in a storage medium in the form of a correspondence between the processor's main frequency, the set power supply voltage, and the set voltage slope, or a correspondence table.

[0191] The second saving method: The target correspondence relationship actually includes two sub-correspondence relationships. For example, the two sub-correspondence relationships include the correspondence relationship between the main frequency of the processor and the set power supply voltage, and the correspondence relationship between the main frequency of the processor and the set voltage slope. For another example, the two sub-correspondence relationships include the correspondence relationship of the set voltage slope and the correspondence relationship of the set power supply voltage, and the correspondence relationship between the main frequency of the processor and the set power supply voltage of the processor. For another example, the two sub-correspondence relationships include the correspondence relationship of the set voltage slope and the correspondence relationship of the set power supply voltage, and the correspondence relationship between the main frequency of the processor and the set voltage slope of the processor.

[0192] As a possible implementation manner, the above target correspondence relationship may be stored in a storage medium before or after leaving the factory.

[0193] After the electronic device leaves the factory, the target correspondence or the relationship table formed by the target correspondence is measured and stored in the storage medium. It should be understood that after the electronic device leaves the factory, the performance of the processor inside the electronic device is determined. Therefore, after the electronic device leaves the factory, the target correspondence obtained by directly debugging the electronic device is the target correspondence of the processor in the electronic device where the storage medium is located. At this time, the target correspondence is best compatible with the processor included in the electronic device.

[0194] For another example: before the electronic device leaves the factory, the target correspondence or the relationship table formed by the target correspondence is stored in a storage medium.

[0195] In practical applications, for processors with different performances, if the same target correspondence is used, there will be a problem that the target correspondence does not match the processor included in the electronic device. In the case of mass production, it should be ensured that the target correspondence stored in the storage medium before leaving the factory has a wide range of applicability, so that different processors can use the same target correspondence. For example: the above target correspondence is the target correspondence of the benchmark processor. The benchmark processor is the processor with the largest minimum power supply voltage at the same main frequency among multiple processors. At this time, the benchmark processor is the processor with the worst performance among multiple processors. If multiple processors are measured using a CPM circuit, it will be found that when multiple processors work at the same main frequency, the CPM circuit corresponding to the benchmark processor has the longest delay time and the highest oscillation frequency. At this time, the target correspondence of the benchmark processor can be applied to any processor among multiple processors. Therefore, when the target correspondence of the benchmark processor is used as the target correspondence, the target correspondence has a wide range of applicability. It should be understood that the minimum power supply voltage of each processor working at a given main frequency can determine the performance of the processor. For processors or chips with good performance, the minimum power supply voltage working at a given main frequency is relatively low, and for processors or chips with relatively poor performance, the minimum power supply voltage working at a given main frequency is relatively high. The performance differences between different processors are mainly caused by the process or aging of the processor. For the same model of processor, there may be differences between different batches of processors.

[0196] The following examples illustrate the classification of various processors and the selection principle of benchmark processors. The following description is for explanation only and is not intended to be limiting.

[0197] The processor or chip with relatively poor performance is defined as a slow chip, and the processor or chip with relatively good performance is defined as a slow chip. Taking into account the differences in various aspects between the extreme fast chip (the best performance fast chip) and the extreme slow chip (the worst performance slow chip) (such as aging differences and process deviation differences), all processors between the extreme fast chip and the extreme slow chip are divided into n processor gears. A processor can be selected from each processor gear as the gear processor. The lowest power supply voltage of the n gear processors is measured at a given main frequency (such as 0.9GHz to 1.5GHz), and a processor or chip with the smallest lowest power supply voltage is selected as the benchmark processor, and then the target correspondence of the benchmark processor is measured and stored in a storage medium.

[0198] It should be noted that the slow film can be one type or multiple types. When there are multiple types of slow films, the differences between the multiple slow films are mainly reflected in the differences in process. Similarly, the fast film can be one type or multiple types. When there are multiple types of fast films, the differences between the multiple fast films are mainly reflected in the differences in process.

[0199] In view of the differences between the processor included in the electronic device and the benchmark processor (in terms of process, performance, etc.), if the target correspondence of the benchmark processor is directly used to search for the set supply voltage V of the main frequency in the next period and the set voltage slope R of the main frequency in the next period, although the processor power consumption can still be reduced to a certain extent, the search result has a large deviation, resulting in unsatisfactory power consumption reduction effect and reliability.

[0200] In order to ensure that the target correspondence relationship has good compatibility with the processor included in the electronic device, the reference processor should be calibrated. For example, the reference processor is calibrated using the AVS technology. Specifically, Fig.10 As shown, before the processor searches for the set supply voltage of the main frequency of the next time period from the target corresponding relationship according to the main frequency of the next time period, the method further includes:

[0201] Step 100c: The processor calibrates the target correspondence according to the performance difference information so that the calibrated target correspondence matches the processor included in the electronic device. The performance difference information is measured by the CPM circuit. According to different characterization methods of the performance difference information, the performance difference information may be a delay level such as a delay time or an oscillation frequency. According to the source of the difference, the performance difference information is process performance difference information, operating temperature performance difference information or aging performance difference information. For example: for the same batch of processors, due to process differences, the minimum supply voltage at a given main frequency is different. For another example: at a given main frequency, the minimum supply voltage of the same processor in different temperature ranges is different. For another example: at a given main frequency, the minimum supply voltage of the same processor at different aging degrees is different.

[0202] In order to assist the processor in calibrating the target correspondence relationship without considering the temperature difference, the storage medium should also pre-store the correspondence relationship between the performance differences of multiple processors and the minimum supply voltage difference without considering the temperature difference. For the convenience of description, the correspondence relationship between the performance differences of multiple processors and the minimum supply voltage difference is referred to as the correspondence relationship of multiple processor differences below.

[0203] In the correspondence relationship between the differences of multiple processors, the performance difference of each processor can be represented by the delay level (such as delay time) or oscillation frequency of the processor, or can be indirectly represented by the delay difference or oscillation frequency difference between the processor and the reference processor at the same voltage. The minimum supply voltage difference corresponding to the performance difference of each processor refers to the minimum supply voltage difference between the processor and the reference processor at the same main frequency.

[0204] Without considering the influence of temperature, the performance difference information detected by the CPM circuit, the processor calibrating the target correspondence relationship according to the performance difference information so that the target correspondence relationship matches the processor includes:

[0205] The processor searches for the lowest power supply voltage difference from a plurality of processor difference correspondences according to the performance difference information, and calibrates the set power supply voltage corresponding to each main frequency in the target correspondence according to the lowest power supply voltage difference, so that the calibrated target correspondence matches the processor included in the electronic device. Since the performance difference information can reflect the current state (such as performance, aging degree, process deviation, use environment, etc.) of the processor included in the electronic device, the processor searches for the lowest power supply voltage difference from a plurality of processor difference correspondences according to the performance difference information, which can ensure that after the processor calibrates the set power supply voltage of each main frequency included in the target correspondence according to the lowest power supply voltage difference, the target correspondence matches the processor included in the electronic device better.

[0206] In the case of considering the influence of temperature, in order to cooperate with the processor to calibrate the target correspondence, the storage medium should also pre-store the correspondence between the performance difference and the minimum supply voltage difference of the various processors at multiple temperature levels. For the convenience of description, the correspondence between the performance difference and the minimum supply voltage difference of the various processors at multiple temperature levels is referred to as the difference correspondence between the various processors at multiple temperature levels.

[0207] In the case of considering the temperature effect, the performance difference information detected by the CPM circuit, and the processor calibrating the target correspondence relationship according to the performance difference information so that the target correspondence relationship matches the processor included in the electronic device include:

[0208] The processor searches for a correspondence between the performance difference and the minimum power supply voltage difference of multiple processors at a temperature level where the current temperature is located from the correspondence between the performance difference and the minimum power supply voltage difference of multiple processors at multiple temperature levels according to the current temperature; searches for a minimum power supply voltage difference that matches the current performance difference information from the correspondence between the performance difference and the minimum power supply voltage difference of multiple processors at a temperature level where the current temperature is located according to the performance difference information; calibrates the set power supply voltage corresponding to each main frequency in the target correspondence according to the minimum power supply voltage difference that matches the performance difference information, so that the calibrated target correspondence matches the processor included in the electronic device, so as to take the influence of the current temperature on the target correspondence into account, thereby further improving the matching of the target correspondence with the processor included in the electronic device.

[0209] The difference correspondences of multiple processors at multiple temperature levels can be divided into n temperature level difference correspondences of multiple processors according to the operating temperature, and the difference correspondences of multiple processors at each temperature level include the difference correspondences of multiple processors at the temperature level. Of course, the target correspondences of multiple processors can also be divided into n processor level difference correspondences according to different processor levels; the difference correspondences of multiple processors at each processor level include the difference correspondences of the processors at the processor level at multiple temperature levels.

[0210] For the same processor, the performance difference information measured by the CPM circuit built into the processor will be different when the operating temperature is different. If the influence of temperature on the performance difference information is not considered, the accuracy of the minimum power supply voltage difference deviation found is not very high. For example: when the storage medium stores the difference correspondence between multiple processors measured at 25°C and the target correspondence between the benchmark processor, when the electronic device is powered on after leaving the factory, the CPM circuit built into the processor measures the performance difference information at 45°C. Based on the performance difference information measured at 45°C, the deviation of the minimum power supply voltage difference found from the difference correspondence between multiple processors measured at 25°C is relatively large.

[0211] If the effect of temperature on the performance difference information is taken into account, the accuracy of the deviation of the minimum power supply voltage difference found is relatively high. For example: when the storage medium stores the difference correspondence between multiple processors at multiple temperature levels (including 45°C) and the target correspondence between the benchmark processor, when the electronic device is powered on after leaving the factory, the CPM circuit built into the processor measures the performance difference information at 45°C, so that compared with the solution that does not consider the effect of temperature on the performance difference information, the deviation of the minimum power supply voltage difference found from multiple processors at multiple temperature levels (including 45°C) based on the performance difference information measured at 45°C is relatively small.

[0212] It should be noted that, regardless of whether the temperature difference is considered or not, if the influence of the main frequency on the minimum power supply voltage difference is considered, the minimum power supply voltage difference found actually includes the minimum power supply voltage difference of the processor at multiple main frequencies, and these main frequencies correspond one to one with the main frequencies included in the target correspondence. At this time, the set power supply voltages of multiple main frequencies in the target correspondence are calibrated according to the minimum power supply voltage difference of the processor at multiple main frequencies. If the influence of the main frequency on the minimum power supply voltage difference is not considered, the minimum power supply voltage difference found actually includes the minimum power supply voltage difference of the processor at a certain main frequency. At this time, the set power supply voltages of all main frequencies in the target correspondence are calibrated according to the minimum power supply voltage difference of the processor at a certain main frequency. The following text involving the calibration of the target correspondence can refer to the description of whether the main frequency is considered here.

[0213] When the storage medium stores the difference correspondence in the form of a correspondence table, the method for the processor to calibrate the target correspondence according to the performance difference information is defined as a table lookup method. The specific process of the table lookup method is described below in the case where the processor has a built-in CPM circuit.

[0214] The first step is to test the target correspondence table of the benchmark processor before delivery, using the benchmark processor as the test object, and save the target correspondence table of the benchmark processor in a storage medium.

[0215] The second step is to divide the operating temperature range into multiple temperature levels before leaving the factory, select a temperature from each temperature level, determine the difference correspondence table of various processors in the corresponding temperature levels, and save the target correspondence of multiple temperature levels in the storage medium.

[0216] For example, the operating temperature range is 0℃~100℃. 0℃~100℃ is divided into five temperature levels of 0℃~20℃, 21℃~40℃, 41℃~60℃, 61℃~80℃, and 81℃~100℃ at intervals of 20℃. 15℃ is selected from 0℃~20℃, 28℃ is selected from 21℃~40℃, 50℃ is selected from 41℃~60℃, 75℃ is selected from 61℃~80℃, and 90℃ is selected from 81℃~100℃. Then, the delay time and the minimum supply voltage of the CPM circuit built into the various processors and the benchmark processor are tested at 15℃, 28℃, 50℃, 75℃ and 90℃ respectively. According to the difference in the delay time and the difference in the minimum supply voltage of the CPM circuit built into the various processors and the benchmark processor, a table of the difference correspondence between the various processors at the five temperature levels is obtained. Table 4 shows the difference correspondence between the three processors at the temperature level of 50℃.

[0217] Table 4 The difference between the three processors at 50℃ temperature level

[0218] Processor Type Delay difference / ns Minimum supply voltage difference / V The first processor ΔX1 Δv1 The second processor ΔX2 Δv2 The third processor ΔX3 Δv3

[0219] ΔX1 is the delay difference between the CPM circuit built in the first processor and the reference processor, ΔX2 is the delay difference between the CPM circuit built in the second processor and the reference processor, ΔX3 is the delay difference between the CPM circuit built in the third processor and the reference processor, Δv1 is the minimum power supply voltage difference between the first processor and the reference processor, Δv2 is the minimum power supply voltage difference between the second processor and the reference processor, and Δv3 is the minimum power supply voltage difference between the third processor and the reference processor.

[0220] Step 3: After leaving the factory, when the electronic device is in use, the CPM circuit measures the current delay time, and the processor searches the table of differences between multiple processors at multiple temperature levels according to the current temperature. The current delay difference is determined based on the current delay time measured by the CPM circuit built into the processor and the current delay time measured by the CPM circuit built into the reference processor. Based on the current delay difference, the lowest power supply voltage difference corresponding to a delay time that is close to (the degree of proximity of the delay difference can be set according to actual conditions) or the same as the current delay difference is searched from the table of differences between multiple processors at the temperature level at the current temperature, and the set power supply voltage for each main frequency in the target correspondence of the reference processor is calibrated based on the lowest power supply voltage difference found.

[0221] For example: the current operating temperature is 45°C, the CPM circuit measures the delay time at 45°C, and the current delay difference is obtained based on the delay time measured by the built-in CPM circuit of the processor at 45°C and the delay time of the built-in CPM circuit of the reference processor at 50°C. Since the temperature range of 45°C is 41°C to 60°C, a delay difference close to or the same as the current delay difference is found from Table 4 based on the current delay difference (the degree of delay difference closeness can be set according to actual conditions), and then the minimum power supply voltage difference is found from Table 4 based on the found delay difference. If the set power supply voltage of a certain main frequency in the target correspondence of the reference processor is V, and the determined minimum power supply voltage difference is Δv3, then the calibrated set power supply voltage is equal to V+Δv3.

[0222] When the difference correspondence is stored in the storage medium in the form of a mathematical function expression, the method for the processor to calibrate the target correspondence according to the performance difference information is defined as a mathematical deduction method. The specific process of the mathematical deduction method is described below in the case where the processor has a built-in CPM circuit.

[0223] The first step is to test the target correspondence table of the benchmark processor before delivery, using the benchmark processor as the test object, and save the target correspondence table of the benchmark processor in a storage medium.

[0224] The second step is to divide the operating temperature range into multiple temperature levels before leaving the factory, select a temperature from each temperature level, determine the delay difference of multiple processors at this temperature and the difference in the minimum power supply voltage, and fit them to determine the functional relationship between the delay difference of multiple processors at this temperature and the difference in the minimum power supply voltage. The functional relationship is Δv=kΔX+a. k is the coefficient, a is a fixed constant, ΔX is the delay difference, and Δv is the minimum operating voltage difference. The mathematical function expression is saved in the storage medium.

[0225] For example, the operating temperature range is 0℃~100℃. 0℃~100℃ is divided into five temperature ranges of 0℃~20℃, 21℃~40℃, 41℃~60℃, 61℃~80℃, and 81℃~100℃ at intervals of 20℃. 15℃ is selected from 0℃~20℃, 28℃ is selected from 21℃~40℃, 50℃ is selected from 41℃~60℃, 75℃ is selected from 61℃~80℃, and 90℃ is selected from 81℃~100℃. Then, five mathematical function relationships are fitted at 15℃, 28℃, 50℃, 75℃, and 90℃, respectively, and the five mathematical function relationships correspond to the mathematical function relationships of the five temperature ranges.

[0226] The third step is that after leaving the factory, when the electronic device is in use, the CPM circuit measures the current delay time, and the processor selects a mathematical function relationship based on the current temperature level. The current delay difference is obtained based on the current delay time of the CPM circuit built into the processor and the delay time of the CPM circuit built into the benchmark processor at the current temperature. The current delay difference is substituted into the selected mathematical function relationship, the minimum power supply voltage difference is calculated, and then the target correspondence of the benchmark processor is calibrated based on the minimum power supply voltage difference.

[0227] For example: the current operating temperature is 45°C, the CPM circuit built into the CPM circuit measures the current delay time at 45°C, and the current delay difference is obtained based on the current delay time measured by the CPM circuit built into the processor at 45°C and the delay time of the CPM circuit built into the reference processor at 45°C. The current delay difference is substituted into the mathematical function relationship of the temperature level of 50°C fitted at 50°C to obtain the minimum power supply voltage difference. If the set power supply voltage of a certain main frequency in the target correspondence of the reference processor is V, and the determined minimum power supply voltage difference is Δv3, then the calibrated set power supply voltage is equal to V+Δv3.

[0228] It should be noted that, without considering the influence of temperature, the determined correspondence between the differences of multiple processors can be regarded as the correspondence between the differences of multiple processors at one temperature level, except that the range of the temperature level is relatively wide. For example, when considering the influence of temperature, the operating temperature of 0℃~100℃ is divided into five temperature levels, namely 0℃~20℃, 21℃~40℃, 41℃~60℃, 61℃~80℃, and 81℃~100℃. If the influence of temperature is ignored, it can be considered that the correspondence between the differences of multiple processors is the correspondence between the differences of multiple processors measured at the temperature level of 0℃~100℃.

[0229] As a possible implementation, multiple target correspondences are written into the electronic device before it leaves the factory, and the final target correspondence is determined after debugging. At this time, the storage medium stores the target correspondences of the reference processor at multiple temperature levels or the target correspondences of multiple processors.

[0230] When the storage medium stores the target correspondence relationship of the benchmark processor at multiple temperature levels as described above, Fig.10 As shown, before the processor sends the power supply adjustment information to the power supply according to the main frequency of the next time period, the method further includes:

[0231] Step 100d: The processor searches for a target correspondence relationship from the target correspondence relationships of the reference processor at multiple temperature levels according to the current temperature. The target correspondence relationship is the target correspondence relationship of the reference processor at the temperature level where the current temperature is located. At this time, the target correspondence relationship of the determined reference processor takes into account the influence of temperature on the target correspondence relationship, so that the calibrated target correspondence relationship is better matched with the processor included in the electronic device.

[0232] The following describes the determination and calibration process of the target correspondence relationship of the above-mentioned benchmark processor by taking the table lookup method described above as an example.

[0233] The first step is that before leaving the factory, the operating temperature range of the benchmark processor is 0℃~100℃. 0℃~100℃ is divided into five temperature levels of 0℃~20℃, 21℃~40℃, 41℃~60℃, 61℃~80℃, and 81℃~100℃ at intervals of 20℃. 15℃ is selected from 0℃~20℃, 28℃ is selected from 21℃~40℃, 50℃ is selected from 41℃~60℃, 75℃ is selected from 61℃~80℃, and 90℃ is selected from 81℃~100℃. Then, the target correspondence of the benchmark processor at 15℃, 28℃, 50℃, 75℃ and 90℃ is tested respectively to obtain the target correspondence of the processor at the five temperature levels.

[0234] The second step is to test the delay time and the minimum supply voltage of the CPM circuit built into the various processors and the benchmark processor at 15°C, 28°C, 50°C, 75°C and 90°C before shipment. Based on the difference in the delay time and the difference in the minimum supply voltage of the CPM circuit built into the various processors and the benchmark processor, a table of the difference correspondence between the various processors at 15°C, 28°C, 50°C, 75°C and 90°C is obtained, that is, the difference correspondence between the various processors at multiple temperature levels.

[0235] Step 3: After leaving the factory, when the electronic device is in use, the current operating temperature is 45°C. The processor finds the target correspondence of the benchmark processor at the temperature level of 45°C from the target correspondence table of the benchmark processor at five temperature levels according to the current temperature (i.e., the target correspondence of multiple processors at 50°C). The processor obtains the current delay difference based on the delay time measured by the built-in CPM circuit of the processor at 45°C and the delay time of the built-in CPM circuit of the benchmark processor at 45°C, and then finds the delay difference close to or the same as the current delay difference from Table 4, and finds the minimum power supply voltage difference from Table 4 according to the found delay difference. If the set power supply voltage of a main frequency in the found target correspondence is V, and the determined minimum power supply voltage difference is Δv3, then the calibrated set power supply voltage is equal to V+Δv3.

[0236] When the storage medium stores target correspondences of multiple processors, without considering the influence of temperature, the electronic device is powered on and the CPM circuit detects performance difference information. Fig.11 As shown, before the processor searches for the set supply voltage of the main frequency of the next time period from the target corresponding relationship according to the main frequency of the next time period, the method further includes:

[0237] Step 100e: The processor searches for a target correspondence relationship that matches the processor included in the electronic device from the target correspondence relationships of the various processors according to the performance difference information.

[0238] When temperature is not considered, each processor has a built-in CPM circuit. In order to cooperate with the processor to find a target correspondence relationship that matches the processor included in the electronic device, the CPM circuit built into each processor can be used to measure the performance difference information such as the oscillation frequency or delay time of multiple processors before leaving the factory, and establish a connection between the performance difference information of multiple processors and the target correspondence relationship of multiple processors. The performance difference information of the multiple processors and the target correspondence relationship of the multiple processors are stored in a storage medium. Exemplarily, the performance difference information of each processor is the delay time of the processor. When the electronic device is powered on before leaving the factory, the CPM circuit built into the processor determines the target correspondence relationship based on the delay time.

[0239] When considering temperature, Fig.12 As shown, before the processor sends the power supply adjustment information to the power supply according to the main frequency of the next time period, the method further includes:

[0240] Step 100f: the processor searches for target correspondences of multiple processors at the temperature level at the current temperature from target correspondences of multiple processors at multiple temperature levels according to the current temperature; searches for a target correspondence that matches the processor included in the electronic device from the target correspondences of multiple processors at the temperature level at the current temperature according to the performance difference information.

[0241] The target correspondences of the above-mentioned multiple processors at multiple temperature gears can be divided into n temperature gear target correspondences according to the operating temperature. Each temperature gear target correspondence includes the target correspondences of multiple processors at the temperature gear. Of course, the target correspondences of multiple processors can also be divided into n processor gear target correspondences according to different processor gears. Each processor gear target correspondence includes the target correspondences of processors at the same gear at n temperature gears. It should be understood that the target correspondences of processors at the same gear at n temperature gears means: selecting a processor from all processors at the processor gear as a test object, and testing the target correspondences of the processor at n temperature gears. Moreover, when n is equal to 1, the target correspondences of multiple processors have only one temperature gear, and at this time, it can be considered that the target correspondences of multiple processors without considering the temperature. When n is an integer greater than or equal to 2, the target correspondences of multiple processors have two or more temperature gears. Moreover, the larger n is, the more temperature gears there are, and the target correspondences finally determined by the processor are closer to the real target correspondences.

[0242] In order to search for a target correspondence relationship matching the processor included in the electronic device from the target correspondence relationship of multiple processors according to the performance difference information, the storage medium should also pre-store the performance difference information of the multiple processors at multiple temperature levels. In addition, the performance difference information of the multiple processors at multiple temperature levels should have a mutual dependence relationship with the target correspondence relationship of the multiple processors at multiple temperature levels, and then the performance difference information of the multiple processors at multiple temperature levels and the target correspondence relationship of the multiple processors at multiple temperature levels are stored in the storage medium.

[0243] In one case, the performance difference information of multiple processors at multiple temperature levels can be classified according to the temperature levels to obtain multiple types of performance difference information corresponding to the multiple temperature levels. Each type of performance difference information includes the performance difference information (such as delay time or oscillation frequency) of the multiple processors at the temperature level.

[0244] In another case, the performance difference information of multiple processors at multiple temperature levels can be classified according to the processor level to obtain multiple types of performance difference information corresponding to the multiple processor levels. Each type of performance difference information includes the performance difference information (such as delay time or oscillation frequency) of the same level processor at multiple temperature levels.

[0245] Exemplarily, the operating temperature range of the processor is 0°C to 100°C. 0°C to 100°C is divided into five temperature levels of 0°C to 20°C, 21°C to 40°C, 41°C to 60°C, 61°C to 80°C, and 81°C to 100°C at intervals of 20°C, 15°C is selected from 0°C to 20°C, 28°C is selected from 21°C to 40°C, 50°C is selected from 41°C to 60°C, 75°C is selected from 61°C to 80°C, and 90°C is selected from 81°C to 100°C. Then, the target correspondence relationship of multiple processors and the delay time of multiple processors are measured at 15°C, 28°C, 50°C, 75°C, and 90°C, respectively, to obtain the target correspondence relationship of multiple processors at the five temperature levels and the delay time of multiple processors at the five temperature levels, and establish the target correspondence relationship of multiple processors at each temperature level and the delay time dependency relationship of multiple processors at each temperature level. When the electronic device is powered on, the CPM circuit built into the processor detects the current delay time at 45°C. A similar or identical delay time is searched from the delay times of various processors at the temperature level of 45°C (i.e., the delay times of various processors at 50°C), and the corresponding target correspondence is determined based on the found delay times.

[0246] As a possible implementation, no matter when the target correspondence stored in the storage medium is stored in the storage medium, and no matter how many types of processor target storage relationships are included in the target correspondence stored in the storage medium, the set power supply voltage and the set voltage slope in each target correspondence are determined as follows, which can ensure that the power supply voltage V provided by the power supply to the processor is out Can reliably and stably reduce processor power consumption.

[0247] The supply voltage setting in the above target correspondence relationship can be determined according to the following relationship: the supply voltage setting of the processor at each main frequency is V (i) , that is, the set supply voltage of each main frequency in the target correspondence is V (i) . V (i) =V min(i) +ΔV (i) , V min(i) ΔV is the minimum supply voltage for normal operation of the processor when the load current increases at each main frequency. (i) ΔV is the supply voltage margin of the processor at each main frequency. (i) =20mV~60mV. For example: 40mV or 50mV, of course, it can also be set according to the actual situation.

[0248] The voltage slope allowed by the processor at each main frequency setting supply voltage can be determined according to the following relationship: The allowable voltage slope of the processor at each main frequency setting supply voltage is R (i) . R (i) =Rmax(i) -ΔR (i) . R max(i) ΔR is the maximum voltage slope of the processor's supply voltage at each clock frequency. (i) is the voltage slope margin of the processor at each main frequency. (i) =0.03mOhm~0.08mOhm. For example: 0.05mOhm or 0.07mOhm. It should be understood that for the target correspondence relationship that the set voltage slopes of all main frequencies are equal, the allowable voltage slope R of the set supply voltage at each main frequency is determined. (i) Finally, the allowable voltage slope R of the supply voltage should be set from each main frequency. (i) Select the minimum value and ensure that the minimum value is greater than 0. Use the minimum value as the set voltage slope that can be shared by multiple main frequencies, that is, the constant voltage slope mentioned above.

[0249] The following examples illustrate the process of determining the target correspondence relationship involved in the method provided in the embodiment of the present application. The following examples are for illustration only and are not intended to be limiting.

[0250] Step 1: The process of generating the corresponding relationship between the processor's main frequency and the set power supply voltage: Before the CPU leaves the factory, the CPU evaluation board is used to measure the relationship between the CPU's main frequency and the minimum power supply voltage. During the test, the voltage slope of the power supply is set to 0Ohm, the test samples cover typical chips (typical chips are also called TT chips) and process deviation chips (also called Corner chips), and the test temperature covers the ambient temperature (i.e., operating temperature) of the CPU's declared specifications, and a set of processor main frequency and minimum power supply voltage curves are measured. The minimum power supply voltage should be able to ensure the minimum power supply voltage at which the processor can operate normally. At the same time, the power supply voltage margin is added to the minimum power supply voltage of each main frequency to obtain the set power supply voltage of the processor's main frequency to prevent the power supply voltage from failing to ensure the normal operation of the processor when the load current increases. The power supply voltage margin refers to the allowable voltage deviation value that allows the minimum power supply voltage to deviate. Fig.13 The main frequency and supply voltage curve of the processor are shown. The X axis is the main frequency and the Y axis is the supply voltage. Fig.13 Curve a in the figure is the processor's main frequency and minimum supply voltage curve. Fig.13 The b in the figure is the processor's main frequency and set supply voltage curve. Fig.13 The minimum operating voltage included in curve a in FIG. 1 is increased by 50mV margin to obtain Fig.13 Curve b in .

[0251] Depend on Fig.13 From the curve b in the figure, we can see that: Fig.13 Curve b covers the frequency and set supply voltage in various typical modes such as low power consumption mode, rated mode, and two overclocking modes. Table 3 shown above shows Fig.13 Curve b in FIG. 3 shows the corresponding relationship between the main frequency and the set supply voltage in different modes. As shown in Table 3, when the CPU works in the low power mode, the CPU main frequency is as low as 0.5 GHz, and the set supply voltage is 0.9 V; when the CPU works in the rated mode, the CPU main frequency is 1.5 GHz, and the set supply voltage is 1.1 V; when the CPU works in the first overclocking mode, the CPU main frequency exceeds the rated frequency and is 2.5 GHz, and the set supply voltage is 1.2 V; when the CPU works in the second overclocking mode, the CPU main frequency is further increased to 3.0 GHz, and the set supply voltage is 1.3 V.

[0252] It should be noted that the correspondence between the main frequency and the set supply voltage of the processor in the method of the present application may also be formed based on the correspondence table between the main frequency and the set supply voltage of the processor used in the existing DVFS technology.

[0253] The second step is the process of generating the correspondence between the processor's main frequency, set power supply voltage and set voltage slope: according to the main frequency and voltage settings of each CPU mode, the maximum voltage slope that can ensure the normal operation of the processor in each mode is determined, and a certain voltage slope margin is retained. The voltage slope margin refers to the allowable error of the maximum voltage slope.

[0254] For example: Fig.14 A voltage slope graph showing a set supply voltage in nominal mode. Fig.14 The oblique line a in the figure is the maximum voltage slope of the set supply voltage in the rated mode. When the processor is in the rated mode, the set supply voltage is 1.1V. When the load current increases, the set supply voltage is controlled to actively drop to the minimum value according to different voltage slopes, and the maximum voltage slope that ensures the normal operation of the processor is selected, and a certain voltage slope margin is subtracted from this to obtain the set voltage slope of the set supply voltage in the rated mode, that is, Fig.14 The slash b in .

[0255] It should be understood that the set voltage slope cannot be too large, otherwise the processor will not work when the load current of the power supply increases. The set voltage slope cannot be too small, otherwise the power consumption reduction effect of the processor will not be obvious. Based on this, the set voltage slope of each mode or each main frequency should be determined through repeated tests and cannot be set with a unified standard. As for the determination process of the set voltage slope of the low power mode, the first overclocking mode and the second overclocking mode, refer to the determination process of the set voltage slope of the rated mode.

[0256] Fig.15 The voltage loadline curves under different power consumption modes are shown. The X coordinate is the load current, and the Y coordinate is the set power supply constant voltage. Fig.15Curve a in the figure is the voltage slope curve in low power mode. Fig.15 Curve b in the figure is the voltage slope curve of the rated mode. Fig.15 Curve c in FIG. 1 is a voltage slope curve of the first overclocking mode. Fig.15 Curve d in FIG. 1 is a voltage slope curve of the second overclocking mode. Fig.13 The curve b in Fig.15 From curves a to d in , the target correspondence shown in Table 1 can be determined.

[0257] It should be noted that when the set voltage slopes corresponding to all main frequencies in the above target correspondence are equal to the constant voltage slope, after the second step, the minimum set voltage slope should be found from the set voltage slopes corresponding to all main frequencies, and ensure that the set voltage slope is greater than 0. The set voltage slope is the voltage slope shared by all main frequencies, that is, the constant voltage slope. For example: in the low power mode, rated mode, first overclocking mode and second overclocking mode in Table 1, the minimum set voltage slope that is not equal to 0 is 0.1V, therefore, 0.1V is used as the set voltage slope shared by the low power mode, rated mode, first overclocking mode and second overclocking mode.

[0258] The above mainly introduces the solution provided by the embodiment of the present application from the perspective of the interaction between various network elements. It can be understood that in order to realize the above functions, each network element, such as a processor and a power supply, includes a hardware structure and / or software module corresponding to the execution of each function. It should be easily appreciated by those skilled in the art that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the embodiments of the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the embodiments of the present application.

[0259] In the case of physical hardware, Fig.16 The embodiment of the present application provides a device. The device is applied to communication equipment or terminal equipment, but is not limited thereto. Fig.16 As shown, the device 200 includes a processor 201 and a power supply 202. The processor 201 is used to support the electronic device to execute step 101 executed by the processor in the above embodiment. The power supply 202 is used to support the electronic device to execute steps 102 and 103 executed by the power supply in the above embodiment.

[0260] In one possible implementation, Fig.16 As shown, the processor 201 is also used to execute step 100 as executed by the processor in the above embodiment.

[0261] In one possible implementation, Fig.16 As shown, the processor 201 is also used to support the electronic device to execute step 100a executed by the processor in the above embodiment.

[0262] The processor 201 is further configured to support the electronic device in executing step 100b and step 104 as executed by the processor in the above embodiment.

[0263] In one possible implementation, Fig.16 As shown, the device 200 further includes a storage medium 203 for storing the correspondence between the computer program and the target. The power supply 202 stores the set voltage slope in the form of a constant voltage slope. The processor 201 is specifically used to execute steps 1011A and 1012A as executed by the processor in the above embodiment.

[0264] In another possible implementation, Fig.16 As shown, the device 200 further includes a storage medium 203 for storing the correspondence between the computer program and the target. The processor 201 is specifically configured to execute steps 1011B and 1012B as executed by the processor in the above embodiment.

[0265] In one possible implementation, Fig.16 As shown, the device 200 further includes a storage medium 203 for storing a target correspondence between a computer program and a reference processor, and the processor 201 is further used to support the electronic device to execute step 100c executed by the processor in the above embodiment.

[0266] In order to cooperate with the processor to perform the corresponding steps, such as Fig.16 As shown, the storage medium 203 is also used to store the difference correspondence between multiple processors, or the difference correspondence between multiple processors at multiple temperature levels.

[0267] In another possible implementation, Fig.16 As shown, the device 200 further includes a storage medium 203 for storing a target correspondence between a computer program and a reference processor at multiple temperature levels, and the processor 201 is further used to support the electronic device to execute step 100d executed by the processor in the above embodiment. In order to cooperate with the processor to execute the corresponding steps, the storage medium 203 is also used to store the differential correspondence between multiple processors at multiple temperature levels.

[0268] In another possible implementation, Fig.16As shown, the device 200 further includes a storage medium 203 for storing a target correspondence between a computer program and a plurality of processors, and the processor 201 is further used to support the electronic device to execute step 100e executed by the processor in the above embodiment. In order to cooperate with the processor to execute the corresponding steps, the storage medium 203 is also used to store performance difference information of the plurality of processors.

[0269] In another possible implementation, Fig.16 As shown, the device 200 further includes a storage medium 203 for storing a computer program and a target correspondence between multiple processors at multiple temperature levels, and the processor 201 is also used to support the electronic device to execute step 100f executed by the processor in the above embodiment. In order to cooperate with the processor to execute the corresponding steps, the storage medium 203 is also used to store performance difference information of multiple processors at multiple temperature levels.

[0270] The embodiment of the present application can divide the processor and the power supply into functional modules according to the above method example. For example, each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0271] In the case of dividing each functional module into corresponding functional modules, Fig.17 FIG. 1 is a schematic diagram showing the structure of a voltage regulating device involved in the above embodiment. The voltage regulating device is a processor or a chip applied to a processor. Fig.17 As shown, the voltage regulating device 300 includes: a sending module 303, which is used to support the voltage regulating device to execute step 101 executed by the processor in the above embodiment.

[0272] In one possible implementation, Fig.17 As shown, the voltage regulating device 300 further includes: a prediction module 301, which is used to support the voltage regulating device to execute step 100 executed by the processor in the above embodiment.

[0273] In one possible implementation, Fig.17 As shown, the voltage regulating device 300 further includes a frequency synthesis module 304, which is used to support the voltage regulating device to execute step 100a, or step 100b and step 104 executed by the processor in the above embodiment.

[0274] In one possible implementation, Fig.17As shown, the voltage regulating device 300 further includes a selection module 302 and a storage module 305. The storage module 305 is used to store the target correspondence relationship. The selection module 302 is also used to support the voltage regulating device to execute step 1011A executed by the processor in the above embodiment, and the sending module 303 is also used to support the voltage regulating device to execute step 1012A executed by the processor in the above embodiment.

[0275] In another possible implementation, Fig.17 As shown, the voltage regulating device 300 further includes a selection module 302 and a storage module 305. The storage module 305 is used to store the target correspondence relationship. The selection module 302 is also used to support the voltage regulating device to execute step 1011B executed by the processor in the above embodiment, and the sending module 303 is also used to support the voltage regulating device to execute step 1012B executed by the processor in the above embodiment.

[0276] In one possible implementation, Fig.17 As shown, the voltage regulating device 400 further includes a relationship correction module 306 .

[0277] In one example, if Fig.17 As shown, the storage module 305 is used to store the target correspondence relationship of the reference processor. The relationship correction module 306 is used to support the voltage regulation device to execute step 100c executed by the processor in the above embodiment.

[0278] In order to cooperate with the processor to execute corresponding steps, the storage module 305 is also used to store the difference correspondence between multiple processors, or the difference correspondence between multiple processors at multiple temperature levels.

[0279] In another possible implementation, Fig.17 As shown, the storage module 305 is used to store the target correspondence relationship of the reference processor at multiple temperature levels and the difference correspondence relationship of multiple processors at multiple temperature levels. The relationship correction module 306 is used to support the voltage regulation device to execute step 100d executed by the processor in the above embodiment.

[0280] In another example, Fig.17 As shown, the storage module 305 is used to store target correspondences of various processors and performance difference information of various processors. The relationship correction module 306 is used to support the voltage regulation device to execute step 100e executed by the processor in the above embodiment.

[0281] In another example, Fig.17As shown, the storage module 305 is used to store target correspondences of various processors and performance difference information of various processors at multiple temperature levels. The relationship correction module 306 is used to support the voltage regulation device to execute step 100f executed by the processor in the above embodiment.

[0282] In the case of dividing each functional module into corresponding functional modules, Fig.18 FIG. 2 shows a schematic diagram of the structure of another voltage regulating device involved in the above embodiment. The voltage regulating device is a power supply or a chip used for a power supply. Fig.18 As shown, the voltage regulating device includes a receiving module 401 and a power supply module 402. The receiving module 401 is used to support the voltage regulating device to execute step 102 executed by the power supply in the above embodiment. The power supply module 402 is used to support the voltage regulating device to execute step 103 executed by the power supply in the above embodiment.

[0283] In one possible implementation, Fig.18 As shown, when the voltage regulation information includes the set supply voltage V of the main frequency of the next period and the set voltage slope R of the next period, the voltage regulation device 400 further includes a voltage identification module 404 and a slope identification module 405. The voltage identification module 404 is used to support the voltage regulation device to perform the above embodiment in which the power supply performs the identification of the set supply voltage V of the main frequency of the next period, thereby determining the reference voltage. The slope identification module 405 is used to support the voltage regulation device to perform the above embodiment in which the power supply performs the setting voltage slope R of the next period, thereby determining the voltage slope of the reference voltage.

[0284] In one possible implementation, Fig.18 As shown, the voltage regulating device 400 further includes a storage medium 403, which is used to store a set voltage slope in a constant voltage slope. The voltage regulating device 400 further includes a voltage identification module 404, which is used to support the voltage regulating device to perform the above embodiment in which the power supply identifies the set supply voltage V of the main frequency of the next time period, thereby determining the reference voltage.

[0285] All relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module, and will not be repeated here.

[0286] In the case of integrated units, Fig.19 It is shown that an embodiment of the present application provides a voltage regulating device. Fig.19 As shown, the voltage regulating device 500 may include: a communication unit 501. Optionally, the voltage regulating device 500 may also include a processing unit 502.

[0287] In one example, if Fig.19As shown, the voltage regulating device 500 is a processor, or a chip used in a processor. In this case, the processing unit 502 is used to support the voltage regulating device to execute step 100 executed by the processor in the above embodiment. The communication unit 501 is used to support the voltage regulating device to execute step 101 executed by the processor in the above embodiment.

[0288] In one possible implementation, Fig.19 As shown, the processing unit 502 is also used to support the voltage regulating device to execute step 100a or step 100b and step 104 executed by the processor in the above embodiment.

[0289] In one possible implementation, Fig.19 As shown, the voltage regulating device further includes a storage unit 503 for storing the target correspondence. The processing unit 502 is also used to support the voltage regulating device to execute step 1011A executed by the processor in the above embodiment. The communication unit 501 is also used to support the voltage regulating device to execute step 1012A executed by the processor in the above embodiment.

[0290] In another possible implementation, Fig.19 As shown, the voltage regulating device 500 further includes a storage unit 503 for storing the target correspondence relationship. The processing unit 502 is also used to support the voltage regulating device to execute step 1011B executed by the processor in the above embodiment, and the communication unit 501 is also used to support the voltage regulating device to execute step 1012B executed by the processor in the above embodiment.

[0291] In one possible implementation, Fig.19 As shown, the storage unit 503 is used to store the target correspondence of the reference processor. The processing unit 502 is also used to support the voltage regulating device to execute step 100c executed by the processor in the above embodiment.

[0292] In order to cooperate with the processing unit 502 to execute corresponding steps, the storage unit 503 is also used to store the difference correspondence between multiple processors, or the difference correspondence between multiple processors at multiple temperature levels.

[0293] In another possible implementation, Fig.19 As shown, the storage unit 503 is used to store the target correspondence between the reference processor and multiple temperature gears. The processing unit 502 is also used to support the voltage regulation device to perform step 100d performed by the processor in the above embodiment. In order to cooperate with the processing unit 502 to perform the corresponding steps, the storage unit 503 is also used to store the differential correspondence between multiple processors and multiple temperature gears.

[0294] In another possible implementation, Fig.19 As shown, the storage unit 503 is used to store target correspondences of various processors. The processing unit 502 is also used to support the voltage regulation device to execute step 100e executed by the processor in the above embodiment. In order to cooperate with the processing unit 502 to execute corresponding steps, the storage unit 503 is also used to store performance difference information of various processors.

[0295] In another possible implementation, Fig.19 As shown, the storage unit 503 is used to store the target correspondence between multiple processors at multiple temperature levels. The processing unit 502 is also used to support the voltage regulation device to execute step 100f executed by the processor in the above embodiment. In order to cooperate with the processing unit 502 to execute the corresponding steps, the storage unit 503 is also used to store the performance difference information of the multiple processors at multiple temperature levels.

[0296] In another example, Fig.19 As shown, the voltage regulating device 500 is a power supply, or a chip used in a power supply. In this case, the communication unit 501 is used to support the voltage regulating device to execute step 102 executed by the power supply in the above embodiment. The processing unit 502 is used to support the voltage regulating device to execute step 103 executed by the power supply in the above embodiment.

[0297] In one possible implementation, Fig.19 As shown, the voltage regulating device 500 may further include a storage unit 503 for storing data such as a set voltage slope in a constant voltage slope and a program code executable by the voltage regulating device.

[0298] Among them, the processing unit 502 can be a processor or a controller, for example, a central processing unit (CPU), a general processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. It can implement or execute various exemplary logic blocks, modules and circuits described in conjunction with the disclosure of the present invention. The processing unit can also be a combination that implements a computing function, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like. The communication unit can be a transceiver, a transceiver circuit or a communication interface, and the like. The storage unit can be a memory.

[0299] The above communication unit may be a communication interface of the device, used to receive signals from other devices. For example, when the device is implemented in a chip, the communication unit is a communication interface of the chip used to receive or send signals from other chips or devices.

[0300] when Fig.19 When the processing unit 502 shown in the figure includes a VRM chip, a logic control circuit and a buck converter, the communication unit 501 includes a communication interface and a power interface, and the storage unit 503 is a memory, the voltage regulating device 500 involved in the embodiment of the present invention can be Figure 2 The power supply shown in .

[0301] when Fig.19 When the processing unit 502 is a processor, the communication unit 501 is a communication interface, and the storage unit 503 is a memory, the voltage regulating device 500 according to the embodiment of the present invention can be Figure 2 The processor shown in .

[0302] Fig. 20 A schematic diagram of the structure of a chip is shown. Fig. 20 As shown, the chip 600 includes one or more (including two) processors 601 and a communication interface 602 .

[0303] Optional, such as Fig. 20 As shown, the chip also includes a memory 603. The memory 603 may include a read-only memory and a random access memory, and provides operation instructions and data to the processor 601. A portion of the memory 603 may also include a non-volatile random access memory (NVRAM).

[0304] In some implementations, the memory 603 stores the following elements, execution modules or data structures, or a subset thereof, or an extended set thereof.

[0305] In the embodiments of the present application, Fig. 20 As shown, the processor 601 performs corresponding operations by calling the target correspondence relationship stored in the memory 603.

[0306] In a possible implementation, the structures of the chips used by the processor and the power supply are similar, and different devices may use different chips to implement their respective functions.

[0307] like Fig. 20 As shown, the processor 601 controls the processing operation of any one of the processor and the power supply included in the electronic device in the embodiment of the present application. The processor 601 can also be called a central processing unit (CPU).

[0308] like Fig. 20 As shown, the memory 603 includes a read-only memory and a random access memory, and provides instructions and data to the processor 601. A portion of the memory 603 may also include an NVRAM. For example, in an application, the memory, the communication interface 602, and the memory 603 are coupled together through a bus system 604, wherein the bus system 604 includes not only a data bus, but also a power bus, a control bus, and a status signal bus. However, for the sake of clarity, in Fig. 20 Various buses are labeled as bus system 604 .

[0309] In one possible implementation, Fig. 20 As shown, the communication interface 602 is used to support the chip to perform the receiving and sending steps of the processor and power supply in the above embodiment. The processor 601 is used to support the chip to perform the processing steps of the processor and power supply in the above embodiment.

[0310] In one aspect, a computer-readable storage medium is provided, wherein instructions are stored in the computer-readable storage medium, and when the instructions are executed, the following is implemented: Figure 4 , Figure 5 and Figure 10-12 The function of the processor.

[0311] On the other hand, a computer-readable storage medium is provided, in which instructions are stored. When the instructions are executed, the following is achieved: Figure 4 , Figure 5 and Figure 10-12 The function of the power supply.

[0312] In one aspect, a computer program product is provided, wherein the computer program product includes instructions, and when the instructions are executed, the following are implemented: Figure 4 , Figure 5 and Figure 10-12 The function of the processor.

[0313] In another aspect, a computer program product comprising instructions is provided. The computer program product comprises instructions. When the instructions are executed, the following are implemented: Figure 4 , Figure 5 and Figure 10-12 The function of the power supply.

[0314] In one aspect, a chip is provided, which is applied to a processor, and the chip includes at least one processor and a communication interface, wherein the communication interface is coupled to the at least one processor, and the processor is used to execute instructions to implement the following Figure 4 , Figure 5 and Figure 10-12 The function of the processor.

[0315] In another aspect, a chip is provided, which is applied to a power supply, and the chip includes at least one processor and a communication interface, wherein the communication interface is coupled to the at least one processor, and the processor is used to execute instructions to implement the following Figure 4 , Figure 5 and Figure 10-12 The function of the power supply.

[0316] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present application.

[0317] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0318] In the several embodiments provided in the embodiments of the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0319] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0320] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0321] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program code.

[0322] The above are only specific implementations of the embodiments of the present application, but the protection scope of the embodiments of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the embodiments of the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A voltage regulation method, characterized in that: Applied to an electronic device having a processor and a power supply, the method comprises: The processor sends power supply adjustment information to the power supply according to the main frequency of the next period; the power supply adjustment information includes a set power supply voltage V of the main frequency of the next period, the set power supply voltage V is the power supply voltage corresponding to the main frequency of the next period determined by the dynamic voltage adjustment technology, and the main frequency of the next period refers to the main frequency predicted according to the current main frequency; The power supply provides a power supply voltage V to the processor according to the set power supply voltage V of the main frequency of the next period and the set voltage slope R of the main frequency of the next period. out , the supply voltage V out =VI*R, I is the load current of the power supply, and the set voltage slope R is the voltage slope corresponding to the next main frequency; The voltage slope refers to the voltage V of the power supply as the load current of the power supply increases. out The falling speed of the supply voltage V out As the load current increases, V min ≤V out ≤V,V min is the minimum supply voltage for normal operation of the processor when the processor is running at the main frequency in the next period and the load current increases; the set voltage slope R of the main frequency in the next period exists in the power supply in the form of a constant voltage slope, and the constant voltage slope is the minimum voltage slope R allowed by the set supply voltage of the processor at each main frequency min , R min >0.

2. The method according to claim 1, characterized in that: The processor sends the set supply voltage V of the processor at the main frequency of the next time period to the power supply according to the main frequency of the next time period, including: The processor searches for a set supply voltage V of the main frequency of the next period from a target corresponding relationship according to the main frequency of the next period, and sends the set supply voltage V of the main frequency of the next period to the power supply; The target corresponding relationship is a corresponding relationship between the main frequency of the processor, the set power supply voltage and the set voltage slope or a corresponding relationship between the main frequency of the processor and the set power supply voltage.

3. The method according to claim 1, characterized in that The power supply adjustment information also includes the set voltage slope R of the main frequency in the next time period.

4. The method according to claim 3, characterized in that The processor sending power supply adjustment information to the power supply according to the main frequency of the next time period includes: The processor searches for the set supply voltage V of the main frequency of the next period and the set voltage slope R of the main frequency of the next period from the target corresponding relationship according to the main frequency of the next period, and sends the set supply voltage V of the main frequency of the next period and the set voltage slope R of the main frequency of the next period to the power supply; The target corresponding relationship is the corresponding relationship among the main frequency of the processor, the set power supply voltage and the set voltage slope.

5. The method according to claim 2 or 4, characterized in that: Before the processor sends power supply adjustment information to the power supply according to the main frequency of the next time period, the method further includes: The processor calibrates the target correspondence according to the performance difference information, so that the calibrated target correspondence matches the processor included in the electronic device, wherein the performance difference information includes delay time or oscillation frequency.

6. The method according to claim 5, characterized in that The processor calibrates the target correspondence relationship according to the performance difference information so that the calibrated target correspondence relationship matches the processor, including: The processor searches for the lowest power supply voltage difference that matches the performance difference information from the correspondence between the performance differences of multiple processors and the lowest power supply voltage difference according to the performance difference information; calibrates the set power supply voltage of each main frequency in the target correspondence according to the lowest power supply voltage difference that matches the performance difference information, so that the calibrated target correspondence matches the processor included in the electronic device; or, The processor searches for a correspondence between the performance differences and the minimum power supply voltage differences of multiple processors at the temperature level where the current temperature is located from the correspondence between the performance differences and the minimum power supply voltage differences of multiple processors at multiple temperature levels according to the current temperature; searches for a minimum power supply voltage difference that matches the performance difference information from the correspondence between the performance differences and the minimum power supply voltage differences of multiple processors at the temperature level where the current temperature is located according to the performance difference information; and calibrates the set power supply voltage of each main frequency in the target correspondence according to the minimum power supply voltage difference that matches the performance difference information, so that the calibrated target correspondence matches the processor included in the electronic device.

7. The method according to claim 6, characterized in that The target correspondence is a target correspondence of a reference processor, and the reference processor is a processor with the largest minimum power supply voltage at the same main frequency among multiple processors.

8. The method according to claim 6 or 7, characterized in that: Before the processor sends power supply adjustment information to the power supply according to the main frequency of the next time period, the method further includes: The processor searches for a target correspondence from the target correspondences of the benchmark processor at multiple temperature levels according to the current temperature; the target correspondence is the target correspondence of the benchmark processor at the temperature level at the current temperature, and the benchmark processor is the processor with the largest minimum power supply voltage at the same main frequency among multiple processors.

9. The method according to claim 2 or 4, characterized in that: Before the processor sends power supply adjustment information to the power supply according to the main frequency of the next time period, the method further includes: The processor searches for a target correspondence relationship matching the processor included in the electronic device from target correspondence relationships of multiple processors according to performance difference information; the performance difference information includes delay time or oscillation frequency; or, The processor searches for the target correspondence between the multiple processors at the temperature level at the current temperature from the target correspondence between the multiple processors at the temperature level at the current temperature; searches for the target correspondence between the multiple processors at the temperature level at the current temperature from the target correspondence between the multiple processors at the temperature level at the current temperature according to the performance difference information; the performance difference information includes delay time or oscillation frequency.

10. The method according to claim 1, characterized in that The set voltage slope of the processor at each of the main frequencies is the voltage slope allowed by the set supply voltage of the processor at each of the main frequencies; or, The set voltage slope of the processor at all main frequencies is equal to the constant voltage slope; the constant voltage slope is the minimum value R of the voltage slope allowed by the set power supply voltage of the processor at each main frequency. min , R min >0.

11. The method according to claim 1, characterized in that: The voltage slope allowed by the processor at each set supply voltage of the main frequency is R (i) , R (i) =R max(i) -ΔR (i) , R max(i) is the maximum voltage slope of the power supply voltage of the processor at each of the main frequencies, ΔR (i) is the voltage slope margin of the processor at each main frequency.

12. The method according to claim 1, characterized in that The processor sets the supply voltage to V at each main frequency. (i) , V (i) =V min(i) +ΔV (i) , V min(i) is the minimum supply voltage for normal operation of the processor when the load current increases at each main frequency operation, ΔV (i) is the supply voltage margin of the processor at each of the main frequencies.

13. The method according to claim 1, characterized in that The method further comprises: When the processor determines that the main frequency of the next time period is not equal to the current main frequency, the processor sets the current main frequency to be equal to the main frequency of the next time period.

14. An electronic device, characterized in that: include: A processor, used for sending power supply adjustment information to the power supply according to the main frequency of the next time period; The power supply adjustment information includes the set power supply voltage V of the main frequency of the next period, the set power supply voltage V is the power supply voltage corresponding to the main frequency of the next period determined by the dynamic voltage adjustment technology, and the main frequency of the next period refers to the main frequency predicted according to the current main frequency; A power supply, used to provide a power supply voltage V to the processor according to the set power supply voltage V of the main frequency of the next period and the set voltage slope R of the main frequency of the next period out , the supply voltage V out =VI*R, I is the load current of the power supply, and the set voltage slope R is the voltage slope corresponding to the next main frequency; The voltage slope refers to the voltage V of the power supply as the load current of the power supply increases. out The falling speed of the supply voltage V out As the load current increases, V min ≤V out ≤V,V min The minimum supply voltage for normal operation of the processor when the processor is running at the main frequency in the next period and the load current increases; The set voltage slope R of the main frequency of the next period exists in the power supply in the form of a constant voltage slope, and the constant voltage slope is the minimum voltage slope R allowed by the set power supply voltage of the processor at each main frequency. min , R min >0.

15. The device according to claim 14, characterized in that The processor is specifically configured to search the set power supply voltage V of the main frequency of the next time period from the target corresponding relationship according to the main frequency of the next time period, and send the set power supply voltage V of the next time period to the power supply; The target corresponding relationship is a corresponding relationship between the main frequency of the processor, the set power supply voltage and the set voltage slope or a corresponding relationship between the main frequency of the processor and the set power supply voltage.

16. The device according to claim 14, characterized in that The power supply adjustment information includes a set voltage slope R of the main frequency in the next time period.

17. The device according to claim 16, characterized in that The processor is specifically used to search the set supply voltage V of the main frequency of the next period and the set voltage slope R of the main frequency of the next period from the target corresponding relationship according to the main frequency of the next period, and send the set supply voltage V of the main frequency of the next period and the set voltage slope R of the main frequency of the next period to the power supply; The target corresponding relationship is the corresponding relationship among the main frequency of the processor, the set power supply voltage and the set voltage slope.

18. The device according to claim 15 or 17, characterized in that The processor is also used to calibrate the target correspondence according to the performance difference information before sending power supply adjustment information to the power supply according to the main frequency of the next time period, so that the calibrated target correspondence matches the processor included in the electronic device, wherein the performance difference information includes delay time or oscillation frequency.

19. The device according to claim 18, characterized in that The processor is specifically used to search for the lowest power supply voltage difference that matches the performance difference information from the correspondence between the performance differences of multiple processors and the lowest power supply voltage difference according to the performance difference information; calibrate the set power supply voltage of each main frequency in the target correspondence according to the lowest power supply voltage difference that matches the performance difference information, so that the calibrated target correspondence matches the processor included in the electronic device; or, The processor is specifically used to find the corresponding relationship between the performance difference and the minimum power supply voltage difference of multiple processors at the temperature level where the current temperature is located from the corresponding relationship between the performance difference and the minimum power supply voltage difference of multiple processors at multiple temperature levels according to the current temperature; According to the performance difference information, the lowest power supply voltage difference matching the performance difference information is searched from the correspondence between the performance differences of multiple processors at the temperature level where the current temperature is located and the lowest power supply voltage difference; according to the lowest power supply voltage difference matching the performance difference information, the set power supply voltage of each main frequency in the target correspondence is calibrated so that the calibrated target correspondence matches the processor included in the electronic device.

20. The device according to claim 19, characterized in that The target correspondence is a target correspondence of a reference processor, and the reference processor is a processor with the largest minimum power supply voltage at the same main frequency among multiple processors.

21. The device according to claim 20, characterized in that The processor is also used to search for a target correspondence from the target correspondences of the benchmark processor at multiple temperature levels according to the current temperature before sending power supply adjustment information to the power supply according to the main frequency of the next time period; the target correspondence is the target correspondence of the benchmark processor at the temperature level where the current temperature is located, and the benchmark processor is the processor with the largest minimum power supply voltage at the same main frequency among multiple processors.

22. The device according to claim 15 or 17, characterized in that The processor is also used to search for a target correspondence relationship matching the processor included in the electronic device from target correspondence relationships of multiple processors according to performance difference information before sending power supply adjustment information to the power supply according to the main frequency of the next time period; The performance difference information includes delay time or oscillation frequency; or, The processor is also used to search the target correspondence relationship of the multiple processors at the temperature level where the current temperature is located from the target correspondence relationship of the multiple processors at the temperature level where the current temperature is located before sending the power supply adjustment information to the power supply according to the main frequency of the next time period; According to the performance difference information, a target correspondence relationship matching the processor included in the electronic device is searched from the target correspondence relationships of the multiple processors at the temperature level where the current temperature is located; the performance difference information includes a delay time or an oscillation frequency.

23. The device according to claim 14, characterized in that The set voltage slope of the processor at each of the main frequencies is the voltage slope allowed by the set supply voltage of the processor at each of the main frequencies; or, The set voltage slope of the processor at all main frequencies is equal to the constant voltage slope; the constant voltage slope is the minimum value R of the voltage slope allowed by the set power supply voltage of the processor at each main frequency. min , R min >0.

24. The device according to claim 14, characterized in that The voltage slope allowed by the processor at each set supply voltage of the main frequency is R (i) , R (i) =R max(i) -ΔR (i) , R max(i) is the maximum voltage slope of the processor at the lowest supply voltage at each main frequency, ΔR (i) is the voltage slope margin of the processor at each main frequency.

25. The device according to claim 14, characterized in that The processor sets the supply voltage to V at each main frequency. (i) , V (i) =V min(i) +ΔV (i) , V min(i) is the minimum supply voltage for normal operation of the processor when the load current increases at each main frequency operation, ΔV (i) is the supply voltage margin of the processor at each of the main frequencies.

26. The device according to claim 14, characterized in that The processor is further configured to, when determining that the main frequency of the next time period is not equal to the current main frequency, set the current main frequency to be equal to the main frequency of the next time period.

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