Semiconductor light emitting device

Abstract

The present invention discloses a semiconductor light-emitting element, comprising a semiconductor stack having a first semiconductor layer, a second semiconductor layer and an active layer; a plurality of first grooves passing through the second semiconductor layer and the active layer to expose a portion of the upper surface of the first semiconductor layer; a second groove passing through the second semiconductor layer and the active layer to expose another portion of the upper surface and a surrounding side surface of the first semiconductor layer, wherein the second groove is located at an outermost side of the active layer and surrounds the active layer and the plurality of first grooves; a first metal region is located on the second semiconductor layer and electrically connected to the second semiconductor layer, a second metal region is located on the second semiconductor layer and filled into one of the plurality of first grooves and the second groove, the second metal region is electrically connected to the first semiconductor layer via one of the plurality of first grooves and the second groove; and a first welding portion and a second welding portion are located on the second semiconductor layer and are electrically connected to the second semiconductor layer and the first semiconductor layer, respectively.

Description

[0001] This application is a divisional application of the Chinese invention patent application (application number: 201710828987.X, application date: September 14, 2017, invention name: semiconductor light-emitting element). Technical Field

[0002] The invention relates to a structure of a semiconductor light emitting element. Background Art

[0003] Light-emitting diodes (LEDs) are currently widely used in optical display devices, traffic signs, data storage devices, communication devices, lighting devices, and medical equipment. Figure 2 As shown, the conventional LED has an n-type semiconductor layer 1104, an active layer 1106, and a p-type semiconductor layer 1108 formed sequentially on a substrate 1102, a portion of the p-type semiconductor layer 1108 and the active layer 1106 are removed to expose a portion of the n-type semiconductor layer 1104, and a p-type electrode a1 and an n-type electrode a2 are formed on the p-type semiconductor layer 1108 and the n-type semiconductor layer 1104, respectively. Because the n-type electrode a2 requires a sufficient area for subsequent manufacturing processes, such as wire bonding, most of the active layer 1106 is removed, resulting in reduced luminous efficiency.

[0004] In addition, the LED mentioned above can be further combined and connected with other components to form a light-emitting apparatus. Figure 1 is a schematic diagram of the structure of an existing light emitting device, such as Figure 1 As shown, a light-emitting device 1200 includes a sub-mount 1202 having at least one circuit 1204; at least one solder 1206 is located on the above-mentioned sub-mount 1202, and the above-mentioned LED 1210 is bonded and fixed to the sub-mount 1202 through this solder 1206 to form an electrical connection between the substrate 1212 of the LED 1210 and the circuit 1204 on the sub-mount 1202; and an electrical connection structure 1208 to electrically connect the electrode 1214 of the LED 1210 and the circuit 1204 on the sub-mount 1202; wherein the above-mentioned sub-mount 1202 can be a leadframe or a large-sized mounting substrate, so as to facilitate the circuit planning of the light-emitting device and improve its heat dissipation effect. Summary of the invention

[0005] A semiconductor light-emitting element comprises a semiconductor stack, comprising a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; a plurality of first grooves, passing through the second semiconductor layer and the active layer to expose a portion of the upper surface of the first semiconductor layer; a second groove, passing through the second semiconductor layer and the active layer to expose another portion of the upper surface and a surrounding side surface of the first semiconductor layer, wherein the second groove is located at an outermost side of the active layer and surrounds the active layer and the plurality of first grooves; a first metal region is located on the second semiconductor layer and is electrically connected to the second semiconductor layer; a second metal region is located on the second semiconductor layer and is filled in one of the plurality of first grooves and in the second groove, wherein the second metal region is electrically isolated from the first metal region, and the second metal region is electrically connected to the first semiconductor layer via one of the plurality of first grooves and via the second groove; a first welding portion is located on the second semiconductor layer and is electrically connected to the first metal region; and a second welding portion is located on the second semiconductor layer and is electrically connected to the second metal region.

[0006] A semiconductor light emitting element comprises a semiconductor stack, comprising a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; a plurality of first grooves passing through the second semiconductor layer and the active layer to expose a portion of the upper surface of the first semiconductor layer; a second groove passing through the second semiconductor layer and the active layer to expose another portion of the upper surface and a surrounding side surface of the first semiconductor layer, wherein the second groove is located at an outermost side of the active layer and surrounds the active layer and the plurality of first grooves; a patterned metal layer is located on the second semiconductor layer and filled into one of the plurality of first grooves and the second groove; The present invention relates to a method for manufacturing a semiconductor device comprising: a first semiconductor layer comprising a first welding portion located on the second semiconductor layer and electrically connected to the second semiconductor layer; a second welding portion located on the second semiconductor layer and electrically connected to the first semiconductor layer; and an insulating layer located between the patterned metal layer and the first welding portion, and / or between the patterned metal layer and the second welding portion, wherein the insulating layer comprises a plurality of openings, the first welding portion is electrically connected to the second semiconductor layer through the plurality of openings, and / or the second welding portion is electrically connected to the first semiconductor layer through the plurality of openings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a schematic diagram of the structure of an existing light-emitting device;

[0008] Figure 2 is a cross-sectional view of an existing LED;

[0009] Figure 3A to Figure 10B is a schematic diagram of a method for manufacturing a semiconductor light emitting element V according to an embodiment of the present invention;

[0010] Fig.11 A top view of a semiconductor light emitting element V according to an embodiment of the present invention;

[0011] Fig.12 for Fig.11 A cross-sectional view of the semiconductor light emitting element V along CC';

[0012] Fig.13 for Fig.11 A cross-sectional view of the semiconductor light emitting element V along DD';

[0013] Figure 14A to Figure 14B and Figures 15A to 21C is a schematic diagram of a method for manufacturing a semiconductor light emitting element T according to an embodiment of the present invention;

[0014] Figure 14C to Figure 14D A top view of a groove according to another embodiment of the present invention; and

[0015] Fig. 22 FIG. 2 is a structural diagram of another embodiment of the present invention.

[0016] Explanation of symbols

[0017] Ⅴ, T, 608 semiconductor light emitting element

[0018] 100, t100, t100', t100" semiconductor stack

[0019] 101, t101 first semiconductor layer

[0020] 102, t102 second semiconductor layer

[0021] 103, t103 active layer

[0022] 110, t110 substrate

[0023] 120 Through hole

[0024] t120a, t120a', t120a' first groove

[0025] t120b, t120b', t120b' second groove

[0026] 200, t200 metal layer

[0027] t200a First metal area

[0028] t200b Second metal area

[0029] t200a1, t200a2, t200a3 sub-region

[0030] 300, t300 transparent conductive structure

[0031] 310, t310 reflective layer

[0032] 320 Barrier layer

[0033] 400, t400 first welding section

[0034] 500, t500 Second welding section

[0035] 700, t700 Second insulation layer

[0036] 800, t800 third insulation layer

[0037] t800a First insulation area

[0038] 1000, t1000 semiconductor structure

[0039] t1000uS top surface

[0040] 1011 Peripheral

[0041] 1011S surrounding surface

[0042] t1011S surrounding side surface

[0043] 1012S, t1012S surface

[0044] 1021, t1021S inclined side wall

[0045] 1200 Surrounding area

[0046] t2001 Ring opening

[0047] 2002 Opening

[0048] 3001 Periphery

[0049] 3101 Peripheral

[0050] 3201 Peripheral

[0051] 6000, t600 first insulation layer

[0052] 6001, t600a The first group, the first insulation area

[0053] t600b Second group first insulation area

[0054] 6002 Second group first insulation opening

[0055] 6003 First insulation opening

[0056] 7001 First group second insulation opening

[0057] t7001 Second insulation opening

[0058] 7002 Second group second insulation opening

[0059] 8001, t8001 The third insulating opening of the first group

[0060] 8002, t8002 The third insulating opening of the second group

[0061] 600 Bulb

[0062] 602 Lampshade

[0063] 604 Lens

[0064] 606 bearing part

[0065] 610 Light emitting module

[0066] 612 Lamp Holder

[0067] 614 Heat sink

[0068] 616 Connection DETAILED DESCRIPTION

[0069] Figure 3A to Figure 10B The present invention provides a method for manufacturing a semiconductor light emitting device V according to an embodiment of the present invention. Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A and Fig. 10A For the floor plan. Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B They are Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A and Fig. 10A Section view along XX'.

[0070] like Figure 3A and Figure 3BAs shown, a semiconductor stack 100 is formed on a growth substrate 110. The growth substrate 110 may be a sapphire substrate, but is not limited thereto. The semiconductor stack 100 includes a first semiconductor layer 101, a second semiconductor layer 102, and an active layer 103 formed between the first semiconductor layer 101 and the second semiconductor layer 102. Each of the first semiconductor layer 101 and the second semiconductor layer 102 may be composed of a single layer or a multilayer. In addition, the active layer 103 may have a single quantum well structure or a multiple quantum well structure. The semiconductor stack 100 may be formed of a III-nitride semiconductor on the growth substrate 110 by metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). A buffer layer (not shown) is formed before the semiconductor stack to alleviate the lattice dislocation between the growth substrate 110 and the semiconductor stack 100, and may be composed of a III-nitride series material, such as gallium nitride, aluminum gallium nitride, or aluminum nitride. The semiconductor stack 100 includes an outer periphery. A plurality of through holes 120 are formed by removing a portion of the first semiconductor layer 101, the second semiconductor layer 102 and the active layer 103, which expose the surface 1012S of the first semiconductor layer 101. A surrounding area 1200 is formed to expose the surrounding surface 1011S of the first semiconductor layer 101 and one or more semiconductor structures 1000 are surrounded by the surrounding area 1200. The semiconductor stack 100 can be patterned by photolithography and etching. The plurality of semiconductor structures 1000 are connected to each other through the first semiconductor layer 101. The semiconductor structure 1000 includes an upper portion and a lower portion, wherein the lower portion includes a width greater than the width of the upper portion in a cross-sectional view. The plurality of through holes 120 include a circular shape in a plan view, and / or the surrounding area 1200 includes a rectangular shape in a plan view, but is not limited thereto. One or more semiconductor structures 1000 include an inclined sidewall 1021. The second semiconductor layer 102 and the active layer 103 are exposed in the surrounding area 1200 and the plurality of through holes 120. The upper portion of the semiconductor structure 1000 is connected to the surface 1011S of the first semiconductor layer 101 via the inclined sidewall 1021 .

[0071] like Figure 4A and Figure 4B As shown, the first insulating layer 6000 covers the surface 1012S of the first semiconductor layer 101 in the plurality of through holes 120 and the oblique sidewall 1021 of the semiconductor structure 1000. In other words, the first insulating layer 6000 includes a first group of first insulating regions 6001 corresponding to the plurality of through holes 120 and a second group of first insulating openings 6002 respectively formed on the upper portion of one or more semiconductor structures 1000 to expose the second semiconductor layer 102. The material of the first insulating layer 6000 includes silicon oxide or silicon nitride. In another embodiment, the plurality of first insulating layers 6000 form a distributed Bragg reflector, which is formed by alternately stacking insulating layers with different refractive indices. For example, by alternately stacking SiOx / TiO x To form a first insulating layer 6000.

[0072] like Figure 5A and Figure 5B As shown, the transparent conductive structure 300 is formed on the second semiconductor layer 102 except for the first group of first insulating regions 6001. In other words, the transparent conductive structure 300 is only formed in the second group of first insulating openings 6002 and directly contacts the second semiconductor layer 102. The periphery 3001 of the transparent conductive structure 300 is not in contact with the first insulating layer 6000. The transparent conductive structure 300 includes a transparent conductive oxide, such as indium tin oxide (ITO) or a thin metal film, such as silver (Ag) or aluminum (Al). The transparent conductive structure 300 can be configured to form an ohmic contact with the second semiconductor layer 102. The transparent conductive structure 300 includes a single layer or multiple layers.

[0073] like Fig. 6A and Figure 6B As shown, the reflective layer 310 is formed on the second semiconductor layer 102 except for the first group of first insulating regions 6001, and the barrier layer 320 is formed on the reflective layer 310 except for the first group of first insulating regions 6001. In other words, the reflective layer 310 and the barrier layer 320 are formed only in the second group of first insulating openings 6002. The periphery 3101 of the reflective layer 310 may be aligned with the periphery 3001 of the transparent conductive structure 300 or formed outside the periphery 3001 of the transparent conductive structure 300. The periphery 3201 of the barrier layer 320 may be aligned with the peripheral edge 3101 of the reflective layer 310 or formed outside the periphery 3101 of the reflective layer 310. When the periphery 3201 of the barrier layer 320 is formed outside the periphery 3101 of the reflective layer 310, the reflective layer 310 is covered by the barrier layer 320, and the barrier layer 320 contacts the second semiconductor layer 102. The periphery 3201 of the barrier layer 320 and the periphery 3101 of the reflective layer 310 are separated from the first insulating layer 6000. The material of the reflective layer 310 includes silver (Ag), gold (Au), aluminum (Al), titanium (T), chromium (Cr), copper (Cu), nickel (Ni), platinum (Pt) or alloys thereof. The material of the barrier layer 320 includes chromium (Cr), platinum (Pt), titanium (Ti), titanium tungsten (TiW), tungsten (W) or zinc (Zn). The plurality of barrier layers 320 are formed by alternately stacking a first barrier layer (not shown) and a second barrier layer (not shown), such as Cr / Pt, Cr / Ti, Cr / TW, Cr / W, Cr / Zn, Ti / Pt, Ti / W, Ti / TiW, Ti / Zn, Pt / TiW, Pt / W, Pt / Zn, TiW / W, TiW / Zn, or W / Zn.

[0074] like Fig. 7A and Figure 7B As shown, a second insulating layer 700 continuously covers the upper portion and the oblique sidewall 1021 of one or more semiconductor structures 1000. The second insulating layer 700 includes a first group of second insulating openings 7001 corresponding to the plurality of through holes 120, wherein in forming the first group of second insulating openings 7001, the first group of first insulating regions 6001 of the first insulating layer 6000 in the plurality of through holes 120 are partially etched away to form a plurality of first insulating openings 6003, and the first group of second insulating openings 7001 and the plurality of first insulating openings 6003 are used to expose the surface 1012S of the first semiconductor layer 101. The second insulating layer 700 also includes a second group of second insulating openings 7002 formed on the upper portion of a portion of the plurality of semiconductor structures 1000 to expose the blocking layer 320 and / or the reflective layer 310. The second insulating layer 700 includes silicon oxide or silicon nitride. In another embodiment, the plurality of second insulating layers 700 form a distributed Bragg reflector, which is formed by alternately stacking insulating layers with different refractive indices. For example, by alternately stacking SiO x / TiO x to form.

[0075] like Fig. 8A and Figure 8B As shown, the metal layer 200 covers the one or more semiconductor structures 1000 and the plurality of through holes 120 except for the region corresponding to the second group of second insulating openings 7002. Specifically, the metal layer 200 continuously covers the upper portion and the oblique sidewalls 1021 of the one or more semiconductor structures 1000, the plurality of through holes 120 and the surrounding surface 1011S of the first semiconductor layer 101. The patterned metal layer 200 serves as the contact structure of the previous embodiment, and includes one or more openings 2002 to expose the reflective layer 310 and / or the barrier layer 320, wherein the positions of the one or more openings 2002 correspond to the positions of the second group of second insulating openings 7002.

[0076] like Fig.9A and Fig. 9B As shown, the third insulating layer 800 continuously covers the upper portion and the oblique sidewalls 1021 of one or more semiconductor structures 1000, and the plurality of through holes 120. The third insulating layer 800 includes one or a first group of third insulating openings 8001 formed on the first metal layer 200, which corresponds to a portion of the plurality of through holes 120, wherein the one or a first group of third insulating openings 8001 exposes the first metal layer 200. In other words, the one or a first group of third insulating openings 8001 overlaps with a portion of the plurality of through holes 120. In another embodiment, the one or a first group of third insulating openings 8001 is formed on the first metal layer 200 outside the region corresponding to the plurality of through holes 120. In other words, as Fig.9AAs shown, one or a first group of third insulating openings 8001' and the plurality of through holes 120 do not overlap. The third insulating layer 800 further includes one or a second group of third insulating openings 8002 to correspond to one or a second group of second insulating openings 7002, wherein one or a second group of third insulating openings 8002 exposes the blocking layer 320 and / or the reflective layer 310. The third insulating layer 800 includes silicon oxide or silicon nitride. In another embodiment, the plurality of third insulating layers 800 can be alternately stacked by insulating layers having different refractive indices to form a distributed Bragg reflector. For example, SiO x / TiO x Alternate stacking to form.

[0077] like Fig. 10A and Fig. 10B As shown, the first welding portion 400 and the second welding portion 500 are formed on the third insulating layer 800. The first welding portion 400 and the second welding portion 500 are separated from each other by a minimum distance D greater than 30 μm, and preferably, the spacing between the first welding portion 400 and the second welding portion 500 is between 50 μm and 250 μm. The first welding portion 400 is connected to the first metal layer 200 through one or a first group of third insulating openings 8001, and the second welding portion 500 is connected to the reflective layer 310 and / or the barrier layer 320 through one or a second group of third insulating openings 8002.

[0078] Fig.11 FIG. 1 is a top view of a semiconductor light emitting element V according to another embodiment of the present invention. Fig.12 for Fig.11 A cross-sectional view of the semiconductor light emitting element V along CC', Fig.13 for Fig.11 A cross-sectional view of a semiconductor light emitting element V along line DD'. The semiconductor light emitting element V is a flip-chip light emitting element. Fig.12 and Fig.13As shown, the semiconductor light emitting element V includes a substrate 110, and a semiconductor stack 100 is formed on the substrate 110. The semiconductor stack 100 includes a first semiconductor layer 101, a second semiconductor layer 102, and an active layer 103 located between the first semiconductor layer 101 and the second semiconductor layer 102. In the present embodiment, the substrate 110 may be a growth substrate of the semiconductor stack 100, and the material of the substrate 110 includes a semiconductor material, such as gallium arsenide (GaAs), gallium phosphide (GaP), gallium nitride (GaN), silicon carbide (SiC) or aluminum nitride (AlN), or an insulating material, such as diamond, glass, quartz or sapphire. In another embodiment, the substrate 110 may be a supporting substrate that is bonded to the semiconductor stack 100 by a bonding material, including an organic material such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cycloolefin copolymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polyimide (PI), polycarbonate (PC), polyetherimide or fluorocarbon polymer, or an inorganic material such as silica gel, glass, aluminum oxide (Al2O3), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium dioxide (TiO2), or fluoride (MgF x ). The first semiconductor layer 101 and the second semiconductor layer 102, such as a cladding layer, include different conductivity, electrical properties, polarity or doping elements to provide electrons and holes. The active layer 103 is formed between the first semiconductor layer 101 and the second semiconductor layer 102. Under current injection, electrons and holes recombine in the active layer 103 to convert electrical energy into light energy to emit a light. The main wavelength of the light is adjusted by changing the physical and chemical composition of one or more layers in the semiconductor stack 100. The material of the semiconductor stack 100 includes III-V semiconductor materials, such as Al x In y Ga (1-x-y) N or Al x In y Ga (1-x-y) P, where 0≤x, y≤1; (x+y)≤1. Depending on the material of the active layer 103, the semiconductor stack 100 can emit red light with a dominant wavelength between 610nm and 650nm, green light with a dominant wavelength between 530nm and 570nm, blue light with a dominant wavelength between 450nm and 490nm, or ultraviolet light with a dominant wavelength between 230nm and 400nm. The active layer 103 includes a single heterostructure (SH), a double heterostructure (DH), a double-sided double heterostructure (DDH), or a multiple quantum well (MQW) structure. The material of the active layer t103 includes a neutral, p-type doped, or n-type doped semiconductor.

[0079] The active layer 103 and the second semiconductor layer 102 away from the periphery 1011 of the semiconductor stack 100 are partially removed to form a plurality of through holes 120. The plurality of through holes 120 pass through the semiconductor stack 100 to expose the surface 1012S of the first semiconductor layer 101. The active layer 103 and the second semiconductor layer 102 close to the periphery 1011 of the semiconductor stack 100 are removed to form an annular exposed surrounding surface 1011S of the first semiconductor layer 101, wherein the annular exposed surrounding surface 11011S is along the periphery of the semiconductor light emitting element V. In other words, the annular exposed surrounding surface 1011S surrounds the active layer 103 and the second semiconductor layer 102. In the present embodiment, the plurality of through holes 120 are arranged in a plurality of rows. The plurality of through holes 120 arranged on two adjacent rows may be aligned or staggered. Each of the plurality of through holes 120 includes a shape, such as a circle, an ellipse or a strip, in the top view of the semiconductor light emitting element V. A method for forming the plurality of through holes 120 includes wet etching or dry etching.

[0080] The first insulating layer 6000 is formed on the semiconductor stack 100 to surround the active layer 103 and protect the epitaxial quality of the active layer 103 from being damaged by subsequent manufacturing processes. The first insulating layer 6000 is patterned on the semiconductor stack 100 by photolithography technology to form a plurality of first insulating openings 6002, 6003. Fig.12 As shown, the plurality of first insulating openings 6002 , 603 of the first insulating layer 6000 expose the second semiconductor layer 102 and the first semiconductor layer 101 respectively.

[0081] The transparent conductive structure 300 is located on the first insulating opening 6002 on the second semiconductor layer 102. When current is injected, the transparent conductive structure 300 forms an electrical connection with the semiconductor stack 100. The material of the transparent conductive structure 300 includes a transparent material that is transparent to the light emitted by the active layer 103. The transparent conductive structure t300 can be a single-layer or multi-layer structure.

[0082] The reflective layer 310 is formed on the second semiconductor layer 102 to improve the light extraction efficiency of the semiconductor light emitting element V, and the barrier layer 320 is formed on the reflective layer 310 to protect the reflective layer 310 and prevent the metal element 310 of the reflective layer from diffusing outward. In one embodiment, the reflective layer 310 directly contacts the second semiconductor layer 102. In this embodiment, the reflective layer 310 directly contacts the transparent conductive structure 300. The sidewall of the barrier layer 320 may be aligned with the sidewall of the reflective layer 310 or extend beyond the sidewall of the reflective layer 310. When the sidewall of the barrier layer 320 is formed beyond the sidewall of the reflective layer 310, the reflective layer 310 is covered by the barrier layer 320, and a portion of the barrier layer 320 directly contacts the second semiconductor layer 102 or the transparent conductive structure 300. The material of the one or more reflective layers 310 includes a metal material with high reflectivity, such as silver (Ag), gold (Au), aluminum (Al), titanium (Ti), chromium (Cr), copper (Cu), nickel (Ni), platinum (Pt) or alloys thereof. The material of the one or more barrier layers 320 includes Cr, Pt, Ti, TiW, W or Zn. The plurality of barrier layers 320 may be formed by alternately stacking a first barrier layer (not shown) and a second barrier layer (not shown), such as Cr / Pt, Cr / Ti, Cr / TiW, Cr / W, Cr / Zn, Ti / Pt, Ti / W, Ti / TiW, Ti / W, Ti / Zn, Pt / TiW, Pt / W, Pt / Zn, TiW / W, TiW / Zn, or W / Zn.

[0083] The second insulating layer 700 is formed on the semiconductor stack 100 to surround the active layer 103. The second insulating layer 700 is patterned by photolithography to form a first group of second insulating openings 7001 and a second group of second insulating openings 7002 on the semiconductor stack 100. Fig.12 and Fig.13 As shown, the first group of second insulating openings 7001 of the second insulating layer 700 exposes the first semiconductor layer 101, and the second group of second insulating openings 7002 of the second insulating layer 700 exposes the blocking layer 320. In one embodiment, the first group of second insulating openings 7001 includes a width different from the width of the second group of second insulating openings 7002. In another embodiment, the number of the first group of second insulating openings 7001 is different from the number of the second group of second insulating openings 7001. In another embodiment, in the top view of the semiconductor light emitting element V, the second group of second insulating openings 7002 is formed on one side of the semiconductor stack 100. In another embodiment, the positions of the first group of second insulating openings 7001 correspond to the positions of the plurality of through holes 120, respectively.

[0084] Except for the area corresponding to the second group of second insulating openings 7002 and the sidewall of the periphery 1011 of the semiconductor light emitting element V, the patterned metal layer 200 covers a portion of the second semiconductor layer 102, a plurality of through holes 120 and an annular exposed peripheral surface 1011S, wherein the annular exposed surface 1011S is formed along the periphery 1011 of the semiconductor light emitting element V. Specifically, from the top view of the semiconductor light emitting element V, the area of ​​the patterned metal layer 200 is larger than the area of ​​the active layer 103. Fig.12 and Fig.13 As shown, a portion of the patterned metal layer 200 is formed on the transparent conductive structure 300 , the reflective layer 310 or the barrier layer 320 . The patterned metal layer 200 includes one or more openings 2002 to expose the reflective layer 310 and / or the barrier layer 320 .

[0085] In another embodiment, the patterned metal layer 200 covers a portion of the second semiconductor layer 102, a plurality of through holes 120, an exposed annular peripheral surface 1011S, and extends to the sidewall of the periphery 1011 of the semiconductor light emitting element V, and the sidewall of the periphery 1011 is the sidewall of the first semiconductor layer 101. In another embodiment, similar to the above embodiment, the patterned metal layer 200 can extend to the surface of the substrate 110 not covered by the first semiconductor layer 101. The material of the patterned metal layer 200 includes metals, such as Al, Cr, Pt, Ti, TiW, W or Zn.

[0086] The third insulating layer 800 is formed on the semiconductor stack 100. The third insulating layer 800 is patterned by photolithography technology to form a first group of third insulating openings 8001 and a second group of third insulating openings 8002 on the semiconductor stack 100. Fig.12 and Fig.13 As shown, the first group of third insulating openings 8001 of the third insulating layer 800 exposes the patterned metal layer 200. The second group of third insulating openings 8002 of the third insulating layer 800 exposes the transparent conductive structure 300, the reflective layer 310 or the barrier layer 320. In one embodiment, in the top view of the semiconductor light emitting element V, the first group of third insulating openings 8001 and the second group of third insulating openings 8002 are formed on both sides of the semiconductor stack 100. In another embodiment, the number of the first group of third insulating openings 8001 is different from the number of the second group of third insulating openings 8002.

[0087] The materials of the first insulating layer 6000, the second insulating layer 700 and the third insulating layer 800 include non-conductive materials, such as organic materials including Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cycloolefin copolymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polyimide (PI), polycarbonate (PC), polyetherimide or fluorocarbon polymer, or inorganic materials such as silica gel, glass, aluminum oxide (Al2O3), silicon nitride (SiNx), silicon oxide (SiO x ), titanium dioxide (TiO2), or fluoride (MgF x ). The first insulating layer 6000, the second insulating layer 700 and the third insulating layer 800 may be formed by screen printing, evaporation or sputtering.

[0088] The first welding portion 400 covers a portion of the plurality of through holes 120 and is electrically connected to the first semiconductor layer 101. The second welding portion 500 covers another portion of the plurality of through holes 120 and is electrically connected to the second semiconductor layer 102. The first welding portion 400 is electrically connected to the first semiconductor layer 101 through the first group of third insulating openings 8001 of the third insulating layer 800, and the second welding portion 500 is electrically connected to the second semiconductor layer 102 through the second group of third insulating openings 8002 of the third insulating layer 800 and the opening 2002 of the patterned metal layer 200. The materials of the first welding portion 400 and the second welding portion 500 include titanium (Ti), platinum (Pt), nickel (Ni), tin (Sn), gold (Au) or an alloy thereof. The area of ​​the first welding portion 400 may be the same as or different from the area of ​​the second welding portion 500.

[0089] Figure 14A to Figure 14B and Figures 15A to 21C The present invention is a method for manufacturing a semiconductor light emitting device T according to an embodiment of the present invention. Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A and Fig.21A For the floor plan. Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 20B , Fig. 21B They are Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A and Fig.21A Cross-sectional view along α-α'. Fig.18C , Fig.19C , Fig. 20C , Fig. 21C They are Fig.18A , Fig.19A , Fig. 20A and Fig.21A Cross-sectional view along β-β'.

[0090] like Fig.14A and Fig. 14B As shown, the manufacturing method of the semiconductor light emitting element T includes forming a semiconductor stack t100 on a growth substrate t110. The growth substrate t110 may be a sapphire substrate, but is not limited thereto. In one embodiment, the growth substrate t110 includes a patterned surface. The patterned surface includes a plurality of patterns. The shape of the pattern includes a cone, a pyramid or a hemisphere. The semiconductor stack t100 includes a first semiconductor layer t101 having a peripheral side surface t1011S, a second semiconductor layer t102, and an active layer t103 formed between the first semiconductor layer t101 and the second semiconductor layer t102. In one embodiment, the semiconductor stack t100 includes one or more first semiconductor layers t101 and one or more second semiconductor layers t102. In addition, the active layer t103 may have a single quantum well structure or a multiple quantum well structure. The semiconductor stack t100 may be formed of a III-nitride semiconductor on the growth substrate t110 by metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). A buffer layer (not shown) is formed before the semiconductor stack t100 to alleviate the lattice dislocation between the growth substrate t110 and the semiconductor stack t100, and is composed of a material of the III-nitride series, such as gallium nitride, aluminum gallium nitride, or aluminum nitride. In one embodiment, the semiconductor stack t100 includes one or more buffer layers. The buffer layer can be formed by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or physical vapor deposition (PVD). Physical vapor deposition (PVD) includes sputtering, such as reactive sputtering, or evaporation, such as electron beam evaporation and thermal evaporation. In one embodiment, the buffer layer includes an aluminum nitride (AlN) buffer layer and is formed by sputtering. The aluminum nitride (AlN) buffer layer is formed on a growth substrate having a patterned surface. The sputtering method can form a dense buffer layer with high uniformity, so that the aluminum nitride (AlN) buffer layer can be conformably deposited on the patterned surface of the growth substrate.

[0091] After forming the semiconductor stack t100, the semiconductor stack t100 is patterned by photolithography and etching to form a plurality of first trenches t120a and a second trench t120b in the semiconductor stack t100, thereby defining a plurality of semiconductor structures t1000. Specifically, a plurality of first trenches t120a and a second trench t120b are formed by removing a portion of the first semiconductor layer t101, the second semiconductor layer t102, and the active layer t103, and exposing the surface t1012S of the first semiconductor layer t101 and forming a plurality of semiconductor structures t1000. Here, the peripheral side surface t1011S of the first semiconductor layer t101 is connected to the surface t1012S of the first semiconductor layer t101.

[0092] The plurality of semiconductor structures t1000 are connected to each other through a portion of the first semiconductor layer t101 located in the first trench t120a and the second trench t120b. In addition, each of the plurality of semiconductor structures t1000 includes a sloping sidewall t1021S. The upper surface t1000uS of the semiconductor structure t1000 and the surface t1012S of the first semiconductor layer t101 are connected through the sloping sidewall t1021S.

[0093] In the present embodiment, a plurality of first trenches t120a and second trenches t120b pass through the second semiconductor layer t102 and the active layer t103. The second trenches t120b expose the surrounding area of ​​the first semiconductor layer t101. The second trenches t120b are disposed at the outermost side of the semiconductor stack t100 and are adjacent to the outermost side of the active layer t103. In other words, the second trenches t120b are disposed around a growth substrate t110. Each of the plurality of first trenches t120a is located between the semiconductor structures t1000, and the plurality of first trenches t120a are surrounded by the second trenches t120b. The plurality of first trenches t120a and the second trenches t120b surround the active layer t103 and the second semiconductor layer t102. Here, one of the plurality of first trenches t120a includes a width W1 that is greater than a width W2 of the second trench t120b, for example, W1=2W2. A plurality of first trenches t120a are parallel to each other, and both ends of each of the plurality of first trenches t120a are connected to the second trench t120b. In a top view, the shape of one of the plurality of first trenches t120a includes a strip, and the shape of the second trench t120b includes a geometric shape, such as a ring. The second trench t120b surrounds the active layer t103 and the second semiconductor layer t102, and is disposed near the surrounding side surface t1011S of the first semiconductor layer t101. The plurality of first trenches t120a and the second trench t120b constitute a plurality of closed geometric shapes, such as a rectangle. In the present embodiment, the number of the second trench t120b is one. In a top view, the active layer t103 and the second semiconductor layer t102b are surrounded by the second trench t120b, but the present invention is not limited thereto.

[0094] like Fig. 14C and Fig.14D As shown, Fig. 14C A top view of a trench in a semiconductor stack t100 ′ on a substrate t110 according to an embodiment of the present invention is illustrated. Fig.14D The top view of the trench in the semiconductor stack t100" on the substrate t110 according to one embodiment of the present invention is illustrated. The structures of the semiconductor stacks t100' and t100" are the same as the structure of the semiconductor stack t100. Fig. 14C As shown, the difference is Fig. 14C The illustrated plurality of first trenches t120a' and the plurality of second trenches t120b' are separated from each other and surround the active layer. Specifically, Fig. 14C Four first trenches t120a' are illustrated, and two first trenches t120a' branch out from two of the plurality of second trenches t120b'. Fig.14DA plurality of first trenches t120a'' and a plurality of second trenches t120b'' are illustrated. The plurality of second trenches t120b'' surround the active layer (not shown) and are disposed around the substrate t110. The plurality of second trenches t120b'' form a rectangular dotted ring.

[0095] like Fig.15A and Fig. 15B As shown, a transparent conductive structure t300 is formed on the second semiconductor layer t102 in a subsequent step. In one embodiment, the transparent conductive structure t300 directly contacts the second semiconductor layer t102 to diffuse current and inject current into the second semiconductor layer t102. The transparent conductive structure t300 does not contact the first semiconductor layer t101. The transparent conductive structure t300 includes a transparent conductive oxide layer, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The transparent conductive structure t300 can be configured to form a low resistance contact, such as an ohmic contact, with the second semiconductor layer t102. The transparent conductive structure t300 includes a single layer or multiple layers. For example, the transparent conductive structure t300 has multiple layers, and the transparent conductive structure t300 can be a distributed Bragg reflector (DBR), which includes multiple layers, one of which has a refractive index different from the refractive index of an adjacent layer. Specifically, the transparent conductive structure t300 forms a distributed Bragg reflector (DBR) by alternately stacking two layers of different materials with different refractive indices.

[0096] like Fig.16A and Fig. 16B As shown, a first insulating layer t600 covers the surrounding side surface t1011S of the first semiconductor layer t101, the surface t1012S and the oblique sidewall t1021S of the first semiconductor layer t101. In other words, the first insulating layer t600 includes a first group of first insulating regions t600a formed on the surface t1012S and the oblique sidewall t1021S of the semiconductor structure t1000, and the first group of first insulating regions t600a corresponds to a plurality of first trenches t120a; and a second group of first insulating regions t600b formed on the surrounding side surface t1011S and the surface t1012S of the first semiconductor layer t101, and on the oblique sidewall t1021S corresponding to the second trench t120b. The material of the first insulating layer t600 may be a non-conductive material. Non-conductive materials include organic materials such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cycloolefin copolymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polyimide (PI), polycarbonate (PC), polyetherimide or fluorocarbon polymer, or inorganic materials such as silica gel, glass, aluminum oxide (Al2O3), silicon nitride (SiN x ), silicon oxide (SiO x), titanium dioxide (TiO2), or fluoride (MgF x ). The first insulating layer t600 includes a single layer or multiple layers. The multiple first insulating layers t600 may form a distributed Bragg reflector (DBR), and the refractive index of one layer is different from the refractive index of the adjacent layer. Specifically, by SiO x and TiO x Alternate stacking to form a distributed Bragg reflector (DBR). Through the difference between the high refractive index and the low refractive index of two adjacent layers, the distributed Bragg reflector provides a high reflectivity for a specific wavelength or a specific wavelength range. The thickness of the two adjacent layers can be different. Alternatively, the two adjacent layers have the same material, but their thickness is different.

[0097] like Fig.17A and Fig. 17B As shown, a reflective layer t310 is formed on the transparent conductive structure t300 and aligned with the transparent conductive structure t300. The shape of the reflective layer t310 corresponds to the shape of the transparent conductive structure t300. In this embodiment, the shape of the reflective layer t310 is close to a rectangle, and the corners of the reflective layer t310 are arc-shaped. An embodiment of the present invention may include one or more reflective layers t310, and the material of the reflective layer t310 includes a metal material with high reflectivity for the light emitted by the active layer t103, such as silver (Ag), gold (Au), aluminum (Al), titanium (Ti), chromium (Cr), copper (Cu), nickel (Ni), platinum (Pt) or its alloy. A barrier layer (not shown) is formed and covered on the reflective layer t310, and the barrier layer can prevent the metal elements in the reflective layer t310 from migrating, diffusing or oxidizing. An embodiment of the present invention includes one or more barrier layers, and the material of the barrier layer includes chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W) or zinc (Zn). Multiple barrier layers can be formed by alternately stacking a first barrier layer (not shown) and a second barrier layer (not shown), such as Cr / Pt, Cr / Ti, Cr / TiW, Cr / W, Cr / Zn, Ti / Pt, Ti / W, Ti / TiW, Ti / Zn, Pt / TiW, Pt / W, Pt / Zn, TiW / W, TiW / Zn, or W / Zn.

[0098] like Figures 18A to 18C As shown, Fig.18B and Fig.18C for Fig.18AA cross-sectional view along α-α' and a cross-sectional view along β-β'. After forming the reflective layer t310, an insulating layer is formed on the plurality of semiconductor structures t1000 and covers the reflective layer t310, the first group of first insulating regions t600a and the second group of first insulating regions t600b. Subsequently, a portion of the insulating layer is removed by photolithography and etching processes to expose the reflective layer t310, the surrounding side surface t1011S and the surface t1012S to form a second insulating layer t700. It should be noted that in the photolithography and etching processes in the same step, a portion of the first group of first insulating regions t600a is removed to expose the surface t1012S. In the present embodiment, the second insulating layer t700 includes a group of second insulating openings t7001 and exposes the reflective layer t310. The shape of the exposed reflective layer t310 corresponds to the shape of the group of second insulating openings t7001. The material of the second insulating layer t700 can be a non-conductive material. Here, the non-conductive material includes an organic material such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cycloolefin copolymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polyimide (PI), polycarbonate (PC), polyetherimide or fluorocarbon polymer, or an inorganic material such as silica gel, glass, alumina (Al2O3), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium dioxide (TiO2), or fluoride (MgF x ). One embodiment of the present invention includes one or more second insulating layers t700. The plurality of second insulating layers t700 may form a distributed Bragg reflector (DBR), and the refractive index of one layer is different from the refractive index of the adjacent layer. Specifically, by SiO x and TiO x Alternate stacking to form a distributed Bragg reflector (DBR). Through the difference between the high refractive index and the low refractive index of two adjacent layers, the distributed Bragg reflector provides a high reflectivity for a specific wavelength or a specific wavelength range. The thickness of the two adjacent layers can be different. The two adjacent layers have the same material but different thicknesses.

[0099] like Figures 19A to 19C As shown, Fig.19A For the top view, Fig.19B and Fig.19C for Fig.19A A cross-sectional view along α-α' and β-β'. After the second insulating layer t700 is formed, a patterned metal layer t200 is formed on the second semiconductor layer t102, the second insulating layer t700 and the reflective layer t310. Figures 19A to 19CAs shown, the patterned metal layer t200 includes a first metal region t200a, a second metal region t200b and a plurality of annular openings t2001. Each of the first metal region t200a and the second metal region t200b can be continuous or divided into a plurality of parts. In the present embodiment, the first metal region t200a is divided into a group of sub-regions t200a1, t200a2, t200a3 by the annular opening t2001. The second metal region t200b in the patterned metal layer t200 is continuously formed on the second semiconductor layer t102, and is filled with a plurality of first trenches t120a and second trenches t120b and covers a plurality of semiconductor structures t1000. In a top view, a group of sub-regions t200a1, t200a2, t200a3 includes a plurality of rectangular patterns surrounded by the second metal region t200b. Since the plurality of annular openings t2001 surround a group of sub-regions t200a1, t200a2, t200a3 respectively, the first metal region t200a is electrically isolated from the second metal region t200b. In the present embodiment, the outline of the patterned metal layer t200 is substantially rectangular. A group of sub-regions t200a1, t200a2, t200a3 covers the exposed portion of the reflective layer t310 corresponding to a group of second insulating openings t7001, and is electrically connected to the second semiconductor layer t102 through the reflective layer t310 and the transparent conductive structure t300. In addition, the second metal region t200b is continuously formed on the second insulating layer t700, fills in the plurality of first trenches t120a and second trenches t120b, covers the surrounding side surface t1011S, the oblique side wall t1021S and the surface t1012S of the first semiconductor layer t101, and contacts the surrounding side surface t1011S and the surface t1012S of the first semiconductor layer t101. Therefore, the second metal region t200b is electrically connected to the first semiconductor layer t101. The functions of the first metal region t200a and the second metal region t200b are similar to those of the contact structure of the previous embodiment.

[0100] An embodiment of the present invention is similar to the above embodiment. Fig. 14C As shown, the second metal region t200b continuously covers the semiconductor stack t100' and the other layers mentioned above, and extends to fill the plurality of first trenches t120a' and the plurality of second trenches t120b'. The second metal region t200b covers the surrounding side surface t1011S and the oblique sidewall t1021S, discontinuously contacts the surface t1012S of the first semiconductor layer t101 in the first trench t120a' and the second trench t120b', and is electrically connected to the first semiconductor layer t101. Specifically, corresponding to Fig.19AThe second metal region t200b shown is located in the first trench t120a and the second trench t120b, the first trench t120a' and the second trench t120b' are discontinuous, and the second metal region t200b directly contacts the surface t1012S of the first semiconductor layer t101 via the plurality of first trenches t120a' and the plurality of second trenches t120b'. From the perspective of top view, the second metal region t200b directly contacting the surface t1012S of the first semiconductor layer t101 includes a shape corresponding to the shape formed by the plurality of first trenches t120a' and the plurality of second trenches t120b'. In another embodiment similar to the above embodiment, as Fig.14D As shown, the second metal region t200b continuously covers the semiconductor stack t100" and other layers, and extends to fill in the plurality of first trenches t120a" and the plurality of second trenches t120b". The second metal region t200b covers the surrounding side surface t1011S and the oblique sidewall t1021S, and discontinuously contacts the surface t1012S of the first semiconductor layer t101 in the first trench t120a' and the second trench t120b', thereby being electrically connected to the first semiconductor layer t101. Corresponding to Fig.19A The second metal region t200b shown is located in the first trench t120a and the second trench t120b, and the first trench t120a' and the second trench t120b" are discontinuous. Part of the second metal region t200b directly contacts the surface t1012S of the first semiconductor layer t101 through multiple first trenches t120a" and multiple second trenches t120b", and from the perspective of top view, the position where the second metal region t200b directly contacts the surface t1012S of the first semiconductor layer t101 corresponds to the position of the multiple first trenches t120a" and the multiple second trenches t120b". It should be noted that the same figure marks are used in each embodiment to represent the same or similar elements of the embodiment, and redundant details thereof are omitted.

[0101] like Figure 20A to Figure 20C As shown, Fig. 20A For the top view, Fig. 20B and Fig. 20C for Fig. 20ACross-sectional view along lines α-α' and β-β'. After the patterned metal layer t200 is formed, a third insulating layer t800 continuously covers the plurality of semiconductor structures t1000 and the oblique sidewalls t1021S of the plurality of semiconductor structures t1000, and fills the plurality of first trenches t120a and second trenches t120b. From a top viewpoint, the third insulating layer t800 includes a first insulating region t800a, a first group of third insulating openings t8001 and a second group of third insulating openings t8002, wherein the first group of third insulating openings t8001 includes one or more openings, and the second group of third insulating openings t8002 includes one or more openings. The first group of third insulating openings t8001 exposes a group of sub-regions t200a1, t200a2, t200a3, respectively, and the second group of third insulating openings t8002 exposes the second metal region t200b. The material of the third insulating layer t800 includes a non-conductive material. Here, the non-conductive material includes an organic material such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cycloolefin copolymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polyimide (PI), polycarbonate (PC), polyetherimide or fluorocarbon polymer, or an inorganic material such as silica gel, glass, alumina (Al2O3), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium dioxide (TiO2), or fluoride (MgF x ). One embodiment of the present invention includes one or more third insulating layers t800. The plurality of third insulating layers t800 may form a distributed Bragg reflector (DBR), and the refractive index of one layer is different from the refractive index of the adjacent layer. Specifically, by SiO x and TiO x Alternate stacking to form a distributed Bragg reflector (DBR). Through the difference between the high refractive index and the low refractive index of two adjacent layers, the distributed Bragg reflector can provide a high reflectivity for a specific wavelength or a specific wavelength range. The thickness of the two adjacent layers can be different, for example, the two adjacent layers have the same material but different thicknesses.

[0102] like Fig.21A , Fig. 21B , Fig. 21C As shown, according to one embodiment of the present invention, Fig.21A A top view of the semiconductor light emitting element T when the manufacturing method is completed. Fig. 21B and Fig. 21C for Fig.21ACross-sectional view along the α-α' line and the β-β' line. The manufacturing method of the semiconductor light emitting element T also includes forming a plurality of first welding portions t400 and a plurality of second welding portions t500 after forming the third insulating layer t800. Here, the plurality of first welding portions t400 are formed on the third insulating layer t800, and respectively contact the first metal region t200a including a group of sub-regions t200a1, t200a2, t200a3 through the first group of third insulating layer openings t8001, so that the plurality of first welding portions t400 are electrically connected to the second semiconductor layer t102. At the same time, the plurality of second welding portions t500 are formed on the third insulating layer t800, and contact the second metal region t200b of the patterned metal layer t200 through the second group of third insulating openings t8002, so that the second welding portions t500 are electrically connected to the first semiconductor layer t101. In addition, the plurality of first welding portions t400 are separated from the plurality of second welding portions t500. In addition, the plurality of first welding portions t400 are separated from each other and arranged in a row to be aligned with the plurality of second welding portions t500 .

[0103] like Figures 21A to 21C As shown, the semiconductor light emitting element T includes a substrate t110, and a semiconductor stack t100 is formed on the substrate t110. The semiconductor stack t100 includes a first semiconductor layer t101 having a peripheral side surface t1011S, a second semiconductor layer t102, and an active layer t103 located between the first semiconductor layer t101 and the second semiconductor layer t102. In the present embodiment, the substrate t110 may be a growth substrate of the semiconductor stack t100, and the material of the substrate t110 includes a semiconductor material, such as gallium arsenide (GaAs), gallium phosphide (GaP), gallium nitride (GaN), silicon carbide (SiC) or aluminum nitride (AlN), or an insulating material, such as diamond, glass, quartz or sapphire. In another embodiment, the substrate t110 can be a supporting substrate bonded to the semiconductor stack t100 by an adhesive material, the adhesive material including an organic material such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cycloolefin copolymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polyimide (PI), polycarbonate (PC), polyetherimide or fluorocarbon polymer, or an inorganic material such as silica gel, glass, aluminum oxide (Al2O3), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium dioxide (TiO2), or fluoride (MgF x). The first semiconductor layer t101 and the second semiconductor layer t102, such as a cladding layer, include different conductivity, electrical properties, polarity or doping elements to provide electrons and holes. The active layer t103 is formed between the first semiconductor layer t101 and the second semiconductor layer t102. Under current injection, electrons and holes recombine in the active layer t103 to convert electrical energy into light energy and then emit a light. The main wavelength of the light is adjusted by changing the physical and chemical composition of one or more layers in the semiconductor stack t100. The material of the semiconductor stack t100 includes III-V semiconductor materials, such as Al x In y Ga (1-x-y) N or Al x In y Ga (1-x-y) P, where 0≤x, y≤1; (x+y)≤1. Depending on the material of the active layer t103, the semiconductor stack t100 can emit red light with a dominant wavelength between 610nm and 650nm, green light with a dominant wavelength between 530nm and 570nm, blue light with a dominant wavelength between 450nm and 490nm, or ultraviolet light with a dominant wavelength between 230nm and 400nm. The active layer t103 includes a single heterostructure (SH), a double heterostructure (DH), a double-sided double heterostructure (DDH), or a multiple quantum well (MQW) structure. The doping methods of the active layer t103 include unintentional doping, p-type doping, or n-type doping.

[0104] Part of the active layer t103 and the second semiconductor layer t102 are removed to form a plurality of first trenches t120a, a second trench t120b and a plurality of semiconductor structures t1000. The plurality of first trenches t120a and the second trench t120b pass through the semiconductor stack t100 to expose the surface t1012S of the first semiconductor layer t101. The second trench t120b is disposed at the outermost side of the semiconductor stack t100, and each of the plurality of first trenches t120a is located between the semiconductor structures t1000. The plurality of first trenches t120a and the second trench t120b surround the active layer t103 and the second semiconductor layer t102. In addition, each of the plurality of first trenches t120a includes two ends, at least one of which is connected to the second trench t120b. Among them, one of the plurality of first trenches t120a includes a width W1 greater than a width W2 of the second trench t120b, for example, W1=2W2. The plurality of first trenches t120a are parallel to each other, and both ends t120a of each first trench are connected to the second trench t120b. From a top viewpoint, one of the plurality of first trenches t120a includes a shape, such as a rectangle, and the second trench t120b includes a geometric shape to surround the active layer t103, such as a ring. The number of the second trenches t120b is one, and the active layer t103 and the second semiconductor layer t102b are disposed in the second trench t120b from a top viewpoint, but are not limited thereto.

[0105] The transparent conductive structure t300 is formed on the second semiconductor layer t102. When current is injected, the transparent conductive structure t300 forms an electrical connection with the semiconductor stack t100. The material of the transparent conductive structure t300 includes a transparent material that is transparent to the light emitted by the active layer t103. The structure of the transparent conductive structure t300 can be a single layer or a multilayer.

[0106] The first insulating layer t600 covers the peripheral side surface t1011S of the first semiconductor layer t101 in the plurality of first trenches t120a and the second trenches t120b and the surface t1012S of the first semiconductor layer t101, and covers the oblique sidewall t1021S of the semiconductor stack t100, so as to protect the epitaxial quality of the semiconductor stack t100 from being damaged by subsequent manufacturing processes. The first insulating layer t600 is patterned by photolithography to form a first group of first insulating regions t600a corresponding to the plurality of first trenches t120a and a second group of first insulating regions t600b corresponding to the second trenches t120b.

[0107] The reflective layer t310 is formed on the transparent conductive structure t300 and aligned with the transparent conductive structure t300 to improve the light extraction efficiency of the semiconductor light emitting element T. In addition, a barrier layer (not shown) is formed and covered on the reflective layer t310, so that the barrier layer can prevent the metal elements in the reflective layer t310 from migrating, diffusing or oxidizing. In one embodiment, the reflective layer t310 directly contacts the transparent conductive structure t300. The sidewall of the barrier layer can be aligned with the sidewall of the reflective layer t310 or extend beyond the sidewall of the reflective layer t310. When the sidewall of the barrier layer extends beyond the sidewall of the reflective layer t310, the reflective layer t310 is covered by the barrier layer, and a portion of the barrier layer directly contacts the second semiconductor layer t102 or the transparent conductive structure t300. One embodiment of the present invention includes one or more reflective layers t310, and the material of the reflective layer t310 includes a metal material with high reflectivity, such as silver (Ag), gold (Au), aluminum (Al), titanium (Ti), chromium (Cr), copper (Cu), nickel (Ni), platinum (Pt) or alloys thereof. One embodiment of the present invention includes one or more barrier layers, and the material of the barrier layers includes chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W) or zinc (Zn). Multiple barrier layers can be formed by alternately stacking a first barrier layer (not shown) and a second barrier layer (not shown), such as Cr / Pt, Cr / Ti, Cr / TiW, Cr / W, Cr / Zn, Ti / Pt, Ti / W, Ti / TiW, Ti / W, Ti / Zn, Pt / TiW, Pt / W, Pt / Zn, TiW / W, TiW / Zn, or W / Zn.

[0108] The second insulating layer t700 covers a portion of the reflective layer t310 and the oblique sidewalls t1021S of the plurality of semiconductor structures t1000. The second insulating layer t700 is patterned by photolithography to expose the surrounding side surfaces t1011S and the surface t1012S of the first semiconductor layer t101 and form a first group of second insulating openings t7001, wherein the first group of second insulating openings t7001 of the second insulating layer t700 exposes a portion of the reflective layer t310.

[0109] The patterned metal layer t200 is located on the second insulating layer t700 and the partial reflective layer t310, and is filled into a plurality of first trenches t120a and second trenches t120b to cover a plurality of semiconductor structures t1000. The patterned metal layer t200 includes a first metal region t200a, a second metal region t200b and a plurality of annular openings t2001. The first metal region t200a includes a group of sub-regions t200a1, t200a2, t200a3. The plurality of annular openings t2001 surround a group of sub-regions t200a1, t200a1, t200a2, t200a3 respectively. In one embodiment, a group of sub-regions t200a1, t200a2, t200a3 are electrically connected to the second semiconductor layer t102 through the reflective layer t310 and the transparent conductive structure t300. In addition, the second metal region t200b continuously covers the second insulating layer t700, and fills the plurality of first trenches t120a and second trenches t120b to cover the surrounding side surface t1011S, contacting the surrounding side surface t1011S and the surface t1012S of the first semiconductor layer t101. Therefore, the second metal region t200b is electrically connected to the first semiconductor layer t101. In another embodiment, similar to the above embodiment, the patterned metal layer t200 may extend to the surface of the substrate t110 not covered by the first semiconductor layer t101. One embodiment of the present invention includes one or more patterned metal layers t200. The material of the patterned metal layer t200 includes a metal, such as aluminum (Al), chromium (Cr), platinum (Pt), titanium (Ti), tungsten (W) or zinc (Zn).

[0110] The third insulating layer t800 is located on the semiconductor stack t100. The third insulating layer t800 is patterned by photolithography to form a first insulating region t800a, a first group of third insulating openings t8001, and a second group of third insulating openings t8002 on the semiconductor stack t100. The first group of third insulating openings t8001 of the third insulating layer t800 exposes the patterned metal layer t200. The first group of third insulating openings t8001 exposes several portions of the sub-regions t200a1, t200a2, and t200a3. The second group of third insulating openings t8002 exposes multiple portions of the second metal region t200b, respectively. In one embodiment, in the top view of the semiconductor light emitting element T, the first group of third insulating openings t8001 and the second group of third insulating openings t8002 are located on both sides of the semiconductor stack t100. In one embodiment, the number of the first group of third insulating openings t8001 is different from the number of the second group of third insulating openings t8002.

[0111] The materials of the first insulating layer t600, the second insulating layer t700 and the third insulating layer t800 include non-conductive materials, such as organic materials including Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cycloolefin copolymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polyimide (PI), polycarbonate (PC), polyetherimide or fluorocarbon polymer, or inorganic materials such as silica gel, glass, aluminum oxide (Al2O3), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium dioxide (TiO2), or fluoride (MgF x ). The first insulating layer t600, the second insulating layer t700 and the third insulating layer t800 may be formed by screen printing, evaporation or sputtering.

[0112] A plurality of first welding portions t400 are located on the second semiconductor layer t102 and the third insulating layer t800, and respectively contact the sub-regions t200a1, t200a2, t200a3 of the first metal region t200a of the patterned metal layer t200 through the first group of third insulating openings t8001, so that the plurality of first welding portions t400 are electrically connected to the second semiconductor layer t102 through the sub-regions t200a1, t200a2, t200a3. At the same time, a plurality of second welding portions t500 are formed on the second semiconductor layer t102 and the third insulating layer t800, and contact the second metal region t200b of the patterned metal layer t200 through the second group of third insulating openings t8002, so that the plurality of second welding portions t500 are electrically connected to the first semiconductor layer t101. It should be noted that the plurality of first welding portions t400 or the plurality of second welding portions t500 do not directly contact the patterned metal layer t200 located in the plurality of first grooves t120a and the second grooves t120b. In addition, the shapes of the plurality of first welding portions t400 include a plurality of first shapes, the shapes of the plurality of second welding portions t500 include a plurality of second shapes, and the plurality of first welding portions t400 are separated from each other and from the plurality of second welding portions t500. The first shape and the second shape may be the same or different. In one embodiment, the first shape and the second shape include the same shape, such as a rectangle. In addition, the plurality of first welding portions t400 are arranged in a row and aligned with the plurality of second welding portions t500, and are surrounded by the plurality of first grooves t120a and the second grooves t120b. As described above, the plurality of first grooves t120a and the second grooves t120b constitute a plurality of rectangles, and in a top view, each of the plurality of first welding portions t400 or the plurality of second welding portions t500 is a rectangle. The material of the plurality of first welding portions t400 and the plurality of second welding portions t500 includes a metal, such as titanium (Ti), platinum (Pt), nickel (Ni), tin (Sn), gold (Au), or an alloy thereof. The area of ​​one of the plurality of first welding portions t400 may be the same as or different from the area of ​​one of the plurality of second welding portions t500.

[0113] In the light emitting element T of the present invention, the patterned metal layer t200 located in the trenches t120a and t120b can evenly diffuse the current, thereby improving the reliability of the light emitting element T and reducing the forward voltage.

[0114] Fig. 22 Schematic diagram of another embodiment of the present invention. A bulb lamp 600 includes a lampshade 602, a lens 604, a light emitting module 610, a lamp holder 612, a heat sink 614, a connecting portion 616 and an electrical connecting element. The light emitting module 610 includes a supporting portion 606 and a plurality of semiconductor light emitting elements 608 in the above-mentioned embodiments on the supporting portion 606.

[0115] The embodiments listed in the present invention are only used to illustrate the present invention, and are not used to limit the scope of the present invention. Any obvious modification or change made by anyone to the present invention does not deviate from the spirit and scope of the present invention.

Claims

1. A semiconductor light emitting element, characterized in that: Include: A semiconductor stack comprising a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; A first trench, passing through the second semiconductor layer and the active layer to expose a portion of the upper surface of the first semiconductor layer; A second trench, passing through the second semiconductor layer and the active layer to expose another portion of the upper surface and the surrounding side surface of the first semiconductor layer, wherein the first trench branches out from the second trench, the second trench is located at the outermost side of the active layer and surrounds the semiconductor stack and the first trench; a reflective layer formed on the second semiconductor layer; A second insulating layer covers the reflective layer and the oblique sidewalls of the semiconductor stack and comprises a first group of second insulating openings exposing the reflective layer; A plurality of first metal regions are respectively located in the first group of second insulating openings and connected to the reflective layer; A second metal region is located on the second semiconductor layer and is filled in the first trench and the second trench, wherein the second metal region is electrically connected to the first semiconductor layer via the first trench and the second trench; A plurality of first welding portions, located on the second semiconductor layer and electrically connected to the plurality of first metal regions; as well as A plurality of second welding portions are located on the second semiconductor layer and electrically connected to the second metal region. 2 . The semiconductor light emitting device as claimed in claim 1 , wherein one end of the first trench is not connected to the second trench. The semiconductor light emitting device as claimed in claim 1 , wherein two ends of the first trench are respectively connected to the second trench. The semiconductor light emitting device as claimed in claim 1 , wherein a width of the first trench is greater than a width of the second trench. 5 . The semiconductor light emitting device as claimed in claim 1 , wherein the second metal region comprises a portion of the second metal region filled in the second trench, and the portion of the second metal region is not in direct contact with the plurality of first soldering portions and the plurality of second soldering portions. The semiconductor light emitting device as claimed in claim 1 , wherein the plurality of first welding portions and the plurality of second welding portions do not cover the first groove and the second groove.

7. The semiconductor light emitting element as described in claim 1 comprises a third insulating layer, located between the semiconductor stack and the plurality of first welding portions and between the semiconductor stack and the plurality of second welding portions, wherein the third insulating layer comprises a first group of third insulating openings and a second group of third insulating openings, the plurality of first welding portions are electrically connected to the second semiconductor layer through the first group of third insulating openings, and the plurality of second welding portions are electrically connected to the first semiconductor layer through the second group of third insulating openings. 8 . The semiconductor light emitting device as claimed in claim 7 , wherein in a top view of the semiconductor light emitting device, the first group of third insulating openings and the second group of third insulating openings do not overlap with the first trench.

9. A semiconductor light emitting element, characterized in that: Include: A semiconductor stack comprising a first semiconductor layer, a second semiconductor layer, and an active layer located between the first semiconductor layer and the second semiconductor layer; A plurality of first trenches passing through the second semiconductor layer and the active layer to expose a portion of the upper surface of the first semiconductor layer; A second trench, passing through the second semiconductor layer and the active layer to expose another portion of the upper surface and the surrounding side surface of the first semiconductor layer, wherein the plurality of first trenches branch out from the second trench, the second trench is located at the outermost side of the active layer and surrounds the semiconductor stack and the plurality of first trenches; a reflective layer formed on the second semiconductor layer; A second insulating layer covers the reflective layer and the oblique sidewalls of the semiconductor stack and comprises a first group of second insulating openings exposing the reflective layer; A plurality of first metal regions are respectively located in the first group of second insulating openings and connected to the reflective layer; A second metal region is located on the second semiconductor layer and is filled in the plurality of first trenches and the second trench, wherein the second metal region is electrically connected to the first semiconductor layer via the plurality of first trenches and the second trench; A first welding portion, located on the second semiconductor layer and electrically connected to the second semiconductor layer via the plurality of first metal regions; A second welding portion, located on the second semiconductor layer and electrically connected to the first semiconductor layer via the second metal region; as well as A third insulating layer is located between the semiconductor stack and the first welding portion and between the semiconductor stack and the second welding portion, wherein the third insulating layer includes a first group of third insulating openings and a second group of third insulating openings, the first welding portion is electrically connected to the second semiconductor layer through the first group of third insulating openings, and the second welding portion is electrically connected to the first semiconductor layer through the second group of third insulating openings. 10 . The semiconductor light emitting device as claimed in claim 9 , wherein one end of each of the plurality of first trenches is not connected to the second trench. The semiconductor light emitting device as claimed in claim 9 , wherein two ends of each of the plurality of first trenches are respectively connected to the second trench. 12 . The semiconductor light emitting device as claimed in claim 9 , wherein a width of one of the plurality of first trenches is greater than a width of the second trench. The semiconductor light emitting device as claimed in claim 9 , wherein the plurality of first trenches are parallel to each other. 14 . The semiconductor light emitting device as claimed in claim 9 , wherein the second metal region comprises a portion of the second metal region filled in the second trench, and the portion of the second metal region is not in direct contact with the first soldering portion and the second soldering portion. 15 . The semiconductor light emitting device as claimed in claim 9 , wherein the first soldering portion and the second soldering portion do not cover the plurality of first grooves and the second grooves. 16 . The semiconductor light emitting device as claimed in claim 9 , wherein in a top view of the semiconductor light emitting device, the first group of third insulating openings and the second group of third insulating openings do not overlap with the plurality of first trenches.

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