Vertical nonvolatile memory device and method of manufacturing the same

Abstract

A vertical nonvolatile memory device and a manufacturing method thereof are provided, the vertical nonvolatile memory device including a substrate having a cell array region of block cells and an extension region, a vertical contact disposed in the extension region, a plurality of vertical channel structures disposed on the substrate in the cell array region, a plurality of dummy channel structures disposed on the substrate in the extension region, and a plurality of gate electrode layers and a plurality of interlayer insulating layers alternately stacked on the substrate. In an electrode pad connected to the vertical contact, the dummy channel structures are disposed on both sides of the vertical contact, and a horizontal cross section of each of the plurality of dummy channel structures has a shape longer in one direction.

Description

[0001] Cross-reference to related applications

[0002] Priority is claimed to Korean Patent Application No. 10-2019-0175495, filed on December 26, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to a non-volatile memory device and a method for manufacturing the same, and more specifically, to a non-volatile memory device and a method for manufacturing the same having a vertical channel structure with increased integration density. Background Technology

[0004] Recently, the use of non-volatile memory devices in electronic devices has increased significantly. For example, MP3 players, digital cameras, mobile phones, camcorders, flash memory cards, and solid-state drives (SSDs) typically include non-volatile memory as storage devices. Among different types of non-volatile memory, flash memory has the ability to electrically erase data one cell at a time and is more widely used as a storage device than hard disk drives. Recently, given the demand for increased storage capacity, a more efficient method for utilizing the storage space of flash memory has been needed. Therefore, as an alternative to using planar transistor structures, non-volatile memory devices with vertical transistor structures have been developed. Summary of the Invention

[0005] Embodiments of the present invention provide a vertical non-volatile memory device with improved reliability and integration, and a method for manufacturing the vertical non-volatile memory device.

[0006] An embodiment of the present invention provides a vertical non-volatile memory device comprising: a substrate having a cell array region and an extension region extending from the cell array region in a first direction parallel to a top surface of the substrate; vertical direct contacts disposed on the substrate in the extension region and extending in a vertical direction perpendicular to the top surface of the substrate; a plurality of vertical channel structures located on the substrate in the cell array region and extending in a vertical direction; a plurality of pseudo-channel structures located on the substrate in the extension region and extending in a vertical direction, and configured adjacent to the vertical direct contacts; a plurality of gate electrode layers and a plurality of interlayer insulating layers alternately stacked on the substrate in the cell array region and the extension region along the sidewalls of the plurality of vertical channel structures and the plurality of pseudo-channel structures; and electrode pads connected to the vertical direct contacts. In the electrode pad, the first pseudo-channel structure and the second pseudo-channel structure of the plurality of pseudo-channel structures are respectively disposed on the first side and the second side of the vertical direct contact in the first direction, and the horizontal cross-section of each of the plurality of pseudo-channel structures has a shape that is longer in the second direction than in the first direction, the second direction being parallel to the top surface of the substrate and extending perpendicular to the first direction.

[0007] An embodiment of the present invention also provides a vertical non-volatile memory device, comprising: a substrate having a cell array region and an extension region extending from the cell array region in a first direction parallel to the top surface of the substrate; a vertical direct contact disposed on the substrate in the extension region and extending in a vertical direction perpendicular to the top surface of the substrate; a plurality of vertical channel structures located on the substrate in the cell array region and extending in a vertical direction; a plurality of pseudo-channel structures located on the substrate in the extension region and extending in a vertical direction, and configured adjacent to the vertical direct contact; a plurality of gate electrode layers and a plurality of interlayer insulating layers alternately stacked on the substrate in the cell array region and the extension region along the sidewalls of the plurality of vertical channel structures and the plurality of pseudo-channel structures; and electrode pads connected to the vertical direct contact. In the electrode pads, the plurality of pseudo-channel structures are respectively disposed at square vertices relative to the vertical direct contact, and the vertical direct contact is located between the plurality of pseudo-channel structures, and the horizontal cross-section of each of the plurality of pseudo-channel structures is a trapezoidal shape with the vertices bent.

[0008] An embodiment of the present invention also provides a vertical non-volatile memory device, comprising: a substrate having a cell array region and an extension region extending from the cell array region in a first direction parallel to the top surface of the substrate; a plurality of vertical channel structures located on the substrate in the cell array region and extending in a vertical direction perpendicular to the top surface of the substrate; a plurality of vertical direct contacts disposed in the extension region and connected to corresponding electrode pads in a plurality of electrode pads; a plurality of pseudo-channel structures located on the substrate in the extension region and extending in a vertical direction, and respectively disposed adjacent to the plurality of vertical direct contacts; a plurality of gate electrode layers and a plurality of interlayer insulating layers alternately stacked on the substrate in the cell array region and the extension region along the sidewalls of the plurality of vertical channel structures and the plurality of pseudo-channel structures; and a partitioning region extending in the first direction and partitioning the plurality of gate electrode layers in a second direction parallel to the top surface of the substrate and perpendicular to the first direction. In at least one of the plurality of electrode pads, some of the plurality of pseudo-channel structures are disposed on both sides of the corresponding vertical direct contact in the first direction, the at least one electrode pad is connected to the corresponding vertical direct contact, and some portions of the pseudo-channel structures are arranged on a line passing through the corresponding vertical direct contact in the first direction.

[0009] Embodiments of the present invention also provide a method for manufacturing a vertical non-volatile memory device, the method comprising the steps of: designing a layout of a pattern of horizontal cross-sections of a pseudo-channel structure to be formed in electrode pads of the vertical non-volatile memory device; performing optical proximity correction (OPC) based on the layout to obtain design data for a mask; manufacturing a mask based on the design data; and forming the pseudo-channel structure using the mask. The vertical non-volatile memory device includes: a substrate having a cell array region and an extended region extending from the cell array region in a first direction; a vertical direct contact disposed in the extended region; and a partitioning region partitioning a gate electrode layer in a second direction perpendicular to the first direction, wherein the pseudo-channel structure is disposed in the electrode pads to surround the vertical direct contact, and a first pseudo-channel structure and a second pseudo-channel structure in the pseudo-channel structure are disposed on a first side and a second side of the vertical direct contact in the first direction, or four pseudo-channel structures in the pseudo-channel structure are disposed at the vertices of a square relative to the vertical direct contact, wherein the vertical direct contact is located between the four pseudo-channel structures. The layout design includes: designing the layout such that the distance between the pseudo-channel structure and the dividing area in the second direction is within a first set range, and the maximum distance between two pseudo-channel structures in the pseudo-channel structure in the diagonal direction across the vertical direct contact is within the second set range.

[0010] An embodiment of the present invention also provides a vertical non-volatile memory device, comprising: a substrate having a cell array region and an extended region extending from the cell array region in a first direction parallel to the top surface of the substrate; a vertical direct contact disposed on the substrate in the extended region and extending in a vertical direction perpendicular to the top surface of the substrate; a plurality of pseudo-channel structures located on the substrate in the extended region and extending in a vertical direction, and configured adjacent to the vertical direct contact; a plurality of gate electrode layers and a plurality of interlayer insulating layers alternately stacked along the sidewalls of the plurality of pseudo-channel structures. On the substrate in the cell array region and the extended region; an electrode pad connected to a vertical direct contact, the electrode pad including at least one first pseudo-channel structure and at least one second pseudo-channel structure among a plurality of pseudo-channel structures, the at least one first pseudo-channel structure being disposed on a first side of the vertical direct contact in a first direction, the at least one second pseudo-channel structure being disposed on a second side of the vertical direct contact in the first direction; and a dividing region extending in the first direction and dividing the plurality of gate electrode layers in a second direction, the second direction being parallel to the top surface of the substrate and extending perpendicular to the first direction. Attached Figure Description

[0011] Embodiments of the present invention will be described in detail with reference to the accompanying drawings, in which:

[0012] Figure 1 An equivalent circuit diagram of a memory cell array of a vertical non-volatile memory device according to an embodiment of the present invention is shown;

[0013] Figure 2 A plan view of a vertical non-volatile memory device according to an embodiment of the present invention is shown;

[0014] Figure 3 It shows along Figure 2 Cross-sectional views taken from lines I-I' and II-II' of a vertical non-volatile memory device;

[0015] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E and Figure 4F A plan view of the horizontal cross-section of the pseudo-channel structure and the vertical direct contact of the vertical non-volatile memory device according to an embodiment of the present invention is shown.

[0016] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E and Figure 5FA plan view of the horizontal cross-section of the pseudo-channel structure and the vertical direct contact of the vertical non-volatile memory device according to an embodiment of the present invention is shown.

[0017] Figure 6A , Figure 6B , Figure 6C , Figure 6D and Figure 6E A plan view of the horizontal cross-section of the pseudo-channel structure and the vertical direct contact of the vertical non-volatile memory device according to an embodiment of the present invention is shown.

[0018] Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E and Figure 7F It shows the method for forming Figures 4A to 4F Conceptual diagrams of patterns on the masks of their respective pseudo-channel structures;

[0019] Figure 8A and Figure 8B It shows in Figures 7A to 7F The design of the pattern on the mask shown is a conceptual diagram describing the selection criteria;

[0020] Figure 9A and Figure 9B A plan view of the horizontal cross-section of the pseudo-channel structure and the vertical direct contact, respectively disposed in the electrode pads, is shown in an embodiment of the vertical non-volatile memory device according to the present invention.

[0021] Figure 10 A flowchart illustrating a method for manufacturing a vertical non-volatile memory device according to an embodiment of the present invention is shown; and

[0022] Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E , Figure 11F and Figure 11G It shows Figure 10 A cross-sectional view of a subsequent process in the method for manufacturing a vertical non-volatile memory device, shown in the diagram, of the mask manufacturing process. Detailed Implementation

[0023] The embodiments will be described in detail below with reference to the accompanying drawings. The same reference numerals refer to the same elements, and repeated descriptions of them may be omitted.

[0024] Figure 1An equivalent circuit diagram of a memory cell array of a vertical non-volatile memory device 10 according to an embodiment of the present invention is shown.

[0025] Reference Figure 1 The vertical non-volatile memory device 10 according to an embodiment may include a common-source line CSL, multiple bit lines BL0 to BLm (e.g., BL0, BL1 to BLm), and multiple cell strings CSTRs. The multiple bit lines BL0 to BLm may be arranged in two dimensions, and the multiple cell strings CSTRs may be connected in parallel with the multiple bit lines BL0 to BLm respectively. The multiple cell strings CSTRs may be connected together to the common-source line CSL.

[0026] Each of the multiple cell strings (CSTRs) may include: multiple string select transistors (e.g., a first string select transistor and a second string select transistor) SST1 and SST2, each having a gate connected to the corresponding string select lines SSL1 and SSL2; multiple cell transistors (MCTs); and a ground select transistor (GST) having a gate connected to the ground select line GSL. Each memory cell transistor (MCT) may include a data storage element. Specifically, the first string select transistor SST1 and the second string select transistor SST2 may be connected in series with each other, the second string select transistor SST2 may be connected to the corresponding bit line, and the ground select transistor GST may be connected to the common-source line CSL. Additionally, the memory cell transistors (MCTs) may be connected in series between the first string select transistor SST1 and the ground select transistor GST. Although in Figure 1 Each of the cell string CSTRs is shown as including a first string select transistor SST1 and a second string select transistor SST2, but in other embodiments, each of the cell string CSTRs may include a single string select transistor.

[0027] like Figure 1 As shown, each of the cell strings CSTRs may include: a first pseudo-cell transistor DMC1 connected between the first string select transistor SST1 and the corresponding memory cell transistor MCT; and a second pseudo-cell transistor DMC2 connected between the ground select transistor GST and the corresponding memory cell transistor MCT. The first pseudo-cell transistor DMC1 may have a gate connected to the pseudo-word line DWL1, and the second pseudo-cell transistor DMC2 may have a gate connected to the pseudo-word line DWL2. Although in Figure 1 Each of the cell string CSTR is shown as including a first pseudo-cell transistor DMC1 and a second pseudo-cell transistor DMC2, but in other embodiments, at least one of the first pseudo-cell transistor DMC1 and the second pseudo-cell transistor DMC2 may be omitted from the cell string CSTR.

[0028] Each cell string (CSTR) may include multiple memory cell transistors (MCTs) at different distances from the common-source line (CSL). Therefore, multiple multilayer word lines WL0 to WLn (e.g., WL0, WLn-1 to WLn) can be positioned between the common-source line (CSL) and bit lines BL0 to BLm. Furthermore, the gate electrodes of memory cell transistors (MCTs) positioned at substantially the same distance from the common-source line (CSL) can be commonly connected to one of the word lines WL0 to WLn and can be in an equivalent potential state.

[0029] In the vertical non-volatile memory device 10 according to the embodiment, vertical direct contacts (see...) are provided. Figure 2 In the extended region of the VC), pseudo-channel structures (see Figure 2 The DCS can be set on the electrode pad corresponding to a vertical direct contact VC (see...). Figure 2 In the ELp), in this case, the horizontal cross-section of the pseudo-channel structure DCS0 can have various shapes based on the characteristics of the manufacturing process. Therefore, the manufacturing process of the vertical non-volatile memory device 10 according to the embodiment can be easily performed, and the vertical non-volatile memory device 10 can have improved reliability and integration based on the shape of the horizontal cross-section of the pseudo-channel structure DCS. Reference will be made below. Figures 2 to 9B Describe in detail the shape of the horizontal cross-section of the pseudo-channel structure DCS.

[0030] Figure 2 A plan view of a vertical non-volatile memory device 100 according to an embodiment of the present invention is shown, and Figure 3 It shows along Figure 2 The cross-sectional views of the vertical non-volatile memory device 100 shown are taken along lines I-I' and II-II'. (This will be combined with...) Figure 1 describe Figure 2 and Figure 3 .

[0031] Reference Figure 2 and Figure 3 The vertical non-volatile memory device 100 according to the embodiment may include a cell array region CAA and an extended region EA, each defined on a substrate 101.

[0032] The substrate 101 may include a top surface FS extending in a first direction (i.e., the x-direction) and a second direction (i.e., the y-direction) that intersect each other and are substantially perpendicular to each other. The substrate 101 may include a semiconductor material (e.g., a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor). Cell regions and peripheral regions disposed outside the cell regions may be defined on the substrate 101.

[0033] The cell array region CAA and the extended region EA can be disposed in the cell region of the substrate 101. The cell array region CAA can be provided with its own configuration as described above. Figure 1 The regions of the string selection transistors SST1 and SST2, the memory cell transistor MCT, and the ground selection transistor GST are described. Multiple bit lines BL0 to BLm can be located in the upper part of the cell array region CAA, and multiple impurity regions and multiple common source lines CSL can be located in the lower part of the cell array region CAA.

[0034] The extended region EA can be a region having electrode pads ELp formed by the gate electrode layers EL of each of the string select transistors SST1 and SST2, the memory cell transistor MCT, and the ground select transistor GST extending from the cell array region CAA in the first direction (x direction). In the extended region EA, the electrode pads ELp can be connected to the vertical direct contact VC. For example... Figure 2 and Figure 3 As seen in the extended region EA, the corresponding length of the gate electrode layer EL in the first direction (x-direction) decreases as the distance from the substrate 101 in the third direction (i.e., z-direction) increases. For example, the lowermost gate electrode layer EL is longer in the x-direction than the gate electrode layer EL adjacent above it, and the uppermost gate electrode layer EL is shorter in the x-direction than the electrode layer EL adjacent below it. The z-direction can be substantially perpendicular to the top surface FS of the substrate 101. The height of the electrode structure ST in the third direction (z-direction) can decrease in a direction away from the cell array region CAA. In addition, the side portions of the gate electrode layers EL can be configured to be spaced apart from each other at a specific interval in the first direction (x-direction).

[0035] Electrode structures ST can extend from the cell array region CAA to the extended region EA in a first direction (x-direction) on the substrate 101. Multiple electrode structures ST can be disposed on the substrate 101. The multiple electrode structures ST can be spaced apart from each other in a second direction (y-direction). For example, a partitioned region extending in the first direction (x-direction) can be disposed, and the electrode structures ST can be spaced apart from each other in the second direction (y-direction), with partitioned regions between the electrode structures ST. These partitioned regions can be referred to as word line cut regions. A buffer insulating layer 110 can be disposed between the electrode structures ST and the substrate 101.

[0036] The electrode structure ST may include a plurality of gate electrode layers EL and a plurality of interlayer insulating layers ILD alternately stacked in a third direction (z-direction) perpendicular to the top surface FS of the substrate 101. The thickness of the gate electrode layers EL may be substantially equal to that of each other. The thickness of the interlayer insulating layers ILD may vary based on the characteristics of the memory device. In addition, the thickness of each of the interlayer insulating layers ILD may be less than the thickness of each of the gate electrode layers EL.

[0037] Each of the gate electrode layers EL may include an electrode pad ELp in the extended region EA. The electrode pads ELp of the gate electrode layers EL may be arranged horizontally and vertically at different locations. That is, the electrode structure ST may include gate electrode layers EL and interlayer insulating layers ILD alternately stacked in the third direction (z direction), and in the extended region EA, the electrode pads ELp connected to the gate electrode layers EL may form a stepped structure.

[0038] The planarization insulating layer 150 may cover the substrate 101 on which the electrode structure ST is disposed. The planarization insulating layer 150 may include a substantially flat top surface. In addition, the planarization insulating layer 150 may cover the stepped structure of the electrode structure ST in the extended region EA. The planarization insulating layer 150 may include a single insulating layer or a stack of insulating layers.

[0039] In the cell array region CAA, multiple vertical channel structures VCS can be formed to pass through the electrode structure ST. Additionally, in the extended region EA, multiple pseudo-channel structures DCS can be formed to pass through the planarization insulating layer 150 and the electrode structure ST. From a one-dimensional perspective, the vertical channel structures VCS can be arranged in a zigzag shape or pattern in the first direction (x-direction).

[0040] The pseudo-channel structure DCS can pass through the stepped structure of the electrode structure ST, and the number of gate electrode layers EL that the pseudo-channel structure DCS passes through decreases as the distance from the cell array region CAA in the first direction (x direction) increases. From a one-dimensional perspective, the pseudo-channel structure DCS can be arranged along the first direction (x direction) on both sides of the vertical direct contact VC in each electrode pad ELp. For example, each electrode pad ELp can include a pair of pseudo-channel structure DCS, and there is a vertical direct contact VC between the pair of pseudo-channel structures DSC. In addition, from a one-dimensional perspective, each pseudo-channel structure DCS can have a structure extending in the second direction (y direction). In other words, from a one-dimensional perspective, the length of each pseudo-channel structure DCS in the second direction (y direction) can be longer than its length in the first direction (x direction). Furthermore, from a one-dimensional perspective, each pseudo-channel structure DCS can have a shape in which both ends along the second direction (y direction) bend toward the vertical direct contact VC. The shape of each of the pseudo-channel structures in a DCS can correspond to the shape of the vertices in the "[" shape (square bracket shape) being bent.

[0041] according to Figure 2 The shape of the horizontal cross-section of each pseudo-channel structure DCS of the vertical non-volatile memory device 100 shown in the embodiment can be consistent with... Figure 4C The horizontal cross-sectional shape of the third pseudo-channel structure DCS3 of the vertical non-volatile memory device 100c shown is basically the same. However, the shape of the horizontal cross-section of each pseudo-channel structure DCS is not limited to... Figure 4C The shape of the third pseudo-channel structure DCS3 shown. For example, the shape of the horizontal cross-section of each pseudo-channel structure DCS of the vertical non-volatile memory device 100 according to the embodiment can have respectively in Figure 4A , Figure 4B and Figures 4D to 4F The diagram shows any of the horizontal cross-sectional shapes of the first pseudo-channel structure DCS1, the second pseudo-channel structure DCS2, and the fourth pseudo-channel structures DCS4 through the sixth pseudo-channel structures DCS6. The following will refer to... Figures 4A to 9B The shape of the horizontal cross-section of the pseudo-channel structure DCS is described in more detail.

[0042] Here, a one-dimensional viewpoint can refer to the view from above as a plane representing the top or bottom surface of the pseudo-channel structure DCS. Alternatively, a one-dimensional viewpoint can refer to the view from above as a plane representing a horizontal cross-section taken along a specific height of the pseudo-channel structure DCS in the third direction (z-direction). In the vertical non-volatile memory device 100 according to the embodiment, this can be achieved by forming a second vertical hole (see...). Figure 11CThe pseudo-channel structure DCS is formed by filling the interior of the second vertical hole (VH2) with structural material. Therefore, the horizontal cross-section of the pseudo-channel structure DCS and the horizontal cross-section of the second vertical hole VH2 can be substantially equal to each other. Therefore, in the following text, the horizontal cross-section of the pseudo-channel structure DCS and the horizontal cross-section of the second vertical hole VH2 can have the same meaning.

[0043] The bottom surfaces of the vertical channel structure VCS and the pseudo-channel structure DCS can be set at essentially the same level in the third direction (z-direction). Furthermore, the vertical channel structure VCS and the pseudo-channel structure DCS can have essentially the same length in the third direction (z-direction). This is because the vertical channel structure VCS and the pseudo-channel structure DCS are formed simultaneously in the same process step.

[0044] The vertical channel structure (VCS) may include a first lower semiconductor pattern (LSP1), a first upper semiconductor pattern (USP1), a first data storage pattern (VP1), and a first buried insulating pattern (V1). The first lower semiconductor pattern (LSP1) may directly contact the substrate 101 and may include a columnar epitaxial layer grown from the substrate 101. The top surface of the first lower semiconductor pattern (LSP1) may be higher than the top surface of the bottommost gate electrode layer (EL) and lower than the top surface of the bottommost interlayer insulating layer (ILD) disposed on the bottommost gate electrode layer (EL). The gate insulating layer (ILD) may be disposed on a portion of the sidewall of the first lower semiconductor pattern (LSP1).

[0045] The first upper semiconductor pattern USP1 can directly contact the first lower semiconductor pattern LSP1. The interior of the first upper semiconductor pattern USP1 can be filled with a first embedded insulating pattern V1 including insulating material. The first lower semiconductor pattern LSP1 and the first upper semiconductor pattern USP1 can pass through the first data storage pattern VP1 and can be electrically connected to each other.

[0046] A first data storage pattern VP1 may be disposed between the electrode structure ST and the first upper semiconductor pattern USP1. The first data storage pattern VP1 may extend in the third direction (z-direction) and may surround the sidewalls of the first upper semiconductor pattern USP1. The first data storage pattern VP1 may include one or more thin layers. In an embodiment, the first data storage pattern VP1 may be a data storage layer of a NAND flash memory device and may include a tunnel insulating layer, a charge storage layer, and a barrier insulating layer.

[0047] The pseudo-channel structure DCS may include a second lower semiconductor pattern LSP2, a second upper semiconductor pattern USP2, a second data storage pattern VP2, and a second buried insulating pattern V2. The internal structure of the pseudo-channel structure DCS can be substantially the same as that of the vertical channel structure VCS. In the third direction (z-direction), the height (or upper surface) of the second lower semiconductor pattern LSP2 may be lower than the height (or upper surface) of the first lower semiconductor pattern LSP1. However, according to other embodiments, the heights of the second lower semiconductor pattern LSP2 and the first lower semiconductor pattern LSP1 may be substantially the same.

[0048] According to an embodiment, in a pseudo-channel structure DCS, the second upper semiconductor pattern USP2 can be removed and omitted, and the second buried insulating pattern V2 can be provided only on the second data storage pattern VP2. In this structure, the second buried insulating pattern V2 can pass through the bottom surface of the second data storage pattern VP2 and can directly contact the second lower semiconductor pattern LSP2.

[0049] The horizontal insulating pattern HP can extend on the top and bottom surfaces of the gate electrode layer EL, between the gate electrode layer EL and the vertical channel structure VCS, and between the gate electrode layer EL and the dummy channel structure DCS. The horizontal insulating pattern HP can be part of the data storage layer of a NAND flash memory device and can include a charge storage layer and a barrier insulating layer. In other embodiments, the horizontal insulating pattern HP may include only a barrier insulating layer.

[0050] Bit line electrode pad BP and bit line contact plug BCP connected to bit line electrode pad BP can be disposed on the upper part of the first upper semiconductor pattern USP1. For example... Figure 3 As shown, the side surface of the bit line electrode pad BP can be surrounded by the first data storage pattern VP1. According to other embodiments, the bit line electrode pad BP can be disposed on the top surface of the first upper semiconductor pattern USP1 and the top surface of the first data storage pattern VP1, and the side surface of the bit line electrode pad BP can be surrounded by the first upper interlayer insulating layer 160.

[0051] The pseudo-bit line electrode pad (DBP) can be disposed on the upper part of the pseudo-channel structure (DCS), and the top surface of the pseudo-bit line electrode pad (DBP) can be coplanar with the top surface of the bit line electrode pad (BP). The first upper interlayer insulating layer 160 can cover the top surface of the pseudo-bit line electrode pad (DBP). However, according to other embodiments, the pseudo-bit line electrode pad (DBP) can be omitted.

[0052] The common-source region CSA can extend parallel to the electrode structure ST in a first direction (x-direction) and can be formed by doping the substrate 101 with a second conductive impurity. A common-source plug CSP can be connected to the common-source region CSA between the electrode structures ST. Figure 2 In this configuration, the common source region (CSA) can be positioned below the common source plug (CSP) in the third direction (z direction).

[0053] An insulating spacer IS can be disposed on each of the two side surfaces of the common source plug CSP. That is, the insulating spacer IS can be disposed between the common source plug CSP and each of the electrode structures ST. According to other embodiments, the common source plug CSP can be disposed only on a portion of the upper part of the common source region CSA, and an isolation layer can be disposed on the common source plug CSP. As previously described, the insulating spacer IS or the isolation layer can construct a segmented region (i.e., a word line cut-out region).

[0054] The first upper interlayer insulation layer 160 can be disposed on the planarization insulation layer 150 in the extended region EA. Furthermore, the first upper interlayer insulation layer 160 can cover the top surface of the vertical channel structure VCS and the top surface of the pseudo-channel structure DCS. The second upper interlayer insulation layer 170 can be disposed on the first upper interlayer insulation layer 160 and can cover the top surfaces of the insulating spacer IS and the common source plug CSP.

[0055] In the extended region EA, the vertical direct contact VC can pass through the first upper interlayer insulating layer 160 and the second upper interlayer insulating layer 170, and can be connected to the electrode pad ELp of the corresponding gate electrode layer EL. The vertical length of the vertical direct contact VC (i.e., the length of the vertical direct contact VC in the third direction (z direction)) can decrease towards the cell array region CAA. In other words, the vertical length of the vertical direct contact VC closest to the cell array region CAA in the first direction (x direction) can be shorter than the vertical length of the vertical direct contact further away from the cell array region CAA in the first direction (x direction). The top surfaces of multiple vertical direct contacts VC can be substantially coplanar. From a one-dimensional perspective, each of the vertical direct contacts VC can be surrounded by a pseudo-channel structure DCS. In other words, each of the vertical direct contacts VC can be positioned between pseudo-channel structures DCS that are adjacent to each other in the first direction (x direction).

[0056] Multiple sub-bit lines SBL can be provided on the second upper interlayer insulating layer 170 of the cell array region CAA, and the multiple sub-bit lines SBL can be electrically connected to the corresponding vertical channel structure VCS through bit line contact plugs BCP. In the extended region EA, multiple connecting lines CL can be provided on the second upper interlayer insulating layer 170, and the multiple connecting lines CL can be connected to the vertical direct contact VC. A third upper interlayer insulating layer 180 can be provided on the second upper interlayer insulating layer 170, and the third upper interlayer insulating layer 180 can cover the sub-bit lines SBL and the connecting lines CL. Multiple bit lines BL can be provided on the third upper interlayer insulating layer 180, and the multiple bit lines BL can cross the electrode structure ST and extend in the second direction (y direction). Although not shown, the bit lines BL can be connected to the sub-bit lines SBL through corresponding contact plugs.

[0057] Figures 4A to 4F A plan view of the horizontal cross-section of the dummy channel structure and the vertical direct contact, respectively disposed in the electrode pads of the vertical non-volatile memory device according to an embodiment, is shown. Hereinafter, for simplicity, references will be simply given or may be omitted. Figures 1 to 3 The provided descriptions are the same or similar.

[0058] Reference Figure 4A In the vertical non-volatile memory device 100a according to an embodiment, four first pseudo-channel structures DCS1 in a first electrode pad ELp1 can be provided at the vertex positions of a square, and a vertical direct contact VC is provided between the vertex positions. The four first pseudo-channel structures DCS1 thus surround the vertical direct contact VC, such that the vertical direct contact VC is located between the four first pseudo-channel structures DCS1. The first electrode pad ELp1 may have a first length L1 in a first direction (x-direction). Figure 4A In the diagram, the portion outside the dashed line in the first direction (x direction) can be another portion of the first electrode pad ELp1. In other words, the first electrode pad outside the dashed line can be located at a different position than the first electrode pad ELp1 in the center portion in the third direction (z direction).

[0059] Each of the multiple first pseudo-channel structures DCS1 can have a trapezoidal cross-sectional shape. Specifically, the first pseudo-channel structure DCS1 can have a trapezoidal shape, with the width of the trapezoid in the first direction (x-direction) gradually narrowing in the second direction (y-direction). For example... Figure 4A As shown in the enlarged view, the horizontal cross-section of the first pseudo-channel structure DCS1 may not be completely or exactly trapezoidal (as indicated by the dashed line), but may have a trapezoidal shape with its vertex portion curved (as indicated by the solid line).

[0060] Two first pseudo-channel structures DCS1 adjacent to each other in the second direction (y-direction) can be configured such that some portions of them are narrower in the first direction (x-direction) than their facing portions. The two first pseudo-channel structures DCS1 with narrower, facing portions can be positioned at each of the two sides of the vertical direct contact VC in the first direction (x-direction). This configuration of the first pseudo-channel structure DCS1 can be based on a T-shaped design when patterning the shape of its horizontal cross-section. (Refer to...) Figure 7A The design of the horizontal cross-section shape of the first pseudo-channel structure DCS1 is described in more detail.

[0061] In the vertical non-volatile memory device 100a according to the current embodiment, the shape of the horizontal cross-section of the first pseudo-channel structure DCS1 can be a shape selected and formed based on various selection criteria, taking into account the characteristics of the manufacturing process. (Refer to...) Figure 8A and Figure 8B A more detailed description of the various selection criteria associated with choosing the shape of the horizontal cross-section.

[0062] Reference Figure 4B In the vertical non-volatile memory device 100b according to an embodiment, second pseudo-channel structures DCS2 can be provided on both sides of the first electrode pad ELp1 in a first direction (x direction), and a vertical direct contact VC is provided between these two sides. The shape of the horizontal cross-section of each of the plurality of second pseudo-channel structures DCS2 can be a rectangular structure that is longer in the second direction (y direction). Specifically, the width of the second pseudo-channel structure DCS2 can be longer in the second direction (y direction) than in the first direction (x direction). Figure 4B As shown in the enlarged view, the horizontal cross-section of the second pseudo-channel structure DCS2 may not be exactly rectangular (as indicated by the dashed line), but may have a rectangle with its apex portion bent (as indicated by the solid line). Therefore, the two ends of the second pseudo-channel structure DCS2 in the second direction (y direction) may have circles.

[0063] When patterning the shape of the horizontal cross-section of the second pseudo-channel structure DCS2, this structure of the second pseudo-channel structure DCS2 can be based on a design with a longer rectangle in the second direction (y direction). (Refer to...) Figure 7B The shape design of the horizontal cross-section of the second pseudo-channel structure DCS2 is described in more detail.

[0064] Reference Figure 4CIn the vertical non-volatile memory device 100c according to an embodiment, a third pseudo-channel structure DCS3 may be provided on each of the two sides of the first electrode pad ELp1 in the first direction (x direction), and a vertical direct contact VC is provided between these two sides. The shape of the horizontal cross-section of each of the plurality of third pseudo-channel structures DCS3 may have a structure surrounding the vertical direct contact VC with a longer shape in the second direction (y direction). Specifically, the width of the third pseudo-channel structure DCS3 may be longer in the second direction (y direction) than in the first direction (x direction), and the third pseudo-channel structure DCS3 may include a first protrusion P1 facing the vertical direct contact VC at each of its two ends in the second direction (y direction). The third pseudo-channel structure DCS3 facing the vertical direct contact VC may therefore have an overall "[" shape, or, in other words, a bracket shape, with the open side of the bracket facing the vertical direct contact VC. Figure 4C As shown in the enlarged view, the horizontal cross-section of the third pseudo-channel structure DCS3 may not be exactly or precisely "[" shaped (as indicated by the dashed line), but may have a "[" shaped with its apex portion bent (as indicated by the solid line). Therefore, the third pseudo-channel structure DCS3 may include a first protrusion P1 protruding from each of the two ends of the third pseudo-channel structure DCS3 in the second direction (y direction) toward (towards) the vertical direct contact VC.

[0065] When designing the pattern of the horizontal cross-section shape of the third pseudo-channel structure DCS3, this structure of the third pseudo-channel structure DCS3 can be based on the design of the "[" shape. (Refer to...) Figure 7C The design of the horizontal cross-section shape of the third pseudo-channel structure DCS3 is described in more detail.

[0066] Reference Figure 4D In the vertical non-volatile memory device 100d according to an embodiment, a fourth pseudo-channel structure DCS4 can be provided on both sides of the first electrode pad ELp1 in a first direction (x direction), and a vertical direct contact VC is provided between these two sides. The shape of the horizontal cross-section of each of the plurality of fourth pseudo-channel structures DCS4 can have a structure that surrounds the vertical direct contact VC and has an elongated shape in a second direction (y direction). Specifically, the fourth pseudo-channel structure DCS4 can have a "(" shape (bracket or curved bracket shape) surrounding the vertical direct contact VC. In other words, the fourth pseudo-channel structure DCS4 can have a bracket or curved bracket shape, with the open side of the bracket facing the vertical direct contact VC.

[0067] When designing the pattern of the horizontal cross-section of the fourth pseudo-channel structure DCS4, this structure of the fourth pseudo-channel structure DCS4 can be based on a bracket shape (hereinafter referred to as the modified bracket shape) with its central portion protruding outward from the vertical direct contact VC. For example... Figure 4D As shown in the enlarged view, the bracket shape of the fourth pseudo-channel structure DCS4 can be formed by bending the vertex portion of the modified square bracket shape. (Refer to...) Figure 7D The design of the horizontal cross-section shape of the fourth pseudo-channel structure DCS4 is described in more detail.

[0068] Reference Figure 4E In the vertical non-volatile memory device 100e according to an embodiment, a fifth pseudo-channel structure DCS5 can be provided on both sides of the first electrode pad ELp1 in a first direction (x direction), and a vertical direct contact VC medium is provided between these two sides. The shape of the horizontal cross-section of each of the plurality of fifth pseudo-channel structures DCS5 can be dumbbell-shaped, which is longer in the second direction (y direction). Specifically, the width of the fifth pseudo-channel structure DCS5 can be longer in the second direction (y direction) than in the first direction (x direction), and the fifth pseudo-channel structure DCS5 can include a second protrusion P2 protruding from both sides in the first direction (x direction) at each of its two ends in the second direction (y direction), and thus can be dumbbell-shaped overall.

[0069] When designing the pattern of the horizontal cross-section of the fifth pseudo-channel structure DCS5, this structure of the fifth pseudo-channel structure DCS5 can be based on an "I" shape design. For example... Figure 4E As shown in the enlarged view, the dumbbell shape of the fifth pseudo-channel structure DCS5 can be formed by bending the vertex portion of the "I" shape, and the fifth pseudo-channel structure DCS5 can include a second protruding portion P2 protruding from both sides in the first direction (x direction) at each of its two ends in the second direction (y direction). (Refer to...) Figure 7E The design of the horizontal cross-section shape of the fifth pseudo-channel structure DCS5 is described in more detail.

[0070] Reference Figure 4F In the vertical non-volatile memory device 100f according to an embodiment, a sixth pseudo-channel structure DCS6 can be provided on both sides of the first electrode pad ELp1 in a first direction (x direction), and a vertical direct contact VC is provided between these two sides. Because the horizontal cross-sectional shape of each of the plurality of sixth pseudo-channel structures DCS6 is dumbbell-shaped, the shape of the horizontal cross-section of each sixth pseudo-channel structure DCS6 can be... Figure 4EThe horizontal cross-sectional shape of the fifth pseudo-channel structure DCS5 shown is similar. However, unlike the fifth pseudo-channel structure DCS5, the sixth pseudo-channel structure DCS6 is arranged at the boundary of the first electrode pad ELp1. In addition, the width of the sixth pseudo-channel structure DCS6 in the first direction (x-direction) is greater than the width of the fifth pseudo-channel structure DCS5 in the first direction (x-direction).

[0071] As mentioned earlier, the first electrode pads adjacent to the first electrode pad ELp1 on both sides in the first direction (x direction) can be first electrode pads located at different positions in the third direction (z direction) relative to the dashed line. Therefore, considering only the central portion of the first electrode pad ELp1, the structure of the sixth pseudo-channel structure DCS6 can have a bracket shape with the apex portion bent, like... Figure 4C The third pseudo-channel structure DCS3 is not dumbbell-shaped. The sixth pseudo-channel structure DCS6 can be set at the boundary portion of the first electrode pad ELp1. Therefore, compared with the third pseudo-channel structure DCS3, the sixth pseudo-channel structure DCS6 can be set to be spaced a long distance from the vertical direct contact VC in the first direction (x direction).

[0072] When designing the pattern of the horizontal cross-sectional shape of the sixth pseudo-channel structure DCS6, the structure of the sixth pseudo-channel structure DCS6 can be based on an "I" shape. Compared with the fifth pseudo-channel structure DCS5, the width of the "I" shape of the sixth pseudo-channel structure DCS6 in the first direction (x direction) can be relatively larger. Furthermore, the position of the sixth pseudo-channel structure DCS6 disposed in the first electrode pad ELp1 can be different. The sixth pseudo-channel structure DCS6 may include a third protrusion P3 protruding from both sides in the first direction (x direction) at each of its two ends in the second direction (y direction). (Refer to...) Figure 7F The shape of the horizontal cross-section of the sixth pseudo-channel structure DCS6 is described in more detail.

[0073] Figures 5A to 5F A plan view of the horizontal cross-section of the dummy channel structure and vertical direct contact of the vertical non-volatile memory device according to an embodiment is shown. In the following, for simplicity, references may be simply given or omitted. Figures 1 to 4F The provided descriptions are the same or similar.

[0074] Reference Figures 5A to 5E Each of the plurality of vertical non-volatile memory devices 200a, 200b, 200c, 200d and 200e according to the present embodiment can be coupled with each of the following: Figures 4A to 4EEach of the vertical non-volatile memory devices 100a, 100b, 100c, 100d and 100e shown is similar, but the following two features may differ.

[0075] First, such as Figures 5A to 5E As shown, a second electrode pad ELp2 is provided. The second electrode pad ELp2 may have a larger [value] in the first direction (x direction) than [value]. Figures 4A to 4E The first electrode pad ELp1 shown has a longer length. For example, the second electrode pad ELp2 may have a second length L2 in the first direction (x direction). For example, the second length L2 of the second electrode pad ELp2 may be 20% or more longer than the first length L1 of the first electrode pad ELp1 in the first direction (x direction).

[0076] Second, an additional pseudo-channel structure can be provided at the boundary of the second electrode pad ELp2. For example, an additional pseudo-channel structure can be provided at the boundary of the first side of the vertical channel in the first direction (x direction), and another additional pseudo-channel structure can be provided at the boundary of the second side of the vertical channel in the first direction. The horizontal cross-section of the additional pseudo-channel structure can be substantially the same as the horizontal cross-section of the pseudo-channel structure. For a detailed example, in Figure 5A In the vertical non-volatile memory device 200a, the horizontal cross-section of the first additional pseudo-channel structure DCS1a can be substantially the same as the horizontal cross-section of the first pseudo-channel structure DCS1. Similarly, Figure 5B , Figure 5C , Figure 5D and Figure 5E The horizontal cross-sections of the second to fifth additional pseudo-channel structures DCS2a, DCS3a, DCS4a and DCS5a can be basically the same as the horizontal cross-sections of the corresponding second to fifth pseudo-channel structures DCS2, DCS3, DCS4 and DCS5.

[0077] In the vertical non-volatile memory devices 200a to 200e according to the current embodiments, the second electrode pads ELp2 that are adjacent to each other in the first direction (x direction) may be second electrode pads located at other positions in the third direction (z direction). Therefore, considering only one second electrode pad ELp2, only half of the first additional pseudo-channel structure DCS1a can be included in the corresponding second electrode pad ELp2 at each of the left and right boundary portions. Furthermore, the second additional pseudo-channel structures DCS2a to the fifth additional pseudo-channel structures DCS5a can be similar.

[0078] Reference Figure 5FThe vertical non-volatile memory device 200f according to the current embodiment may include a second electrode pad ELp2, but unlike the vertical non-volatile memory devices 200a to 200e, the vertical non-volatile memory device 200f does not include an additional pseudo-channel structure. Additionally, in Figure 5F In the vertical non-volatile memory device 200f, the sixth pseudo-channel structure DCS6' can be disposed at the boundary portion of the second electrode pad ELp2 in the first direction (x direction), like... Figure 4F Like the vertical non-volatile memory device 100f. The horizontal cross-sectional shape of the sixth pseudo-channel structure DCS6' can be dumbbell-shaped, and can be... Figure 4F The horizontal cross-sectional shape of the sixth pseudo-channel structure DCS6 is basically the same. The length of the second electrode pad ELp2 in the first direction (x direction) can be relatively long. Therefore, the distance between the vertical direct contact VC and the sixth pseudo-channel structure DCS6' in the first direction (x direction) can be greater than [missing information]. Figure 4F The distance between the sixth pseudo-channel structure DCS6 and the vertical direct contact VC.

[0079] Figures 6A to 6E A plan view of the horizontal cross-section of the dummy channel structure and vertical direct contact of the vertical non-volatile memory device according to an embodiment is shown. In the following, for simplicity, references may be simply given or omitted. Figures 1 to 5F The provided descriptions are the same or similar.

[0080] Reference Figures 6A to 6E Each of the plurality of vertical non-volatile memory devices 300a, 300b, 300c, 300d and 300e according to the present embodiment can be coupled with each of the following: Figures 5A to 5E The vertical non-volatile memory devices 200a, 200b, 200c, 200d, and 200e shown are similar to each other. Because the vertical non-volatile memory devices 300a to 300e according to the present embodiment include the same additional pseudo-channel structure DCSa, the vertical non-volatile memory devices 300a to 300e can be similar to those respectively in… Figures 5A to 5E The vertical non-volatile memory devices 200a to 200e shown are different. In detail, each of the vertical non-volatile memory devices 300a to 300e according to the present embodiment may include an additional pseudo-channel structure DCSa, so that its horizontal cross-sectional shape is circular, and thus two additional pseudo-channel structures DCSa are disposed at the respective boundary portions of the second electrode pad ELp2.

[0081] Additionally, considering that the second electrode pads ELp2 that are adjacent to each other in the first direction (x direction) are second electrode pads located at other positions in the third direction (z direction), in a second electrode pad ELp2, only half of the additional pseudo-channel structure DCSa (i.e., the semi-circular portion) can be included in the corresponding second electrode pad ELp2 at each of the left and right boundary portions.

[0082] exist Figures 4A to 6E In the vertical non-volatile memory devices 100a to 100f, 200a to 200f, and 300a to 300e, the cases where the electrode pad is a first electrode pad ELp1 and the cases where the electrode pad is a second electrode pad ELp2 have been described above. However, the vertical non-volatile memory device according to other embodiments may include a structure that provides a first electrode pad ELp1 and a second electrode pad ELp2, rather than a structure that provides only one electrode pad.

[0083] Figures 7A to 7F It shows the location used for forming Figures 4A to 4F A conceptual diagram of a pattern on a mask of a pseudo-channel structure and corresponding to one of the four or two pseudo-channel structures located on the right side of the first electrode pad ELp1.

[0084] Reference Figure 7A It shows the method for forming Figure 4A The pattern on the mask of the first pseudo-channel structure DCS1. Specifically, the layout of the pattern corresponding to the horizontal cross-section of the first pseudo-channel structure DCS1 can be designed to be applied to the substrate (…). Figure 3 A first pseudo-channel structure DCS1 is formed on 101). For example, the pattern layout can be T-shaped.

[0085] After designing the pattern layout, optical proximity correction (OPC) can be performed, thus obtaining the outline of the target pattern as the OPC result. OPC can represent a method for correcting the pattern layout on the mask to overcome the optical proximity effect (OPE) that occurs in the exposure process due to the influence of fine patterns between neighboring patterns. OPC can be performed by repeatedly comparing the target pattern to be formed on the substrate with the outline of the target pattern as the OPC result, and changing the pattern layout on the mask. Here, the target pattern can be the shape of the horizontal cross-section of the first pseudo-channel structure DCS1. Based on this OPC, the pattern layout on the mask can be finally determined, and Figure 4A The shape of the pattern on the mask is shown based on a defined layout of the pattern on the mask.

[0086] As a result, it can be seen that the trapezoidal layout of the horizontal cross-section of the first pseudo-channel structure DCS1 is based on a T-shaped pattern. This is achieved by observing the characteristic that the vertices or corners of the pattern are bent during the reaction OPC process and etching process, such as... Figure 4A As shown, the horizontal cross-section of the first pseudo-channel structure DCS1 can have a trapezoidal shape with its apex portion bent.

[0087] Reference Figure 7B First, the layout of the pattern corresponding to the horizontal cross-section of the second pseudo-channel structure DCS2 can be designed. For example, the pattern layout can have a rectangular shape that is longer in the second direction (y-direction). Next, the pattern layout on the mask can be finalized by performing an OPC process, and... Figure 4B The shape of the pattern on the mask is shown based on a defined layout of the pattern on the mask.

[0088] As a result, it can be seen that the rectangular shape of the horizontal cross-section of the second pseudo-channel structure DCS2 is based on a layout of a pattern with a rectangular shape. This is achieved by incorporating the characteristic of the vertices or corners of the pattern being bent during the reaction OPC process and etching process, such as... Figure 4B As shown, the horizontal cross-section of the second pseudo-channel structure DCS2 can have a rectangular shape with its apex portion bent.

[0089] Reference Figure 7C First, it is possible to design with Figure 4C The layout of the pattern corresponding to the horizontal cross-section of the third pseudo-channel structure DCS3. For example, the pattern layout can have a bracket shape. Next, the final layout of the pattern on the mask can be determined by performing an OPC process, and... Figure 4C The shape of the pattern on the mask is shown based on a defined layout of the pattern on the mask.

[0090] As a result, it can be seen that the bracket shape of the horizontal cross-section of the third pseudo-channel structure DCS3 is based on a layout of a pattern with a bracket shape. This is achieved by incorporating the characteristic of the vertices or corners of the pattern being bent in the reaction OPC process and etching process, such as... Figure 4C As shown, the horizontal cross-section of the third pseudo-channel structure DCS3 can have a bracket shape with its vertex portion bent.

[0091] Reference Figure 7D First, it is possible to design with Figure 4D The fourth pseudo-channel structure DCS4 corresponds to the pattern layout on the horizontal cross-section. For example, the pattern layout can have a modified bracket shape corresponding to the bracket shape protruding outward from the center portion. Next, the pattern layout on the mask can be finalized by performing an OPC process, and... Figure 4D The shape of the pattern on the mask is shown based on a defined layout of the pattern on the mask.

[0092] As a result, it can be seen that the bracket shape of the horizontal cross-section of the fourth pseudo-channel structure DCS4 is based on a layout of a pattern with a modified square bracket shape. This is achieved by incorporating the characteristic of the vertices or corners of the pattern being bent in the reaction OPC process and etching process, such as... Figure 4D As shown, the horizontal cross-section of the fourth pseudo-channel structure DCS4 can have a bracket shape with its vertex portion bent.

[0093] Reference Figure 7E First, it is possible to design with Figure 4E The layout of the pattern corresponding to the horizontal cross-section of the fifth pseudo-channel structure DCS5. For example, the pattern layout can be I-shaped. Next, the final layout of the pattern on the mask can be determined by performing an OPC process, and... Figure 4E The shape of the pattern on the mask is shown based on a defined layout of the pattern on the mask.

[0094] As a result, it can be seen that the horizontal cross-section of the fifth pseudo-channel structure DCS5 has a dumbbell shape based on an "I" shaped pattern layout. This is achieved by observing the characteristic of the vertices or corners of the pattern being bent during the reaction OPC process and etching process, such as... Figure 4E As shown, the horizontal cross-section of the fifth pseudo-channel structure DCS5 can have a dumbbell shape with its apex portion bent.

[0095] Reference Figure 7F First, it is possible to design with Figure 4F The layout of the pattern corresponding to the horizontal cross-section of the sixth pseudo-channel structure DCS6. For example, the pattern layout can have an "I" shape with a larger width in the first direction (x direction) (hereinafter referred to as a modified "I" shape). As described above, the sixth pseudo-channel structure DCS6 can be provided at the boundary between electrode pads that are adjacent to each other in the first direction (x direction). Therefore, the pattern layout can have a modified "I" shape that covers both electrode pads, or it can have a bracket shape in one electrode pad.

[0096] Next, the layout of the pattern on the mask can be finalized by performing the OPC process, and Figure 4F The shape of the pattern on the mask is shown, based on a defined layout of the pattern on the mask. As described above, the sixth pseudo-channel structure DCS6 can be disposed at the boundary between electrode pads that are adjacent to each other in the first direction (x direction). Therefore, for ease of understanding, Figure 7F The shape of the pattern on the mask is shown, extending rightward from the boundary portion of the electrode pads to the portion of another electrode pad.

[0097] As a result, it can be seen that the dumbbell shape (or, in terms of a single electrode pad, a bent bracket shape) of the horizontal cross-section of the sixth pseudo-channel structure DCS6 is based on a layout with a modified "I"-shaped pattern. This is achieved by incorporating the characteristic of the vertices or corners of the pattern being bent in the reaction OPC and etching processes, such as... Figure 4F As shown, the horizontal cross-section of the sixth pseudo-channel structure DCS6 can have a dumbbell shape (or bracket shape) with its vertex portion bent.

[0098] Figure 8A and Figure 8B It shows in Figures 7A to 7F The design of the pattern on the mask shown is a conceptual diagram describing the selection criteria.

[0099] Reference Figure 8A and Figure 8B Various features of the manufacturing process for forming a pseudo-channel structure DCS can be considered. Figure 8A Four selection criteria are shown, and Figure 8B A selection criterion is shown. Figure 8A The pseudo-channel structure DCS0 shown can correspond to the pattern of the horizontal cross-section of any pseudo-channel structure used to describe the selection criteria.

[0100] First, the first distance ① between the partition region DA and the dividing region DA in the second direction (y-direction) can be a selection criterion. The partition region DA can divide the area of ​​the gate electrode layer in the second direction (y-direction) and can be called the word line cut region. The partition region DA may include a pseudo-cut region. When the first distance ① is short, the pseudo-channel structure DCS0 may be attached to the partition region DA. Therefore, the first distance ① between the pseudo-channel structure DCS0 and the partition region DA in the second direction (y-direction) can ensure that, within a first set range, the pseudo-channel structure DCS0 does not attach to the partition region DA.

[0101] Next, the maximum distance ② between the pseudo-channel structures DCS0 in the diagonal direction spanning the vertical direct contact VC can be a selection criterion. When the vertical direct contact VC is formed after the pseudo-channel structure DCS0 is formed, the impact caused by the pseudo-channel structure DCS0 can be minimized. Therefore, it is possible to ensure that the pseudo-channel structure DCS0 and the vertical direct contact (see...) are within acceptable limits. Figure 11G The distance between the vertical direct contact holes (150H) is within a second set range, thereby minimizing interference caused by the pseudo-channel structure DCS0. Here, the vertical direct contact hole 150H can indicate the hole used to form the vertical direct contact VC. Vertical direct contact hole (see Figure 11CThe distance margin between VH2 and the vertical direct contact hole 150H can indicate the contact (MC) margin, and can ensure the MC margin when the pseudo-channel structure DCS0 is formed. With the size of the horizontal cross-section of the vertical direct contact VC remaining constant, the MC margin can increase as the maximum distance ② increases. Furthermore, the MC margin can indicate the distance margin between the pseudo-channel structure DCS0 and the vertical direct contact hole 150H.

[0102] Additionally, when the MC margin is too large, that is, when the distance between the pseudo-channel structure DCS0 and the vertical direct contact hole 150H is too large, the molded structure (see...) Figure 11A The likelihood of collapse of the molded structure 210 can increase. This means that when the pseudo-channel structures DCS0 are densely arranged, the collapse of the molded structure 210 can be prevented by smoothly performing the support function of the molded structure 210 during the replacement process of the gate electrode layer EL. Therefore, the MC margin can be based on two characteristics such as the distance margin for easy formation of the vertical direct contact VC and the support function of the molded structure 210.

[0103] Additionally, the major axis length ③ and minor axis length ④ of the pseudo-channel structure DCS0 can be selected as criteria. Increasing the major axis length ③ can enhance the fixation of the distortion angle. Increasing the minor axis length ④ can help prevent not-open (N / O) defects.

[0104] To provide a more detailed description, in the case of forming a second vertical aperture VH2 for the pseudo-channel structure DCS0, when the size of the horizontal cross-section of the pseudo-channel structure DCS0 is small, the second vertical aperture VH2 may not completely penetrate to reach the substrate (see...). Figure 3 The top surface of (101) leads to N / O defects, preventing the substrate from being exposed. Additionally, distortion angle defects can occur during the etching process, causing the horizontal cross-section of the pseudo-channel structure DCS to be distorted in any direction. Figure 8B The distortion angle (θ) is shown in the figure, and the distortion angle (θ) ⑤ can be a selection criterion.

[0105] This ensures sufficient horizontal cross-sectional area to prevent N / O defects or distortion angle defects. Furthermore, the major axis length of the horizontal cross-section can be increased to prevent distortion angle defects. Increasing the major axis length enhances distortion angle fixation, thereby minimizing distortion angle defects. Considering pattern density, the pattern density of the horizontal cross-section of the pseudo-channel structure DCS can be increased to minimize N / O defects or distortion angle defects. Here, pattern density can be defined as the area of ​​the horizontal cross-section of the pseudo-channel structure DCS relative to the total area of ​​the electrode pads.

[0106] The above text has described five selection criteria, and the selection criteria for the shape of the horizontal cross-section of the pseudo-channel structure DCS0 are not limited to these. For example, whether OPC can actually form the horizontal cross-section of the pseudo-channel structure DCS0 could be a selection criterion.

[0107] In describing the target Figures 7A to 7F When considering the advantages of the selection criteria for patterns on the mask, and... Figure 8A Compared to the pseudo-channel structure pattern of DCS0, Figure 7A The minor axis length of the mask pattern can be increased. Therefore, Figure 7A The mask pattern can remain consistent with Figure 8A The pseudo-channel structure DCS0 has a similar shape to the pattern, therefore it can avoid large deformation and reduce N / O defects caused by the increase in short axis length.

[0108] and Figure 8A Compared to the pattern of the pseudo-channel structure DCS0, in Figures 7B to 7E In the pattern on the mask, the pattern can extend in the second direction (y-direction), therefore, the length in the second direction (y-direction) can be increased. Therefore, in Figures 7B to 7E In the mask pattern, N / O defects can be reduced based on the increase of pattern density, and due to the structure connected in the second direction (y direction), the distance margin between pseudo-channel structures that are adjacent to each other in the second direction (y direction) can be disregarded.

[0109] and Figure 8A Compared to the pattern of the pseudo-channel structure DCS0, in Figure 7F In the mask pattern, due to the structure connected in the second direction (y direction), the length in the second direction (y direction) can be increased. Furthermore, the pattern can be set at the boundary portion of the electrode pads, thus increasing the maximum distance in the diagonal direction. Therefore, like... Figures 7B to 7E Like the pattern of a mask, Figure 7F The mask pattern can reduce N / O defects caused by increased pattern density, and... Figure 7F In the mask pattern, the distance margin between adjacent pseudo-channel structures in the second direction (y direction) can be disregarded. Furthermore, the maximum distance in the diagonal direction can be increased, thus ensuring sufficient MC margin.

[0110] Figure 9A and Figure 9B A plan view of the horizontal cross-section of the pseudo-channel structure and the vertical direct contact of the vertical non-volatile memory device according to an embodiment is shown. Figure 9A and Figure 9B The left side corresponds to the top surface of the upper molded structure, and Figure 9A and Figure 9B The right side corresponds to the top surface of the lower molded structure.

[0111] Reference Figure 9A Because the vertical non-volatile memory device 400a according to the embodiment is formed in a multilayer stacking process to include an upper molding structure and a lower molding structure, the vertical non-volatile memory device 400a according to the current embodiment can be coupled with structures respectively in… Figures 4A to 4F The vertical non-volatile memory devices 100a to 100f shown are different. Here, multilayer stacking process can refer to a process in which the height of the vertical non-volatile memory device increases in the vertical direction, making it difficult to form multiple holes through to the substrate in one step. Therefore, the molded structure is formed by performing two processes (see...). Figure 11A (210), and holes are formed separately in each molded structure.

[0112] The vertical non-volatile memory device 400a according to the current embodiment may include and Figure 4C The vertical non-volatile memory device 100c has a pseudo-channel structure similar to the third pseudo-channel structure DCS3. However, since the vertical non-volatile memory device 400a according to the present embodiment is formed by a multi-layer stacking process, the size of the upper pseudo-channel structure DCS3u formed in the upper molding structure can be different from the size of the lower pseudo-channel structure DCS3l formed in the lower molding structure. For example, as Figure 9A As shown, the horizontal cross-section of the upper pseudo-channel structure DCS3u formed in the upper molding structure can be smaller than the horizontal cross-section of the lower pseudo-channel structure DCS3l formed in the lower molding structure. Here, for example, the horizontal cross-section can correspond to the top surface of each of the upper pseudo-channel structure DCS3u and the lower pseudo-channel structure DCS3l. According to other embodiments, the horizontal cross-section of the upper pseudo-channel structure DCS3u can be larger than the horizontal cross-section of the lower pseudo-channel structure DCS3l, or can be substantially the same as the horizontal cross-section of the lower pseudo-channel structure DCS3l. Furthermore, although the upper molding structure and the lower molding structure have been described as separate elements, they can correspond to all electrode structures after the replacement process.

[0113] The vertical non-volatile memory device 400a according to the present embodiment is not limited to... Figure 4C The vertical non-volatile memory device 100c has a third pseudo-channel structure DCS3, and may include a structure having a pseudo-channel with respect to the vertical non-volatile memory device 100c. Figure 4A , Figure 4B and Figures 4D to 4FThe pseudo-channel structures shown in the figure are similar in shape to any one of the pseudo-channel structures DCS1, DCS2, and DCS4 to DCS6 of the vertical non-volatile memory devices 100a, 100b, and 100d to 100f. Furthermore, the dimensions of the upper pseudo-channel structure formed in the upper molding structure may differ from the dimensions of the lower pseudo-channel structure formed in the lower molding structure.

[0114] Reference Figure 9B Because the shape of the upper pseudo-channel structure DCS3u formed in the upper molding structure is different from the shape of the lower pseudo-channel structure DCS1l formed in the lower molding structure, the vertical non-volatile memory device 400b according to the current embodiment can be used with... Figure 9A This differs from the vertical non-volatile memory device 400a. For example, the vertical non-volatile memory device 400b according to the current embodiment can be formed by a multilayer stacking process to include an upper molding structure and a lower molding structure, and the upper pseudo-channel structure DCS3u can have the same characteristics as... Figure 4C The third pseudo-channel structure DCS3 has a similar shape, and the lower pseudo-channel structure DCS11 can have a similar shape to... Figure 4A The shape is similar to that of the first pseudo-channel structure DCS1 in the present embodiment. The pseudo-channel structure of the vertical non-volatile memory device 400b according to the present embodiment is not limited to the combination described above, but may include, for example, the corresponding... Figures 4A to 4F Various combinations of the first pseudo-channel structure DCS1 to the sixth pseudo-channel structure DCS6 in the model.

[0115] Figure 10 A flowchart illustrating a method for manufacturing a vertical non-volatile memory device according to an embodiment is shown. For brevity, references will be simply given below or may be omitted. Figures 1 to 9B The provided descriptions are the same or similar.

[0116] Reference Figure 10 First, the method for manufacturing a vertical non-volatile memory device according to the current embodiment can design the layout of a pattern of the horizontal cross-section of a pseudo-channel structure DCS in operation S110. The layout design operation (S110) can include a process for designing the layout of patterns DCP1 to DCP6 of the horizontal cross-section of the pseudo-channel structure DCS. (Refer to the above...) Figures 7A to 9B The description can be based on the characteristics of the manufacturing process and various selection criteria to design the pattern layout. For example, the pattern layout can be designed based on the five selection criteria mentioned above. However, the number of selection criteria is not limited to five.

[0117] Next, in operation S120, the design data of the mask can be obtained by performing OPC based on the layout. The operation of obtaining the design data of the mask (S120) may include a process of obtaining the outline of the target pattern as the result of OPC. In other words, OPC can be performed until an outline close to the target pattern is obtained, and when the desired reference outline is obtained, data corresponding to the layout of the pattern on the mask can be obtained as the design data of the mask.

[0118] Next, in operation S130, a mask can be manufactured by performing an exposure process based on the mask design data. To provide a more detailed description, the mask design data can be transferred to the mask manufacturing group as Mask Design To (MTO) design data. Mask Data Preparation (MDP) can be performed using the MTO design data, and a mask including the corresponding pattern can be manufactured by performing an exposure process on the substrate used for the mask.

[0119] After mask fabrication, in operation S140, a pseudo-channel structure DCS can be formed using the mask. The operation (S140) of forming the pseudo-channel structure DCS may include processes for forming a vertical channel structure VCS in the cell array region CAA and for forming the pseudo-channel structure DCS in the extended region EA. The operation (S140) of forming the pseudo-channel structure DCS may include processes for forming a first vertical hole VH1 and a second vertical hole VH2 and filling the first vertical hole VH1 and the second vertical hole VH2 with structural material. Prior to the operation (S140) of forming the pseudo-channel structure DCS, a molded structure 210 may be formed on the substrate 101.

[0120] Next, in operation S150, the vertical non-volatile memory device can be completed by performing subsequent semiconductor processes. These subsequent semiconductor processes can include various technologies. See below for details. Figures 11A to 11G The process following the mask manufacturing operation (S130) is described in more detail.

[0121] Figures 11A to 11G It shows in Figure 10 The cross-sectional view of the process following the mask fabrication process in the method for manufacturing a vertical non-volatile memory device is shown below. Figure 2 and Figure 3 And refer to Figures 11A to 11G This describes a method for manufacturing a vertical non-volatile memory device, and for brevity, the following will simply provide or may omit references. Figures 1 to 10 The provided descriptions are the same or similar.

[0122] Reference Figure 11AA molded structure 210 can be formed in the cell array region CAA and the extended region EA of the substrate 101. The molded structure 210 may include a plurality of sacrificial layers SL and a plurality of interlayer insulating layers ILDs stacked vertically and alternately. In the molded structure 210, the sacrificial layers SL may include a material with etch selectivity relative to the interlayer insulating layers ILDs. A trimming process can be performed on the molded structure 210 such that its vertical cross-section in the extended region EA has a stepped structure.

[0123] Reference Figure 11B After forming the molded structure 210, a planarization insulating layer 150 can be formed on the entire surface of the substrate 101. The planarization insulating layer 150 may include an insulating material that has etch selectivity relative to the sacrificial layer SL. After forming the planarization insulating layer 150, an etch stop layer 151 and a buffer insulating layer 153 may be sequentially formed on the planarization insulating layer 150. Here, the etch stop layer 151 may include a material that has etch selectivity relative to the planarization insulating layer 150 and the buffer insulating layer 153.

[0124] Reference Figure 11C Multiple first vertical holes VH1 can be formed in the cell array region CAA, passing through the buffer insulating layer 153, the etch stop layer 151, and the molding structure 210. Multiple second vertical holes VH2 can be formed in the extended region EA, passing through the buffer insulating layer 153, the etch stop layer 151, the planarization insulating layer 150, and the molding structure 210. Since the second vertical holes VH2 are formed in the extended region EA, the number of sacrificial layers SL passing through the second vertical holes VH2 can be reduced as the second vertical holes VH2 move away from the cell array region CAA.

[0125] Reference Figure 11D A first lower semiconductor pattern LSP1 and a second lower semiconductor pattern LSP2 can be formed to fill the lower portions of the first vertical aperture VH1 and the second vertical aperture VH2. The first lower semiconductor pattern LSP1 and the second lower semiconductor pattern LSP2 can be formed by performing a selective epitaxial growth (SEG) process using a substrate 101 exposed at the first vertical aperture VH1 and the second vertical aperture VH2 as a seed layer. The first lower semiconductor pattern LSP1 and the second lower semiconductor pattern LSP2 can be formed simultaneously; therefore, the first lower semiconductor pattern LSP1 and the second lower semiconductor pattern LSP2 can include the same semiconductor material.

[0126] Reference Figure 11EIn the cell array region CAA, a first data storage pattern VP1, a first upper semiconductor pattern USP1, and a first buried insulating pattern V1 can be formed in the first vertical aperture VH1 to complete the vertical channel structure VCS. Simultaneously, in the extended region EA, a second data storage pattern VP2, a second upper semiconductor pattern USP2, and a second buried insulating pattern V2 can be formed in the second vertical aperture VH2 to complete the pseudo-channel structure DCS. The first upper semiconductor pattern USP1 and the second upper semiconductor pattern USP2 can be connected to the first lower semiconductor pattern LSP1 and the second lower semiconductor pattern LSP2, respectively.

[0127] Next, multiple bit line electrode pads BP can be formed on the first upper semiconductor pattern USP1 of the vertical channel structure VCS, and multiple pseudo bit line electrode pads DBP can be formed on the second upper semiconductor pattern USP2 of the pseudo channel structure DCS. According to other embodiments, the second upper semiconductor pattern USP2 and the pseudo bit line electrode pads DBP may not be formed in the pseudo channel structure DCS.

[0128] Next, the buffer insulating layer 153 and the etch stop layer 151 are removed, and a first upper interlayer insulating layer 160 covering the top surface of the vertical channel structure VCS and the pseudo-channel structure DCS can be formed on the planarization insulating layer 150. (Refer to...) Figure 11F and Figure 11G After the first upper interlayer insulating layer 160 is formed, the electrode structure ST can be formed by performing a gate electrode layer replacement process in which the gate electrode layer EL replaces the sacrificial layer SL.

[0129] After forming the electrode structure ST, the common source region CSA, the insulating spacer IS, and the common source plug CSP can be formed (for example, see...). Figure 2 And a second interlayer insulating layer 170 can be formed on the first interlayer insulating layer 160. Next, in the extended region EA, a vertical direct contact hole 150H can be formed through the first interlayer insulating layer 160, the second interlayer insulating layer 170, and the planarization insulating layer 150. The vertical direct contact hole 150H can be formed between multiple pseudo-channel structures DCS. Next, conductive material can be embedded in the vertical direct contact hole 150H, thus forming a vertical direct contact VC connected to each of the gate electrode layers EL. Next, the aforementioned bit line contact plug BCP, sub-bit line SBL, bit line BL, and interconnect CL (e.g., see...) can be formed. Figure 3 ).

[0130] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the following claims.

Claims

1. A vertical non-volatile memory device, comprising: A substrate having a cell array region and an extended region extending from the cell array region in a first direction parallel to the top surface of the substrate; A vertical contact element is disposed on a substrate in the extended region and extends in a vertical direction perpendicular to the top surface of the substrate; Multiple vertical channel structures are located on the substrate in the unit array region and extend in the vertical direction; Multiple pseudo-channel structures are located on the substrate in the extended region and extend in the vertical direction, and are configured to be adjacent to the vertical direct contact; Multiple gate electrode layers and multiple interlayer insulating layers are alternately stacked on the substrate in the cell array region and the extended region along the sidewalls of the multiple vertical channel structures and the multiple pseudo channel structures; Electrode pads, which are connected to the vertical direct contact; as well as An additional electrode pad, which is longer than the electrode pad in the first direction. In the electrode pad, the first and second pseudo-channel structures of the plurality of pseudo-channel structures are respectively disposed on the first and second sides of the vertical direct contact in the first direction, and each of the plurality of pseudo-channel structures has a horizontal cross-section that is longer in the second direction than in the first direction. The second direction is parallel to the top surface of the substrate and extends perpendicular to the first direction. The additional pseudo-channel structure in the plurality of pseudo-channel structures is disposed at the boundary between the additional electrode pad and the adjacent electrode pad, and only half of the additional pseudo-channel structure is disposed in the additional electrode pad, while the other half of the additional pseudo-channel structure is disposed in the adjacent electrode pad.

2. The vertical non-volatile memory device according to claim 1, wherein, Each of the plurality of pseudo-channel structures has a horizontal cross-section that is one of a square, a bracket, a parenthesis, or a dumbbell shape, wherein the vertex portion of the horizontal cross-section is bent, and Some portions of the plurality of pseudo-channel structures are arranged on a line passing through the vertical direct contact in the first direction.

3. The vertical non-volatile memory device according to claim 1, wherein, The shape of the horizontal cross-section of the additional pseudo-channel structure is the same as the shape of the horizontal cross-section of each of the plurality of pseudo-channel structures.

4. The vertical non-volatile memory device according to claim 1, wherein, Each of the plurality of pseudo-channel structures comprises a semiconductor material.

5. The vertical non-volatile memory device according to claim 1, further comprising: The plurality of gate electrode layers are divided into regions extending in the first direction and in the second direction. Each of the plurality of gate electrode layers and the plurality of interlayer insulating layers has a stepped structure in the extended region along the vertical cross-section of the second direction. The distance between each of the plurality of pseudo-channel structures and the divided region in the second direction is within a first predetermined range, and The maximum distance between two pseudo-channel structures in the diagonal direction across the vertical direct contact member is within a second predetermined range.

6. A vertical non-volatile memory device, comprising: A substrate having a cell array region and an extended region extending from the cell array region in a first direction parallel to the top surface of the substrate; A vertical contact element is disposed on a substrate in the extended region and extends in a vertical direction perpendicular to the top surface of the substrate; Multiple vertical channel structures are located on the substrate in the unit array region and extend in the vertical direction; Multiple pseudo-channel structures are located on the substrate in the extended region and extend in the vertical direction, and are configured to be adjacent to the vertical direct contact; Multiple gate electrode layers and multiple interlayer insulating layers are alternately stacked on the substrate in the cell array region and the extended region along the sidewalls of the multiple vertical channel structures and the multiple pseudo channel structures; Electrode pads, which are connected to the vertical direct contact; as well as An additional electrode pad, which is longer than the electrode pad in the first direction. In the electrode pads, the plurality of pseudo-channel structures are respectively positioned at the vertices of a square relative to the vertical direct contact, and the vertical direct contact is located between the plurality of pseudo-channel structures. Furthermore, the horizontal cross-section of each of the plurality of pseudo-channel structures is a trapezoidal shape with its vertices bent. The additional pseudo-channel structure in the plurality of pseudo-channel structures is disposed at the boundary between the additional electrode pad and the adjacent electrode pad, and only half of the additional pseudo-channel structure is disposed in the additional electrode pad, while the other half of the additional pseudo-channel structure is disposed in the adjacent electrode pad.

7. The vertical non-volatile memory device according to claim 6, wherein, The shape of the horizontal cross-section of the additional pseudo-channel structure is the same as the trapezoidal shape of the horizontal cross-section of each of the plurality of pseudo-channel structures.

8. A vertical non-volatile memory device, comprising: A substrate having a cell array region and an extended region extending from the cell array region in a first direction parallel to the top surface of the substrate; Multiple vertical channel structures are located on the substrate in the unit array region and extend in a vertical direction perpendicular to the top surface of the substrate; Multiple vertical direct contacts are disposed in the extended area and connected to corresponding electrode pads in the multiple electrode pads; Multiple pseudo-channel structures are located on the substrate in the extended region and extend in the vertical direction, and are respectively configured to be adjacent to the multiple vertical direct contacts; Multiple gate electrode layers and multiple interlayer insulating layers are alternately stacked on the substrate in the cell array region and the extended region along the sidewalls of the multiple vertical channel structures and the multiple pseudo channel structures; as well as The substrate is divided into regions extending in the first direction and in a second direction extending parallel to the top surface of the substrate and perpendicular to the first direction. In at least one of the plurality of electrode pads, some of the plurality of pseudo-channel structures are disposed on both sides of the corresponding vertical direct contact in the first direction. The at least one electrode pad is connected to the corresponding vertical direct contact, and portions of the pseudo-channel structures are arranged on a line passing through the corresponding vertical direct contact in the first direction. The plurality of electrode pads include a first electrode pad and a second electrode pad, wherein the second electrode pad is longer than the first electrode pad in the first direction, and an additional pseudo-channel structure in the plurality of pseudo-channel structures is disposed at the boundary between the first electrode pad and the second electrode pad that are adjacent to each other, and only half of the additional pseudo-channel structure is disposed in the second electrode pad, while the other half of the additional pseudo-channel structure is disposed in the first electrode pad.

9. The vertical non-volatile memory device according to claim 8, wherein, Each of the plurality of pseudo-channel structures has a horizontal cross-section that is longer in the second direction than in the first direction.

10. The vertical non-volatile memory device according to claim 9, wherein, The shape of the horizontal cross-section of the additional pseudo-channel structure is the same as the shape of the horizontal cross-section of each of the plurality of pseudo-channel structures.

11. A method for manufacturing a vertical non-volatile memory device, the method comprising the steps of: The design will be a layout of a pattern of horizontal cross-sections forming the pseudo-channel structure in the electrode pads of the vertical non-volatile memory device. Based on the layout, perform optical proximity correction (OPC) to obtain mask design data; The mask is manufactured based on the design data; as well as The pseudo-channel structure is formed using the mask. The vertical non-volatile memory device includes: a substrate having a cell array region and an extended region extending from the cell array region in a first direction; a vertical contact disposed in the extended region; a partitioning region partitioning a gate electrode layer in a second direction perpendicular to the first direction; and an additional electrode pad longer than the electrode pad in the first direction. The pseudo-channel structure is disposed in the electrode pad to surround the vertical direct contact, and the first and second pseudo-channel structures in the pseudo-channel structure are disposed on the first and second sides of the vertical direct contact in the first direction, or the four pseudo-channel structures in the pseudo-channel structure are disposed at the vertices of a square relative to the vertical direct contact, with the vertical direct contact located between the four pseudo-channel structures. The layout design includes: designing the layout such that the distance between the pseudo-channel structure and the divided area in the second direction is within a first predetermined range, and the maximum distance between two pseudo-channel structures in the diagonal direction crossing the vertical direct contact member is within a second predetermined range. The layout design includes: further designing the layout of the pattern of the additional pseudo-channel structure to be formed in the additional electrode pads, and The formation of the pseudo-channel structure includes: further forming the additional pseudo-channel structure at the boundary between the additional electrode pad and the adjacent electrode pad, wherein only half of the additional pseudo-channel structure is formed in the additional electrode pad and the other half of the additional pseudo-channel structure is formed in the adjacent electrode pad.

12. The method according to claim 11, wherein, With the first pseudo-channel structure and the second pseudo-channel structure configured, the pattern has a shape that is longer in the second direction than in the first direction, and The layout design includes: designing the layout such that the pattern is placed on both sides of the vertical direct contact in the first direction.

13. The method according to claim 12, wherein, The pattern has one of the following shapes: rectangular, square bracket, modified square bracket, and I-shaped. The horizontal cross-section has one of a square, a bracket, a parenthesis, and a dumbbell shape, wherein, in the pattern, the vertex portion of the horizontal cross-section is bent.

14. The method according to claim 11, wherein, With the four pseudo-channel structures configured, the pattern has a T-shape. The layout design includes: arranging the two patterns on opposite sides of the vertical direct contact in the first direction, such that the T-shaped tails face each other in the second direction. The horizontal cross-section has a trapezoidal shape, wherein the vertex portion of the horizontal cross-section is bent. The trapezoidal shape is one in which the width gradually decreases or increases in the second direction, and The two pseudo-channel structures that are adjacent to each other in the second direction are configured such that the narrower portions of the trapezoidal shape face each other.

15. A vertical non-volatile memory device, comprising: A substrate having a cell array region and an extended region extending from the cell array region in a first direction parallel to the top surface of the substrate; A vertical contact element is disposed on a substrate in the extended region and extends in a vertical direction perpendicular to the top surface of the substrate; Multiple pseudo-channel structures are located on the substrate in the extended region and extend in the vertical direction, and are configured to be adjacent to the vertical direct contact; Multiple gate electrode layers and multiple interlayer insulating layers are alternately stacked on the substrate in the cell array region and the extended region along the sidewalls of the multiple pseudo-channel structures; An electrode pad is connected to the vertical direct contact, wherein the electrode pad includes at least one first pseudo-channel structure and at least one second pseudo-channel structure among a plurality of pseudo-channel structures, the at least one first pseudo-channel structure is disposed on a first side of the vertical direct contact in the first direction, and the at least one second pseudo-channel structure is disposed on a second side of the vertical direct contact in the first direction. The plurality of gate electrode layers are divided into regions extending in the first direction and in a second direction extending parallel to the top surface of the substrate and perpendicular to the first direction; and An additional electrode pad, which is longer than the electrode pad in the first direction. The additional pseudo-channel structure in the plurality of pseudo-channel structures is disposed at the boundary between the additional electrode pad and the adjacent electrode pad, and only half of the additional pseudo-channel structure is disposed in the additional electrode pad, while the other half of the additional pseudo-channel structure is disposed in the adjacent electrode pad.

Images