Clock time synchronization method, device, equipment and storage medium

Abstract

This application proposes a clock time synchronization method, apparatus, device, and storage medium. The method includes: sending a delay determination signal to a signal transceiver port within a slave node; obtaining a delay feedback signal from the slave node; determining a master-slave time difference based on the delay feedback signal and the delay determination signal; sending the master-slave time difference to the slave node; and synchronizing clock time with the slave node based on the master-slave time difference. The technical solution of this application, by determining the master-slave time difference of the signal between the master node and the slave node through the delay determination signal and the delay feedback signal, and compensating for clock time based on the master-slave time difference, improves the accuracy of clock time synchronization, reduces time errors caused by asymmetric transmission paths, and can improve service stability.

Description

Technical Field

[0001] The present application relates to a wired communication network, and in particular to a clock time synchronization method, device, system and storage medium. Background Art

[0002] The existing clock time synchronization method in the communication network is mainly based on PTP1588 technology. One of the two connected nodes is used as a master node and the other as a slave node. Under normal circumstances, the slave node synchronizes the clock of the master node, and the nodes use the same clock. The master and slave nodes communicate through 1588 messages to send and receive data packets to achieve clock time synchronization between nodes. This clock time synchronization method consumes time when the 1588 message is transmitted internally between the master node and the slave node. There is a time difference between the master and slave nodes when synchronizing the clock time. The accuracy of the clock time is poor. When the node state changes, the synchronization time is prone to sudden changes, which affects the business. Summary of the invention

[0003] The present application provides a clock time synchronization method, apparatus, device and storage medium.

[0004] The embodiment of the present application provides a clock time synchronization method, which is applied to a master node, including:

[0005] Send a delay determination signal to a signal transceiver port in a slave node; obtain a delay feedback signal from the slave node; determine a master-slave time difference according to the delay feedback signal and the delay determination signal; send the master-slave time difference to the slave node, and synchronize the clock time with the slave node according to the master-slave time difference.

[0006] The embodiment of the present application provides a clock time synchronization method, which is applied to a slave node, including:

[0007] A delay determination signal is received from a signal transceiver port in a master node; a delay feedback signal is sent to the master node; a master-slave time difference determined by the master node according to the delay determination signal and the delay feedback signal is received, and clock time synchronization is performed with the master node according to the master-slave time difference.

[0008] The embodiment of the present application provides a clock time synchronization device, which is applied to a master node, including:

[0009] An information sending module is used to send a delay determination signal to a signal transceiver port in a slave node; a signal receiving module is used to obtain a delay feedback signal from the slave node; a delay determination module is used to determine a master-slave time difference according to the delay feedback signal and the delay determination signal; a clock synchronization module is used to send the master-slave time difference to the slave node and perform clock time synchronization with the slave node according to the master-slave time difference.

[0010] The embodiment of the present application provides a clock time synchronization device, which is applied to a slave node, including:

[0011] A signal receiving module is used to receive a delay determination signal from a signal transceiver port in a master node; a signal feedback module is used to send a delay feedback signal to the master node; a clock synchronization module is used to receive a master-slave time difference determined by the master node according to the delay determination signal and the delay feedback signal, and perform clock time synchronization with the master node according to the master-slave time difference.

[0012] The present application provides a device, including:

[0013] One or more processors; a memory for storing one or more programs;

[0014] When the one or more programs are executed by the one or more processors, the one or more processors implement the clock time synchronization method as described in any one of the embodiments of the present application.

[0015] An embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, wherein when the program is executed by a processor, a clock time synchronization method as described in any one of the embodiments of the present application is implemented.

[0016] The technical solution of the embodiment of the present application determines the time deviation between the master node and the slave node by sending a delay determination signal to the slave node, obtaining the delay feedback signal of the slave node, and performing time synchronization with the slave node based on the time deviation, thereby reducing the time error caused by time consumption during internal transmission, improving the accuracy of the synchronized clock time of the master node and the slave node, solving the time mutation problem caused by the change of node status, and reducing business impact.

[0017] With regard to the above embodiments and other aspects of the present application and their implementation, further description is provided in the accompanying drawings, detailed description and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a flow chart of a clock time synchronization method provided by an embodiment of the present application;

[0019] Figure 2 It is a topological structure diagram of a network element provided in an embodiment of the present application;

[0020] Figure 3 is a flow chart of a clock time synchronization method provided by an embodiment of the present application;

[0021] Figure 4 It is a structural diagram of a master node provided in an embodiment of the present application;

[0022] Figure 5 is an example diagram of a clock time synchronization method provided by an embodiment of the present application;

[0023] Figure 6 is a flow chart of a clock time synchronization method provided by an embodiment of the present application;

[0024] Figure 7 is a flow chart of a clock time synchronization method provided by an embodiment of the present application;

[0025] Figure 8 It is a structural diagram of a clock time synchronization device provided in an embodiment of the present application;

[0026] Fig. 9 It is a structural diagram of a clock time synchronization device provided in an embodiment of the present application;

[0027] Fig.10 It is a structural schematic diagram of a device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the present application more clear, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0029] Figure 1 is a flowchart of a clock time synchronization method provided by an embodiment of the present application. The embodiment of the present application can be applied to the case of synchronizing the clock time of network elements in a communication network. The method can be executed by a clock time synchronization device in an embodiment of the present application. The device can be implemented by software and / or hardware and can generally be integrated in the master node of the network element device. See Figure 1 , the clock time synchronization method of the embodiment of the present application includes:

[0030] Step 101: Send a delay determination signal to a signal transceiver port in a slave node.

[0031] Among them, the master node can be a network element node that sends clock time when performing clock synchronization, and the slave node can be a network element node that receives clock time when performing clock synchronization. The master node and the slave node can be connected in a wired or wireless manner. Figure 2 This is a topological diagram of a network element provided in an embodiment of the present application, see Figure 2 When network element A sends the clock time to network element B for clock synchronization, network element A can be the master node and network element B can be the slave node; when network element B sends the clock time to network element C for clock synchronization, network element B can be the master node and network element C can be the slave node.

[0032] Specifically, the information transceiver port can be a port for receiving signals within the slave node, and specifically can be an optical monitoring port on the interface board in the network element. The master node can send a delay determination signal to the signal transceiver port of the slave node to obtain the time error inside the master node and the slave node, wherein the delay determination signal can be a service signal transmitted between the master node and the slave node, and specifically can be a GE optical signal or a 10GE signal, etc. The delay determination signal can be transmitted between the master node and the slave node, and can be used to determine the time error inside network elements such as the master node and the slave node.

[0033] Step 102: Obtain a delay feedback signal from the slave node.

[0034] Among them, the delay feedback signal can be a business signal sent from the node to the master node, specifically a GE optical signal or a 10GE signal, etc. The delay feedback signal can include custom-coded TOD information, the TOD information can be composed of the sending time and receiving time of the delay determination signal and the sending time and receiving time of the delay feedback information. The delay feedback signal can include the receiving time of the delay determination information at the slave node and the sending time of the delay feedback signal at the slave node.

[0035] In an embodiment of the present application, a delay feedback signal sent from a node may be obtained. Specifically, an optical monitoring port in an interface board of the slave node may be monitored to obtain the delay feedback signal sent from the node.

[0036] Step 103: Determine the master-slave time difference according to the delay feedback signal and the delay determination signal.

[0037] The master-slave time difference may be the error time between the master node and the slave node clocks, and the master-slave time difference may be the time deviation between the master node and the slave node due to transmission processing inside the network element node.

[0038] Specifically, the time consumed by the message in the master node and the time consumed in the slave node can be determined based on the delay feedback signal and the delay determination signal reception time and transmission time, so that the time deviation caused by internal time consumption can be reduced when the master and slave nodes perform clock synchronization. The delay determination signal can be parsed to obtain the master node message sending time and message receiving time in the delay determination signal. The delay feedback signal can be parsed to obtain the message sending time and message receiving time in the slave node. The internal time deviation of the master node sending and receiving messages and the internal time deviation of the slave node sending and receiving messages can be determined through the message sending time and message receiving time of the master node and the slave node. The master-slave time difference between the master node clock time and the slave node clock time can be determined through the above deviations.

[0039] Step 104: Send the master-slave time difference to the slave node, and perform clock time synchronization with the slave node according to the master-slave time difference.

[0040] Specifically, the master node can send the master-slave time difference to the slave node, and the slave node can compensate the local clock time of the slave node according to the master-slave time difference. For example, the time of the local clock of the slave node plus the master-slave time difference can be added to the new time. The master node can also compensate for the synchronized clock time when performing clock synchronization, and the slave node can use the acquired clock time as the clock time of the slave node.

[0041] The technical solution of the embodiment of the present application sends a delay determination signal to the slave node and obtains the delay feedback signal of the slave node, determines the master-slave time difference between the master node and the slave node through the delay determination signal and the delay feedback information, and performs clock synchronization based on the master-slave time difference, thereby reducing the time error caused by time consumption during internal transmission, improving the accuracy of clock time, solving the time mutation problem caused by node state changes, and enhancing business stability.

[0042] Figure 3 is a flow chart of a clock time synchronization method provided in an embodiment of the present application. To further improve the accuracy of the clock time, the master node in the embodiment of the present application uses the clock at the interface board as the standard to determine the master-slave time difference of the data. Figure 3 , the clock time synchronization method of the embodiment of the present application includes:

[0043] Step 201: Determine a signal receiving and transmitting port according to the acquired board number and port number of the slave node.

[0044] Among them, the slave node may include an interface board, a main control board and a service board. The single board number can identify the information of the interface board, the main control board and the service board. The interface board may include one or more optical monitoring ports, and the port number can identify different optical monitoring ports.

[0045] Specifically, an optical monitoring port in the slave node can be determined in advance by means of a single board number and a port number, and the port can be used as an access point for determining the master-slave time difference between the master node and the slave node. Exemplarily, a port status mark can be automatically or manually set in the optical monitoring port, and when the port status mark in the optical monitoring port is 1, it can be identified that the optical monitoring port belongs to the master node, and when the port status mark in the optical monitoring port is 0, it can be identified that the optical monitoring port belongs to the slave node.

[0046] Step 202: Send the delay determination signal from the optical monitoring port of the interface board to the signal transceiver port.

[0047] The optical monitoring port of the interface board may be a port for sending a delay determination signal in the master node.

[0048] In the embodiment of the present application, the master node can establish a connection from the interface board optical port to the predetermined signal transceiver port, and can send the delay determination signal to the transceiver port through the interface optical monitoring port. Figure 4 This is a schematic diagram of the structure of a master node provided in an embodiment of the present application, see Figure 4 ,Since the delay determination signal is generated in the master control, and the delay determination signal is sent at the ,optical monitoring port of the interface board in the master node, in order to reduce the error of the master-slave time difference, a timestamp can be added to the delay determination signal at the ,optical monitoring port of the interface board, and the timestamp time can be the time of the FPGA in the ,interface board.

[0049] Step 203: Determine the first sending time of the delay determination signal at the optical monitoring port of the interface board.

[0050] The first sending time may be the time when the delay determination signal is sent from the optical monitoring port of the interface board of the master node. The first sending time may be added to the delay determination signal and sent. The first sending time may also be stored in the master node.

[0051] Specifically, when the delay determination signal is sent from the optical monitoring port of the interface board, a timestamp of the delay determination signal may be generated, and the time corresponding to the timestamp may be used as the first sending time of the delay determination signal. Figure 4 This is a schematic diagram of the structure of a master node provided in an embodiment of the present application, see Figure 4 ,Since the delay determination signal is generated in the master control, and the delay determination signal is sent at the ,optical monitoring port of the interface board in the master node, in order to reduce the error of the master-slave time difference, a timestamp can be added to the delay determination signal at the ,optical monitoring port of the interface board, and the timestamp time can be the time of the FPGA in the ,interface board.

[0052] In one embodiment, determining the first sending time of the delay determination signal at the optical monitoring port of the interface board includes:

[0053] Obtain a first entry clock phase of the delay determination signal entering a signal processing device in an optical monitoring port of the interface board; obtain a first output clock phase of the delay determination signal output from the signal processing device; use a phase difference between the first output clock phase and the first entry clock phase as a first sending compensation time for the delay determination signal, and determine a first sending time according to the port clock of the optical monitoring port of the interface board and the first sending compensation time.

[0054] In an embodiment of the present invention, since the received delay determination signal needs to be processed inside the network element, the accurate reception time of the message can only be obtained after processing, so it is necessary to compensate for the time of processing the delay determination signal to improve the accuracy of the clock, wherein the signal processing device can specifically be a serdes, and the phase of the system clock of the master node when the delay determination signal enters the signal processing device can be recorded as the first entry clock phase, and the phase of the system clock output from the signal processing device by the delay determination signal can be recorded as the first output clock phase, and the phase difference between the first output clock phase and the first entry clock phase can be calculated, and the time length corresponding to the phase difference can be used as the first sending compensation time for processing the delay determination signal, and the first sending compensation time can be added on the basis of the first sending time obtained by the master node, so as to obtain the actual sending time of the delay determination signal sent in the master node.

[0055] Step 204: Receive the delay feedback signal sent by the signal transceiver port of the slave node through the optical monitoring port of the interface board.

[0056] In an embodiment of the present application, the optical monitoring port of the interface board of the master node can monitor the transceiver port of the slave node. When the slave node sends a delay feedback signal from the transceiver port, the delay feedback signal in the transceiver port can be obtained. The delay feedback signal may include the time when the slave node receives the delay determination information.

[0057] Step 205: Determine a second receiving time of the delay feedback signal at the optical monitoring port of the interface board.

[0058] The second receiving time may be the time when the master node receives the delay feedback signal, and may be determined by the FPGA in the interface board.

[0059] Specifically, when the master node receives the delay feedback signal, it can generate a timestamp to identify the second receiving time of the delay feedback signal, and the determination of the timestamp can be performed by the FPGA in the master node interface board. Further, since the message receiving time can be determined only after the delay feedback signal passes through the signal processing device of the optical monitoring port, the processing time can be determined by the clock phase difference between the delay feedback signal entering and outputting the signal processing device, and the processing time can be subtracted from the second receiving time to obtain the real second receiving time when the master node receives the delay feedback signal.

[0060] Step 206: Obtain a first sending time of the delay determination signal and a second receiving time of the delay feedback signal in the master node.

[0061] Specifically, the first sending time and the second receiving time can be stored in the master node, for example, can be stored in the FPGA of the interface board. When determining the master-slave time difference, the first sending time and the second receiving time can be sent by the interface board to the master control of the master node.

[0062] Step 207: parse the delay feedback signal to obtain the first receiving time of the delay determination signal and the second sending time of the delay feedback signal.

[0063] Specifically, the delay feedback information may include a first receiving time and a second sending time of receiving a delay determination signal from a node. It is understandable that the first receiving time and the second sending time may be the time at an optical monitoring port of an interface board in the slave node.

[0064] Step 208: Determine a master-slave time difference according to the first sending time, the first receiving time, the second sending time, and the second receiving time.

[0065] Specifically, the difference between the first receiving time and the first sending time can be used as the transmission time of the delay determination signal, and the difference between the second receiving time and the second sending time can be used as the transmission time of the delay feedback signal. In the embodiment of the present invention, the transmission time error of the message between the master node and the slave node may be ignored. For example, a single-fiber bidirectional transmission method can be used to ensure that the data transmission time of the master node and the slave node is the same, and the average value of the transmission time of the delay determination signal and the transmission time of the delay feedback signal can be used as the master-slave time difference.

[0066] Step 209: Send the master-slave time difference to the slave node, and perform clock time synchronization with the slave node according to the master-slave time difference.

[0067] In one implementation, the master-slave time difference is encapsulated into a transmission signal in a preset format; the transmission signal is sent to the slave node, so that the slave node synchronizes the clock time according to the master-slave time difference.

[0068] Specifically, the master-slave time difference can be encapsulated in a preset format, for example, it can be encapsulated as TOD information, each TOD information can include 4 time information, which can be the first sending time, the first receiving time, the second sending time and the second receiving time, each time information is 10 bytes, 2 CRCs, and 8 bytes of reserved information. The TOD information can be sent 1000 times or more per second so that the master node and the slave node can obtain the time error inside the network element in time, so that the slave node can achieve accurate time synchronization between the master node and the slave node according to the master-slave time difference. The technical solution of the embodiment of the present application determines the signal transceiver port by acquiring the board number and port number of the slave node, sends the delay determination signal from the optical monitoring port of the receiving board to the information transceiver port, determines the first sending time of the delay determination signal at the optical monitoring port of the interface board, determines the second receiving time of the delay feedback signal at the optical monitoring end of the interface board, parses the delay feedback signal to obtain the first receiving time of the delay determination signal and the second sending time of the delay feedback signal, determines the master-slave time difference according to the first sending time, the first receiving time, the second sending time and the second receiving time, sends the master-slave time difference to the slave node, and synchronizes the clock time with the slave node according to the master-slave time difference, thereby realizing accurate synchronization of the clock time, reducing the error caused by the asymmetry of the transmission path, and improving the stability of the service.

[0069] For example, Figure 5 This is an example diagram of a clock time synchronization method provided by an embodiment of the present application, see Figure 5 The delay feedback signal can be specifically GE signal 0. The GE signal 0 recovered and processed by the optical monitoring port of the interface board can be modified to add a custom-coded TOD signal 1. The TOD signal can be sent periodically. The TOD information can be sent 1000 times or more per second. Each TOD information can include 4 time information, which can be the sending time and receiving time of the delay determination signal and the sending time and receiving time of the delay feedback signal. Each time information is 10 bytes, 2 CRCs, and 8 bytes of reserved information. Figure 5Custom coded TOD information is generated at number 5. Serdes pins can be introduced for GE signals. Reference clock 2 can use 250M system clock. Serdes of FPGA can extract 125M CDR clock from connected GE signal 0 and divide it to SEC chip as possible clock source 4. Meanwhile, the phase difference (phase difference △p of clock edge) between 250M system clock 2 and 125M CDR clock 4 is measured. Meanwhile, the phase relationship between system clock 2 and the edge of transmitted GE signal is measured inside FPGA. Meanwhile, the delay from GE signal 0 of serdes input pin 5 to received internal GE signal 6 is measured. The delay from transmitted GE signal 8 to GE signal 7 of serdes output pin is measured. These delays are variable values. By measuring the variable values, the variable values ​​of this part can be compensated. For serdes sampling, the 250M system clock can be used as the serdes reference clock, and the 125M signal can be treated as the sampled signal. In this way, the serdes rx data is the 250MRX_GE_CLK clock plus the 32-bit width data. Note that the 250M clock RX_GE_CLK and the 250M system clock are synchronized but out of phase. RX_GE_CLK can be provided by the FPGA. According to RX_GE_CLK and 32-bit data, a normal signal and a data GE_RX_DATA can be obtained through the algorithm to represent the sampled GE signal. At the same time, an RX_GE_OFFSET signal is generated to represent the deviation value of the actual position of the GE signal relative to the rising edge of RX_GE_CLK. RX_GE_CLK plus the normal signal to obtain a 125M clock equal to the GE recovery clock. The logic calculates the phase difference between RX_GE_CLK and the 250M system clock, and then the phase difference between the GE signal and the 250M system clock can be calculated based on RX_GE_OFFSET.

[0070] Figure 6 is a flowchart of a clock time synchronization method provided by an embodiment of the present application. The embodiment of the present application can be applied to the case of synchronizing the clock time of network elements in a communication network. The method can be executed by a clock time synchronization device in an embodiment of the present application. The device can be implemented by software and / or hardware, and can generally be integrated in a slave node of a network element device. See Figure 6 , the clock time synchronization method of the embodiment of the present application includes:

[0071] Step 301: Receive a delay determination signal from a signal transceiver port in a master node.

[0072] Among them, the signal transceiver port can be an optical monitoring port in the master node interface board, which can be pre-identified with the slave node by means of the board number and the port number. When the slave node sends and receives signals with the master node, it can be done through the pre-identified signal transceiver port.

[0073] Specifically, the slave node may monitor the signal transceiver port to obtain the delay determination signal sent by the master node through the signal transceiver port, wherein the delay determination signal may be used to determine the communication delay between the master node and the slave node.

[0074] Step 302: Send a delay feedback signal to the master node.

[0075] In an embodiment of the present application, the slave node may also send a delay feedback signal to the master node, which may be used to determine the transmission time from the slave node to the master node. It may be understood that the slave node may send the delay feedback signal to the master node after receiving the delay determination signal sent by the master node, and the delay feedback signal may include the time when the slave node sends the delay feedback signal.

[0076] Step 303: Receive the master-slave time difference determined by the master node according to the delay determination signal and the delay feedback signal, and perform clock time synchronization with the master node according to the master-slave time difference.

[0077] Specifically, the slave node can receive the master-slave time difference based on the delay determination signal and the delay feedback signal of the master node. Since the network element node consumes time to process the signal internally, there is a deviation between the synchronized clock time and the true clock time. The delay determination signal and the delay feedback signal can be used to determine the time error of the signal processed internally by the master node and the slave node respectively. The deviation of the internal time causes the time difference between the master and slave nodes. The master-slave time difference can be determined by the delay determination signal and the delay feedback signal. Specifically, the clock synchronization can be performed through the master-slave time difference determined by the master node, and the master-slave time difference can be supplemented on the basis of the clock time sent by the master node. For example, the master-slave time difference can be added or subtracted from the clock time as the clock time of the slave node.

[0078] The technical solution of the embodiment of the present application receives a delay determination signal from the signal transceiver port of the master node, sends a delay feedback signal to the master node, receives the master-slave time difference determined by the master node according to the delay determination signal and the delay feedback signal, and performs clock synchronization with the master node according to the master-slave time difference, thereby achieving high-precision synchronization of the clock time of the master node and the slave node, reducing errors caused by time consumption during internal transmission, and enhancing the stability of the business.

[0079] Figure 7is a flowchart of a clock time synchronization method provided in an embodiment of the present application, which specifies the clock time for determining the master-slave time difference, see Figure 7 , the clock time synchronization method of the embodiment of the present application includes:

[0080] Step 401: Obtain the board number and port number of the master node.

[0081] Specifically, an optical monitoring port in the master node may be determined in advance by means of a board number and a port number, and the port may be used as an access point for determining the master-slave time difference between the master node and the slave node.

[0082] Step 402: Use the optical monitoring port corresponding to the board number and the port number in the master node as a signal transceiver port.

[0083] Specifically, the corresponding interface board in the master node can be searched according to the single board number, and the corresponding optical monitoring port can be determined in the found interface board according to the port number. The optical monitoring port can be used as a signal transceiver port for signal transmission between the master node and the slave node, and the slave node can monitor the signal transceiver port to obtain communication signals.

[0084] Step 403: Receive the delay determination signal sent by the signal transceiver port.

[0085] In an embodiment of the present application, the slave node can monitor the signal transceiver port on the interface board in the master node to obtain the delay determination signal sent by the master node, wherein the delay determination signal may include the time sent from the optical monitoring port in the master node.

[0086] Step 404: Determine a first receiving time at which the delay determination signal is received by the optical monitoring port of the interface board of the slave node.

[0087] Specifically, the optical monitoring port of the interface board of the slave node can receive the delay determination signal sent by the master node. When the slave node receives the delay determination signal, it can determine the first receiving time based on the clock at the slave node interface board, wherein the first receiving time can be the time when the slave node receives the delay determination signal. By using the clock time at the interface board as the first receiving time, the accuracy of the clock time synchronization between the master node and the slave node can be further improved.

[0088] In one implementation, determining a first reception time of the delay determination signal received by an optical monitoring port of an interface board of a slave node includes:

[0089] Obtain a second entry clock phase of the delay determination signal entering a signal processing device in an optical monitoring port of the interface board; obtain a second output clock phase of the delay determination signal output from the signal processing device; use a phase difference between the second output clock phase and the second entry clock phase as a first reception compensation time of the delay determination signal, and determine a first reception time according to the port clock of the optical monitoring port of the interface board and the first reception compensation time.

[0090] In an embodiment of the present invention, since the received delay determination signal needs to be processed inside the network element, the accurate reception time of the message can be obtained only after processing, so it is necessary to compensate for the time of processing the delay determination signal to improve the accuracy of the clock, wherein the signal processing device can specifically be a serdes, and the phase of the system clock of the slave node when the delay determination signal enters the signal processing device can be recorded as the second entry clock phase, and the phase of the system clock output from the signal processing device of the delay determination signal can be recorded as the second output clock phase, and the phase difference between the second output clock phase and the second entry clock phase can be calculated, and the time length corresponding to the phase difference can be used as the first reception compensation time for the slave node to process the delay determination signal, and the first reception compensation time can be subtracted from the first reception time obtained by the master node, and the actual reception time of the delay determination signal can be received from the node.

[0091] Step 405: Send the delay feedback signal from the optical monitoring port of the interface board to the signal transceiver port.

[0092] Specifically, the delay feedback signal can be a signal that determines the signal transmission time from the slave node to the master node. The delay feedback signal can be sent to the master node by the optical monitoring port of the interface board of the slave node, and the master node can receive the delay feedback signal through the signal transceiver port.

[0093] Step 406: Determine a second sending time of the delay feedback signal at the optical monitoring port of the interface board.

[0094] In the embodiment of the present application, when the slave node sends the delay feedback signal, it can determine the second sending time of the optical monitoring port of the interface board, and the second sending time can be specifically the clock time from the node interface board. Further, the second sending time can be added to the delay feedback signal in the form of timestamp information and sent together, and the second sending time can also be sent separately to the master node.

[0095] Furthermore, since the delay feedback signal can only be received from the node after passing through the signal processing device of the optical monitoring port, the determined delay feedback signal sending time must be earlier than the time when the delay feedback signal is sent from the node. The processing time can be determined by the clock phase difference of the delay feedback signal entering and outputting the signal processing device. The processing time can be added to the second sending time to obtain the real time when the delay feedback signal is sent from the node.

[0096] Step 407: Receive the master-slave time difference determined by the master node according to the delay determination signal and the delay feedback signal, and perform clock time synchronization with the master node according to the master-slave time difference.

[0097] Specifically, the slave node can receive the master-slave time difference based on the delay determination signal and the delay feedback signal from the master node. Due to the asymmetry of communication transmission between the master node and the slave node, the communication delay of the signal from the master node to the slave node and the communication delay of the signal from the slave node to the master node can be determined respectively through the delay determination signal and the delay feedback signal. The master-slave time difference can be determined at the master node through the communication delays in two directions. When the slave node is synchronized according to the clock time of the master node, it can compensate for the master-slave time difference based on the clock time sent by the master node.

[0098] The technical solution of the embodiment of the present application obtains the single board number and port number of the master node, determines the optical monitoring port in the master node as the signal transceiver port according to the single board number and the port number, receives the delay determination signal sent by the signal transceiver port, and determines a first receiving time for receiving the delay determination signal, sends a delay feedback signal to the master node, and determines a second sending time for sending the delay feedback signal, receives the master-slave time difference determined by the master node according to the delay determination signal and the delay feedback signal, and performs clock time synchronization according to the master-slave time difference, thereby achieving high-precision synchronization of the clock time of the master node and the slave node, reducing the time error caused by signal processing and transmission inside the network element, and improving the stability of the service.

[0099] Figure 8 This is a schematic diagram of the structure of a clock time synchronization device provided by an embodiment of the present application. The embodiment of the present application can be applied to the situation of network element clock time synchronization, and can execute the clock time synchronization method provided by any embodiment of the present application, and has the corresponding functional modules and beneficial effects of the execution method. The device can be implemented by software and / or hardware, and can be integrated in the master node of the network element, see Figure 8 The device of the embodiment of the present application specifically includes: an information sending module 501, a signal receiving module 502, a delay determination module 503 and a clock synchronization module 504.

[0100] The information sending module 501 is used to send a delay determination signal to a signal transceiver port in a slave node.

[0101] The signal receiving module 502 is used to obtain a delay feedback signal from the slave node.

[0102] The delay determination module 503 is used to determine the master-slave time difference according to the delay feedback signal and the delay determination signal.

[0103] The clock synchronization module 504 is used to send the master-slave time difference to the slave node, and perform clock time synchronization with the slave node according to the master-slave time difference.

[0104] The technical solution of the embodiment of the present application is to send a delay determination signal to the slave node through the information sending module, the signal receiving module obtains the delay feedback signal of the slave node, the delay determination module determines the master-slave time difference between the master node and the slave node through the delay determination signal and the delay feedback information, and the clock synchronization module performs time synchronization according to the master-slave time difference, thereby reducing the time difference caused by time uncertainty inside the master node, improving the accuracy of the clock time, solving the time mutation problem caused by the change of node status, and enhancing the stability of the business.

[0105] In one implementation, the device of the embodiment of the present application further includes:

[0106] The port determination module is used to determine the signal receiving and transmitting port according to the obtained board number and port number of the slave node.

[0107] In one implementation, the information sending module 501 includes:

[0108] The signal sending unit is used to send the delay determination signal from the optical monitoring port of the interface board to the signal transceiver port.

[0109] The sending time unit is used to determine the first sending time of the delay determination signal at the optical monitoring port of the interface board.

[0110] In one implementation, the sending time unit is specifically used for:

[0111] Obtain a first entry clock phase of the delay determination signal entering a signal processing device in an optical monitoring port of the interface board; obtain a first output clock phase of the delay determination signal output from the signal processing device; use a phase difference between the first output clock phase and the first entry clock phase as a first sending compensation time for the delay determination signal, and determine a first sending time according to the port clock of the optical monitoring port of the interface board and the first sending compensation time.

[0112] In one implementation, the signal receiving module 502 includes:

[0113] A signal receiving unit is used to receive the delay feedback signal sent by the signal transceiver port of the slave node through the optical monitoring port of the interface board.

[0114] The receiving time unit is used to determine the second receiving time of the delay feedback signal at the optical monitoring port of the interface board.

[0115] In one implementation, the delay determination module 503 includes:

[0116] The time acquisition unit is used to acquire the first sending time of the delay determination signal and the second receiving time of the delay feedback signal in the master node.

[0117] A signal parsing unit is used to parse the delay feedback signal to obtain a first receiving time of the delay determination signal and a second sending time of the delay feedback signal.

[0118] A master-slave time difference unit is used to determine a master-slave time difference according to the first sending time, the first receiving time, the second sending time and the second receiving time.

[0119] In one implementation, the clock synchronization module 504 includes:

[0120] A signal encapsulation unit is used to encapsulate the master-slave time difference into a transmission signal in a preset format.

[0121] A signal sending unit is used to send the transmission signal to the slave node so that the slave node synchronizes the clock time according to the master-slave time difference.

[0122] Fig. 9 This is a schematic diagram of the structure of a clock time synchronization device provided by an embodiment of the present application. The embodiment of the present application can be applied to the situation of network element clock time synchronization, and can execute the clock time synchronization method provided by any embodiment of the present application, and has the corresponding functional modules and beneficial effects of the execution method. The device can be implemented by software and / or hardware, and can be integrated in the slave node of the network element, see Fig. 9 The device of the embodiment of the present application specifically includes: a signal receiving module 601, a signal feedback module 602 and a clock synchronization module 603.

[0123] The signal receiving module 601 is used to receive a delay determination signal from a signal transceiver port in the master node.

[0124] The signal feedback module 602 is used to send a delay feedback signal to the master node.

[0125] The clock synchronization module 603 is used to receive the master-slave time difference determined by the master node according to the delay determination signal and the delay feedback signal, and perform clock time synchronization with the master node according to the master-slave time difference.

[0126] According to the technical solution of the embodiment of the present application, the signal receiving module receives the delay determination signal from the signal transceiver port of the master node, the signal feedback module sends the delay feedback signal to the master node, the clock synchronization module receives the master-slave time difference determined by the master node according to the delay determination signal and the delay feedback signal, and performs clock synchronization with the master node according to the master-slave time difference, thereby achieving high-precision synchronization of the clock time of the master node and the slave node, reducing the error caused by internal transmission time consumption, and enhancing the stability of the business.

[0127] In one embodiment, the device provided in the embodiment of the present application also includes: a port determination module, which is specifically used to: obtain the single board number and port number of the master node; and use the optical monitoring port corresponding to the single board number and the port number in the master node as a signal transceiver port.

[0128] In one implementation, the signal receiving module 601 includes:

[0129] A delay signal unit is used to receive the delay determination signal sent by the signal transceiver port.

[0130] The delay time unit is used to determine a first receiving time of the delay determination signal received by the optical monitoring port of the interface board of the slave node.

[0131] In one implementation, the delay time unit is specifically used for:

[0132] Obtain a second entry clock phase of the delay determination signal entering a signal processing device in an optical monitoring port of the interface board; obtain a second output clock phase of the delay determination signal output from the signal processing device; use a phase difference between the second output clock phase and the second entry clock phase as a first reception compensation time of the delay determination signal, and determine a first reception time according to the port clock of the optical monitoring port of the interface board and the first reception compensation time.

[0133] In one implementation, the signal feedback module 602 includes:

[0134] The feedback signal unit is used to send the delay feedback signal from the optical monitoring port of the interface board to the signal transceiver port.

[0135] The feedback time unit is used to determine the second sending time of the delay feedback signal at the optical monitoring port of the interface board.

[0136] In one implementation, the clock synchronization module 603 includes:

[0137] A signal receiving unit is used to receive a transmission signal in a preset format sent by the master node.

[0138] The signal extraction unit is used to extract the master-slave time difference in the transmission signal.

[0139] The clock synchronization unit is used to synchronize the local clock time of the slave node according to the master-slave time difference.

[0140] Fig.10 is a schematic diagram of the structure of a device provided in an embodiment of the present application, such as Fig.10 As shown, the device includes a processor 50, a memory 51, an input device 52 and an output device 53; the number of processors 50 in the device can be one or more. Fig.10 A processor 50 is taken as an example; the device processor 50, the memory 51, the input device 52 and the output device 53 can be connected by a bus or other means. Fig.10 The example of connecting through bus is taken in the following.

[0141] The memory 51, as a computer-readable storage medium, can be used to store software programs, computer executable programs and modules, such as the modules corresponding to the clock time synchronization device in the embodiment of the present application (information sending module 501, signal receiving module 502, delay determination module 503 and clock synchronization module 504, or signal receiving module 601, signal feedback module 602 and clock synchronization module 603). The processor 50 executes various functional applications and data processing of the device by running the software programs, instructions and modules stored in the memory 51, that is, realizing the above-mentioned clock time synchronization method.

[0142] The memory 51 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system and at least one application required for a function; the data storage area may store data created according to the use of the terminal, etc. In addition, the memory 51 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some instances, the memory 51 may further include a memory remotely arranged relative to the processor 50, and these remote memories may be connected to the device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0143] The input device 52 may be used to receive input digital or character information and generate key signal input related to user settings and function control of the device. The output device 53 may include a display device such as a display screen.

[0144] The embodiment of the present application further provides a storage medium containing computer executable instructions, wherein the computer executable instructions are used to execute a clock time synchronization method when executed by a computer processor, the method comprising:

[0145] Sending a delay determination signal to a signal transceiver port in the slave node;

[0146] Acquire a delay feedback signal from the slave node;

[0147] Determine a master-slave time difference according to the delay feedback signal and the delay determination signal;

[0148] The master-slave time difference is sent to the slave node, and clock time synchronization is performed with the slave node according to the master-slave time difference.

[0149] or,

[0150] receiving a delay determination signal from a signal transceiver port in the master node;

[0151] Sending a delay feedback signal to the master node;

[0152] The master-slave time difference determined by the master node according to the delay determination signal and the delay feedback signal is received, and clock time synchronization is performed with the master node according to the master-slave time difference.

[0153] Of course, the storage medium containing computer executable instructions provided in the embodiment of the present application, whose computer executable instructions are not limited to the method operations described above, can also execute related operations in the clock time synchronization method provided in any embodiment of the present invention.

[0154] Through the above description of the implementation method, the technicians in the relevant field can clearly understand that the present invention can be implemented by means of software and necessary general hardware, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as a computer floppy disk, read-only memory (ROM), random access memory (RAM), flash memory (FLASH), hard disk or optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0155] It is worth noting that in the embodiment of the above-mentioned clock time synchronization device, the various units and modules included are only divided according to functional logic, but are not limited to the above-mentioned division, as long as the corresponding functions can be achieved; in addition, the specific names of the functional units are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application.

[0156] The above description is merely an exemplary embodiment of the present application and is not intended to limit the protection scope of the present application.

[0157] It will be appreciated by those skilled in the art that the term user terminal covers any suitable type of wireless user equipment, such as a mobile phone, a portable data processing device, a portable web browser or a vehicle-mounted mobile station.

[0158] In general, various embodiments of the present application can be implemented in hardware or dedicated circuits, software, logic or any combination thereof. For example, some aspects can be implemented in hardware, while other aspects can be implemented in firmware or software that can be executed by a controller, microprocessor or other computing device, although the present application is not limited thereto.

[0159] Embodiments of the present application may be implemented by executing computer program instructions by a data processor of a mobile device, for example in a processor entity, or by hardware, or by a combination of software and hardware. The computer program instructions may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages.

[0160] The block diagram of any logic flow in the accompanying drawings of the present application can represent program steps, or can represent interconnected logic circuits, modules and functions, or can represent a combination of program steps and logic circuits, modules and functions. The computer program can be stored on a memory. The memory can have any type suitable for the local technical environment and can be implemented using any suitable data storage technology, such as but not limited to read-only memory (ROM), random access memory (RAM), optical memory device and system (digital versatile disc DVD or CD disc), etc. Computer-readable media may include non-transient storage media. The data processor can be any type suitable for the local technical environment, such as but not limited to a general-purpose computer, a special-purpose computer, a microprocessor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a programmable logic device (FGPA) and a processor based on a multi-core processor architecture.

[0161] By way of exemplary and non-limiting examples, a detailed description of exemplary embodiments of the present application has been provided above. However, various modifications and adjustments to the above embodiments will be apparent to those skilled in the art when considered in conjunction with the accompanying drawings and claims, but will not depart from the scope of the present invention. Therefore, the proper scope of the present invention will be determined according to the claims.

Claims

1. A clock time synchronization method, characterized in that: Applied to the master node, including: Sending a delay determination signal to a signal transceiver port in the slave node; Acquire a delay feedback signal from the slave node; Determine a master-slave time difference according to the delay feedback signal and the delay determination signal; Encapsulating the master-slave time difference into a transmission signal in a preset format, wherein the transmission signal in the preset format is a TOD signal with a frequency greater than or equal to 1 kHz; The transmission signal is sent to the slave node, so that the slave node synchronizes clock time according to the master-slave time difference.

2. The method according to claim 1, characterized in that Also includes: The signal receiving and transmitting port is determined according to the acquired board number and port number of the slave node.

3. The method according to claim 1, characterized in that The sending of the delay determination signal to the signal transceiver port in the slave node includes: Sending the delay determination signal from the interface board optical monitoring port to the signal transceiver port; A first sending time of the delay determination signal at the optical monitoring port of the interface board is determined.

4. The method according to claim 3, characterized in that The step of determining a first sending time of the delay determination signal at the optical monitoring port of the interface board comprises: Acquire a first incoming clock phase of the delay determination signal entering a signal processing device in an optical monitoring port of the interface board; Acquire a first output clock phase of the delay determination signal output from the signal processing device; The phase difference between the first output clock phase and the first input clock phase is used as the first sending compensation time of the delay determination signal, and the first sending time is determined according to the port clock of the optical monitoring port of the interface board and the first sending compensation time.

5. The method according to claim 1, characterized in that The obtaining of a delay feedback signal from the slave node comprises: Receiving the delay feedback signal sent by the signal transceiver port of the slave node through the optical monitoring port of the interface board; A second receiving time of the delay feedback signal at the optical monitoring port of the interface board is determined.

6. The method according to claim 1, characterized in that The determining the master-slave time difference according to the delay feedback signal and the delay determination signal comprises: Acquire a first sending time of the delay determination signal and a second receiving time of the delay feedback signal in the master node; Parse the delay feedback signal to obtain a first receiving time of the delay determination signal and a second sending time of the delay feedback signal; A master-slave time difference is determined according to the first sending time, the first receiving time, the second sending time, and the second receiving time.

7. A clock time synchronization method, characterized in that: Applied to slave nodes, including: receiving a delay determination signal from a signal transceiver port in the master node; Sending a delay feedback signal to the master node; Receiving a transmission signal in a preset format sent by the master node, where the transmission signal in the preset format is a TOD signal with a frequency greater than or equal to 1 kHz; Extracting a master-slave time difference in the transmission signal; The local clock time of the slave node is synchronized according to the master-slave time difference.

8. The method according to claim 7, characterized in that Before the signal transceiver port in the slave master node receives the delay determination signal, the method further includes: Obtaining the board number and port number of the master node; The optical monitoring port corresponding to the board number and the port number in the master node is used as a signal transceiver port.

9. The method according to claim 7, characterized in that: The receiving the delay determination signal from the signal transceiver port in the master node includes: receiving the delay determination signal sent by the signal transceiver port; A first receiving time of the delay determination signal received by the optical monitoring port of the interface board of the slave node is determined.

10. The method according to claim 9, characterized in that The determining of a first receiving time at which the delay determination signal is received by the optical monitoring port of the interface board of the slave node comprises: Acquire a second incoming clock phase of the delay determination signal entering a signal processing device in an optical monitoring port of the interface board; Acquire a second output clock phase of the delay determination signal output from the signal processing device; The phase difference between the second output clock phase and the second input clock phase is used as the first receiving compensation time of the delay determination signal, and the first receiving time is determined according to the port clock of the optical monitoring port of the interface board and the first receiving compensation time.

11. The method according to claim 7, characterized in that The sending of the delay feedback signal to the master node comprises: Sending the delay feedback signal from the interface board optical monitoring port to the signal transceiver port; Determine a second sending time of the delay feedback signal at the optical monitoring port of the interface board.

12. A clock time synchronization device, characterized in that: Applied to the master node, including: An information sending module, used for sending a delay determination signal to a signal transceiver port in a slave node; A signal receiving module, used for obtaining a delay feedback signal from the slave node; A delay determination module, used to determine the master-slave time difference according to the delay feedback signal and the delay determination signal; A clock synchronization module is used to encapsulate the master-slave time difference into a transmission signal of a preset format, wherein the transmission signal of the preset format is a TOD signal with a frequency greater than or equal to 1kHz; and send the transmission signal to the slave node so that the slave node synchronizes the clock time according to the master-slave time difference.

13. A clock time synchronization device, characterized in that: Applied to slave nodes, including: A signal receiving module, used for receiving a delay determination signal from a signal transceiver port in the master node; A signal feedback module, used to send a delay feedback signal to the master node; A clock synchronization module is used to receive a transmission signal of a preset format sent by the master node, wherein the transmission signal of the preset format is a TOD signal with a frequency greater than or equal to 1kHz; extract the master-slave time difference in the transmission signal; and synchronize the local clock time of the slave node according to the master-slave time difference.

14. A clock time synchronization device, characterized in that: include: one or more processors; A memory for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the clock time synchronization method as described in any one of claims 1-11.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the clock time synchronization method as described in any one of claims 1 to 11 is implemented.

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