Phase shorting switch

Abstract

An analog-to-digital converter (ADC) may include the ability to sense and / or compensate for undesirable effects when receiving input from a microphone. For example, a sensing node may be provided between differential inputs and separated from the differential inputs by two or more switches. The sensing node may allow measurement of an average voltage of the differential inputs. The average voltage of the activated switches may be obtained to sample a capacitor coupled to the differential inputs. The average voltage may be used as common mode (CM) data. A controller may receive the CM data as well as differential mode (DM) data and use the CM and DM data to determine undesirable effects, such as DC or AC mismatch at the microphone interface. The controller may then generate a signal for applying compensation to the differential inputs to reduce or eliminate the undesirable effects.

Description

[0001] This application is a divisional application of the Chinese invention patent application with application number CN201680045326.3, application date August 12, 2016, and invention name “Phase Short Circuit Switch”.

[0002] Cross-references to related patent applications

[0003] This application claims the benefit of U.S. patent application No. 15 / 236,163, filed by Zanbaghi ​​et al. on August 12, 2016, entitled “Phase Shorting Switch,” which is a partial continuation of U.S. patent application No. 14 / 826,996, filed by Zanbaghi ​​et al. on August 14, 2015, entitled “Dual Processing Paths for Differential Mode and Common Mode Signals for an Adaptable Analog-To-Digital Converter (ADC) Topology,” each of which is incorporated herein by reference. Technical Field

[0004] The present disclosure relates to analog-to-digital converters (ADCs). More specifically, portions of the present disclosure relate to adapting the ADC to operate according to different input device configurations. Background Art

[0005] A microphone generates an electrical signal representing noise and sound in the environment around the microphone. A microphone is an important device for many electronic devices because sound, particularly speech, is one of the most important ways of interaction between people and electronic devices and between people and another person through electronic devices. A microphone usually generates an analog signal, but the processor within an electronic device is usually a digital component that operates on a digital signal. Therefore, the analog signal of the microphone must be converted to a digital signal for further processing within the electronic device. For example, an analog microphone output can be converted to a digital signal to allow an individual's voice to be transmitted from one cellular phone to another. In another example, an analog microphone output can be converted to a digital signal to allow a cellular phone to detect a voice command from a user. A component coupled to a microphone to convert an analog signal into a digital signal is an analog-to-digital converter (ADC).

[0006] Therefore, ADC is an important component in electronic devices. One complexity of using ADC is that the coupling configuration between the microphone and ADC changes the way the ADC processes the analog output of the microphone to generate a digital representation of the microphone output. That is, the ADC must be matched to the specific microphone coupled to the ADC. This limitation constrains the ability of users to use their electronic devices with any microphone. In addition, this limitation constrains the ability of manufacturers to substitute different microphones due to supply shortages. Some different coupling configurations are shown in Figures 1A-1D.

[0007] The microphone is either fully differential (FD) or pseudo differential (PD) and is either AC coupled or DC coupled to an analog-to-digital converter (ADC). Thus, there are at least four different microphone topology configurations that require different operations and interfaces to the ADC. FIG1A shows an AC coupled fully differential configuration of a microphone and an ADC. Microphone 102 may provide outputs 104 and 106. Outputs 104 and 106 are also inputs to ADC 108, which generates a D-sub containing a digital representation of the sound captured by microphone 102. 输出 (D out ) digital signal. In an AC coupled configuration (such as in FIG. 1A ), capacitors 112 and 114 are coupled between microphone 102 and ADC 108. Capacitors 112 and 114, together with the input impedance of ADC 108, form a high pass filter to prevent DC signals from microphone 102 from reaching ADC 108. Capacitors 112 and 114 may be integrated into a chip with ADC 108, or separate from a chip containing ADC 108. In either case, capacitors 112 and 114 consume space in the electronic device, which increases the size and thickness of the electronic device. Similar to FIG. 1A , FIG. 1B shows an AC coupled pseudo differential configuration of a microphone and ADC. The pseudo differential configuration 120 of FIG. 1B is similar to the fully differential configuration 110 of FIG. 1A , but wherein one terminal of microphone 102 is grounded to node 116.

[0008] As an alternative to the AC coupled topology of FIGS. 1A and 1B , a DC coupled topology may be implemented to interface the ADC to the microphone. The DC coupled microphone topology does not require capacitors 112 and 114 to block the DC value of the microphone output. Removing the capacitors reduces cost and size, but requires additional processing to make the ADC compatible with fully differential (FD) and pseudo differential (PD) microphones. FIGS. 1C and 1D illustrate a DC coupled fully differential (FD) configuration 130 and a DC coupled pseudo differential (PD) configuration 140, respectively. An example of additional processing is that the fully differential (FD) microphone 102 may provide V in and V ip, but these values ​​may not match each other and may not match the expected DC value for proper operation of the ADC. Another example of a configuration that requires additional processing is one where V in Configuration of a pseudo differential (PD) microphone with the signal connected to ground 116. In both examples, the ADC 108 must apply processing specific to the microphone configuration of FIG. 1C or FIG. 1D.

[0009] As described above, each of the four configurations of microphone topologies shown in FIG1A , FIG1B , FIG1C , and FIG1D requires different operation and interface to the ADC. For example, an AC-coupled microphone requires a capacitor at the input of the ADC to block DC signals. As another example, an AC-coupled microphone requires a common-mode voltage generator coupled to the ADC to set the input V in and V ip As yet another example, a DC-coupled fully differential microphone needs to be processed by an ADC to match the microphone input signal to a desired DC value. Due to these different requirements, ADCs are traditionally designed to match specific microphone configurations and thus generally cannot be used for other microphone configurations.

[0010] In addition, when the microphone is connected to the ADC interface through differential input coupling, undesirable effects may occur. For example, the common mode (CM) voltage values ​​of the fully differential input may not match, so that the common mode at the input node 104 is different from the common mode at the input node 106. Any mismatch between the input CM values ​​can be converted into a differential signal that can limit and saturate the components of the ADC. As another example, the AC signal amplitude mismatch between the differential inputs can produce similar limiting and saturation in the ADC. Figures 1E-1G show examples of these undesirable effects. The graphs of Figures 1E-1G show the differential input signal and the modulator output when the input voltages are matched in Figure 1E, with a mismatched CM voltage in Figure 1F, and with a mismatched DM voltage in Figure 1G. Both the mismatched CM and mismatched DM examples of Figures 1F and 1G may cause quantizer saturation or limiting within the ADC, respectively, and thus cause poor ADC performance. In the mismatched CM of Figure 1F, the modulator output experiences a voltage difference approximately equal to half of the input CM mismatch value (ΔV CM / 2). In the AC amplitude mismatch of FIG. 1G , there is no offset shift on the output code, but the mismatch causes gain scaling that may lead to symmetrical clipping in the quantizer.

[0011] Although the undesirable effects described above occur during fully differential (FD) operation, they may also occur during pseudo differential (PD) operation, where one input is coupled to ground and the other input produces a signal V ip =Vcmi +V dm In pseudo-differential (PD) operation, unbalanced DC shifts between the differential outputs of components in the ADC may cause swing-driven distortion (such as distortion caused by even-order harmonics). This undesirable effect also leads to poor ADC performance.

[0012] The disadvantages mentioned herein are merely representative and are included merely to emphasize that there is a need for improved electrical components, particularly for ADCs employed in consumer-grade devices such as mobile phones. The embodiments described herein address certain disadvantages, but not necessarily every disadvantage described herein or known in the art. Summary of the invention

[0013] According to the present invention, an analog-to-digital converter circuit is provided, comprising: a differential input, the differential input comprising a first input node and a second input node; at least two sampling capacitors, the at least two sampling capacitors comprising a first capacitor coupled to the first input node and a second capacitor coupled to the second input node; at least two switch sets, the at least two switch sets comprising a first set of two short-circuit switches respectively coupled to first sides of the at least two sampling capacitors and a second set of two short-circuit switches respectively coupled to second sides of the at least two sampling capacitors, wherein the first set of the two short-circuit switches couples the differential input to a sensing node, and the second set of the two short-circuit switches couples the differential input to a common-mode voltage node, the common-mode voltage node being a common-mode voltage, wherein the sensing node is a common-mode voltage. A node is measured and used to determine a mismatch between an external common mode and an internal common mode; a first digital-to-analog converter configured to generate a common mode value based on the internal common mode value and the external common mode value; a second digital-to-analog converter configured to process a signal from the differential input to generate a quantized output and differential mode information; a controller configured to use the quantized output to generate a digital output of the analog-to-digital converter and to use the digital output to generate a control signal for controlling a feedback path; and a feedback path comprising a main digital-to-analog converter and an auxiliary digital-to-analog converter, wherein the main digital-to-analog converter receives the quantized output and feeds the quantized output value back to the analog-to-digital converter, and the auxiliary digital-to-analog converter applies a signal to the sensing node to compensate for the common mode mismatch.

[0014] In some embodiments, an analog-to-digital converter (ADC) can be configured to automatically determine the microphone configuration and adjust the operation to match the determined microphone configuration. Therefore, regardless of the configuration of the microphone at the ADC input, a single ADC device can be used. Before selecting a microphone, the ADC configuration can allow a user to be unfamiliar with the ADC design of an electronic device. The ADC configuration can also allow manufacturers to manufacture electronic devices with one ADC, but still be able to change the microphone configuration during manufacturing. For example, if there is a shortage of AC-coupled fully differential microphones, the manufacturer can switch to some production batches of AC-coupled pseudo-differential microphones without replacing the ADC in the electronic device. This consideration is important because the ADC can be integrated with other components in the electronic device, which means that changing the microphone configuration during production may lead to a significant redesign of the electronic device.

[0015] A method for processing microphone input in an ADC to determine the microphone configuration is to process the microphone input signal in two processing paths, wherein one processing path processes the difference between the differential input signals and the other processing path processes the average value of the differential input signals. The outputs of these processing paths can be combined to generate a digital signal representing an analog signal from a microphone. The digital signal contains a digital version of the audio in the environment around the microphone, but can also be used to detect the microphone topology and configure various aspects of the processing path to match the detected microphone topology. A device for an ADC can implement these two processing paths as two delta-sigma modulator loops. Feedback from the output digital signal can be converted to an analog signal in a digital-to-analog converter (DAC). The operation of these DACs can be adjusted by a controller based on the microphone topology.

[0016] The improved operation of analog-to-digital converter (ADC) can be beneficial, for example, in electronic devices including entertainment devices (such as audio or video players, smart phones, tablet computers and personal computers). ADC can be coupled to any of the multiple microphones in these electronic devices. ADC can detect and adapt to the microphone topology used in the electronic device. Although this description relates to the ADC used with a microphone, the embodiment of the ADC described herein can be coupled to an analog device other than a microphone, and the ADC can process the information in a similar manner. That is, the analog-to-digital converter (ADC) described herein can be coupled to any analog device that provides an analog signal, and the analog signal needs to be processed in a digital electronic device. In addition, the ADC described herein can be used in any electronic device that processes an analog signal. For example, although the operation of a consumer device such as a cellular phone can be described, ADC can be used in other components (such as audio equipment).

[0017] In addition to the ability to detect the microphone interface configuration described above or in the absence of this ability, the ADC may also include the ability to sense and / or compensate for undesirable effects. For example, a sensing node may be provided between differential inputs, wherein the sensing node is separated from the differential input by two or more switches. The sensing node may allow measurement of the average voltage of the differential input. The switch may be activated to neutralize the charge stored on the sampling capacitor coupled to the differential input to obtain an average voltage. The average voltage may be used as common mode (CM) data for operation of the ADC. The controller may receive CM data and differential mode (DM) data, and use CM and DM data to determine undesirable effects, such as DC or AC mismatch at the interface between the microphone interface or microphone signal and the analog-to-digital converter (ADC). The controller may then generate a signal for applying compensation to the differential input (e.g., by an auxiliary digital-to-analog converter (DAC)) to reduce or eliminate undesirable effects.

[0018] According to one embodiment, an analog-to-digital converter (ADC) for converting an input analog signal into an output digital signal may include: a first input node for receiving a first input representing a differential signal of the input analog signal; a second input node for receiving a second input representing the differential signal of the input analog signal; a common mode input node for receiving a reference common mode signal; a first processing path coupled to the first input node and to the second input node, wherein the first processing path is configured to output a first digital signal indicating the received differential signal at a first processing output node; a second processing path coupled to the first input node, to the second input node, and to the common mode input node, wherein the second processing path is configured to output a second digital signal indicating a comparison result between an average value of the received differential signal and the reference common mode signal at a second processing output node; a combiner module coupled to the first processing output node of the first processing path and the second processing output node of the second processing path, wherein the combiner module is configured to generate the output digital signal based at least in part on the first digital signal and the second digital signal.

[0019] In certain embodiments, the analog-to-digital converter (ADC) may further include a controller, wherein the controller is configured to receive the output digital signal, determine a coupling configuration of an input device coupled to the first input node and the second input node based at least in part on the received output digital signal, and adjust operation of the analog-to-digital converter (ADC) based at least in part on the determined coupling configuration; a first digital output data node coupled to the combiner module; and may further include a second digital output data node coupled to the combiner module, wherein the output at the first digital output data node and the second digital output data node is a representation of the output digital signal; and may further include a first digital-to-analog converter (DAC) coupled to the first digital output data node and to at least a first input of the first processing path; and / or may further include a second digital-to-analog converter (DAC) coupled to the second digital output data node and to at least a second input of the first processing path, wherein the controller is coupled to the first DAC and the second DAC and is further configured to adjust operation of the analog-to-digital converter (ADC) by performing steps including operating the first DAC and the second DAC based at least in part on the received digital output data.

[0020] In certain embodiments, the controller may determine that the coupling configuration is one of AC-coupled full differential, AC-coupled pseudo differential, DC-coupled full differential, and DC-coupled pseudo differential; the combiner module may be configured to output the output digital signal at the first digital output data node and the second digital output data node; the combiner module may output a first digital signal at the first digital output data node based at least in part on the sum of the output of the first processing path and the output of the second processing path; the combiner may output a second digital signal at the second digital output data node based at least in part on the difference between the output of the first processing path and the output of the second processing path; the first processing path may include a first Δ-Σ modulator loop; the second processing path may include a second Δ-Σ modulator; and / or the first input node and the second input node may be configured to be coupled to a microphone having a differential output.

[0021] According to another embodiment, a method may include: receiving a first input of an analog differential signal by an analog-to-digital converter (ADC); receiving a second input of the analog differential signal by the analog-to-digital converter (ADC); processing a difference between the first input and the second input by the analog-to-digital converter (ADC) in a first processing loop; processing an average of the first input and the second input by the analog-to-digital converter (ADC) in a second processing loop; and / or combining the processed difference of the first processing loop with the processed average of the second processing loop by the analog-to-digital converter (ADC) to generate a digital signal indicating the analog differential signal.

[0022] In some embodiments, the method may further include determining, by a controller, a coupling configuration of an input device that generates the first input and the second input to an analog-to-digital converter (ADC); may further include adjusting, by the controller, the operation of the analog-to-digital converter (ADC) based at least in part on the determined coupling configuration; may further include converting a first digital output of a combined digital signal into a first analog feedback signal; may further include providing the first analog feedback signal to the first processing loop; may further include converting a second digital output of the combined digital signal into a second analog feedback signal; and / or may further include providing the second analog feedback signal to an input of a first processing loop, the input of the first processing loop being different from an input of the first processing loop coupled to the first analog feedback signal.

[0023] In some embodiments, the step of determining the coupling configuration may include at least one of the following steps: determining that the coupling configuration of the input device is AC-coupled fully differential, determining that the coupling configuration of the input device is AC-coupled pseudo-differential, determining that the coupling configuration of the input device is DC-coupled fully differential, and determining that the coupling configuration of the input device is DC-coupled pseudo-differential; the step of combining to generate a digital signal may include outputting a first digital signal based at least in part on the sum of the output of the first processing path and the output of the second processing path, and / or outputting a second digital signal based at least in part on the difference between the output of the first processing path and the output of the second processing path; the step of processing in a first processing loop may include processing in a first delta-sigma modulator loop; the step of processing in a second processing loop may include processing in a second delta-sigma modulator loop; and / or the steps of receiving the first input and receiving the second input may include receiving input from a microphone having a differential output.

[0024] According to another embodiment, an apparatus may include: a first input node for receiving a first input of an analog differential signal; a second input node for receiving a second input of the analog differential signal; a digital output node; an analog-to-digital converter (ADC) configured to convert the analog differential signal (which may be a pseudo differential signal) into a digital signal at the digital output node; and / or a controller coupled to the analog-to-digital converter. The analog-to-digital converter (ADC) may include: a first processing loop configured to process a difference between the first input and the second input; a second processing loop configured to process an average of the first input and the second input; and / or a combiner module configured to receive an output of the first processing loop, receive an output of the second processing loop, and generate the digital signal based at least in part on the output of the first processing loop and the output of the second processing loop. The controller can be configured to determine a coupling configuration of an input device that generates the first input and the second input to an analog-to-digital converter (ADC), wherein the determined configuration is based at least in part on a digital signal; and / or configured to adjust the operation of the analog-to-digital converter (ADC) based at least in part on the determined coupling configuration.

[0025] In certain embodiments, the combiner may be configured to output a pseudo-differential digital signal comprising a first component and a second component, wherein the first component comprises digital data indicating the sum of an output of the first processing path and an output of the second processing path, and wherein the second component comprises digital data indicating a difference between an output of the first processing path and an output of the second processing path; the first processing path may comprise a first delta-sigma modulator loop; the second processing path may comprise a second delta-sigma modulator; the first input node and the second input node may be microphone input nodes; and / or the device may be at least one of an entertainment device, a smart phone, a tablet computer, and a personal computer.

[0026] According to another embodiment, a method for compensating for common-mode mismatch and differential-mode mismatch of an analog-to-digital converter (ADC) may include: receiving digital common-mode (CM) data and differential-mode (DM) data, and / or generating a control signal for output to a digital-to-analog converter (DAC) so that the digital-to-analog converter (DAC) provides compensation in the analog-to-digital converter (ADC) for at least one of common-mode mismatch and differential-mode mismatch.

[0027] In some embodiments, the step of receiving common mode (CM) data may include receiving a DC average voltage level and / or an AC voltage level between differential input nodes of an analog-to-digital converter (ADC), wherein the DC average voltage level is received from a common mode (CM) sense node coupled to the differential input node via a switch; the method may also include the step of activating the switch to obtain an average voltage value in a sampling capacitor coupled to the differential input node; the step of receiving differential mode (DM) data may include receiving a difference between the differential input nodes, wherein the difference is received from a quantizer of the analog-to-digital converter (ADC); and / or the step of generating the control signal includes determining a configuration of a microphone coupled to the differential input node of the analog-to-digital converter (ADC) and / or determining a common mode mismatch and a differential mode mismatch in the analog-to-digital converter (ADC), wherein the step of generating the control signal includes generating the control signal based at least in part on the determined configuration of the microphone and the determined common mode mismatch and differential mode mismatch.

[0028] According to another embodiment, an apparatus may include a controller configured to operate an analog-to-digital converter (ADC) by performing steps including the method described above for compensating for common-mode mismatch and differential-mode mismatch.

[0029] According to another embodiment, a method for sensing an average value of a differential input voltage at two input nodes in a common-mode switched capacitor system may include providing a differential input to the switched capacitor system, wherein at least two sampling capacitors are coupled to each of the two input nodes; and / or the method may include operating two or more switches to obtain an average voltage of the differential input at the sampling nodes. The method may also include: converting an analog value of the average voltage to a digital value for feedback to a controller of the switched capacitor system, and / or compensating for undesirable effects at the differential input based at least in part on the average voltage generated at the output node.

[0030] According to another embodiment, an apparatus may include: a differential input including a first input node and a second input node; at least two sampling capacitors, the at least two sampling capacitors including a first capacitor coupled to the first input node and a second capacitor coupled to the second input node; at least two switches, the at least two switches including a first switch coupled to the first capacitor and a second switch coupled to the second capacitor and coupled to the first switch; and / or a controller coupled to the at least two switches, wherein the controller is configured to perform the following steps including: operating the at least two switches to obtain an average voltage of the differential input at an output node between the first switch and the second switch. In some embodiments, the apparatus may also include an analog-to-digital converter (ADC) coupled to the output node and to the controller, wherein the ADC is configured to provide common mode (CM) data to the controller based on the average voltage, and / or the apparatus may include an analog-to-digital converter (ADC), wherein the controller is further configured to operate the ADC to compensate for mismatch at the differential input based at least in part on the average voltage generated at the output node.

[0031] Certain features and technical advantages of embodiments of the present invention have been outlined quite extensively above so that the following detailed description may be better understood. Additional features and advantages that form the subject matter of the claims of the present invention will be described below. It should be understood by those skilled in the art that the disclosed concepts and specific embodiments may be easily used as a basis for modifying or designing other structures for performing the same or similar purposes. It should also be recognized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present invention as set forth in the appended claims. The additional features will be better understood from the following description when considered in conjunction with the accompanying drawings. However, it is to be expressly understood that each of the accompanying drawings is for illustration and description purposes only and is not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] For a more complete understanding of the disclosed systems and methods, reference is now made to the following description taken in conjunction with the accompanying drawings.

[0033] 1A is a block diagram showing a microphone coupled to an analog-to-digital converter (ADC) in a fully differential AC-coupled configuration.

[0034] 1B is a block diagram showing a microphone coupled to an analog-to-digital converter (ADC) in a pseudo-differential AC-coupled configuration.

[0035] 1C is a block diagram showing a microphone coupled to an analog-to-digital converter (ADC) in a fully differential DC coupled configuration.

[0036] 1D is a block diagram showing a microphone coupled to an analog-to-digital converter (ADC) in a pseudo-differential DC coupled configuration.

[0037] IE is a graph illustrating a modulator digital output code in an analog-to-digital converter (ADC).

[0038] IF is a graph illustrating modulator digital output codes in an analog-to-digital converter (ADC) with a fully differential input having mismatched common mode (CM) values.

[0039] 1G is a graph illustrating modulator digital output codes in an analog-to-digital converter (ADC) with a fully differential input having mismatched differential mode (DM) values.

[0040] Figure 2 is a flow chart illustrating a method of detecting and adjusting the operation of an analog-to-digital converter (ADC) to match a microphone topology according to one embodiment of the present disclosure.

[0041] Figure 3 is a block diagram illustrating a portion of an analog-to-digital converter (ADC) having two processing paths for processing analog signals according to one embodiment of the present disclosure.

[0042] Figure 4 is a flow chart illustrating a method of converting an analog signal into a digital signal in an analog-to-digital converter (ADC) having two processing paths according to one embodiment of the present disclosure.

[0043] Figure 5 is a circuit schematic diagram illustrating a portion of an analog-to-digital converter having two processing paths according to one embodiment of the present disclosure.

[0044] Figure 6 is a circuit schematic of a digital-to-analog converter (DAC) showing a feedback path from an analog-to-digital converter (ADC) according to one embodiment of the present disclosure.

[0045] Figure 7 is a table showing exemplary output from a 5-bit analog-to-digital converter (ADC) configured in accordance with one embodiment of the present disclosure.

[0046] Figure 8 is a diagram showing an electronic device having an analog-to-digital converter (ADC) capable of operating microphones of different topologies according to one embodiment of the present disclosure.

[0047] Fig. 9is a circuit schematic diagram showing a front-end switch for an analog-to-digital converter (ADC) having a shorted phase switch configured to provide a sense node according to one embodiment of the present disclosure.

[0048] Fig.10 is a circuit schematic diagram showing interface detection and compensation for an analog-to-digital converter (ADC) according to one embodiment of the present disclosure.

[0049] Fig.11 is a flow chart illustrating an exemplary method for determining microphone configuration and applying mismatch compensation according to one embodiment of the present disclosure.

[0050] Fig.12 is a flow chart illustrating an exemplary method for compensating for undesired effects in an analog-to-digital converter (ADC) according to one embodiment of the present disclosure.

[0051] Fig.13 is a flow chart illustrating an exemplary method for sensing common mode (CM) data in an analog-to-digital converter (ADC) according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0052] Figure 2 2 is a flow chart illustrating a method of detecting and adjusting the operation of an analog-to-digital converter (ADC) to match a microphone topology according to one embodiment of the present disclosure. Method 200 begins at box 202 by monitoring the output of an analog-to-digital converter (ADC) that receives an analog input from a microphone. The monitored output may be, for example, a digital output or a pseudo-digital output from the ADC. Then, at box 204, a coupling configuration of the microphone may be determined based on the output of the ADC monitored at box 202. The determination may be made based on an instantaneous value at the ADC output, or the determination may be made by evaluating the ADC output over a period of time. Next, at box 206, the operation of the analog-to-digital converter (ADC) may be adjusted based on the determined coupling configuration of the microphone. Method 200 may be performed by a controller coupled to the analog-to-digital converter or a controller integrated with the analog-to-digital converter.

[0053] An analog signal from a microphone is processed in an ADC to determine Figure 2 The method of the microphone configuration described in the embodiment of the present invention is to process the microphone input signal in two processing paths. The first processing path can process the difference between the differential input signals, and the second processing path can process the average value of the differential input signals. Figure 3is a block diagram showing a portion of an analog-to-digital converter (ADC) having two processing paths for processing analog signals according to one embodiment of the present disclosure. The analog-to-digital converter (ADC) 300 may include a first input node 302 and a second input node 304. The input nodes 302 and 304 may be configured to couple to a microphone 310 to receive an analog signal generated by the microphone 310 indicating sound in the environment surrounding the microphone 310 as a differential input or a pseudo differential input. Figure 3 Only portions of ADC 300 (such as loop filter components) are shown, but other components may be present in the ADC. Figure 3 Additional components not shown.

[0054] ADC 300 may process inputs received at input nodes 302 and 304 to generate a digital output D at output node 308. 输出 Processing may occur through two processing paths 312 and 322. The differential processing path 322 may process the difference between the differential signals at the input nodes 302 and 304. The common mode processing path 312 may process the average of the differential inputs at the input nodes 302 and 304. In one embodiment, the common mode processing path 312 may generate a common mode voltage V between the average of the differential inputs and the ideal common mode voltage V received at the input node 306. CMI The outputs of processing paths 312 and 322 may be provided to combiner 332, which generates at least one digital output signal D at output node 308. 输出 .

[0055] refer to Figure 4 A method for Figure 3 The two processing paths of the ADC are shown to process analog differential signals. Figure 4 4 is a flow chart illustrating a method for converting an analog signal into a digital signal in an analog-to-digital converter (ADC) having two processing paths according to one embodiment of the present disclosure. The method 400 begins at block 402 by receiving a first input and a second input of an analog differential signal to be converted into a digital signal. Then, at block 404, a first processing loop (such as Figure 3 Next, at block 406, in a second processing path (such as in Figure 3 The processing of blocks 404 and 406 may occur simultaneously. In other embodiments, the processing of blocks 404 and 406 may occur in a serial manner for each sample taken from the first input and the second input. Then, at block 408, for example, Figure 3The output of the difference processing of block 404 and the average processing of block 406 are combined in combiner 332 to produce a digital signal. The digital signal produced by combining the outputs of the processing paths corresponds to a digital representation of the analog difference signal. When a microphone is coupled to the first input and the second input, the digital signal is a digital representation of the sound in the environment surrounding the microphone.

[0056] like Figure 5 As shown in FIG. , one embodiment for implementing an analog-to-digital converter (ADC) having two processing paths implements the two processing paths as Figure 5 The delta-sigma modulator shown in FIG. Figure 5 1 is a circuit diagram showing a portion of an analog-to-digital converter (ADC) with two processing paths according to an embodiment of the present disclosure. The analog-to-digital converter (ADC) 500 supports all microphone topologies, which support microphone topologies such as AC coupling, DC coupling, full differential and pseudo differential microphones. The first processing path 322 and the second processing path 312 include loop filters 522 and 512 and quantizers 524 and 514, respectively. The processing paths 312 and 322 are output to the combiner 332, which generates pseudo digital signals at output nodes 308A and 308B. The pseudo digital signals at nodes 308A and 308B are provided to the inputs of the processing paths 312 and 322, respectively, through the feedback path 540. The feedback path 540 includes digital-to-analog converters (DACs) 542 and 544. The outputs of the DACs 542 and 544 can be coupled to the first input and the second input of the differential processing path 322, respectively. In addition, the outputs of the DACs 542 and 544 can be averaged to be input to the common mode processing path 312. Thus, each of the processing paths 312 and 322 is a functional ADC loop coupled to the same front end and back end. However, each of the processing paths 312 and 322 processes different aspects of the input signals received at the input nodes 302 and 304.

[0057] Input nodes 302 and 304 couple the differential signal to two front-end summing nodes V xn 、V xp and enters differential mode (DM) loop filter 522. Input nodes 302 and 304 also couple the average of the differential signal to common mode (CM) loop filter 512. The common mode loop filter also receives the ideal CM voltage V from input node 306. CMI, which may indicate a desired common-mode voltage selected to match the desired input at the amplifiers (not shown) within loop filters 512 and 522. Thus, the differential error signal passes through DM loop filter 522, and the common-mode error signal passes through CM loop filter 512. Loop filters 512 and 522 may include, for example, integrators including operational amplifiers. Those operational amplifiers may be designed to provide a desired common-mode voltage V received at node 306. CMI The outputs of loop filters 512 and 522 are quantized in quantizers 514 and 524, respectively, to generate digital outputs D CM and D DM . D DM The digital output can contain a value based on the average value of the input and the ideal common-mode voltage V CMI A digital representation of the error signal for comparison; D DM The digital output may include a digital representation of an error signal based on the differential input at input nodes 302 and 304. After quantization, the CM and DM digital outputs D CM and D DM The pseudo digital data may be combined at combiner 332, such as by using a decoder to generate pseudo digital data carrying CM and DM information. The pseudo digital data may be provided as D p and D n Signal output, where D p Contains CM +D DM / 2) information, and D n Contains CM -D DM The combiner may include an amplifier 532 and summing blocks 534 and 536 to generate an output D from the outputs of paths 312 and 322. p and D n Signal.

[0058] Pseudo digital data (D n , D p ) may be coupled to DACs 544 and 542, respectively, in feedback path 540. In one embodiment, DACs 544 and 542 may be implemented as current steering DACs. Figure 6 5 is a circuit diagram of a digital-to-analog converter (DAC) showing a feedback path from an analog-to-digital converter (ADC) according to one embodiment of the present disclosure. In DACs 542 and 544, the pseudo digital output D p Controlling the DAC p 542 is the current DAC switch, and D n Controlling the DAC n 544 switch.

[0059] Figure 5 The operation of ADC 500 can refer to Figure 7 To explain, Figure 7 is a table showing exemplary outputs of ADC 500 when configured as a 5-bit ADC. For an AC-coupled fully differential microphone topology, V in and V ip The DC value can be set internally to V CMI And the CM error can be zero. Therefore, the DAC 542 output value I p Can be from -32*I DAC to +32*I DAC , and the DAC 544 outputs a value of I n Can be from +32*I DAC To -32*I DAC , got D n and D p For a DC-coupled fully differential topology, if the DC value of the input at nodes 302 and 304 is equal to V at node 306, CMI If the DC value of the input at nodes 304 and 304 is matched to V at node 306, there will not be any common-mode error signal and the output will be similar to the output of the AC-coupled FD case. For the DC-coupled fully differential topology, if the DC value of the input at nodes 304 and 304 is equal to V at node 306, CMI If the CM loop filter 512 is not matched (so that there is a CM error), the CM loop filter 512 can adjust l p and I n to cancel the CM error. The output will then again resemble the output for the AC coupled FD case. Therefore, if something like Figure 5 The controller 550 or the like detects D n and D p If the average value of the digital output code is zero, the controller can determine that the microphone topology is fully differential. The controller can also distinguish between AC-coupled and DC-coupled variations of the fully differential topology by receiving additional information. For example, the controller can receive a programmed signal from a memory or a fuse. In another example, the controller can determine that the microphone topology is fully differential. CMI The amount of current drawn by input node 306.

[0060] For AC-coupled pseudo-differential topologies, V ip and V in The DC value is matched to the V received at the input node 306. CMI Then, D p and I p The values ​​can be similar to those of the AC-coupled FD case, but the difference is that I n The value of will be zero (Dn =

[10000] , which is the intermediate code), because for V in There is no AC signal at node 304, and its DC value is determined by V cm The generator block (not shown) is set. Therefore, if Figure 5 The controller 550 or the like detects D n If the value is

[10000] , the controller can determine that the microphone topology is AC-coupled pseudo-differential.

[0061] For DC coupled pseudo differential topology, D p and I p The values ​​will be similar to those for the AC-coupled pseudo-differential topology (assuming V ip The DC value on V CMI matches), but I p Will reach a maximum value of +32*I DAC To set V xn The DC value of the node generates the output value D n =

[11111] . Therefore, if Figure 5 The controller 550 or the like detects D n If the value is

[11111] , the controller can determine that the microphone topology is a DC-coupled pseudo-differential topology.

[0062] The controller can monitor D p and D n The data pattern uses a digital detection algorithm to detect the microphone topology and distinguish various topologies based on this. In some embodiments, additional information can be provided to the controller to assist in the determination. After determining the microphone topology, the controller can adjust the operation of the ADC based on the determined topology. For example, when the topology is pseudo-differential AC coupled, the controller 550 can turn off the DAC 544. Alternatively, several units of the DAC 544 can remain turned on to determine the mismatch. As another example, when the topology is pseudo-differential DC coupled, the controller can turn off the NMOS side current of the DAC 544 to reduce power consumption. In some embodiments, the controller can wait to adjust the operation of the DAC until a stable state is reached within the ADC. A stable state can be reached after a signal first appears at the input of the ADC or after a period of time has passed since the ADC was started. Alternatively, a stable state can be reached when the output of the DAC reaches the expected signal. The controller 550 described herein can be integrated with the DAC or outside the DAC.

[0063] The DAC configurations described above as universal and / or adaptive DACs for various microphone topologies may be implemented in electronic devices having a microphone (or other analog input device that interacts with digital components). Figure 8804B, 804C, and / or 806 to process input signals from microphones 804A, 804B, 804C, and / or 806. ADC 810 of electronic device 802 may include two processing loops, such as reference 804A, 804B, 804C, and / or 806. Figure 3 , Figure 4 , Figure 5 and Figure 6 ADC 810 may also include a reference Figure 2 and Figure 7 The monitoring and adjustment capabilities described herein. The generic nature of the ADC 810 supporting different topologies benefits the end user because the end user does not need to know the microphone topology, and benefits the manufacturer because the manufacturer can change microphone suppliers during the manufacture of the electronic device without changing the ADC 810. In addition, when the microphone is an AC coupled topology, the interface between the ADC 810 and the microphone does not require a coupling capacitor (such as capacitors 112 and 114 of Figures 1A and 1B). Therefore, the use of the ADC disclosed herein can reduce the space occupied by the microphone and ADC interface in the electronic device. The following describes portions of the ADC or additional embodiments of the ADC that can be implemented in an electronic device (such as the mobile device 802).

[0064] Figure 5 Shown and referenced Figure 5 The description of FIG. 5 describes the use of feedback path 540 under the operation of controller 550 to apply a signal to V xp and V xn , which is coupled to differential input nodes 302 and 304. In some embodiments, the digital-to-analog converter (DAC) of feedback path 540 can be used as an auxiliary digital-to-analog converter (DAC) to provide compensation for common-mode and differential-mode mismatches. In some of these embodiments, the auxiliary DAC can be controlled based on measurements from a common-mode (CM) sense node. The CM sense node can be provided by two or more switches coupled between the differential inputs. Fig. 9 One such embodiment using short-circuiting phase switches is shown in . Fig. 9 1 is a circuit schematic diagram showing a front-end switch for an analog-to-digital converter (ADC) having a shorting phase switch configured to provide a sensing node according to one embodiment of the present disclosure. Circuit 900 includes two shorting switches 912 and 914, which can be operated, such as by a controller (not shown), to short-circuit two input sampling capacitors during a second clock phase of operation. A sensing node 916 between the two shorting switches 912 and 914 can provide a common mode (CM) sensing node.

[0065] Specifically, during certain operating times of the circuit 900, the voltage at the sense node 916 can provide data about the average voltage between the input nodes 902 and 904. The shorting switches 912 and 914, together with any parasitic capacitance (not shown) between the switches 912 and 914, form a switch-capacitor (SC) resistor. The SC resistor may have a large resistance value because the value is inversely proportional to a small parasitic capacitance value. Fig. 9 The embodiment of uses switches to form two large resistors for providing CM sense nodes. When switches 912 and 914 are turned on, intermediate node 916 settles to a voltage level close to the average of the input voltages at input nodes 902 and 904.

[0066] An input from sense node 916 may be provided to a controller to operate a DAC in the feedback path of the ADC. Fig.10 The CM sensing node and the similar reference Figure 3 or Figure 5 The described interface detection hardware implements one embodiment of a feedback ADC. Fig.10 is a circuit diagram showing interface detection and compensation for an analog-to-digital converter (ADC) according to one embodiment of the present disclosure. Fig.10 A specific ADC configuration is shown in FIG. 4 , but the sensing nodes and / or controllers described herein may be implemented in other ADC configurations including switched-capacitor ADC circuits and continuous-time ADC circuits.

[0067] Analog-to-digital converter (ADC) circuit 1000 includes a first set of shorting switches 1012 and 1014 coupled on first sides of sampling capacitors 1022 and 1024, respectively. Shorting switches 1012 and 1014 couple differential input nodes 1002 and 1004 to sensing node 1016. Circuit 1000 also includes a second set of shorting switches 1032 and 1034 coupled on second sides of sampling capacitors 1022 and 1024, respectively. Shorting switches 1032 and 1034 couple differential inputs to node 1036, and node 1036 may be a common mode V cm Voltage.

[0068] The sense node 1016 can be measured and used to determine the external common mode V cm,p With the internal common mode V cm,i The external common mode V can be monitored by controlling switches 1012 and 1014 to enter a conducting mode to allow sense node 1016 to balance to the average voltage between differential input nodes 1002 and 1004 external to ADC 1000. cm,p The digital-to-analog converter (DAC) 1042 can measure the external common-mode V cm,p ADC 1042 can be based on V cm,i Value and V cm,p value to generate the common mode value D cm The common mode value D cm Provided to controller 1044. V cm,i Value and V cm,p The mismatch between the values ​​produces a differential signal that may appear at the output of circuit 1000 , or produces noise in the output of circuit 1000 , such that the output of circuit 1000 may be improved by detecting the mismatch and compensating for the mismatch.

[0069] Compensation can be obtained through feedback path 1060. The controller 1044 can be used according to the D cm and D main The compensation is provided by auxiliary DAC 1062 based on the digital code selected by monitoring the output. The differential input signal may be processed by ADC component 1050 (such as by sampling capacitors 1022 and 1024, comparator 1052, other loop filter components 1054, and quantizer 1056) to generate a quantized output D main The quantized output D main Provided to controller 1044 and used by controller 1044 to generate a digital output D of circuit 1000 out Controller 1044 can also use the quantized output D main The feedback path 1060 may include an auxiliary DAC 1062. The feedback path 1060 may also include a main DAC 1064 that receives the quantized output D main And D main The value is fed back to the ADC 1000. The controller 1044 may generate a control signal for operating the auxiliary DAC 1062, which applies a signal to the internal CM sense node to compensate for the CM mismatch.

[0070] The controller 1044 may be configured to process the microphone interface configuration. The interface configuration may be determined in part based on the quantizer 1056 output. The quantizer 1056 digital output code represents a differential mode (DM) representation of the input. That is, after filtering the quantization noise, the quantized output D main With V ip -V in Information, where V ip is the input at node 1002, and V in is the input at node 1004. The interface configuration may also be determined in part based on the ADC 1042 output, which includes information from the sense node 1016. By digitizing the sense node 1016 voltage, the controller 1044 may have common mode (CM) information, e.g., the value of the differential input voltage (V ip +V in Using the DM and CM information, the controller 1044 can determine the interface configuration (eg, fully differential FD or pseudo differential PD), and the controller 1044 can also determine possible DM or CM mismatches of the differential input signals at the input nodes 1002 and 1004.

[0071] When the DM output is at an output code centered on the intermediate code and the CM data indicates that the AC signal item appears at the sensing node, the controller 1044 can determine that the microphone is in a pseudo differential (PD) configuration. If the pseudo differential (PD) configuration is not detected, the controller 1044 can determine that the microphone is operating under a full differential (FD) configuration. When the CM data includes an AC signal item and the DM data has no code shift, the controller 1044 can determine that there is an AC mismatch. When the CM data does not indicate an AC signal item and the DM data has a code shift, the controller 1044 can determine that there is a DC mismatch. When the CM data indicates an AC signal item and the DM data has a code shift, the controller 1044 can determine that there is an AC mismatch and a DC mismatch. In any of these cases, the AC signal item on the CM input may be proportional to the input AC mismatch amplitude, and the code shift on the DM input may be proportional to the DC mismatch.

[0072] exist Fig.11 A method for operation of controller 1044 is shown in FIG. Fig.11 1 is a flow chart illustrating an exemplary method for determining microphone configuration and applying mismatch compensation according to one embodiment of the present disclosure. The method 1100 begins at block 1102 by determining a microphone configuration based on common mode (CM) data and differential mode (DM) data. The CM data may be received as a signal indicating a voltage level at a CM sense node (such as from a Fig.10 The signal D of ADC 1042 in cm). The DM data may be received as a signal from a quantizer in a differential mode path, such as from Fig.10 The signal D of the quantizer 1056 in main . The method 1100 then proceeds to block 1104 to determine undesirable effects within the ADC based on the microphone input. For example, block 1104 may include determining the presence of an AC mismatch or a DC mismatch between differential input nodes and / or between internal and external common modes. Next, at block 1106, the method 1100 may include controlling components of the ADC, such as an auxiliary DAC, to compensate for the undesirable effects of block 1104. For example, the auxiliary DAC 1062 may be controlled to apply a signal to the differential input of the ADC to compensate for the mismatch.

[0073] The compensation of block 1106 may be applied, for example, to eliminate the mismatched portion of the input transfer charge. The total ADC input path charge of the differential input may be given by q i,p and q i，n Given, q i,p and q i，n As shown below:

[0074]

[0075] The charge of the DAC path at the differential input can be calculated by q dac,p and q dac,n Given, q dac,p and q dac,n As shown below:

[0076] q dac，p =C dac，main .V refn，main (D main )+C dac，aux .V refn，aux (D aux )

[0077] q dac，n =C dac，main .V refp，main (D main )+C dac，aux .V refp，aux (D aux )

[0078] The auxiliary DAC can be controlled to cancel the mismatched portion of the input transfer charge In one embodiment, the controller 1044 may generate a digital code value D for output to the auxiliary DAC 1062. aux , which causes the auxiliary DAC 1062 to apply enough charge to cancel the mismatched portion of the input transfer charge.

[0079] In some embodiments, the controller 1044 may take specific actions as part of the compensation step at block 1106. In the following example, V CM refers to the external common mode, and V cm,i and V cm,p They refer to the input V in and V ip For example, when D cm Only has a DC term (which can be compared with V cm,i -V cm proportional) and D main Without a DC shift, the controller 1044 may determine that the interface is fully differential (FD) with matched DC and AC values, and thus generate a DC aux The output may be neutral (such as set at mid-code). As another example, when D cm Only has a DC term (which can be compared with V cm,i -V cm +ΔV cm,i / 2) and D main has a DC shift (which can be related to ΔV cm,i When the interface is fully differential (FD) and the input DC value is mismatched, the controller 1044 may determine that the interface is fully differential (FD) and the input DC value is mismatched, and may therefore select the generated D aux Output to compensate with ΔV cm,i / 2 is proportional to the undesired charge. As another example, when D cm has a DC term (which can be compared with V cm,i -V cm proportional to ΔV dm,i proportional) and D main Without a DC shift, the controller 1044 may determine that the interface is fully differential (FD) with matched DC input values ​​but mismatched AC values, and may therefore select the generated DC aux The output is compensated with ΔV dm,i / 2 is proportional to the undesired charge. As another example, when D cm has a DC term (which can be compared with V cm,i -V cm +ΔV cm,i / 2) and the AC term (which can be related to ΔV dm,i proportional) and D main With a DC shift, the controller 1044 may determine that the interface is fully differential (FD) with mismatched AC and DC values, and may therefore select the generated DC aux Output to compensate with (ΔV cm,i +ΔV dm,i) / 2. As another example, when D cm has a DC term (which can be compared with V cm,i / 2-V cm proportional to V dm,i / 2), D main No DC shift, D cm has a high DC term, and D cm With high (eg, >=V dm,i / 2)AC term, the controller 1044 may determine that the interface is a pseudo differential (PD) and may therefore select the generated D aux Output is compensated with V cm,i / 2, thereby removing the DC shift on the output of the active components.

[0080] refer to Fig.12 An exemplary embodiment of determining undesirable effects and applying compensation is described in more detail. Fig.12 1 is a flow chart illustrating an exemplary method for compensating for undesirable effects in an analog-to-digital converter (ADC) according to one embodiment of the present disclosure. Method 1200 may begin at block 1202 by receiving common mode (CM) data and differential mode (DM) data. The received CM data and DM data may be, for example, an average value of a differential input node voltage and a difference of a differential input node voltage, respectively. Then, at block 1204, undesirable effects such as common mode (CM) and / or differential mode (DM) mismatch may be determined. CM mismatch and DM mismatch may be two unknowns calculated based in part on the CM data and DM data received from block 1202. Next, at block 1206, a control signal for an output to a digital-to-analog converter (DAC) may be generated, wherein the control signal is selected so that the DAC provides compensation for at least some of the undesirable effects determined at block 1204. For example, the DAC may be controlled to counteract a DC mismatch between differential inputs.

[0081] can be detected from the CM sensing node within the ADC (such as Fig.10 The CM sensing node 1016 of the embodiment receives the CM data received at block 1202. Fig.13 An exemplary method for obtaining CM data is described in more detail. Fig.13 1 is a flow chart illustrating an exemplary method for sensing common mode (CM) data in an analog-to-digital converter (ADC) according to one embodiment of the present disclosure. The method 1300 may begin at block 1302 by receiving a differential input through two input nodes of two sampling capacitors coupled to a switched capacitor circuit. For example, Fig.10The differential input is received at input nodes 1002 and 1004 of sampling capacitors 1022 and 1024. Then, at block 1304, two or more switches may be controlled to sample the two sampling capacitors such that an average voltage is generated at an output node between the two or more switches. For example, switches 1012 and 1014 may be controlled to switch to a conductive state to sample the average voltage of sampling capacitors 1022 and 1024.

[0082] Figure 2 , Figure 4 , Fig.11 , Fig.12 ,and Fig.13 The schematic flow chart of is generally described as a logical flow chart. In this way, the depicted order and the marked steps indicate various aspects of the disclosed method. It is conceivable that other steps and methods are equivalent to one or more steps or parts thereof of the method shown in terms of function, logic or effect. In addition, the format and symbols adopted will be provided to explain the logical steps of the method, and the format and symbols adopted are understood to not limit the scope of the method. Although various arrow types and line types can be used in the flow chart, they are understood to not limit the scope of the corresponding method. In fact, some arrows or other connectors can be used to indicate only the logical flow of the method. For example, an arrow can indicate a waiting or monitoring time period of unspecified duration between the enumerated steps of the depicted method. In addition, the order in which a particular method occurs may strictly comply with or not strictly comply with the order of the corresponding steps shown.

[0083] The operations performed by the controller as described above can be performed by any circuit configured to perform the described operations. Such a circuit can be an integrated circuit (IC) built on a semiconductor substrate and include a logic circuit (such as a transistor configured as a logic gate) and a memory circuit, such as a transistor configured as a dynamic random access memory (DRAM), an electrically programmable read-only memory (EPROM) and a capacitor or other storage device. The logic circuit can be configured by hard-wired connection or by programming with instructions contained in the firmware. In addition, the logic circuit can be configured as a general-purpose processor capable of executing instructions contained in the software. If implemented in firmware and / or software, the functions described above can be stored as one or more instructions or codes on a computer-readable medium or in a memory circuit. If implemented in firmware and / or software, the functions described above can be stored as one or more instructions or codes on a computer-readable medium or in a memory circuit. Examples include non-temporary computer-readable media encoded with a data structure and computer-readable media encoded with a computer program. Computer-readable media include physical computer storage media. The storage medium can be any available medium that can be accessed by a computer. By way of example and not limitation, such computer readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage device, magnetic disk storage device or other magnetic storage device, or any other medium that can be used to store desired program code in the form of instructions or data structures and can be accessed by a computer. Disks and optical disks include compact discs (CDs), laser discs, optical disks, digital versatile discs (DVDs), floppy disks, and Blu-ray discs. Typically, disks reproduce data magnetically, and optical disks reproduce data optically. The above combinations should also be included within the scope of computer readable media.

[0084] In addition to storage on a computer-readable medium, instructions and / or data may be provided as signals on a transmission medium included in a communication device. For example, the communication device may include a transceiver with signals indicating instructions and data. The instructions and data are configured to cause one or more processors to implement the functions outlined in the claims.

[0085] Although the present disclosure and some representative advantages have been described in detail, it should be understood that various changes, substitutions and modifications can be made herein without departing from the spirit and scope of the present disclosure as defined by the appended claims. In addition, the scope of the present application is not intended to be limited to the specific embodiments of the processes, machines, manufactures, material compositions, means, methods and steps described in the specification. For example, although analog-to-digital converters (ADCs) are described throughout the specific embodiments, aspects of the present invention can be applied to the design of other converters, such as digital-to-analog converters (DACs) and digital-to-digital converters, or other circuits and components based on delta-sigma modulation. As another example, although a microphone interface for an analog-to-digital converter (ADC) is described herein, the ADC disclosed herein can be applied to any analog input device. As will be readily understood by those skilled in the art from the present disclosure, processes, machines, manufactures, material compositions, means, methods or steps that currently exist or are later developed to perform functions substantially the same as the corresponding embodiments described herein or to achieve substantially the same results can be utilized. Therefore, the appended claims are intended to include such processes, machines, manufactures, material compositions, means, methods or steps within their scope.

Claims

1. An analog-to-digital converter circuit (1000), comprising: A differential input, the differential input comprising a first input node (1002) and a second input node (1004); at least two sampling capacitors (1022, 1024), the at least two sampling capacitors (1022, 1024) comprising a first capacitor (1022) coupled to the first input node (1002) and a second capacitor (1024) coupled to the second input node (1004); at least two switch sets, the at least two switch sets comprising a first set of two short-circuit switches (1012, 1014) respectively coupled to a first side of the at least two sampling capacitors (1022, 1024) and a second set of two short-circuit switches (1032, 1034) respectively coupled to a second side of the at least two sampling capacitors (1022, 1024), The first set of the two shorting switches (1012, 1014) couples the differential input to a sensing node (1016), and the second set of the two shorting switches (1032, 1034) couples the differential input to a common-mode voltage node (1036), wherein the common-mode voltage node (1036) is a common-mode voltage (V cm ), The sensing node (1016) is measured and used to determine the external common mode (V cm,p ) and the internal common mode (V cm,i ) between the two; The first digital-to-analog converter (1042) is configured to cm,i ) value and the external common mode (V cm,p ) value to generate the common mode value (D cm ); A second digital-to-analog converter (1050) is configured to process the signal from the differential input to generate a quantized output (D main ) and differential mode information; A controller (1044) is configured to use the quantized output (D main ) to generate a digital output (D out ) and using the digital output (D out ) to generate a control signal for controlling a feedback path (1060); and A feedback path (1060) includes a main digital-to-analog converter (1064) and an auxiliary digital-to-analog converter (1062), wherein the main digital-to-analog converter (1064) receives the quantized output (D main ) and the quantized output (D main ) value is fed back to the analog-to-digital converter circuit (1000), and the auxiliary digital-to-analog converter (1062) applies a signal to the sensing node (1016) to compensate for the common-mode mismatch.

2. The analog-to-digital converter circuit according to claim 1, wherein: The first set of two shorting switches (1012, 1014) is controlled to enter a conducting mode so that the sensing node (1016) is balanced to the average voltage between the first input node (1002) and the second input node (1004) to monitor the external common mode (V cm,p ).

3. The analog-to-digital converter circuit according to claim 1, wherein: The controller (1044) is also configured to process an interface configuration of an analog device providing an analog signal, receive the differential mode information output by the second digital-to-analog converter (1050), obtain common mode information by digitizing the voltage of the sensing node (1016), and use the differential mode information and the common mode information to determine the interface configuration and determine a possible differential mode or common mode mismatch of the differential input signal at the first input node (1002) and the second input node (1004).

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