Integrated circuit, integrated circuit layout structure and method for forming an integrated circuit

Abstract

Embodiments of the present invention relate to integrated circuits, integrated circuit layout structures, and methods for forming integrated circuits. Embodiments of the present invention relate to an integrated circuit, comprising: a substrate having a first region and a second region; a first isolation structure placed in the substrate and separating the first region from the second region; a first device placed in the first region; a second device placed in the second region; and a semiconductor dummy structure placed on the first isolation structure. The first isolation structure has a first top surface and a second top surface lower than the first top surface. The semiconductor dummy structure covers a portion of the first top surface, a portion of the second top surface, and a boundary between the first top surface and the second top surface.

Description

Technical Field

[0001] Embodiments of the present invention relate to an integrated circuit, an integrated circuit layout structure, and a method for forming an integrated circuit. Background Art

[0002] In semiconductor technology, as devices become smaller due to the continued reduction in device dimensions, it may be desirable to improve transistor performance. Furthermore, it may be desirable to fabricate integrated circuit ("IC") semiconductor devices that incorporate transistors for low, high, and sometimes intermediate voltage range applications in a single integrated circuit. For example, transistors for logic functions operating at relatively low voltages and transistors for high power applications operating at relatively high voltages may be designed and fabricated on the same IC.

[0003] Transistors operating in two different voltage ranges are located on different regions of the IC, and the use of shallow trench isolation (STI) is a typical method of allowing regions for various types of transistors to be integrated onto an IC by creating electrically isolated regions within a single substrate. Summary of the invention

[0004] An embodiment of the present invention relates to an integrated circuit, comprising: a substrate, comprising a first region and a second region; a first isolation structure, which is placed in the substrate and separates the first region from the second region, wherein the first isolation structure has a first top surface and a second top surface lower than the first top surface; a first device, which is placed in the first region; a second device, which is placed in the second region; and a semiconductor dummy structure, which is placed on the first isolation structure, wherein the semiconductor dummy structure covers a portion of the first top surface, a portion of the second top surface, and a boundary between the first top surface and the second top surface.

[0005] An embodiment of the present invention relates to an integrated circuit layout structure, which includes: a substrate, which includes a low voltage (LV) region and a high voltage (HV) region; an LV device placed in the LV region and an HV device placed in the HV region; an isolation structure, which is placed in the substrate and surrounds the LV region and the HV region and separates the LV region from the HV region; and a frame-shaped semiconductor dummy structure, which is placed on the isolation structure, wherein a portion of the frame-shaped semiconductor dummy structure is placed between the LV region and the HV region, a width of the frame-shaped semiconductor dummy structure is smaller than a width of a portion of the isolation structure between the LV region and the HV region, and the width of the frame-shaped semiconductor dummy structure is greater than a width of the LV device and a width of the HV device.

[0006] An embodiment of the present invention relates to a method for forming an integrated circuit, which includes receiving a substrate having a first region, a second region, and an isolation structure separating the first region from the second region; removing a portion of the substrate and a portion of the isolation structure so that the second region is recessed and the isolation structure obtains a first top surface, a second top surface lower than the first top surface, and a boundary between the first top surface and the second top surface; forming a first device in the first region, a second device in the second region, a portion of the first top surface, a portion of the second top surface, and a dummy structure on the boundary between the first top surface and the second top surface; forming a dielectric structure above the substrate to cover the first device, the second device, and the dummy structure; and removing a portion of the dielectric structure, a portion of the first device, a portion of the second device, and a portion of the dummy structure so that the top surface of the first device, the top surface of the second device, and the top surface of the dummy structure are aligned with each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a flow chart representing a method for forming an integrated circuit according to aspects of the present disclosure.

[0009] Figures 2A to 2M is a cross-sectional view illustrating stages of a method for forming an integrated circuit according to aspects of the present disclosure.

[0010] Figure 3 is a top view illustrating an integrated circuit layout structure according to aspects of the present disclosure.

[0011] Figure 4 is a top view illustrating an integrated circuit layout structure according to aspects of the present disclosure.

[0012] Figure 5 is a cross-sectional view illustrating an integrated circuit according to aspects of the present disclosure. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. The following describes specific examples of components and arrangements to simplify this disclosure. Of course, this type is only an example and does not wish to limit. For example, the first component in the following description is formed above or on the second component and may include an embodiment in which the first component and the second component are formed to directly contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not directly contact. In addition, this disclosure may repeat element symbols and / or letters in various examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] This description of the illustrative embodiment is intended to be read in conjunction with the accompanying drawings that should be considered as a part of the complete written description. In the description of the embodiments disclosed herein, any reference to direction or orientation is intended only for the convenience of description and is not intended to limit the scope of the present disclosure in any way. Relative terms such as "lower", "upper", "horizontal", "vertical", "above", "below", "upward", "downward", "top" and "bottom" and their derivatives (e.g., "horizontally", "downwardly", "upwardly", etc.) should be interpreted as referring to the orientation as described next or as shown in the drawings in the discussion. Such relative terms are only for the convenience of description and do not require the device to be constructed or operated in a specific orientation. Terms such as "attachment", "attachment", "connection" and "interconnection" refer to the relationship in which the structures are directly or indirectly fixed or attached to each other through an intermediary structure, and both removable or rigid attachments or relationships, unless otherwise explicitly described. Furthermore, the features and benefits of the present disclosure are described by reference to the embodiments. Therefore, the present disclosure should not be explicitly limited to such embodiments that illustrate a possible non-limiting combination of features that can exist alone or in other combinations of features, and the scope of the present disclosure should be defined by the appended claims.

[0015] Although the numerical ranges and parameters describing the broad scope of the present disclosure are approximate values, the numerical values ​​explained in the specific examples are reported as accurately as possible. However, any numerical value inherently contains certain errors that are not necessarily derived from the standard deviation found in the corresponding test measurements. Again, as used herein, the term "substantially", "approximately" or "approximately" generally means within a value or range that can be expected by a person of ordinary skill in the art. Alternatively, when considered by a person of ordinary skill in the art, the term "substantially", "approximately" or "approximately" means within an acceptable standard error of the mean value. A person of ordinary skill in the art can understand that the acceptable standard error can vary according to different technologies. Except in the operating / working examples, or unless otherwise explicitly specified, all numerical ranges, amounts, values ​​and percentages (such as for the amount of material, duration, temperature, operating conditions, ratio of amounts and numerical ranges, amounts, values ​​and percentages of the analogs thereof disclosed herein) should be understood to be modified by the term "substantially", "approximately" or "approximately" in all examples. Therefore, unless otherwise indicated, the numerical parameters set forth in this disclosure and the appended claims are approximate values ​​that may vary as necessary. Each numerical parameter should at least be interpreted in light of the number of reported significant figures and by applying ordinary rounding techniques. Ranges may be expressed herein as from one endpoint to another or between two endpoints. All ranges disclosed herein include the endpoints unless otherwise specified.

[0016] Silicon-on-insulator (SOI) substrates have been widely used in semiconductor manufacturing operations. Due to the advantages provided by SOI (such as low parasitic capacitance, lower noise, less short channel effects, and better swing performance), high voltage (HV) devices can be embedded and integrated with HV devices and low voltage (LV) devices using SOI technology.

[0017] In addition, high-k metal gate (HKMG) technology is expected to play an important role in the next generation of CMOS devices. This technology incorporates high-k dielectrics, which reduce leakage and improve the dielectric constant. In order to help Fermi level pinning and allow the gate to be adjusted to reduce the threshold voltage, a metal gate is used instead of a polysilicon gate. By combining a metal gate and a high-k dielectric, HKMG technology reduces gate leakage, thereby increasing transistor capacitance and allowing the chip to function with reduced power requirements. Therefore, integrating HV and LV devices with HKMG is a technology that enables conventional scaling of transistors and reduces the required standby power due to a reduction in gate leakage.

[0018] However, studies have found that when an HV device is integrated with HKMG technology, this may cause high-k dielectric residues at the boundary between the LV device and the HV device. The high-k dielectric residues may cause contamination during subsequent manufacturing operations.

[0019] Thus, the present disclosure provides a boundary architecture for integrating HV devices and LV devices with HKMG technology. Thus, in some embodiments, the present disclosure provides a boundary architecture for integrating HV devices and LV devices with high-k first and metal gate last technology. In some embodiments, a dummy structure (e.g., a dummy polysilicon structure) may be placed on the boundary between the area accommodating the HV device and the area accommodating the LV device. The dummy structure is provided to completely seal the high-k dielectric residue generated during the manufacturing operation, and because of this, the high-k residue contamination can be mitigated.

[0020] In some embodiments, a high voltage (HV) device as used herein refers to a device that generally has an operating voltage greater than the operating voltage of a logic device, such as an integrated circuit die input / output (I / O) device. For example, an HV device may have an operating voltage greater than approximately 2.5 volts, while a logic device may have an operating voltage less than approximately 1.2 volts. In some embodiments, a logic device having a relatively low operating voltage is referred to as a LV device. However, the operating voltage may vary for different applications, and therefore it is not limited thereto.

[0021] Figure 1 1 is a flow chart representing a method 10 for forming an integrated circuit according to aspects of the present disclosure. Method 10 includes a number of operations (101, 102, 103, 104, 105, 106, 107, 108, 109, and 110). Method 10 will be further described according to one or more embodiments. It should be noted that the operations of method 10 may be rearranged or otherwise modified within the scope of various aspects. It should be further noted that additional processes may be provided before, during, and after method 10, and some other processes may be only briefly described herein. Therefore, other implementations are possible within the scope of the various aspects described herein.

[0022] Figures 2A to 2M 1 is a cross-sectional view illustrating stages of a method for forming an integrated circuit according to aspects of the present disclosure. At operation 101, a substrate 200 having a first region 202a, a second region 202b, and an isolation structure 210 separating the first region 202a from the second region 202b is received or provided. In some embodiments, the first region 202a may be used to accommodate LV devices (e.g., logic devices) and the second region 202b may be used to accommodate HV devices (e.g., I / O devices), but the present disclosure is not limited thereto. In some embodiments, the isolation structure 210 is formed to surround the first region 202a and the second region 202b such that at least a portion of the isolation structure 210 is placed between the first region 202a and the second region 202b, as shown in FIG. Figure 2ATherefore, the first region 202a and the second region 202b are electrically separated from each other by the isolation structure 210. In some embodiments, the isolation structure 210 may be a shallow trench isolation (STI), but the present disclosure is not limited thereto.

[0023] In some embodiments, structure 200 may be a silicon-on-insulator (SOI) substrate. Figure 2A , substrate 200 may include a semiconductor block 204, a semiconductor layer 208, and a dielectric layer 206 disposed between the semiconductor block 204 and the semiconductor layer 208. In some embodiments, the semiconductor layer 208 may include a semiconductor material such as silicon, germanium, silicon germanium, or a combination thereof, but the disclosure is not limited thereto. In some embodiments, the dielectric layer 206 may be, for example, a buried oxide (BOX) layer or a silicon oxide layer, but the disclosure is not limited thereto. In some embodiments, the semiconductor block 204 may include silicon, but the disclosure is not limited thereto. In other embodiments, substrates that may be used include multilayer substrates, gradient substrates, or hybrid oriented substrates. In some embodiments, the sum of the thickness of the semiconductor layer 208 and the thickness of the dielectric layer 206 may be between approximately 200 angstroms and approximately 50 angstroms, but the disclosure is not limited thereto. In some embodiments, a device formed over an SOI substrate may be referred to as an SOI device. In addition to the ability to maintain low intra-well and inter-well leakage currents, the dielectric layer 206 also allows for a smaller distance for isolation spacing, thus allowing for increased packing density. Additional advantages of SOI devices over bulk devices include reduced soft error sensitivity, improved turn-on characteristics, reduced leakage current, and improved reliability by eliminating junction spurs.

[0024] At operation 102, a portion of the substrate 200 is removed so that the second region 202b is recessed, and a portion of the isolation structure 210 is removed so that the isolation structure 210 obtains a first top surface 212a, a second top surface 212b lower than the first top surface 212a, and a boundary between the first top surface 212a and the second top surface 212b. Figure 2B , in some embodiments, a patterned mask 211 (e.g., a patterned photoresist) may be formed over the substrate 200. A suitable etching operation may be performed to remove portions of the substrate 200 in the second region 202 b and portions of the isolation structure 210 exposed by the patterned mask 211. In some embodiments, portions of the semiconductor layer 208 and portions of the dielectric layer 206 in the second region 202 b are removed, such that the semiconductor bulk 204 is exposed. In other embodiments, portions of the semiconductor layer 208, portions of the dielectric layer 206, and portions of the semiconductor bulk 204 in the second region 202 b are removed. Thus, as shown in FIG. Figure 2B The recessed second region 202b' is obtained as shown in FIG.

[0025] In addition, the portion of the isolation structure 210 exposed by the patterned mask 211 is removed, wherein the thickness of the removed portion of the isolation structure 210 is similar to the thickness of the removed portion of the substrate 200. Therefore, the isolation structure 210 obtains a first top surface 212a, a second top surface 212b, and a boundary between the first top surface 212a and the second top surface 212b. The second top surface 212b is lower than the first top surface 212a. In addition, the first top surface 212a of the isolation structure 210 and the top surface of the substrate 200 in the first region 202a are aligned with each other, or are at the same level, while the second top surface 212b of the isolation structure 210 and the top surface of the substrate 200 in the second region 202b' are aligned with each other, or are at the same level. Figure 2B 2 , a step height H is formed at the boundary between the first top surface 212a and the second top surface 212b of the isolation structure 210. In some embodiments, the step height H may be equal to or greater than the thickness of the removed portion of the substrate 200. For example, when an etching operation is performed to remove a portion of the semiconductor layer 208 and a portion of the dielectric layer 206 in the second region 202b', the step height H is equal to or greater than the sum of the thickness of the semiconductor layer 208 and the thickness of the dielectric layer 206, for example, between approximately 200 angstroms and approximately 500 angstroms, but the disclosure is not limited thereto. The patterned mask 211 may then be removed.

[0026] like Figure 2C , in some embodiments, a sacrificial insulating layer 213 is formed to completely cover the substrate 200. After forming the sacrificial insulating layer 213, a well region 220 may be formed in the substrate 200 in the second region 202b'. In some embodiments, implantation and annealing may be performed on the semiconductor bulk 204 in the second region 202b'. Thus, the well region 220 is obtained. In some embodiments, the sacrificial insulating layer 213 helps protect the substrate 200 in the first region 202a and the isolation structure 210 and alleviates the outgassing problem during the formation of the well region 220. In some embodiments using an n-type HV device, the well region 220 may have an n-type dopant. In some embodiments, the well region 220 may be referred to as a drift region. In some embodiments, the drift region is between the device channel (e.g., under the gate structure to be formed) and the drain region to be formed. The drift region is configured to provide a high device breakdown voltage and protection from hot carrier injection (HCI).

[0027] refer to Figure 2DAfter forming the well region 220, a body region 222 is formed. The body region 222 may be placed in the well region 220. In embodiments using an n-type HV device, the body region 222 may have a p-type dopant that is opposite to the dopant type of the well region 220. In some embodiments, a body contact region (not shown) may be formed in the body region 222. The body contact region may have the same dopant type as the body region 222. The body contact region may provide an electrical connection for the body region 222. It should be understood that Figure 2D The locations of the well region 220 and the body region 222 (and the body contact region) shown in are merely exemplary and may be modified by one skilled in the art to achieve a desired HV device.

[0028] Still refer to Figure 2D After forming the body region 222, a well region 224 is formed in the substrate 200 in the first region 202a. In some embodiments, the well region 224 is formed in the semiconductor layer 208 in the first region 202a. In other embodiments, the well region 224 is formed in both the semiconductor layer 208 and the semiconductor bulk 204. In addition, depending on the type of LV device to be formed, the well region 224 may include n-type or p-type dopants. In some embodiments, a well implantation is performed, and then the sacrificial insulating layer 213 is removed. Before removing the sacrificial insulating layer 213, an annealing is performed. Finally, the well region 224 of the LV device is obtained.

[0029] At operation 103, a high-K gate dielectric layer 228 is formed over the substrate 200. In some embodiments, before forming the high-K gate dielectric layer 228, an interfacial layer (IL) 226 may be formed on the substrate 200. An example of the IL 226 is a thin silicon oxide layer. In some embodiments, the thin silicon oxide layer may be formed by thermal oxidation. In other embodiments, the thin silicon oxide layer may be formed by atomic layer deposition (ALD). When thermal oxidation is utilized to form the IL 226, the IL 226 is formed only on the top surface of the semiconductor material. Thus, the IL 226 is formed on the semiconductor layer 208 in the first region 202a and on the semiconductor bulk 204 in the second region 202b', while the isolation structure 210 is free of the IL 226, as shown in FIG. Figure 2E 226 is shown in FIG. In other words, IL 226 is formed on the well region 224 in the first region 202a and on the drift region 220 and the body region 222 in the second region 202b′. It has been observed that IL 226 can provide a remedy for some high-k dielectric gate stack integration issues such as carrier trapping and carrier mobility reduction of HK. IL 226 can also be important as a diffusion barrier to prevent undesirable interface reactions between the HK dielectric material and the substrate 200.

[0030] Still refer to Figure 2EThe high-k gate dielectric layer 228 may be formed on the IL 226 by ALD, chemical vapor deposition (CVD), metal organic CVD (MOCVD), physical vapor deposition (PVD), thermal oxidation, a combination thereof, or other suitable techniques. In some embodiments, the high-k gate dielectric layer 228 may include a binary or ternary high-k film, such as HfO X In some embodiments, the high-K gate dielectric layer 228 may include a high-K material such as LaO, AlO, ZrO, TiO, Ta 2 O 5 , U 2 O 3 、SiTiO 3 (STO), BaTiO 3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO 3 (BST), Al 2 O 3 、Si 3 N 4 , nitrogen oxides or other suitable materials.

[0031] At operation 104, a semiconductor layer 230 is formed on the high-K gate dielectric layer 228. In some embodiments, the semiconductor layer 230 may be a polysilicon layer placed by deposition techniques over the high-K gate dielectric layer 228. In other embodiments, the semiconductor layer 230 may be an amorphous silicon layer.

[0032] At operation 105, the semiconductor layer 230 and the high-k gate dielectric layer 228 are patterned to form a first sacrificial gate 232a in the first region 202a, a second sacrificial gate 232b in the second region 202b', and a dummy structure 232c on the isolation structure 210. Figure 2F , a patterned hard mask 231 is formed over the semiconductor layer 230 to define the location and size of the sacrificial gate, and an etching operation is performed to remove portions of the semiconductor layer 230 and the high-k gate dielectric layer 228. As a result, a first sacrificial gate 232a is formed in the first region 202a, a second sacrificial gate 232b is formed in the second region 202b', and a dummy structure 232c is obtained. In addition, the dummy structure 232c covers a portion of the first top surface 212a of the isolation structure 210, a portion of the second top surface 212b of the isolation structure 210, and a boundary between the first top surface 212a and the second top surface 212b, as shown in FIG. Figure 2F In some embodiments, the thicknesses of the first sacrificial gate 232a, the second sacrificial gate 232b, and the dummy structure 232c are similar.

[0033] In some comparative embodiments, the semiconductor layer 230 and the high-k gate dielectric layer 228 above the isolation structure 210 are removed. However, it is found that due to the step height H, the high-k material at the boundary between the first top surface 212a and the second top surface 212b may not be completely removed. In addition, the high-k residue may cause contamination problems in subsequent manufacturing operations. In some comparative embodiments, the high-k gate dielectric layer may be overetched to remove the high-k material from the boundary. However, it is found that the high-k gate dielectric layer under the sacrificial gate is damaged and reliability issues arise. Compared to the comparative embodiment, the dummy structure 232c is formed above the boundary of the first top surface 212a and the second top surface 212b, and therefore the high-k material (i.e., the high-k gate dielectric layer 228) is completely covered by the semiconductor layer 230 of the dummy structure 232c.

[0034] In addition, the width of the dummy structure 232c is greater than approximately 2 times the minimum critical dimension of the integrated circuit. It should be understood that the critical dimension (or design rule limit) defines the minimum width of a line or the minimum space between two lines allowed in the manufacture of the device. It should be noted that if the width of the dummy structure 232c is less than 2 times the minimum critical dimension of the integrated circuit, then when the dummy structure 232c is offset from the boundary due to process variations (such as misalignment), high-k material may remain above the boundary between the first top surface 212a and the second top surface 212b. Therefore, the undesirable high-k residue problem occurs.

[0035] refer to Figure 2G In some embodiments, a spacer 234 is formed over the sidewalls of each of the first sacrificial gate 232a, the second sacrificial gate 232b, and the dummy structure 232c. Figure 2F 2, the spacer 234 covers the sidewalls of the patterned hard mask 231, the semiconductor layer 230, the high-k gate dielectric layer 228, and the IL 226 of the first sacrificial gate 232a and the second sacrificial gate 232b. The spacer 234 also covers the sidewalls of the patterned hard mask 231, the semiconductor layer 230, and the high-k gate dielectric layer 228 of the dummy structure 232c. Therefore, the high-k gate dielectric layer 228 above the boundary between the first top surface 212a and the second top surface 212b can be completely enclosed within the semiconductor layer 230 and the spacer 234 of the dummy structure 232c, as shown in FIG. Figure 2GIn some embodiments, the spacer 234 may be a multi-layer structure. For example, the spacer 234 may be an oxide-nitride (ON) structure, which includes a silicon nitride sealing layer 234a in contact with the IL 226, a high-k gate dielectric layer 228, a semiconductor layer 230, and a silicon oxide layer 234b covering the silicon nitride sealing layer 234a, but the present disclosure is not limited thereto.

[0036] Still refer to Figure 2G After forming the spacer 234, doped regions 236a and 236b are formed in the substrate 200. The doped regions 236a and 236b are used as source regions and drain regions, respectively. In some embodiments, in the first region 202a, the doped regions 236a and 236b are formed in the substrate at both sides of the first sacrificial gate 232a, respectively. In some embodiments, in the second region 202b, the doped regions 236a and 236b are formed in the body region 222 and the drift region 220, respectively. For example, Figure 2G As shown in FIG. 1 , the doped region 236a is formed in the body region 222 and the doped region 236b is formed in the drift region 220 and is separated from the dummy structure 232b by the drift region 220. Therefore, at operation 106, a first device 240a is formed in the first region 202a, a second device 240b is formed in the second region 202b′, and a dummy structure 240c is formed on the isolation structure 210. Figure 2G , the dummy structure 240c covers a portion of the first top surface 212a, a portion of the second top surface 212b, and a boundary between the first top surface 212a and the second top surface 212b. Thereafter, a protective layer 237 (e.g., a resistance protection oxide (RPO) layer) may be formed to cover a portion of the second device 240b, a portion of the doped region 236b, and a portion of the drift region 220. Subsequently, a silicide layer 238 is formed over the exposed doped regions 236a and 236b, as shown in FIG. Figure 2G In some embodiments, after forming the silicide layer 238, the patterned hard mask 231 is removed.

[0037] At operation 107, a dielectric structure is formed over the substrate 200 to cover the first device 240a, the second device 240b, and the dummy structure 240c. In some embodiments, the dielectric structure may include a contact etch stop layer (CESL) 242 and an interlayer dielectric (ILD) 244, such as Figure 2H. In some embodiments, CESL 242 may include a material selected from silicon nitride, silicon carbide, or other dielectric materials. In some embodiments, ILD 244 may be blanket formed to a thickness sufficient to form a top surface that is higher than the top surfaces of first device 240a, second device 240b, and dummy structure 240c. ILD 244 may be formed of an oxide using, for example, flowable chemical vapor deposition (FCVD). ILD 244 may also be a spin-on glass formed using spin coating. In some embodiments, ILD 244 may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS) oxide, TiN, SiOC, or other low-k non-porous dielectric materials.

[0038] At operation 108, portions of the dielectric structure, portions of the first device 240a, portions of the second device 240b, and portions of the dummy structure 240c are removed. Fig.2I 240a, and a portion of the semiconductor layer 230 of the dummy structure 240c. As shown in FIG. 240b, in some embodiments, planarization (e.g., a chemical mechanical polishing (CMP) operation) is performed to remove portions of the dielectric structure, i.e., portions of the ILD 244 and portions of the CESL 242. CMP is also performed to remove portions of the first sacrificial gate 232a and portions of the spacer 234 of the first device 240a, portions of the second sacrificial gate 232b and portions of the spacer 234 of the second device 240b, and portions of the semiconductor layer 230 and portions of the spacer 234 of the dummy structure 240c. Thus, the top surface of the first device 240a, the top surface of the second device 240b, and the top surface of the dummy structure 240c are aligned with each other, or are at the same level, such as Fig.2I Displayed in.

[0039] refer to Figure 2J In some embodiments, a dielectric layer 245 is formed over the dummy structure 240c, but the first device 240a in the first region 202a and the second device 240b in the second region 202b' are exposed through the dielectric layer 245. The dielectric layer 245 is used as a protective layer for providing protection during subsequent operations. In some embodiments, the dielectric layer 245 may include a material similar to the ILD 244, but the present disclosure is not limited thereto. The thickness of the dielectric layer 245 should be large enough to withstand subsequent operations.

[0040] At operation 109, the first sacrificial gate 232a and the second sacrificial gate 232b are removed. Figure 2K2 , the first sacrificial gate 232a (i.e., the semiconductor layer 230) is removed to form a first gate trench 246a in the first region 202a, and the high-k gate dielectric layer 228 is exposed through the bottom of the first gate trench 246a. The second sacrificial gate 232b (i.e., the semiconductor layer 230) is removed to form a second gate trench 246b in the second region 202b′, and the high-k gate dielectric layer 228 is exposed through the bottom of the second gate trench 246b. The semiconductor layer 230 above the isolation structure 210 (i.e., above a portion of the first top surface 212a, a portion of the second top surface 212b, and a boundary between the first top surface 212a and the second top surface 212b) is protected by the dielectric layer 245 compared to the removed portions of the semiconductor layer 230 in the first region 202a and the second region 202b′.

[0041] At operation 110, a first metal gate 248a is formed in the first gate trench 246a and a second metal gate 248b is formed in the second gate trench 246b. Figure 2L . In some embodiments, the first metal gate 248a and / or the second metal gate 248b may include at least a barrier metal layer, a work function metal layer, and a gap filling metal layer. The barrier metal layer may include, for example, but not limited to, TiN. The work function metal layer may include a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of such materials, but is not limited thereto. For n-channel FETs, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as work function metal layers, and for p-channel FETs, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used as work function metal layers. In some embodiments, the gap filling metal layer may include a conductive material, such as Al, Cu, AlCu, or W, but is not limited to the materials mentioned above. In some embodiments, another planarization such as CMP is performed to remove excess metal material and the dielectric layer 245. Therefore, the top surface of the first metal gate 248a, the top surface of the metal gate 248b, the top surface of the dummy structure 240c, and the top surface of the dielectric structure (including the CESL 242 and the ILD 244) are aligned with each other, or are at the same level. However, the thickness of the second metal gate 248b is greater than the thickness of the first metal gate 248a. In addition, the dummy structure 240c may include a first portion 241-1 and a second portion 241-2 coupled to each other. The thickness of the first portion 242-1 is similar to the thickness of the first metal gate 248a and the thickness of the second portion 241-2 is similar to the thickness of the second metal gate 248b, as shown in FIG. Figure 2L Displayed in.

[0042] refer to Figure 2M In some embodiments, another ILD 250 may be formed over the substrate 200, and a contact structure 252 may be formed in the ILD 250 and the ILD 244. In addition, the contact structure 252 may penetrate the ILD 250 and 244, so that the contact structure 252 is coupled to the doped regions 236a and 236b to provide electrical connections between the first device 240a and the second device 240b and other devices.

[0043] Therefore, an integrated circuit 20 is provided. Figure 3 , Figure 4 and Figure 2M ,in Figure 3 and Figure 4 is a top view illustrating an integrated circuit layout structure according to aspects of the present disclosure, and Figure 2M It is along Figure 3 and Figure 4 The integrated circuit 20 includes a substrate 200, wherein the substrate 200 may be a dielectric layer 206 including a semiconductor block 204, a semiconductor layer 208, and a semiconductor layer 206 between the semiconductor block 204 and the semiconductor layer 208. A first region 202a and a second region 202b' are defined in the substrate 200. In some embodiments, the second region 202b' is a recessed region such that the top surface of the substrate 200 in the second region 202b' is lower than the top surface of the substrate 200 in the first region 202a. In some embodiments, the first region 202a may be used to accommodate LV devices and the second region 202b' may be used to accommodate HV devices, and therefore, the first region 202a may be referred to as a LV region and the second region 202b' may be referred to as a HV region.

[0044] In addition, the substrate 200 includes an isolation structure 210 disposed in the substrate 200 and separating the first region 202a from the second region 202b′. Figure 2M , the isolation structure 210 has a first top surface 212a and a second top surface 212b lower than the first top surface 212a. As mentioned above, the first top surface 212a of the isolation structure 210 and the top surface of the substrate 200 in the first region 202a are aligned with each other or at the same level, while the second top surface 212b of the isolation structure 210 and the top surface of the substrate 200 in the second region 202b' are aligned with each other or at the same level. Figure 2B2 , the step height H is formed at the boundary between the first top surface 212a and the second top surface 212b of the isolation structure 210, and the step height H is also formed between the first region 202a and the second region 202b′ of the substrate 200. In some embodiments, the step height H is equal to or greater than the sum of the thickness of the semiconductor layer 208 and the thickness of the dielectric layer 206, but the disclosure is not limited thereto.

[0045] The integrated circuit 20 includes a first device 240a in the first region 202a and a second device 240b in the second region 202b'. In some embodiments, the first device 240a may be a LV device and the second device 240b may be a HV device, but the disclosure is not limited thereto. In addition, the integrated circuit 20 includes a semiconductor dummy structure 240c placed on the isolation structure 210. Figure 2M , the semiconductor dummy structure 240c covers a portion of the first top surface 212a, a portion of the second top surface 212b, and a boundary between the first top surface 212a and the second top surface 212b. In some embodiments, the semiconductor dummy structure 240c is a frame-like structure. In some embodiments, the frame-like semiconductor dummy structure 240c surrounds the first region 202a, such as Figure 3 In other embodiments, the frame-shaped semiconductor dummy structure 240c surrounds the second region 202b', such as Figure 4 A portion of the frame-shaped semiconductor dummy structure 240c is placed between the first region 202a and the second region 202b', as shown in FIG. Figure 3 , Figure 4 and Figure 2M The width of the frame-shaped semiconductor dummy structure 240c is smaller than the width of the portion of the isolation structure 210 between the first region 202a and the second region 202b', as shown in FIG. Figure 3 and Figure 4 In addition, the width of the frame-shaped semiconductor dummy structure 240c is greater than the width of the first device 240a and the width of the second device 240b. Figure 2M Displayed in.

[0046] Still refer to Figure 3 and Figure 4 In some embodiments, the integrated circuit 20 further includes a frame-shaped doped region 214 disposed in the substrate 100. Figure 3 and Figure 4, the frame-shaped doped region 214 can surround the second region 202b' and serve as a guard ring for the HV device in the second region 202b'. In some embodiments, although not shown, the doped region 214 is separated from the second region 202b' by another isolation structure. In some embodiments, the frame-shaped semiconductor dummy structure 240c is placed on the isolation structure 210 and surrounds the first region 202a. In addition, the frame-shaped semiconductor dummy structure 240c is offset from the doped region 214, such as Figure 3 In other embodiments, the frame-shaped semiconductor dummy structure 240c is placed on the isolation structure 210 but surrounds both the second region 202b' and the doped region 214. In addition, the frame-shaped semiconductor dummy structure 240c is offset from the doped region 214, such as Figure 4 Displayed in.

[0047] Reference again Figure 2M In some embodiments, the first device 240a includes a first metal gate 248a, a high-k gate dielectric layer 228 below the first metal gate 248a, an IL 226 below the high-k gate dielectric layer 228, and doped regions 236a and 236b. The second device 240b includes a second metal gate 248b, a high-k gate dielectric layer 228 below the second metal gate 248b, an IL 226 below the high-k gate dielectric layer 228, and doped regions 236a and 236b. Compared to the first device 240a and the second device 240b, the semiconductor dummy structure 240c includes a semiconductor layer 230 and a high-k gate dielectric layer 228 below the semiconductor layer 230. The first device 240a further includes a spacer 234 placed over the sidewalls of the first metal gate 248a, the high-k gate dielectric layer 228, and the IL 226. The second device 240b further includes a spacer 234 disposed over the sidewalls of the second metal gate 248b, the high-k gate dielectric layer 228, and the IL 226. The semiconductor dummy structure 240c further includes a spacer 234 disposed over the sidewalls of the semiconductor layer 230 and the high-k gate dielectric layer 228. Thus, the high-k gate dielectric layer 228 of the semiconductor dummy structure 240c is completely enclosed within the semiconductor layer 230 and the spacer 234, as shown in FIG. Figure 2M Displayed in.

[0048] The thickness of the second device 240b is greater than the thickness of the first device 240a. The semiconductor dummy structure 240c includes a first portion 241-1 and a second portion 241-2 coupled to each other, the thickness of the first portion 241-1 is similar to the thickness of the first device 240a in the first region 202a, and the thickness of the second portion 241-2 is similar to the thickness of the second device 240b in the second region 202b'. Since the thickness of the second device 240b is greater than the thickness of the first device 240a, the thickness of the second portion 241-2 of the semiconductor dummy structure 240c is greater than the thickness of the first portion 241-1 of the semiconductor dummy structure 240c. Therefore, the top surfaces of the first device 240a, the semiconductor dummy structure 240c, and the second device 240b are aligned with each other or are at the same level.

[0049] In some embodiments, the width of the second device 240b is greater than the width of the first device 240a, and the width of the semiconductor dummy structure 240c is greater than the width of both the first device 240a and the second device 240b. In some embodiments, the width of the semiconductor dummy structure 240c is greater than 2 times the minimum critical dimension (CD) of the integrated circuit. As mentioned above, the critical dimension (or design rule restriction) defines the minimum width of a line or the minimum space between two lines allowed in the manufacture of the device. As mentioned above, if the width of the semiconductor dummy structure 240c (i.e., the semiconductor layer 230) is less than 2 times the minimum threshold dimension of the integrated circuit 20, then when the semiconductor dummy structure 240c is offset from the boundary due to process variations (e.g., misalignment), high dielectric constant material may remain above the boundary between the first top surface 212a and the second top surface 212b. Therefore, an undesirable high dielectric constant residue problem occurs.

[0050] Please refer to Figure 5 , which is a cross-sectional view of an integrated circuit according to aspects of the present disclosure. It should be noted that Figure 2M and Figure 5 Like elements in the drawings are indicated by like numerals and are referred to in the following for simplicity. Figure 5 Omitted from the description Figure 2M and Figure 5 In some embodiments, the integrated circuit 20 includes another isolation structure 216 disposed in the second region 202b'. The isolation structure 216 may be a STI or a field oxide (FOX). Figure 5 As shown in FIG. 2 , a portion of the second metal gate 248 b and a portion of the high-k gate dielectric layer 228 cover a portion of the isolation structure 216 .

[0051] Therefore, the present disclosure provides a boundary architecture for integrating HV SOI devices and LV SOI devices with HKMG technology. Therefore, in some embodiments, the present disclosure provides a boundary architecture for integrating HV SOI devices and LV SOI devices with high dielectric constant first and gate last technology. In some embodiments, a dummy structure (e.g., a semiconductor dummy structure) is placed on the boundary between the areas for accommodating HV devices and LV devices. A semiconductor dummy structure is provided to completely seal high dielectric constant dielectric materials that may be generated during manufacturing operations, and because of this, high dielectric constant residue contamination can be alleviated. In addition, the method for forming a semiconductor dummy structure is compatible with manufacturing operations for SOI technology, HKMG technology, and HV-LV integration and can be easily integrated into manufacturing operations for SOI technology, HKMG technology, and HV-LV integration.

[0052] According to one embodiment of the present invention, an integrated circuit is provided. The integrated circuit includes: a substrate having a first region and a second region; a first isolation structure placed in the substrate and separating the first region from the second region; a first device placed in the first region; a second device placed in the second region; and a semiconductor dummy structure placed on the first isolation structure. The first isolation structure has a first top surface and a second top surface lower than the first top surface. In some embodiments, the semiconductor dummy structure covers a portion of the first top surface, a portion of the second top surface, and a boundary between the first top surface and the second top surface.

[0053] According to one embodiment of the present invention, an integrated circuit layout structure is provided. The integrated circuit layout structure includes: a substrate having a low voltage (LV) region and a high voltage (HV) region; an LV device placed in the LV region and an HV device placed in the HV region; an isolation structure placed in the substrate and separating the LV region from the HV region; and a frame-shaped semiconductor dummy structure placed on the isolation structure. In some embodiments, a portion of the frame-shaped semiconductor dummy structure is placed between the LV region and the HV region. In some embodiments, the width of the frame-shaped semiconductor dummy structure is smaller than the width of the portion of the isolation structure between the LV region and the HV region. In some embodiments, the width of the frame-shaped semiconductor dummy structure is greater than the width of the LV device and the width of the HV device.

[0054] According to one embodiment of the present invention, a method for forming an integrated circuit is provided. The method includes the following operations. A substrate having a first region, a second region, and an isolation structure separating the first region from the second region is received. A portion of the substrate is removed so that the second region is recessed, and a portion of the isolation structure is removed so that the isolation structure obtains a first top surface, a second top surface lower than the first top surface, and a boundary between the first top surface and the second top surface. A first device is formed in the first region, a second device is formed in the second region, and a dummy structure is formed over a portion of the first top surface, a portion of the second top surface, and the boundary between the first top surface and the second top surface. A dielectric structure is formed over the substrate to cover the first device, the second device, and the dummy structure. A portion of the dielectric structure, a portion of the first device, a portion of the second device, and a portion of the dummy structure are removed so that the top surface of the first device, the top surface of the second device, and the top surface of the dummy structure are aligned with each other.

[0055] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purpose and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

[0056] Explanation of symbols

[0057] 10: Methods

[0058] 20: Integrated Circuits

[0059] 101: Operation

[0060] 102: Operation

[0061] 103: Operation

[0062] 104: Operation

[0063] 105: Operation

[0064] 106: Operation

[0065] 107: Operation

[0066] 108: Operation

[0067] 109: Operation

[0068] 110: Operation

[0069] 200: substrate

[0070] 202a: District 1

[0071] 202b: District 2

[0072] 202b': Depression zone 2

[0073] 204: Semiconductor block

[0074] 206: Dielectric layer

[0075] 208: Semiconductor layer

[0076] 210: Isolation Structure

[0077] 211: Patterned mask

[0078] 212a: first top surface

[0079] 212b: second top surface

[0080] 213: Sacrificial insulation layer

[0081] 214: frame-shaped doped region

[0082] 220: Well region

[0083] 222: Main area

[0084] 224: Well region

[0085] 226:Interface layer (IL)

[0086] 228: High dielectric constant gate dielectric layer

[0087] 230: Semiconductor layer

[0088] 231: Patterned hard mask

[0089] 232a: first sacrificial gate

[0090] 232b: second sacrificial gate

[0091] 232c: Virtual structure

[0092] 234: Spacer

[0093] 234a: Silicon nitride sealing layer

[0094] 234b: Silicon oxide layer

[0095] 236a: doped region

[0096] 236b: doped region

[0097] 237: Protective layer

[0098] 238: Silicide layer

[0099] 240a: First device

[0100] 240b: Second device

[0101] 240c: Virtual structure

[0102] 241-1: Part 1

[0103] 241-2: Part 2

[0104] 242: Contact Etch Stop Layer (CESL)

[0105] 244: Interlayer dielectric (ILD)

[0106] 245: Dielectric layer

[0107] 246a: first gate trench

[0108] 246b: second gate trench

[0109] 248a: first metal gate

[0110] 248b: second metal gate

[0111] 250: Interlayer dielectric (ILD)

[0112] 252: Contact structure

[0113] H: Step height

Claims

1. An integrated circuit, wherein include: a substrate comprising a first region and a second region; a first isolation structure disposed in the substrate and separating the first region from the second region, wherein the first isolation structure has a first top surface and a second top surface lower than the first top surface; a first device placed in the first zone; a second device placed in the second zone; a frame-shaped semiconductor dummy structure placed on the first isolation structure, wherein the frame-shaped semiconductor dummy structure covers a portion of the first top surface, a portion of the second top surface, and a boundary between the first top surface and the second top surface and wherein a width of the frame-shaped semiconductor dummy structure is smaller than a width of a portion of the first isolation structure between the first region and the second region, and the width of the frame-shaped semiconductor dummy structure is greater than a width of the first device and a width of the second device; and A high-k gate dielectric layer separates the first isolation structure from the frame-shaped semiconductor dummy structure.

2. The integrated circuit according to claim 1, wherein the frame-shaped semiconductor dummy structure includes a first portion and a second portion coupled to each other, a thickness of the first portion is similar to a thickness of the first device in the first region, and a thickness of the second portion is similar to a thickness of the second device in the second region.

3. The integrated circuit of claim 2, wherein the thickness of the second device is greater than the thickness of the first device, and the thickness of the second portion of the frame-shaped semiconductor dummy structure is greater than the thickness of the first portion of the frame-shaped semiconductor dummy structure. 4 . The integrated circuit of claim 1 , wherein a top surface of the first device, a top surface of the second device, and a top surface of the frame-shaped semiconductor dummy structure are aligned with each other.

5. An integrated circuit according to claim 1, wherein the first device includes a first metal gate and a first high-k gate dielectric layer below the first metal gate, the second device includes a second metal gate and a second high-k gate dielectric layer below the second metal gate, and the frame-shaped semiconductor dummy structure includes a semiconductor layer and the high-k gate dielectric layer below the semiconductor layer.

6. The integrated circuit according to claim 5, wherein the frame-shaped semiconductor dummy structure further comprises a spacer, wherein the spacer is placed above the sidewalls of the semiconductor layer and the sidewalls of the high-k gate dielectric layer so that the high-k gate dielectric layer is completely enclosed within the semiconductor layer and the spacer.

7. The integrated circuit of claim 5, further comprising a second isolation structure disposed in the second region, wherein a portion of the second metal gate and a portion of the second high-K gate dielectric layer cover a portion of the second isolation structure. 8 . The integrated circuit of claim 1 , wherein a step height is formed between the first top surface and the second top surface of the first isolation structure and at the boundary between the first region and the second region of the substrate.

9. The integrated circuit of claim 1, wherein a width of the frame-shaped semiconductor dummy structure is greater than twice a minimum critical dimension of the integrated circuit.

10. An integrated circuit layout structure, wherein include: A substrate including a low voltage LV region and a high voltage HV region; an LV device placed in the LV area and an HV device placed in the HV area; an isolation structure disposed in the substrate and surrounding the LV region and the HV region and separating the LV region from the HV region; and a frame-shaped semiconductor dummy structure, which is placed on the isolation structure, A portion of the frame-shaped semiconductor dummy structure is placed between the LV region and the HV region, a width of the frame-shaped semiconductor dummy structure is smaller than a width of a portion of the isolation structure between the LV region and the HV region, and the width of the frame-shaped semiconductor dummy structure is greater than a width of the LV device and a width of the HV device. 11 . The integrated circuit layout structure according to claim 10 , wherein the frame-shaped semiconductor dummy structure surrounds the LV region. 12 . The integrated circuit layout structure according to claim 10 , wherein the frame-shaped semiconductor dummy structure surrounds the HV region.

13. The integrated circuit layout structure of claim 10, further comprising a doped region disposed in the substrate and surrounding the HV region. 14 . The integrated circuit layout structure according to claim 13 , wherein the frame-shaped semiconductor dummy structure surrounds the HV region and the doping region.

15. A method for forming an integrated circuit, comprising: receiving a substrate having a first region, a second region, and an isolation structure separating the first region from the second region; removing a portion of the substrate and a portion of the isolation structure so that the second region is recessed and the isolation structure obtains a first top surface, a second top surface lower than the first top surface, and a boundary between the first top surface and the second top surface; forming a first device in the first region, a second device in the second region, and a portion of the first top surface, a portion of the second top surface, and a frame-shaped semiconductor dummy structure on the boundary between the first top surface and the second top surface, wherein the forming of the first device, the second device, and the frame-shaped semiconductor dummy structure further comprises: forming a high-k gate dielectric layer over the substrate; and forming a semiconductor layer on the high-k gate dielectric layer, wherein the high-k gate dielectric layer separates the isolation structure from the frame-shaped semiconductor dummy structure; forming a dielectric structure over the substrate to cover the first device, the second device, and the frame-shaped semiconductor dummy structure; and A portion of the dielectric structure, a portion of the first device, a portion of the second device, and a portion of the frame-shaped semiconductor dummy structure are removed so that a top surface of the first device, a top surface of the second device, and a top surface of the frame-shaped semiconductor dummy structure are aligned with each other and wherein a width of the frame-shaped semiconductor dummy structure is smaller than a width of a portion of the isolation structure between the first region and the second region, and the width of the frame-shaped semiconductor dummy structure is greater than a width of the first device and a width of the second device.

16. The method of claim 15, wherein the substrate comprises a semiconductor block, a semiconductor layer, and a dielectric layer placed between the semiconductor block and the semiconductor layer, and the removing of the portion of the substrate removes a portion of the semiconductor layer and a portion of the dielectric layer in the second zone so that the semiconductor block in the second zone is exposed.

17. The method according to claim 15, wherein the forming of the first device, the second device, and the frame-shaped semiconductor dummy structure further comprises: include: patterning the high-k gate dielectric layer and the semiconductor layer to form a first sacrificial gate in the first region, a second sacrificial gate in the second region, and the frame-shaped semiconductor dummy structure on the isolation structure, The frame-shaped semiconductor dummy structure covers the portion of the first top surface, the portion of the second top surface and the boundary between the first top surface and the second top surface, and the first sacrificial gate, the second sacrificial gate and the frame-shaped semiconductor dummy structure have similar thicknesses.

18. The method according to claim 17, further comprising: include: removing the first sacrificial gate and the second sacrificial gate to form a first gate trench and a second gate trench; and forming a first metal gate in the first gate trench and forming a second metal gate in the second gate trench, The thickness of the second metal gate is greater than the thickness of the first metal gate. 19 . The method of claim 18 , further comprising forming a dielectric layer over the frame-shaped semiconductor dummy structure before the removing the first sacrificial gate and the second sacrificial gate.

20. The method according to claim 18, wherein the frame-shaped semiconductor dummy structure includes a first portion and a second portion coupled to each other, a thickness of the first portion is similar to the thickness of the first metal gate, and a thickness of the second portion is similar to the thickness of the second metal gate.

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