Harmonic combination module and algorithm of multi-level APF with interleaved parallel connection of common AC and DC bus

Abstract

The present invention discloses a common AC / DC bus staggered parallel multi-level APF harmonic combination module, which mainly includes a harmonic combination algorithm module, a PWM module, a DC side capacitor, and a common AC / DC bus staggered parallel output unit; the common AC / DC bus staggered parallel output unit is composed of two three-level diode midpoint clamped inverter circuit units staggered in parallel; the DC side capacitor is connected to the three-level diode midpoint clamped inverter circuit unit to provide a DC voltage for it; the output of the harmonic combination algorithm module is used as a PWM module modulation wave, and the output of the PWM module controls the output of the common AC / DC bus staggered parallel output unit. A common AC / DC bus staggered parallel multi-level APF harmonic combination module is also disclosed. The present invention can effectively improve the utilization rate of DC voltage, reduce the manufacturing cost of equipment, and improve the working reliability of equipment.

Description

Technical Field

[0001] The present invention relates to the field of power quality, and in particular to a common AC / DC bus staggered parallel multi-level APF harmonic combination module and algorithm. Background Art

[0002] In the power industry of all countries in the world, almost all use a single constant frequency sinusoidal power supply, but the investment of a large number of power electronic equipment has caused a large number of harmonics in the power grid. The commonly used solutions are passive filtering and active filtering. Active filtering usually uses power electronic equipment to compensate for harmonics. Due to the superposition of various harmonics, the use of traditional APF may cause a large voltage drop on the inductor, which is higher after superimposing with the grid side voltage. This requires a higher voltage on the DC side, which may cause the capacitor's withstand voltage to exceed the value, reduce the capacitor's life, and even cause accidents such as capacitor explosion.

[0003] Therefore, there is an urgent need to provide a new type of common AC / DC bus staggered parallel multi-level APF harmonic combination module and algorithm to solve the above problems. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a common AC / DC bus staggered parallel multi-level APF harmonic combination module and algorithm, which can effectively improve the DC voltage utilization rate, reduce the equipment manufacturing cost, and improve the equipment working reliability.

[0005] In order to solve the above technical problems, a technical solution adopted by the present invention is: providing a common AC / DC bus staggered parallel multi-level APF harmonic combination module, mainly including a harmonic combination algorithm module, a PWM module, a DC side capacitor, and a common AC / DC bus staggered parallel output unit;

[0006] The common AC / DC busbar interleaved parallel output unit is composed of two three-level diode midpoint clamped inverter circuit units interleaved in parallel;

[0007] The DC side capacitor is connected to a three-level diode midpoint clamped inverter circuit unit to provide a DC voltage therefor;

[0008] The output of the harmonic combination algorithm module is used as a modulation wave of the PWM module, and the output of the PWM module controls the output of the common AC / DC bus staggered parallel output unit.

[0009] In a preferred embodiment of the present invention, the three-level diode midpoint clamped inverter circuit unit includes an input end connected to a DC side capacitor, an output end connected to a power grid, a plurality of switch tube circuits, and a diode clamping circuit. The diode clamping circuit is connected in parallel to the same bridge arm of the same three-level diode midpoint clamped inverter circuit unit and is located between two adjacent switch tube circuits on both sides of the midpoint.

[0010] In order to solve the above technical problems, another technical solution adopted by the present invention is to provide a common AC / DC bus staggered parallel multi-level APF harmonic combination algorithm, comprising the following steps:

[0011] S1: Sample all the three-phase harmonics to be compensated, and then integrate all the three-phase harmonic currents to be compensated Get the parameters of the corresponding voltage on the DC side;

[0012] S2: By dividing the low-order harmonics into two groups and combining them, all possible combinations and sums of all harmonics to be compensated are obtained. N is the highest harmonic to be compensated;

[0013] S3: Combine all possible harmonic peak values ​​and v in step S2 ave Compare them pairwise and select the one with the smallest peak value as the best combination as the PWM module modulation wave.

[0014] In a preferred embodiment of the present invention, when the PWM module is modulating, the same bridge arm Q1 (Q2) and Q3 (Q4) tubes of the same three-level diode mid-point clamped inverter circuit unit are complementary turned on, the conduction angles of the three-phase bridge arms of the same three-level diode mid-point clamped inverter circuit unit differ by 120°, and the switch tube circuits at corresponding positions of the two three-level diode mid-point clamped inverter circuit units in the common AC / DC bus staggered parallel output unit are turned on at the same time.

[0015] The beneficial effects of the present invention are as follows: the present invention hybridly connects two three-level diode clamped inverter units through a common AC / DC bus staggered parallel structure, divides different frequency harmonic combinations into two output paths, reduces the requirements for DC side voltage, and effectively improves the DC voltage measurement utilization rate; further, the harmonic combination algorithm module analyzes the optimal combination of two paths with lower peak voltages when different harmonics are superimposed, and on the basis of the two-path output, ensures that the output result of each path is optimal, which can further improve the DC side voltage utilization rate, reduce the DC side voltage, reduce the number of DC side capacitors, reduce the manufacturing cost of the equipment, improve the power density of the entire converter, and improve the working reliability of the equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a circuit structure diagram of a multi-level APF harmonic combination module of the present invention with common AC and DC bus staggered parallel connection;

[0017] Figure 2 This is a schematic diagram of the waveform of the sum of the inductance and the grid voltage during the traditional APF inverter output;

[0018] Figure 3 It is a schematic diagram of the inductance and grid voltage waveform when the APF inverter output of the present invention is adopted;

[0019] Figure 4 yes Figure 2 and Figure 3 Waveform comparison diagram. DETAILED DESCRIPTION

[0020] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present invention.

[0021] See also Figure 1 , the embodiment of the present invention includes:

[0022] A common AC / DC bus staggered parallel multi-level APF harmonic combination module mainly comprises a harmonic combination algorithm module, a PWM module, a DC side capacitor, and a common AC / DC bus staggered parallel output unit.

[0023] The common AC-DC bus staggered parallel output unit is composed of two three-level diode midpoint clamped inverter circuit units staggered in parallel. The three-level diode midpoint clamped inverter circuit unit includes an input terminal connected to a DC side capacitor, an A, B, C three-phase output terminal connected to a power grid, a plurality of switch tube circuits, and a diode clamping circuit. The diode clamping circuit is connected in parallel to the same bridge arm of the same three-level diode midpoint clamped inverter circuit unit and is located between two adjacent switch tube circuits on both sides of the midpoint. The DC side capacitor is connected to the three-level diode midpoint clamped inverter circuit unit to provide a DC voltage for it. The output of the harmonic combination algorithm module is used as a PWM module modulation wave, and the output of the PWM module controls the output of the common AC-DC bus staggered parallel output unit.

[0024] This module calculates the harmonic combination of the two outputs through the harmonic combination algorithm module. The output of the harmonic combination algorithm module is used as the modulation wave of the PWM module. The output of the PWM module is used as the control signal of the switch tube circuit to control the switching of the switch tube.

[0025] The embodiment of the present invention further provides a harmonic combination algorithm of a multi-level APF with common AC / DC bus staggered parallel connection, comprising the following steps:

[0026] S1: Sample all the three-phase harmonics to be compensated, and then integrate all the three-phase harmonic currents to be compensated Get the parameters of the corresponding voltage on the DC side;

[0027] S2: By dividing the low-order harmonics into two groups and combining them, all possible combinations and sums of all harmonics to be compensated are obtained. N is the highest harmonic to be compensated;

[0028] S3: Combine all possible harmonic peak values ​​and v in step S2 aveCompare them pairwise and select the one with the smallest peak value as the best combination as the PWM module modulation wave.

[0029] When the PWM module is modulating, the same bridge arm Q1 (Q2) and Q3 (Q4) tubes of the same three-level diode midpoint clamped inverter circuit unit are complementary turned on, the conduction angles of the three-phase bridge arms of the same three-level diode midpoint clamped inverter circuit unit differ by 120°, and the switch tube circuits at corresponding positions of the two three-level diode midpoint clamped inverter circuit units in the common AC / DC bus staggered parallel output unit are turned on at the same time.

[0030] Take the 3rd, 5th, and 7th harmonics of phase A as an example, and the other two phases are the same to illustrate the specific steps of this algorithm:

[0031] S1: The harmonic current i a3 、i a5 、i a7 integral Get v a3 、v a5 、v a7 Three voltage parameters;

[0032] S2: The harmonic combination algorithm module divides the low-order harmonics into two groups and combines them to obtain all possible combinations of harmonic combinations (v a3 +v a5 and v a7 、v a3 +v a7 and v a5 、v a3 and v a5 +v a7 Three combinations) and v aave =(v a3 +v a5 +v a7 ) / 2;

[0033] S3: v a3 +v a5 and v a7 The larger peak value of the two is selected and recorded as v amax1 、v a3 +v a7 and v a5 The larger peak value of the two is selected and recorded as v amax2 、v a3 and v a5 +v a7 The larger peak value of the two is selected and recorded as v amax3 , select v amax1 、v amax2 、v amax3 、v aaveThe one with the smallest peak value is the best combination and is used as the modulation wave of the PWM module.

[0034] Combination Figures 2 to 4 , Figure 2 This is a waveform diagram of the sum of the inductance and the grid voltage during traditional APF inverter output. Figure 3 This is a schematic diagram of the inductance and grid voltage waveforms when the APF inverter output is used according to the present invention. Figure 4 The two curves are compared in FIG. 1 , where the black line is the traditional APF inverter output waveform, and the gray line is the APF inverter output waveform described in the present invention. The output peak value after the algorithm is used is significantly lower than the traditional APF inverter output peak value.

[0035] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A harmonic combination algorithm of multi-level APF with common AC / DC bus staggered parallel connection, characterized in that: A multi-level APF harmonic combination module with common AC / DC bus staggered parallel connection is adopted, which mainly includes a harmonic combination algorithm module, a PWM module, a DC side capacitor, and a common AC / DC bus staggered parallel connection output unit; The common AC / DC busbar interleaved parallel output unit is composed of two three-level diode midpoint clamped inverter circuit units interleaved in parallel; The DC side capacitor is connected to a three-level diode midpoint clamped inverter circuit unit to provide a DC voltage therefor; The output of the harmonic combination algorithm module is used as a modulation wave of the PWM module, and the output of the PWM module controls the output of the common AC / DC bus staggered parallel output unit; The algorithm consists of the following steps: S1: Sample all the three-phase harmonics to be compensated, and then differentiate all the three-phase harmonic currents to be compensated , get the parameters of the corresponding voltage on the DC side; S2: By dividing the low-order harmonics into two groups and combining them, all possible combinations and sums of all harmonics to be compensated are obtained. , N is the highest harmonic to be compensated; S3: Combine all possible harmonic peak values ​​in step S2 and Compare them pairwise and select the one with the smallest peak value as the best combination as the PWM module modulation wave.

2. The harmonic combination algorithm of multi-level APF with common AC / DC bus staggered parallel connection according to claim 1 is characterized in that: When the PWM module is modulating, the same bridge arm Q1 and Q3 tubes of the same three-level diode midpoint clamped inverter circuit unit are complementary turned on, the same bridge arm Q2 and Q4 tubes of the same three-level diode midpoint clamped inverter circuit unit are complementary turned on, the conduction angles of the three-phase bridge arms of the same three-level diode midpoint clamped inverter circuit unit differ by 120°, and the switch tube circuits at corresponding positions of the two three-level diode midpoint clamped inverter circuit units in the common AC / DC bus staggered parallel output unit are turned on at the same time.

3. The harmonic combination algorithm of multi-level APF with common AC / DC bus staggered parallel connection according to claim 1 is characterized in that: The three-level diode midpoint clamped inverter circuit unit includes an input end connected to a DC side capacitor, an output end connected to a power grid, a plurality of switch tube circuits, and a diode clamping circuit. The diode clamping circuit is connected in parallel to the same bridge arm of the same three-level diode midpoint clamped inverter circuit unit and is located between two adjacent switch tube circuits on both sides of the midpoint.

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