Circuit including multi-bit flip-flop and method of operating the same

Abstract

A circuit including a multi-bit flip-flop, comprising: a multi-bit flip-flop; an integrated clock gating circuit connected to the multi-bit flip-flop; and a control circuit connected to the integrated clock gating circuit and the multi-bit flip-flop. The control circuit compares output data of the multi-bit flip-flop corresponding to input data with the input data. The control circuit generates an enable signal based on comparing the output data of the multi-bit flip-flop corresponding to the input data with the input data of the multi-bit flip-flop. The control circuit provides the enable signal to the integrated clock gating circuit, wherein the integrated clock gating circuit provides a clock signal to the multi-bit flip-flop based on the enable signal, thereby triggering the multi-bit flip-flop. Embodiments of the present invention also relate to a method for operating a multi-bit flip-flop.

Description

Technical Field

[0001] Embodiments of the present invention relate to circuits including multi-bit flip-flops and methods of operating the same. Background Art

[0002] A flip-flop is a circuit that has two stable states and can therefore be used as a bit of memory. A flip-flop is usually controlled by one or two control signals and a clock signal. Outputs usually include complements as well as normal outputs. A flip-flop can be simple (transparent) or timed (or non-transparent). Clock flip-flops are designed for synchronous (discrete-time) systems and are usually implemented as master-slave devices. Flip-flops can be further divided into the following types: RS ("set-reset"), D ("data" or "delay"), T ("toggle") and JK types are common types. A D flip-flop is called a delay flip-flop (because its output Q looks like a delay of the input D) or a data latch. The behavior of a particular type of flip-flop can be described by a so-called characteristic equation, which derives the "current state" output from the input signal and / or the "previous state" signal of the flip-flop. Summary of the invention

[0003] According to one aspect of an embodiment of the present invention, a circuit including a multi-bit trigger is provided, including: a multi-bit trigger; an integrated clock gating circuit connected to the multi-bit trigger; and a control circuit connected to the integrated clock gating circuit and the multi-bit trigger, wherein the control circuit is used to: compare output data of the multi-bit trigger corresponding to input data with the input data; generate an enable signal based on comparing the output data of the multi-bit trigger corresponding to the input data with the input data of the multi-bit trigger, and provide the enable signal to the integrated clock gating circuit, wherein the integrated clock gating circuit provides a clock signal to the multi-bit trigger based on the enable signal, thereby triggering the multi-bit trigger.

[0004] According to another aspect of an embodiment of the present invention, there is provided a circuit including a multi-bit flip-flop, including: a plurality of single-bit flip-flops; an integrated clock gating circuit, wherein an output terminal of the integrated clock gating circuit is connected to a clock input terminal of each of the plurality of single-bit flip-flops; a plurality of disambiguation logic circuits connected to the plurality of single-bit flip-flops, wherein each of the plurality of disambiguation logic circuits is used to determine logical disambiguation of input data and output data corresponding to the input data of a corresponding single-bit flip-flop of the plurality of single-bit flip-flops; and a separation circuit connected to the plurality of disambiguation logic circuits, wherein the separation circuit is used to: determine logical separation of a plurality of outputs of the plurality of disambiguation logic circuits, and provide an enable signal according to the logical separation.

[0005] According to another aspect of an embodiment of the present invention, a method for operating a multi-bit trigger is provided, comprising: providing input data to the multi-bit trigger; determining logical disambiguation of the input data and output data from the multi-bit trigger corresponding to the input data; determining logical separation of the input data and the output data of the multi-bit trigger corresponding to the input data for logical disambiguation; based on the logical separation, providing an enable signal to an integrated clock gating circuit connected to the multi-bit trigger; and generating a clock signal for the multi-bit trigger based on the enable signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a block diagram illustrating an example of a processing system according to some embodiments.

[0008] Figure 2 Depicted is an example of a D-type flip-flop with a shared clock terminal and one output in accordance with some embodiments.

[0009] Figure 3 Depicted is an example block diagram of a multi-bit flip-flop circuit in accordance with some embodiments.

[0010] Figure 4A Depicted are partial block diagrams and partial circuit diagrams of multi-bit flip-flop circuits in accordance with some embodiments.

[0011] Figure 4B A truth table of an XOR logic circuit of a multi-bit flip-flop circuit according to some embodiments is shown.

[0012] Figure 4C Depicted is a truth table for a separate circuit of a multi-bit flip-flop circuit in accordance with some embodiments.

[0013] Figure 5 is a block diagram illustrating an example of a multi-bit flip-flop composed of two single-bit flip-flop cells according to some embodiments.

[0014] Figure 6 is a flow chart illustrating an example method for operating a multi-bit flip-flop according to some embodiments. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0017] Electronic design automation (EDA) tools and methodologies facilitate the design, segmentation, and placement of microelectronic integrated circuits on semiconductor substrates. The process typically involves converting the behavioral description of the circuit into a functional description, which is then decomposed into logical functions and mapped into cells using a standard cell library. After mapping, synthesis is performed to convert the structural design into a physical layout, clock trees are built for synchronous structural elements, and the design is optimized after layout.

[0018] Figure 1 1 is a block diagram illustrating an example of a processing system 100 according to some embodiments disclosed herein. The processing system 100 can be used to perform methods for operating a multi-bit flip-flop according to various processes discussed herein. The processing system 100 includes a processing unit 110, such as a desktop computer, a workstation, a laptop computer, a dedicated unit customized for a specific application, a smart phone or a tablet computer, etc. The processing system 100 can be equipped with a display 114 and one or more I / O devices 112, such as a mouse, a keyboard, a touch screen, a printer, etc. The processing unit 110 also includes a central processing unit (CPU) 120, a memory 122, a mass storage device 124, and an I / O interface 128 connected to a bus 130 by a video adapter 126.

[0019] Bus 130 may be any one or more of several bus architectures, including a memory bus or memory controller, a peripheral bus, or a video bus. CPU 120 may include any type of electronic data processor, and memory 122 may include any type of system memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), or read-only memory (ROM).

[0020] Mass storage device 124 may include any type of storage device configured to store data, programs, and other information and make the data, programs, and other information accessible via bus 130. Mass storage device 124 may include, for example, one or more of a hard drive, a magnetic disk drive, an optical disk drive, flash memory, and the like.

[0021] The term "computer-readable medium" as used herein may include computer storage media, such as the system memory and storage devices described above. Computer storage media may include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, or program modules. Memory 122 and mass storage device 124 are examples of computer storage media (e.g., memory storage). Mass storage device 124 may further store a library of standard cells, as will be discussed further below.

[0022] Computer storage media may include RAM, RO, electrically erasable read-only memory (EEPROM), flash memory or other storage technology, CD-ROM, digital versatile disk (DVD) or other optical storage, magnetic tape, magnetic tape, magnetic disk storage devices or other magnetic storage devices, or any other article of manufacture that can be used to store information and can be accessed by processing device 100. Any such computer storage media may be part of processing device 100. Computer storage media does not include carrier waves or other propagated or modulated data signals.

[0023] Communication media may be embodied by computer readable instructions, data structures, program modules, or other data in a modulated data signal (e.g., a carrier wave or other transport mechanism), and communication media includes any information delivery media. The term "modulated data signal" may describe a signal that has one or more characteristics set or changed in such a way as to encode information in the signal. By way of example, and not limitation, communication media may include wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, radio frequency (RF), infrared, and other wireless media.

[0024] Video adapter 126 and I / O interface 128 may provide interfaces for coupling external input and output devices to processing unit 110. Figure 1As shown, examples of input and output devices include a display 114 coupled to a video adapter 126 and an I / O. I / O devices 112 such as a mouse, keyboard, printer, etc. are coupled to an I / O interface 128. Other devices may be coupled to the processing unit 110, and more or fewer interface cards may be utilized. For example, a serial interface card (not shown) may be used to provide a serial interface for a printer. The processing unit 110 may also include a network interface 140, which may be a wired link and / or a wireless link to a local area network (LAN) or wide area network (WAN) 116.

[0025] Embodiments of the processing system 100 may include other components. For example, the processing system 100 may include a power supply, cables, a motherboard, removable storage media, a housing, etc. These other components are not shown but are considered part of the processing system 100.

[0026] In some examples, the software code is executed by CPU 120 to operate the multi-bit flip-flops. CPU 120 may access the software code from memory 122, mass storage device 124, etc. via bus 130, or remotely through network interface 140. Additionally, in some examples, a physical integrated circuit layout may be created based on a functional integrated circuit design, which may be received and / or stored in memory 122 or 124 via I / O interface 128 according to various methods and processes implemented by the software code.

[0027] A standard cell may include an entire device, such as a transistor, diode, capacitor, resistor, or inductor, or may include a group of multiple devices arranged to implement a particular function, such as an inverter, flip-flop, memory cell, or amplifier. In addition to making functional designs easier to conceptualize, the use of standard cells may also reduce the verification time of design rule checking (DRC) of layout components within an IC, because standard cells repeated throughout the layout may be checked at once in the DRC, rather than each instance being checked individually. Based on the received functional circuit description, the system 100 is configured to select a standard cell from a cell library.

[0028] As mentioned above, a flip-flop circuit can be included in a standard cell library. A flip-flop is a circuit that has two stable states and can therefore be used as a bit of memory. A flip-flop is typically controlled by one or two control signals and a clock signal. Outputs typically include complements as well as normal outputs. A flip-flop can be simple (transparent) or timed (or non-transparent). Clock flip-flops are designed specifically for synchronous (time discrete) systems and are typically implemented as master-slave devices. Flip-flops can be further divided into the following types: RS ("set-reset"), D ("data" or "delay"), T ("toggle"), and JK types are common types. A D flip-flop is called a delay flip-flop (because its output Q looks like a delay of the input D) or a data latch. The behavior of a particular type of flip-flop can be described by a so-called characteristic equation, which derives the "current state" output from the input signal and / or the "previous state" signal of the flip-flop.

[0029] The D flip-flop captures the value of the D input at a certain part of the clock cycle (such as the rising edge of the clock). The captured value becomes the Q output. At other times, the output Q remains unchanged. The D flip-flop can be viewed as a memory cell, a zero-order hold, or a delay line.

[0030] Figure 2 An exemplary D-type flip-flop 200 according to aspects of the present disclosure is depicted. Figure 2 As shown, the trigger 200 includes a data input terminal 202 and a data output terminal 204. In addition, Figure 2 The flip-flop 200 includes a clock input terminal CK in 206. The flip-flop 200 captures a value, namely input data D provided at a determined portion of a clock cycle (such as a rising edge of the clock) on the data input terminal 202. The captured input data D becomes output data Q at the data output terminal 204. Sometimes, the output data Q does not change. In some examples, the flip-flop 200 can be viewed as a memory cell, a zero-order hold, or a delay line.

[0031] form Figure 2 The example of the flip-flop 200 has multiple single-bit flip-flops arranged to form a multi-bit flip-flop. The multi-bit flip-flop has multiple input terminals and output terminals (D and Q pins). For example, some two-bit multi-bit flip-flops may have two input terminals and two output terminals (D0, D1, Q0, Q1 pins) and a common clock, scan input, and scan enable pins. In a two-bit flip-flop, the scan input pin of the second-bit flip-flop is connected to the first-bit flip-flop Q pin (Q0), so they are in scan order. The layout of the multi-bit flip-flop can be designed in a compact manner so that the effective area of ​​the multi-bit flip-flop is less than the summed area of ​​the single-bit flip-flop.

[0032] Known multi-bit flip-flops can be used to save power by sharing local clock buffers between flip-flops, and power can be optimized by reducing clock triggering devices. The disclosed embodiments further save power by using multiple low clock pulses to trigger single-bit flip-flops and self-timed integrated clock gating (ICG) cells. In some examples, power is reduced by more than 30%.

[0033] Figure 3 is a block diagram of a multi-bit flip-flop circuit 300 according to some embodiments. Figure 3 As shown, the multi-bit flip-flop circuit 300 includes a multi-bit flip-flop 302, an integrated clock gating circuit 304, and a control circuit 306. The multi-bit flip-flop 302 is connected to the integrated clock gating circuit 304 and the control circuit 306. The control circuit 306 includes a disambiguation circuit 308 and a separation circuit 310. After reading this disclosure, it is obvious to a person skilled in the art that the components of the multi-bit flip-flop circuit 300 are relatively simple. Figure 3 More than what is described in .

[0034] like Figure 3 As shown, the multi-bit flip-flop 302 includes a data input terminal 312, a data output terminal 314, and a clock input terminal 316. The multi-bit flip-flop 302 captures input data D provided at the data input terminal 312 and provides the captured input data D as output data Q at the output terminal 314. The multi-bit flip-flop 302 receives a clock signal CLK at the clock input terminal 316 and is triggered in response to receiving the clock signal CLK. In some examples, the multi-bit flip-flop 302 includes a plurality of single-bit flip-flops arranged to form a multi-bit flip-flop 302 for temporarily storing a predetermined number of bits of data input. The multi-bit flip-flop 302 is connected to the control circuit 306.

[0035] The control circuit 306 includes a first input terminal 318 and a second input terminal 320. In some examples, the disambiguation circuit 308 of the control circuit 306 includes the first input terminal 318 and the second input terminal 320. The first input terminal 318 is connected to the input terminal 312 of the multi-bit flip-flop 302. The second input terminal 320 is connected to the output terminal 314 of the multi-bit flip-flop 302. In some examples, the control circuit 306 compares the input data with the output data of the multi-bit flip-flop 302 corresponding to the input data, and provides an enable signal EN according to the comparison result. The control circuit 306 provides the enable signal EN at the control circuit output terminal 326.

[0036] For example, the disambiguation circuit 308 of the control circuit 306 determines the logic disambiguation of the input data D of the multi-bit flip-flop 302 and the output data Q corresponding to the input data D. The disambiguation circuit 308 provides the result of the logic disambiguation determination at the disambiguation circuit output terminal 322 of the disambiguation circuit 308. The disambiguation circuit output terminal 322 is connected to the disambiguation circuit input terminal 324 of the separation circuit 310. Therefore, the result of the logic disambiguation determination of the input data D and the output data Q of the multi-bit flip-flop 302 corresponding to the input data D are provided to the separation circuit 310 as input data.

[0037] The separation circuit 310 determines a logical separation of a logical disambiguation result of the input data D and the output data Q of the multi-bit flip-flop 302 corresponding to the input data D. Based on the logical separation determination of the logical disambiguation result of the input data D and the output data Q of the multi-bit flip-flop 302 corresponding to the input data D, the separation circuit 310 generates an enable signal EN. The separation circuit 310 provides the enable signal EN as an output at a separation circuit output terminal 326 (also referred to as a control circuit output terminal 326).

[0038] The separation circuit output terminal 326 or the control circuit output terminal 326 is connected to a second input terminal 330 of the integrated clock gating circuit 304. The first input terminal 328 of the integrated clock gating circuit 304 is used to receive the clock pulse CP. The integrated clock gating circuit 304 generates a clock signal CLK at an integrated clock gating circuit output terminal 332.

[0039] In some examples, the integrated clock gating circuit 304 generates a clock signal CLK from the clock pulse CP based on the enable signal EN. For example, when the enable signal EN becomes logic high, the integrated clock gating circuit 304 generates the clock signal CLK. The clock signal CLK is provided to the integrated clock gating circuit output terminal 332, which is connected to the clock input terminal 316 of the multi-bit flip-flop 302. The clock signal CLK is provided to the multi-bit flip-flop 302 and triggers the multi-bit flip-flop 302.

[0040] Figure 4A 4 shows a partial block diagram and a partial circuit diagram of a multi-bit flip-flop circuit 400 according to some embodiments. Figure 4A As shown, the multi-bit flip-flop circuit 400 includes a plurality of single-bit flip-flops, for example, a first single-bit flip-flop 200(1), a second single-bit flip-flop 200(2), a third single-bit flip-flop 200(3), and a fourth single-bit flip-flop 200(4). In some examples, the plurality of single-bit flip-flops form a multi-bit flip-flop 302. Although Figure 4AThe multi-bit flip-flop circuit 400 is shown as including only four single-bit flip-flops, but it is obvious to a person of ordinary skill in the art after reading this disclosure that the multi-bit flip-flop circuit 400 may include a different number of single-bit flip-flops. For example, the multi-bit flip-flop circuit 400 may include two single-bit flip-flops, eight single-bit flip-flops, sixteen single-bit flip-flops, and so on.

[0041] In addition, the multi-bit flip-flop circuit 400 includes a plurality of exclusive OR (XOR) logic circuits, for example, a first XOR logic circuit 402(1), a second XOR logic circuit 402(2), a third XOR logic circuit 402(3), and a fourth XOR logic circuit 402(4). In some examples, the first XOR logic circuit 402(1), the second XOR logic circuit 402(2), the third XOR logic circuit 402(3), and the fourth XOR logic circuit 402(4) form the disambiguation circuit 304. One of the plurality of XOR logic circuits is associated with one of the plurality of single-bit flip-flops. For example, the first XOR logic circuit 402(1) is associated with the first single-bit flip-flop 200(1), the second XOR logic circuit 402(2) is associated with the second single-bit flip-flop 200(2), the third XOR logic circuit 402(3) is associated with the third single-bit flip-flop 200(3), and the fourth XOR logic circuit 402(4) is associated with the fourth single-bit flip-flop 200(4). Therefore, and in accordance with some embodiments, the multi-bit flip-flop circuit 400 includes an equal number or an equal number of multiple XOR logic circuits and multiple single-bit flip-flops.

[0042] The first single-bit flip-flop 200(1) includes a data input terminal 202(1), a data output terminal 204(1) and a clock input terminal 206(1). In addition, the first single-bit flip-flop 200(1) includes a scan input terminal 208(1). The data input terminal 202(1) of the first single-bit flip-flop 200(1) is used to receive the first input data D1. The clock input terminal 206(1) of the first single-bit flip-flop 200(1) is connected to the clock gating circuit output terminal 332 and is used to receive the clock signal CLK from the integrated clock gating circuit 304. The scan input terminal 208(1) of the first single-bit flip-flop 200(1) is used to receive the scan input signal SI.

[0043] The first single-bit flip-flop 200(1) is used to capture the first input data D1 received at the data input terminal 202(1) and provide the captured first input data D1 as the first output data Q1 at the data output terminal 204(1). The data output terminal 204(1) of the first single-bit flip-flop 200(1) is connected to the second input terminal 406(1) of the first XOR logic circuit 402(1). The first input terminal 404(1) of the first XOR logic circuit 402(1) is connected to the data input terminal 202(1) of the first single-bit flip-flop 200(1). Therefore, the first input terminal 404(1) of the first XOR logic circuit 402(1) receives the first input data D1 of the first single-bit flip-flop 200(1), and the second input terminal 406(1) of the first XOR logic circuit 402(1) receives the first output data Q1 of the first single-bit flip-flop 200(1) corresponding to the first input data D1.

[0044] The first XOR logic circuit 402(1) determines a logical disambiguation between a first input data D1 of the first single bit flip-flop 200(1) and a first output data Q1 of the first single bit flip-flop 200(1) corresponding to the first input data D1. The first XOR logic circuit 402(1) provides a first output data X1 which is a logical disambiguation between the first input data D1 of the first single bit flip-flop 200(1) and the first output data Q1 of the first single bit flip-flop 200(1) corresponding to the first input data D1 at the output terminal 408(1). According to some embodiments, Figure 4B An example truth table 450 is shown of example logical disambiguation of first input data D1 of the first single bit flip-flop 200 ( 1 ) and first output data Q1 of the first single bit flip-flop 200 ( 1 ) corresponding to the first input data D1 .

[0045] like Figure 4B As shown, the truth table 450 includes the first input data D1 of the first single-bit flip-flop 200(1), the first output data Q1 of the first single-bit flip-flop 200(1) corresponding to the first input data D1, and the first output data X1 of the first XOR logic circuit 402(1). In some examples, the first output data X1 of the first XOR logic circuit 402(1) depends on the first input data D1 of the first single-bit flip-flop 200(1) and the first output data Q1 of the first single-bit flip-flop 200(1) corresponding to the first input data D1. For example, when the first input data D1 of the first single-bit flip-flop 200(1) is logic zero (0) and the first output data Q1 of the first single-bit flip-flop 200(1) corresponding to the first input data D1 is logic 0, the first output data X1 of the first XOR logic circuit 402(1) is logic 0.

[0046] As another example, when the first input data D1 of the first single bit flip-flop 200(1) is logic 0 and the first output data Q1 of the first single bit flip-flop 200(1) corresponding to the first input data D1 is logic one(1), then the first output data X1 is logic 1. As yet another example, when the first input data D1 of the first single bit flip-flop 200(1) is logic 1 and the first output data Q1 of the first single bit flip-flop 200(1) corresponding to the first input data D1 is logic 0, then the first output data X1 of the first XOR logic circuit 402(1) is logic 1. As yet another example, when the first input data D1 of the first single bit flip-flop 200(1) is logic 1 and the first output data Q1 of the first single bit flip-flop 200(1) corresponding to the first input data D1 is logic 1, then the first output data X1 of the first XOR logic circuit 402(1) is logic 0. Therefore, when the first output data Q1 of the first single bit flip-flop 200(1) corresponding to the first input data D1 is different from the first input data D1, the first XOR logic circuit 402(1) provides the first output data X1 of logic 1. In addition, when the first output data Q1 of the first single bit flip-flop 200(1) corresponding to the first input data D1 is the same as the first input data D1, the first XOR logic circuit 402(1) provides the first output data X1 of logic 0.

[0047] return Figure 4A , the second single-bit flip-flop 200(2) includes a data input terminal 202(2), a data output terminal 204(2) and a clock input terminal 206(2). In addition, the second single-bit flip-flop 200(2) includes a scan input terminal 208(2). The data input terminal 202(2) of the second single-bit flip-flop 200(2) is used to receive the second input data D2. The clock input terminal 206(2) of the second single-bit flip-flop 200(2) is connected to the clock gating circuit output terminal 332 and is used to receive the clock signal CLK from the integrated clock gating circuit 304. The scan input terminal 208(2) of the second single-bit flip-flop 200(2) is connected to the output terminal 204(1) of the first single-bit flip-flop 200(1) and is used to receive the first output data Q1 of the first single-bit flip-flop 200(1).

[0048] The second single-bit flip-flop 200(2) is used to capture the second input data D2 received at the data input terminal 202(2) and provide the captured second input data D2 as the second output data Q2 at the data output terminal 204(2). The data output terminal 204(2) of the second single-bit flip-flop 200(2) is connected to the second input terminal 406(2) of the second XOR logic circuit 402(2). The first input terminal 404(2) of the second XOR logic circuit 402(2) is connected to the data input terminal 202(2) of the second single-bit flip-flop 200(2). Therefore, the first input terminal 404(2) of the second XOR logic circuit 402(2) receives the second input data D2 of the second single-bit flip-flop 200(2), and the second input terminal 406(2) of the second XOR logic circuit 402(2) receives the second output data Q2 of the second single-bit flip-flop 200(2) corresponding to the second input data D2.

[0049] The second XOR logic circuit 402(2) determines a logical disambiguation between the second input data D2 of the second single bit flip-flop 200(2) and the second output data Q2 of the second single bit flip-flop 200(2) corresponding to the second input data D2. The second XOR logic circuit 402(2) provides a second output data X2, which is a logical disambiguation between the second input data D2 of the second single bit flip-flop 200(2) and the second output data Q2 of the second single bit flip-flop 200(2) corresponding to the second input data D2 at the output terminal 408(2). In the example, when the second output data Q2 of the second single bit flip-flop 200(2) corresponding to the second input data D2 is different from the second input data D2, the second XOR logic circuit 402(2) provides the second output data X2 of logic 1. In addition, when the second output data Q2 of the second single bit flip-flop 200(2) corresponding to the second input data D2 is the same as the second input data D2, the second XOR logic circuit 402(2) provides the second output data X2 of logic 0.

[0050] continue Figure 4A, the third single-bit flip-flop 200(3) includes a data input terminal 202(3), a data output terminal 204(3) and a clock input terminal 206(3). In addition, the third single-bit flip-flop 200(3) includes a scan input terminal 208(3). The data input terminal 202(3) of the third single-bit flip-flop 200(3) is used to receive the third input data D3. The clock input terminal 206(3) of the third single-bit flip-flop 200(3) is connected to the clock gating circuit output terminal 332 and is used to receive the clock signal from the clock gating circuit 304. The scan input terminal 208(3) of the third single-bit flip-flop 200(3) is connected to the output terminal 204(2) of the second single-bit flip-flop 200(2) and is used to receive the second output data Q2 of the second single-bit flip-flop 200(2).

[0051] The third single-bit flip-flop 200(3) is used to capture the third input data D3 received at the data input terminal 202(3) and provide the captured third input data D3 as the third output data Q3 at the data output terminal 204(3). The data output terminal 204(3) of the third single-bit flip-flop 200(3) is connected to the second input terminal 406(3) of the third XOR logic circuit 402(3). The first input terminal 404(3) of the third XOR logic circuit 402(3) is connected to the data input terminal 202(3) of the third single-bit flip-flop 200(3). Therefore, the first input terminal 404(3) of the third XOR logic circuit 402(3) receives the third input data D3 of the third single-bit flip-flop 200(3), and the second input terminal 406(3) of the third XOR logic circuit 402(3) receives the third output data Q3 of the third single-bit flip-flop 200(3) corresponding to the third input data D3.

[0052] The third XOR logic circuit 402(3) determines the logic disambiguation of the third input data D3 of the third single bit flip-flop 200(3) and the third output data Q3 of the third single bit flip-flop 200(3) corresponding to the third input data D3. The third XOR logic circuit 402(3) provides the third output data X3, which is the logic disambiguation of the third input data D3 of the third single bit flip-flop 200(3) and the third output data Q3 of the third single bit flip-flop 200(3) corresponding to the third input data D3 at the output terminal 408(3). In the example, when the third output data Q3 of the third single bit flip-flop 200(3) corresponding to the third input data D3 is different from the third input data D3, the third XOR logic circuit 402(3) provides the third output data X3 of logic 1. In addition, when the third output data Q3 of the third single bit flip-flop 200(3) corresponding to the third input data D3 is the same as the third input data D3, the third XOR logic circuit 402(3) provides the third output data X3 of logic 0.

[0053] Still continue Figure 4A , the fourth single-bit flip-flop 200(4) includes a data input terminal 202(4), a data output terminal 204(4) and a clock input terminal 206(4). In addition, the fourth single-bit flip-flop 200(4) includes a scan input terminal 208(4). The data input terminal 202(4) of the fourth single-bit flip-flop 200(4) is used to receive fourth input data D4. The clock input terminal 206(4) of the fourth single-bit flip-flop 200(4) is connected to the clock gating circuit output terminal 332 and is used to receive the clock signal from the clock gating circuit 304. The scan input terminal 208(4) of the fourth single-bit flip-flop 200(4) is connected to the output terminal 204(3) of the third single-bit flip-flop 200(3) and is used to receive the third output data Q3 of the third single-bit flip-flop 200(3).

[0054] The fourth single-bit flip-flop 200(4) is used to capture the fourth input data D4 received at the data input terminal 202(4) and provide the captured fourth input data D4 as the fourth output data Q4 at the data output terminal 204(4). The data output terminal 204(4) of the fourth single-bit flip-flop 200(4) is connected to the second input terminal 406(4) of the fourth XOR logic circuit 402(4). The first input terminal 404(4) of the fourth XOR logic circuit 402(4) is connected to the data input terminal 202(4) of the fourth single-bit flip-flop 200(4). Therefore, the first input terminal 404(4) of the fourth XOR logic circuit 402(4) receives the fourth input data D4 of the fourth single-bit flip-flop 200(4), and the second input terminal 406(4) of the fourth XOR logic circuit 402(4) receives the fourth output data Q4 of the fourth single-bit flip-flop 200(4) corresponding to the fourth input data D4.

[0055] The fourth XOR logic circuit 402(4) determines a logical disambiguation between the fourth input data D4 of the fourth single-bit flip-flop 200(4) and the fourth output data Q4 corresponding to the fourth input data D4 and the fourth single-bit flip-flop 200(4). The fourth XOR logic circuit 402(4) provides a fourth output data X4, which is a logical disambiguation between the fourth input data D4 of the fourth single-bit flip-flop 200(4) and the fourth output data Q4 of the fourth single-bit flip-flop 200(4) corresponding to the fourth input data D4 at the output terminal 408(4). In the example, when the fourth output data Q4 of the fourth single-bit flip-flop 200(4) corresponding to the fourth input data D4 is different from the fourth input data D4, the fourth XOR logic circuit 402(4) provides the fourth output data X4 of logic 1. Furthermore, when the fourth output data Q4 of the fourth single-bit flip-flop 200 ( 4 ) corresponding to the fourth input data D4 is identical to the fourth input data D4 , the fourth XOR logic circuit 402 ( 4 ) provides fourth output data X4 of logic 0.

[0056] The first output data X1 of the first XOR logic circuit 402(1), the second output data X2 of the second XOR logic circuit 402(2), the third output data X3 of the third XOR logic circuit 402(3), and the fourth output data X4 of the fourth XOR logic circuit 402(4) are provided to the separation circuit 310 of the multi-bit flip-flop circuit 400. For example, the output terminal 408(1) of the first XOR logic circuit 402(1) is connected to one of the plurality of input terminals of the separation circuit 310. In addition, the output terminal 408(2) of the second XOR logic circuit 402(2) is connected to another of the plurality of input terminals of the separation circuit 310. In addition, the output terminal 408(3) of the third XOR logic circuit 402(3) is connected to another of the plurality of input terminals of the separation circuit 310. In addition, the output terminal 408(4) of the fourth XOR logic circuit 402(4) is connected to another of the plurality of input terminals of the separation circuit 310.

[0057] Separation circuit 310 determines logical separation of first output data X1 of first XOR logic circuit 402(1), second output data X2 of second XOR logic circuit 402(2), third output data X3 of third XOR logic circuit 402(3), and fourth output data X4 of fourth XOR logic circuit 402(4) received at a plurality of input terminals of separation circuit 310, and generates enable signal EN based on the logical separation. In some examples, separation circuit 310 is an OR logic circuit. Figure 4C A truth table 460 showing the logical separation of the first output data X1 of the first XOR logic circuit 402(1), the second output data X2 of the second XOR logic circuit 402(2), the third output data X3 of the third XOR logic circuit 402(3), and the fourth output data X4 of the fourth XOR logic circuit 402(4) received at the plurality of input terminals of the separation circuit 310.

[0058] like Figure 4CAs shown, truth table 460 includes columns for first output data X1 of first XOR logic circuit 402(1), second output data X2 of second XOR logic circuit 402(2), third output data X3 of third XOR logic circuit 402(3), fourth output data X4 of fourth XOR logic circuit 402(4), and enable signal EN. In some examples, the logic value of enable signal EN depends on first output data X1 of first XOR logic circuit 402(1), second output data X2 of second XOR logic circuit 402(2), third output data X3 of third XOR logic circuit 402(3), and fourth output data X4 of fourth XOR logic circuit 402(4). For example, when the first output data X1 of the first XOR logic circuit 402(1) is logic 0 or 1 (indicated as don't care), the second output data X2 of the second XOR logic circuit 402(2) is logic 0 or 1, the third output data X3 of the third XOR logic circuit 402(3) is logic 0 or 1, and the fourth output data X4 of the fourth XOR logic circuit 402(4) is logic 1, the logic value of the enable signal EN is logic 1.

[0059] As another example, when the first output data X1 of the first XOR logic circuit 402(1) is logic 0 or 1, the second output data X2 of the second XOR logic circuit 402(2) is logic 0 or 1, the third output data X3 of the third XOR logic circuit 402(3) is logic 1, and the fourth output data X4 of the fourth XOR logic circuit 402(4) is logic 0 or 1, the logic value of the enable signal EN is logic 1. As yet another example, when the first output data X1 of the first XOR logic circuit 402(1) is logic 0 or 1, the second output data X2 of the second XOR logic circuit 402(2) is logic 1, the third output data X3 of the third XOR logic circuit 402(3) is logic 0 or 1, and the fourth output data X4 of the fourth XOR logic circuit 402(4) is logic 0 or 1, the logic value of the enable signal EN is logic 1.

[0060] As another example, when the first output data X1 of the first XOR logic circuit 402(1) is logic 1, the second output data X2 of the second XOR logic circuit 402(2) is logic 0 or 1, the third output data X3 of the third XOR logic circuit 402(3) is logic 0 or 1, and the fourth output data X4 of the fourth XOR logic circuit 402(4) is logic 0 or 1, the logic value of the enable signal EN is logic 1. As another example, when the first output data X1 of the first XOR logic circuit 402(1) is logic 0, the second output data X2 of the second XOR logic circuit 402(2) is logic 0, the third output data X3 of the third XOR logic circuit 402(3) is logic 0, and the fourth output data X4 of the fourth XOR logic circuit 402(4) is logic 0, the logic value of the enable signal EN is logic 0.

[0061] Therefore, when any of the first output data X1 of the first XOR logic circuit 402(1), the second output data X2 of the second XOR logic circuit 402(2), the third output data X3 of the third XOR logic circuit 402(3), or the fourth output data X4 of the fourth XOR logic circuit 402(4) is logic 1, the logic value of the enable signal EN is logic 1. That is, when the output data Q1 for any of the first single-bit flip-flop 200(1), the second single-bit flip-flop 200(2), the third single-bit flip-flop 200(3), and the fourth single-bit flip-flop 200(4) is different from the corresponding input data D, the enable signal EN is logic 1.

[0062] The enable signal EN is provided at the separation circuit output terminal 326, which is connected to the second input terminal 330 of the integrated clock gating circuit 304. Therefore, the enable signal EN is provided to the integrated clock gating circuit 304. The clock gating circuit 304 generates a clock signal at the integrated clock gating circuit output terminal 332. For example, when the logic value of the enable signal EN is logic 1, the integrated clock gating circuit 304 provides the clock signal. As previously described, when the output data of one of the plurality of single-bit flip-flops of the multi-bit flip-flop circuit 400 is different from the input data of one of the plurality of single-bit flip-flops from which the output data is captured, the logic value of the enable signal EN is logic 1.

[0063] Figure 55 is a graph 500 showing signals of one of the multiple single-bit flip-flops of the multi-bit flip-flop 400 according to some embodiments. For example, a first graph 502 of the graph 500 represents a clock pulse CP of the integrated clock gating circuit 304 of the multi-bit flip-flop 400. A second graph 504 of the graph 500 represents input data D of one of the multiple single-bit flip-flops of the multi-bit flip-flop 400. A third graph 506 of the graph 500 represents output data Q of one of the multiple single-bit flip-flops of the multi-bit flip-flop 400. A fourth graph 408 represents an enable signal EN.

[0064] As shown at the first mark 510, when the input data D and the output data Q are both at the same logic value (i.e., logic 0), the enable signal EN is also at logic 0. However, as shown at the second mark 512, when the input data D rises to logic 1 and the output data Q remains at logic 0, the enable signal EN rises to logic 1. In addition, as shown at the third mark 514, when the input data D and the output data Q both rise to logic 1, the enable signal EN falls to logic zero.

[0065] Therefore, and according to an example embodiment, the integrated clock gating circuit generates a clock signal to trigger the multi-bit flip-flop 302 only when the output data of the multi-bit flip-flop 302 corresponding to the input data is different from the input data. This can minimize the clock pulse CP and reduce the clock tree power. In addition, the disclosed process results in less triggering of the multi-bit flip-flop 302, thereby saving power. For example, the disclosed process results in a power saving of approximately 30.4% at 10% data activity (i.e., triggering) and a power saving of approximately 64.3% at 0% data activity.

[0066] Figure 6 6 is a flow chart of a method 600 for operating a multi-bit flip-flop according to some embodiments. In some examples, the method 600 is performed by the processing system 100. In other embodiments, the method 600 is stored as instructions on a non-transitory computer-readable medium, and when the non-transitory computer-readable medium is executed by the processing unit 110, the method 600 is performed.

[0067] At block 610 of method 600, input data is provided to the multi-bit flip-flop. For example, the input data is provided at input terminal 312 of multi-bit flip-flop 302. Multi-bit flip-flop 302 is used to capture the input data and provide output data at output terminal 314. In some examples, the data input may include two bits, four bits, eight bits, etc. In some examples, the input data and the output data corresponding to the input data of multi-bit flip-flop 302 are both provided to disambiguation circuit 308.

[0068] At block 620 of method 600, a logical disambiguation of input data and output data corresponding to the input data provided to the multi-bit flip-flop is determined. For example, disambiguation circuit 308 of multi-bit flip-flop circuit 300 determines a logical disambiguation of input data and output data corresponding to the input data provided to multi-bit flip-flop 302. The logical disambiguation of the input data and output data corresponding to the input data provided to the multi-bit flip-flop 302 is provided to separation circuit 310.

[0069] At block 630 of method 600, a logical separation of the input data and the output data corresponding to the input data provided to the multi-bit flip-flop is determined. For example, separation circuit 310 of multi-bit flip-flop circuit 300 determines a logical separation of the input data and the output data corresponding to the input data provided to the multi-bit flip-flop 302 for logical disambiguation.

[0070] At block 640 of method 600, an enable signal is provided to an integrated clock gating circuit connected to the multi-bit flip-flop based on the logical separation. For example, the enable signal EN is provided to the integrated clock gating circuit 304 connected to the multi-bit flip-flop 302. The enable signal EN is generated based on a logical separation of the input data and the logical disambiguation of the output data corresponding to the input data provided to the multi-bit flip-flop 302.

[0071] At block 650 of method 600, a clock signal for the multi-bit flip-flop is generated based on the enable signal. For example, the integrated clock gating circuit 304 generates the clock signal based on the enable signal EN from the clock pulse CP. In some examples, the clock signal is provided to the multi-bit flip-flop 302 by the integrated clock gating circuit 304. At block 660 of method 600, the multi-bit flip-flop is triggered in response to the clock signal. For example, when the clock signal rises to a logic high (i.e., a logic 1), the multi-bit flip-flop 302 is triggered.

[0072] According to an example embodiment, a circuit includes: a multi-bit flip-flop; an integrated clock gating circuit connected to the multi-bit flip-flop; and a control circuit connected to the integrated clock gating circuit and the multi-bit flip-flop, wherein the control circuit is used to: compare output data of the multi-bit flip-flop corresponding to input data with the input data; generate an enable signal based on comparing the output data of the multi-bit flip-flop corresponding to the input data with the input data of the multi-bit flip-flop, and provide the enable signal to the integrated clock gating circuit, wherein the integrated clock gating circuit provides a clock signal to the multi-bit flip-flop based on the enable signal, thereby triggering the multi-bit flip-flop.

[0073] In the above circuit, the control circuit includes a disambiguation circuit and a separation circuit.

[0074] In the above circuit, the multi-bit flip-flop includes a plurality of single-bit flip-flops arranged to form the multi-bit flip-flop, wherein the disambiguation circuit includes a plurality of XOR logic circuits, and wherein each of the plurality of XOR logic circuits is associated with one of the plurality of single-bit flip-flops.

[0075] In the above circuit, each of the multiple XOR logic circuits is used to: compare the input data of the associated single-bit trigger of the multiple single-bit triggers with the output data of the associated single-bit trigger corresponding to the input data; and provide an output, which includes the logical disambiguation of the input data of the associated single-bit trigger and the output data of the associated single-bit trigger corresponding to the input data.

[0076] In the above circuit, logical disambiguation of input data of the associated single bit flip-flop and input data of the associated single bit flip-flop corresponding to input data of each of a plurality of XOR logic circuits is provided as an input of the separation circuit.

[0077] In the above circuit, the separation circuit is used to: determine the logical separation of the logical disambiguation of the input data of the relevant single-bit flip-flop and the output data of the relevant single-bit flip-flop corresponding to the input data of multiple XOR logic circuits, and generate an enable signal according to the logical separation.

[0078] In the above circuit, the multi-bit flip-flop includes a plurality of single-bit flip-flops arranged to form the multi-bit flip-flop, and wherein the output of the integrated clock gating circuit is connected to a clock input terminal of each of the plurality of single-bit flip-flops.

[0079] In the above circuit, the multi-bit flip-flop includes eight single-bit flip-flops.

[0080] In an exemplary embodiment, a circuit includes: a plurality of single-bit flip-flops; an integrated clock gating circuit, wherein an output terminal of the integrated clock gating circuit is connected to a clock input terminal of each of the plurality of single-bit flip-flops; a plurality of disambiguation logic circuits connected to the plurality of single-bit flip-flops, wherein each of the plurality of disambiguation logic circuits is used to determine logical disambiguation of input data and output data corresponding to the input data of a corresponding single-bit flip-flop of the plurality of single-bit flip-flops; and a separation circuit connected to the plurality of disambiguation logic circuits, wherein the separation circuit is used to: determine logical separation of a plurality of outputs of the plurality of disambiguation logic circuits, and provide an enable signal based on the logical separation.

[0081] In the above circuit, each of the plurality of single-bit flip-flops includes a data input terminal, a data output terminal, and a clock input terminal.

[0082] In the above circuit, each of the plurality of disambiguation logic circuits includes a first input terminal, a second input terminal, and an output terminal.

[0083] In the above circuit, a sub-first input terminal of each of the multiple disambiguation logic circuits is connected to a data input terminal of a corresponding single-bit trigger, wherein a second input terminal of each of the multiple disambiguation logic circuits is connected to a data output terminal of a corresponding single-bit trigger, and wherein an output terminal of each of the multiple disambiguation logic circuits is connected to an input terminal of a separation circuit.

[0084] In the above circuit, an enable signal is provided to the integrated clock gating circuit.

[0085] In the above circuit, the integrated clock gating circuit is used to generate a clock signal in response to an enable signal.

[0086] In the above circuit, a plurality of single-bit flip-flops are triggered in response to a clock signal.

[0087] According to an example embodiment, a method includes: providing input data to a multi-bit flip-flop; determining a logical disambiguation of the input data and output data from the multi-bit flip-flop corresponding to the input data; determining a logical separation of the logical disambiguation of the input data and the output data of the multi-bit flip-flop corresponding to the input data; based on the logical separation, providing an enable signal to an integrated clock gating circuit connected to the multi-bit flip-flop; and generating a clock signal for the multi-bit flip-flop based on the enable signal.

[0088] In the above method, providing the input data to the multi-bit flip-flop includes providing the input data to an input terminal of each of a plurality of single-bit flip-flops forming the multi-bit flip-flop.

[0089] In the above method, determining the logical disambiguation of input data and output data corresponding to the input data provided to a multi-bit flip-flop includes: determining the logical disambiguation of input data and output data from each of a plurality of single-bit flip-flops, wherein the output data from each of a plurality of single-bit flip-flops corresponds to the input data provided to each of the plurality of single-bit flip-flops.

[0090] The above method further includes: triggering a multi-bit trigger in response to a clock signal.

[0091] In the above method, it also includes: triggering the multi-bit flip-flop in response to the clock signal changing from the first logic value to the second logic value.

[0092] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. A circuit comprising a multi-bit flip-flop, comprising: Multi-bit flip-flops, including multiple single-bit flip-flops; an integrated clock gating circuit, comprising a data input terminal, an enable input terminal, and an output terminal, wherein the data input terminal of the integrated clock gating circuit receives a clock pulse, and the output terminal of the integrated clock gating circuit is directly connected to a clock input terminal of each single-bit flip-flop of the multi-bit flip-flop; and A control circuit, comprising a plurality of XOR logic circuits and an OR logic circuit, wherein the OR logic circuit comprises a plurality of input terminals and output terminals, wherein a first input terminal of each of the plurality of XOR logic circuits is connected to an input terminal of a related single-bit flip-flop of the plurality of single-bit flip-flops, and a second input terminal of each of the plurality of XOR logic circuits is connected to an output terminal of the related single-bit flip-flop, and an output terminal of each of the plurality of XOR logic circuits is connected to one of the plurality of input terminals of the OR logic circuit, and an output terminal of the OR logic circuit is connected to the enable input terminal of the integrated clock gating circuit, and wherein each of the plurality of OR logic circuits of the control circuit is used to: determining a logical separation of output data corresponding to input data of the associated single bit flip-flop from the input data; providing output data to one of the plurality of input terminals of the OR logic circuit in accordance with the logical separation of the output data from the input data; Wherein, the OR logic circuit is used for: generating an enable signal based on logical separation of the output data of each of the plurality of XOR logic circuits corresponding to the input data, wherein the OR logic circuit generates the enable signal according to the logical separation of the output data of each of the plurality of XOR logic circuits corresponding to the input data, comprising: when the output data corresponding to the input data of any one of the plurality of single-bit flip-flops is different from the input data, the OR logic circuit generates the enable signal having a first logic value, and providing the enable signal to the enable input terminal of the integrated clock gating circuit of the integrated clock gating circuit, wherein the integrated clock gating circuit is used to: generating a clock signal from the clock pulse received at the data input terminal of the integrated clock gating circuit when the enable signal having the first logic value is received at the enable input terminal of the integrated clock gating circuit, and The clock signal is directly provided to each single-bit flip-flop of the multi-bit flip-flops, thereby causing the multi-bit flip-flops to trigger.

2. The circuit according to claim 1, wherein The control circuit includes a disambiguation circuit and a separation circuit, wherein the disambiguation circuit includes the multiple XOR logic circuits and the separation circuit includes the OR logic circuit.

3. The circuit according to claim 2, wherein: Each of the plurality of XOR logic circuits is associated with one of the plurality of single-bit flip-flops.

4. The circuit according to claim 2, wherein: The plurality of XOR logic circuits include four XOR logic circuits.

5. The circuit according to claim 1, wherein: The first logic value comprises a logic one.

6. The circuit according to claim 1, wherein: The integrated clock gating circuit includes a D flip-flop.

7. The circuit according to claim 1, wherein: Each of the plurality of single-bit flip-flops includes a D flip-flop.

8. The circuit according to claim 1, wherein: The multi-bit flip-flops include eight single-bit flip-flops.

9. A circuit comprising a multi-bit flip-flop, comprising: Multiple single bit flip-flops; an integrated clock gating circuit, comprising a data input terminal, an enable input terminal, and an output terminal, wherein the data input terminal of the integrated clock gating circuit receives a clock pulse, and the output terminal of the integrated clock gating circuit is directly connected to a clock input terminal of each of the plurality of single-bit flip-flops; a plurality of disambiguation circuits, wherein each of the plurality of disambiguation circuits comprises a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of each of the plurality of disambiguation circuits is connected to an input terminal of an associated single-bit flip-flop of the plurality of single-bit flip-flops, the second input terminal of each of the plurality of disambiguation circuits is connected to an output terminal of the associated single-bit flip-flop, and wherein each of the plurality of disambiguation circuits is used to determine a logical disambiguation between input data of the associated single-bit flip-flop of the plurality of single-bit flip-flops and output data corresponding to the input data; and A separation circuit comprising a plurality of input terminals and an output terminal, wherein the output terminal of each of the plurality of disambiguation circuits is connected to one of the plurality of input terminals of the separation circuit, the output terminal of the separation circuit is connected to the enable input terminal, wherein the separation circuit is configured to: determining a logical separation of a plurality of outputs of the plurality of disambiguation circuits, generating an enable signal based on the logical separation of the plurality of outputs of the plurality of disambiguation circuits, wherein the separation circuit generating the enable signal based on the logical separation of the plurality of outputs of the plurality of disambiguation circuits comprises the separation circuit generating the enable signal having a first logic value when the output data corresponding to the input data of any one of the plurality of single-bit flip-flops is different from the input data, and The enable signal is provided to the enable input terminal of the integrated clock gating circuit, wherein the integrated clock gating circuit is used to generating a clock signal from the clock pulse received from the data input terminal and the enable signal having the first logic value received from the enable input terminal; A clock signal is provided to each of the plurality of single-bit flip-flops.

10. The circuit according to claim 9, wherein: Each of the plurality of single-bit flip-flops includes a D flip-flop.

11. The circuit according to claim 9, wherein: Each of the plurality of disambiguation circuits includes an exclusive-OR logic circuit.

12. The circuit according to claim 9, wherein: The first logic value comprises a logic one.

13. The circuit according to claim 9, wherein: The separation circuit includes an OR logic circuit.

14. The circuit according to claim 13, wherein: The integrated clock gating circuit is used to provide the clock signal to the plurality of single-bit flip-flops.

15. The circuit of claim 14, wherein: The plurality of single-bit flip-flops are triggered in response to the clock signal.

16. A method of operating a multi-bit flip-flop, comprising: providing input data to each of the plurality of single-bit flip-flops of the multi-bit flip-flop; determining, by one of a plurality of disambiguation circuits, a logical disambiguation of the input data and the output data corresponding to the input data of each of a plurality of single-bit flip-flops of the multi-bit flip-flops, wherein each of the plurality of disambiguation circuits comprises a first input terminal, a second input terminal and an output terminal, wherein the first input terminal of each of the plurality of disambiguation circuits is connected to an input terminal of a related single-bit flip-flop of the plurality of single-bit flip-flops, and the second input terminal of each of the plurality of disambiguation circuits is connected to an output terminal of the related single-bit flip-flop; determining a logical separation of the logical disambiguation of the input data and the output data corresponding to the input data of each of the plurality of single-bit flip-flops of the multi-bit flip-flops by a separation circuit, wherein the separation circuit comprises a plurality of input terminals and an output terminal, the output terminal of each of the plurality of disambiguation circuits being connected to one of the plurality of input terminals of the separation circuit; generating, by the separation circuit, an enable signal based on the logical separation of the input data of each of the plurality of single-bit flip-flops of the multi-bit flip-flops and the logical disambiguation of the output data corresponding to the input data, wherein generating the enable signal comprises generating the enable signal having a first logic value when the output data corresponding to the input data of any one of the plurality of single-bit flip-flops is different from the input data; providing the enable signal to an integrated clock gating circuit connected to the multi-bit flip-flop through the separation circuit, wherein the output terminal of the separation circuit is connected to an enable input terminal of the integrated clock gating circuit; and A clock signal for the multi-bit flip-flop is generated by the integrated clock gating circuit based on the enable signal received by the enable input terminal having the first logic value and a clock pulse received from a data input terminal of the integrated clock gating circuit.

17. The method according to claim 16, wherein: The separation circuit includes an OR logic circuit.

18. The method according to claim 16, wherein: Each of the plurality of disambiguation circuits includes an exclusive-OR logic circuit.

19. The method according to claim 16, further comprising: The multi-bit flip-flop is triggered in response to the clock signal.

20. The method of claim 16, further comprising: The multi-bit flip-flop is triggered in response to the clock signal changing from a first logic value to a second logic value.

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