Wiring structure and vertical memory device including the same

Abstract

A wiring structure includes first to third metal patterns on a substrate. The first metal pattern extends in a second direction and has a first width in a third direction. The second metal pattern extends in the third direction to intersect with the first metal pattern and has a second width in the second direction. The third metal pattern is connected to the first metal pattern and the second metal pattern at a region where the first metal pattern and the second metal pattern intersect each other, and has a substantially rectangular shape with a recess in each corner. The third metal pattern has a third width, which is defined as the minimum distance between opposite recesses in the recess in a fourth direction that is acutely angled with the second direction and the third direction, and the third width is less than or equal to the smaller of the first width and the second width.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2020-0006397 filed on January 17, 2020 in the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Aspects of the present disclosure relate to a wiring structure and a vertical memory device including the wiring structure. Background Art

[0004] The width of a portion of the metal wiring at an area where metal wirings extending in various directions intersecting each other at right angles meet may be greater than the width of other portions of the metal wiring, and the portion of the metal wiring may be discontinuous, so that the characteristics of the metal wiring may be degraded. Summary of the invention

[0005] Example embodiments provide a wiring structure having improved electrical characteristics.

[0006] Example embodiments provide a vertical memory device including a wiring structure having improved electrical characteristics.

[0007] According to some example embodiments, a wiring structure is provided. The wiring structure may include a first metal pattern, a second metal pattern, and a third metal pattern. The first metal pattern may be formed on a substrate. The first metal pattern may extend in a second direction parallel to an upper surface of the substrate, and may have a first width in a third direction, the third direction being parallel to the upper surface of the substrate and perpendicular to the second direction. The second metal pattern may extend in the third direction to intersect the first metal pattern, and have a second width in the second direction. The third metal pattern may be located on the substrate at a region where the first metal pattern and the second metal pattern intersect each other. The third metal pattern may be connected to the first metal pattern and the second metal pattern, and have a substantially rectangular shape in a plan view. The third metal pattern may have a recess in each of its corners. The third metal pattern may have a third width, which is defined as the minimum distance between the opposite recesses of the recess in a fourth direction, the fourth direction being parallel to the upper surface of the substrate and forming an acute angle with respect to each of the second direction and the third direction, and the third width may be less than or equal to the smaller of the first width and the second width. The first metal pattern may have a first boundary surface in a central portion thereof in the third direction. The first boundary surface may extend in a first direction perpendicular to the upper surface of the substrate. The third metal pattern may have a third boundary surface at a center portion thereof in the fourth direction. The third boundary surface may extend in the first direction. A bottom of the first boundary surface may be farther from the substrate than a bottom of the third boundary surface.

[0008] According to some example embodiments, a wiring structure is provided. The wiring structure may include a first metal pattern, a second metal pattern, a third metal pattern and an insulating spacer. The first metal pattern may be formed on a substrate. The first metal pattern may extend in a second direction parallel to an upper surface of the substrate and have a first width in a third direction, the third direction being parallel to the upper surface of the substrate and perpendicular to the second direction. The second metal pattern may extend in a third direction to intersect with the first metal pattern and have a second width in the second direction. The third metal pattern may be located on the substrate at a region where the first metal pattern and the second metal pattern intersect each other. The third metal pattern may be connected to the first metal pattern and the second metal pattern and have a substantially rectangular shape in a plan view. The insulating spacer may be located on the substrate. The insulating spacer may be located at a central portion of the third metal pattern in a plan view and may cover a sidewall of the third metal pattern. The third width, which is defined as the minimum distance between the vertex of the third metal pattern and the insulating spacer, may be less than or equal to the smaller of the first width and the second width.

[0009] According to some example embodiments, a wiring structure is provided. The wiring structure may include a first metal pattern, a second metal pattern, and a third metal pattern. The first metal pattern may be formed on a substrate. The first metal pattern may extend in a second direction parallel to the upper surface of the substrate and have a first width in a third direction, the third direction being parallel to the upper surface of the substrate and perpendicular to the second direction. The second metal pattern may extend in a third direction and have a first width in the second direction. The third metal pattern may be located at a region where an end of the first metal pattern meets an end of the second metal pattern. The third metal pattern may be connected to the first metal pattern and the second metal pattern and may have a substantially triangular shape. The second width defined as the minimum distance from the vertex of the third metal pattern to its opposite edge in a fourth direction may be equal to or less than the first width, the fourth direction being parallel to the upper surface of the substrate and forming an acute angle with respect to each of the second direction and the third direction. Each metal pattern may have a respective boundary surface at its central portion and may extend in a first direction perpendicular to the upper surface of the substrate. The bottom of the boundary surface of the first metal pattern and the second metal pattern may be further away from the substrate than the bottom of the boundary surface of the third metal pattern.

[0010] According to some example embodiments, a wiring structure is provided. The wiring structure may include a first metal pattern, a second metal pattern, and a third metal pattern. The first metal pattern may be located on a substrate. The first metal pattern may extend in a second direction parallel to the upper surface of the substrate and have a first width in a third direction, the third direction being parallel to the upper surface of the substrate and perpendicular to the second direction. The second metal pattern may extend in a third direction and have a first width in the second direction. The third metal pattern may be located at a region where an end of the first metal pattern meets an end of the second metal pattern in the third direction. The third metal pattern may be connected to the first metal pattern and the second metal pattern and have a substantially triangular shape including a concave portion in a plan view. The minimum width between the concave portion of the third metal pattern and another vertex thereof in a fourth direction may be equal to or less than the first width, the fourth direction being parallel to the upper surface of the substrate and forming an acute angle with respect to each of the second direction and the third direction. Each metal pattern may have a boundary surface at its central portion. Each boundary surface may extend in a first direction perpendicular to the upper surface of the substrate. The bottom of each of the boundary surfaces of the first metal pattern and the second metal pattern may be further away from the substrate than the bottom of the boundary surface of the third metal pattern.

[0011] According to some example embodiments, a wiring structure is provided. The wiring structure may include a first metal pattern, a second metal pattern, and a third metal pattern. The first metal pattern may be located on a substrate. The first metal pattern may extend in a second direction parallel to the upper surface of the substrate and have a first width in a third direction, the third direction being parallel to the upper surface of the substrate and perpendicular to the second direction. The second metal pattern may extend in a third direction and have a second width in the second direction. The third metal pattern may be located at an area where a central portion of the first metal pattern meets an end portion of the second metal pattern. The third metal pattern may be connected to the first metal pattern and the second metal pattern and have a substantially rectangular shape including a first side and a second side facing each other in the third direction. The second side of the rectangle may not contact the second metal pattern and may be recessed. The third width, which is defined as the minimum distance between the first side and the second side of the third metal pattern in the third direction, may be less than or equal to the smaller of the first width and the second width. Each metal pattern may have a boundary surface at its central portion, which may extend in a first direction perpendicular to the upper surface of the substrate. The bottom of each of the boundary surfaces of the first metal pattern and the second metal pattern may be farther away from the substrate than the bottom of the boundary surface of the third metal pattern.

[0012] According to some example embodiments, a wiring structure is provided. The wiring structure may include a first metal pattern, a second metal pattern, and a third metal pattern. The first metal pattern may be formed on a substrate. The first metal pattern may extend in a second direction parallel to the upper surface of the substrate and have a first width in a third direction, the third direction being parallel to the upper surface of the substrate and perpendicular to the second direction. The second metal pattern may extend in the third direction and have a second width in the second direction. The third metal pattern may be located at a region where the first metal pattern and the second metal pattern intersect or intersect each other. The third metal pattern may be connected to the first metal pattern and the second metal pattern. The minimum width between some parts of the third metal pattern in a fourth direction may be equal to or less than the first width, the fourth direction being parallel to the upper surface of the substrate and forming an acute angle with respect to each of the second direction and the third direction. The angle of the sidewall of the first metal pattern relative to the upper surface of the substrate and the angle of the sidewall of the second metal pattern relative to the upper surface of the substrate may be greater than the angle of the sidewall of the third metal pattern relative to the upper surface of the substrate.

[0013] According to some example embodiments, a vertical memory device is provided. The vertical memory device may include a transistor, a lower wiring structure, a second substrate, a gate electrode, a channel, and an upper wiring structure. The transistor may be formed on a first substrate. The lower wiring structure may be formed on the first substrate and may be electrically connected to the transistor. The second substrate may be formed on the transistor and the lower wiring structure. The gate electrodes may be spaced apart from each other in a first direction on the second substrate. The first direction may be perpendicular to the upper surface of the second substrate. Each of the channels may extend through the gate electrode in the first direction on the second substrate. The upper wiring structure may be formed on the gate electrode and may be electrically connected to the gate electrode. The lower wiring structure and / or the upper wiring structure may include a first metal pattern, a second metal pattern, and a third metal pattern. The first metal pattern may be formed on the first substrate. The first metal pattern may extend in a second direction parallel to the upper surface of the first substrate and have a first width in a third direction, the third direction being parallel to the upper surface of the first substrate and perpendicular to the second direction. The second metal pattern may extend in the third direction and have a second width in the second direction. The third metal pattern may be located at a region where the first metal pattern and the second metal pattern meet each other. The third metal pattern may be connected to the first metal pattern and the second metal pattern. The minimum width between some parts of the third metal pattern in a fourth direction may be equal to or less than the first width, the fourth direction being parallel to the upper surface of the substrate and forming an acute angle with respect to each of the second direction and the third direction. Each metal pattern may have a boundary surface at its center portion, the boundary surface extending perpendicularly to the upper surface of the substrate. The bottom of the boundary surface of the first metal pattern is farther away from the substrate than the bottom of the boundary surface of the third metal pattern.

[0014] A vertical memory device according to some example embodiments may include a wiring structure having no void or cut portion therein, and thus may have improved electrical characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figures 1 to 6 are plan views and cross-sectional views illustrating a method of forming a wiring structure according to some example embodiments.

[0016] Figures 7 to 9 are plan views and cross-sectional views illustrating a wiring structure according to some example embodiments.

[0017] Fig. 10A , Fig. 10B , Fig.11 and Fig.12 are plan views and cross-sectional views illustrating a wiring structure according to some example embodiments.

[0018] Fig.13A and Fig. 13B is a plan view illustrating a wiring structure according to some example embodiments.

[0019] Fig.14 , Fig.15A , Fig. 15B , Fig.16 , Fig.17A and Fig. 17B are plan views and cross-sectional views illustrating a wiring structure according to some example embodiments.

[0020] Fig.18 and Fig.19 is a cross-sectional view illustrating a vertical memory device according to some example embodiments.

[0021] Figures 20 to 32 is a cross-sectional view illustrating a method of manufacturing a vertical memory device according to some example embodiments. DETAILED DESCRIPTION

[0022] The wiring structure and the method for forming the same and the vertical memory device and the method for manufacturing the same according to some example embodiments will be described more fully below with reference to the accompanying drawings. It will be understood that although the terms "first", "second" and / or "third" may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section.

[0023] In the following description (not necessarily in the claims), a direction substantially perpendicular to the upper surface of the substrate may be defined as a first direction, and two directions substantially parallel to the upper surface of the substrate and intersecting each other may be defined as a second direction and a third direction, respectively. Two directions substantially parallel to the upper surface of the substrate and forming an acute angle with the second direction and the third direction, respectively, may be defined as a fourth direction and a fifth direction, respectively. In some example embodiments, the second direction and the third direction may be substantially perpendicular to each other, and the fourth direction and the fifth direction may each be at an angle of 45 degrees relative to the second direction and the third direction, respectively. The fourth direction and the fifth direction may be substantially perpendicular to each other.

[0024] Figures 1 to 6 1 is a plan view and a cross-sectional view showing a method of forming a wiring structure according to some example embodiments. Specifically, Figure 1 and Figure 4 It is a floor plan. Figure 2 , Figure 3 And 5. Figure 6 is along Figure 1 A cross-sectional view taken along line AA'. Figure 1 The first part of the line A-A' extends in the third direction, Figure 1 The second portion of line AA' extends in the fourth direction.

[0025] Reference Figure 1 and Figure 2 , the insulating interlayer 20 may be formed on the substrate 10 , and may be partially etched to form a first opening 32 , a second opening 33 , and a third opening 34 each exposing an upper surface of the substrate 10 .

[0026] In some example embodiments, the first opening 32 and the second opening 33 may extend in the second direction and the third direction, respectively, and the third opening 34 may be connected to the first opening 32 and the second opening 33 at the area where the first opening 32 and the second opening 33 meet or intersect each other. In some example embodiments, the portion of the insulating interlayer 20 adjacent to the third opening 34 may include a protruding portion 25 protruding toward the center of the third opening 34 in a plan view. That is, the third opening 34 may have a rectangular shape having a recess in each corner of the third opening 34. The recess may be referred to as a vertex portion herein. The recess or vertex portion of the third opening 34 may be defined by a concave curve, edge, or arc segment adjacent to the protruding portion 25 of the insulating interlayer 20. In some example embodiments, each recess may be defined by a concave curve, edge, or arc segment that may be an ellipse or a partial ellipse. Each concave curve, edge, or arc segment may start at a point adjacent to the first opening 32 and may extend to a point adjacent to the second opening 33. In some embodiments, the third opening 34 may have a cross shape, the arms of which are narrower at the center of the third opening 34 and flare wider at the periphery of the third opening 34. The periphery of the third opening 34 may be where the third opening 34 meets the first opening 32 and the second opening 33.

[0027] The first opening 32 may have a first width W1 in the third direction, the second opening 33 may have a first width W1 in the second direction, and the third opening 34 may have a second width W2 equal to or less than the first width W1. The second width W2 may be defined as a minimum distance between the protruding portions 25 of the insulating interlayer 20 facing each other in each of the fourth and fifth directions.

[0028] In some embodiments, the insulating interlayer 20 may not have the protruding portion 25, and the third opening 34 may have a rectangular shape (with rounded vertices in some example embodiments), a rectangular ellipse, and / or a superellipse in a plan view. In embodiments where the insulating interlayer 20 does not have a protruding portion, the width of the third opening 34 in the fourth direction and the fifth direction may be greater than the first width W1. On the other hand, in embodiments where the insulating interlayer 20 has a protruding portion 25, the width of the third opening 34 in the fourth direction and the fifth direction may be equal to or less than the first width W1. Hereinafter, only the case where the second width W2 is less than the first width W1 will be described.

[0029] In with Figure 1In some example embodiments different from the embodiment shown in , the first opening 32 and the second opening 33 may have different widths, and the width of the first opening 32 may be smaller or larger than the width of the second opening 33. The inventive concepts described herein are demonstrated in some example embodiments in which the widths of the first opening 32 and the second opening 33 are both larger than the second width W2. That is, although the width of the second opening 33 may be larger or smaller than the width of the first opening 32, each is larger than the second width W2 of the third opening 34.

[0030] In some example embodiments, a first angle θ1 of a sidewall of each of the first opening 32 and the second opening 33 (e.g., a sidewall of an opening having a relatively large width or first width W1) relative to the upper surface of the substrate 10 may be greater than a second angle θ2 of a sidewall of the third opening 34 (e.g., a sidewall of an opening having a relatively small width or second width W2) relative to the upper surface of the substrate 10. The first angle θ1 may be closer to a vertical angle than the second angle θ2. This may be because an etching gas used in an etching process for forming the first opening 32, the second opening 33, and the third opening 34 may be more easily provided to lower portions of the first opening 32 and the second opening 33 due to characteristics of the etching process.

[0031] Since each of the first opening 32, the second opening 33, and the third opening 34 has a sidewall that is not vertical but inclined relative to the upper surface of the substrate 10, the width of the lower portion of each of the first opening 32, the second opening 33, and the third opening 34 may be smaller than the width of the upper portion thereof. Here, the width of each of the first opening 32, the second opening 33, and the third opening 34 will be referred to as the width of the bottom thereof or a portion adjacent to the upper surface of the substrate 10. That is, the bottom of each of the first opening 32 and the second opening 33 may have a first width W1, and the bottom of the third opening 34 may have a second width W2.

[0032] The insulating interlayer 20 may include an oxide such as silicon oxide or a nitride such as silicon nitride.

[0033] In some example embodiments, each of the first opening 32, the second opening 33, and the third opening 34 may not necessarily expose the upper surface of the substrate 10, and may only partially extend through the insulating interlayer 20. In some example embodiments, each of the first opening 32, the second opening 33, and the third opening 34 may expose the upper surface of a structure that may be included in the insulating interlayer 20.

[0034] Reference Figure 3 , a metal layer 40 may be formed on the substrate 10 and the insulating interlayer 20 , which may fill the first opening 32 , the second opening 33 , and the third opening 34 .

[0035] The metal layer 40 may include, for example, tungsten, aluminum, copper, etc. The metal layer 40 may be formed by any process selected based on the material used to form the metal layer 40. For example, if the metal layer 40 includes tungsten, aluminum, etc., the metal layer 40 may be formed by a deposition process such as a chemical vapor deposition (CVD) process. As another example, if the metal layer 40 includes copper, the metal layer 40 may be formed by an electroplating (EP) process. Hereinafter, only some example embodiments in which the metal layer 40 includes tungsten, aluminum, etc. by a deposition process will be described.

[0036] Before forming the metal layer 40 on the bottom and sidewalls of the first opening 32, the second opening 33 and the third opening 34 and the upper surface of the insulating interlayer 20, a barrier layer (not shown) including a metal nitride (eg, titanium nitride, tantalum nitride, etc.) may also be formed thereon.

[0037] In some example embodiments, during the deposition process, the metal layer 40 may be gradually deposited into the first opening 32, the second opening 33, and the third opening 34, starting from the bottom and the sidewall thereof. Thus, a first boundary surface 52 (e.g., a seam extending in the first direction at the center of the first opening 32 in the third direction) may be formed, and a third boundary surface 54 (e.g., a seam extending in the first direction at the center of the third opening 34 in the third direction) may be formed. At the same time, a second boundary surface (not shown) (e.g., a seam extending in the first direction at the center of the second opening 33 in the third direction) may also be formed.

[0038] The boundary surface may not contact the substrate 10. In some example embodiments, a first height H1 of the bottom of the first boundary surface 52 or the second boundary surface in the first direction (i.e., a distance from the upper surface of the substrate 10 to the bottom of the first boundary surface 52) may be greater than a second height H2 of the bottom of the third boundary surface 54 in the first direction (i.e., a distance from the upper surface of the substrate 10 to the bottom of the third boundary surface 54). This is because when the metal layer 40 is deposited on the opposite sidewalls of each of the first opening 32 and the second opening 33 having a relatively large width, portions of the metal layer 40 from the opposite sidewalls spend a longer time contacting each other, and therefore, when portions of the metal layer 40 from the opposite sidewalls contact each other, portions of the metal layer 40 deposited on the bottom of each of the first opening 32 and the second opening 33 may have a greater height.

[0039] The deposition process may be based on the width of the first opening 32 and the second opening 33, such as the first width W1. As such, in an embodiment where the insulating interlayer 20 does not include the protruding portion 25, unlike the portion of the metal layer 40 deposited in the first opening 32 and the second opening 33 extending in the second and third directions, respectively, and having the first width W1, if the third opening 34 has a width greater than the first width W1 in the fourth and fifth directions, respectively, the portion of the metal layer 40 deposited in the third opening 34 may not fill (e.g., completely fill) the third opening 34.

[0040] In an embodiment where the insulating interlayer 20 includes the protruding portion 25, therefore, the third opening 34 may have a second width W2 in the fourth and fifth directions that is smaller than the first width W1 or smaller than the widths of the first and second openings 32 and 33. Therefore, a void may not be formed in the third opening 34 during the deposition process, and the metal layer 40 may fill (e.g., completely fill) the third opening 34.

[0041] The portion of the metal layer 40 located on each of the first opening 32, the second opening 33 and the third opening 34 may have a recessed upper surface, and therefore, the upper surface of the center portion of the metal layer 40 located on each of the first opening 32, the second opening 33 and the third opening 34 may be lower than the upper surface of the portion of the metal layer 40 located on the insulating interlayer 20.

[0042] If the metal layer 40 includes copper by performing the EP process, a boundary surface may not exist in each of the first opening 32 , the second opening 33 , and the third opening 34 .

[0043] Reference Figure 4 and Figure 5 , an upper portion of the metal layer 40 may be planarized until the upper surface of the insulating interlayer 20 is exposed, and thus a first metal pattern 42 , a second metal pattern 43 , and a third metal pattern 44 may be formed in the first opening 32 , the second opening 33 , and the third opening 34 , respectively.

[0044] In some example embodiments, the planarization process may include a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0045] In some example embodiments, each of the first metal pattern 42, the second metal pattern 43, and the third metal pattern 44 may have a flat upper surface, and a third height H3 of the upper surfaces of the first metal pattern 42, the second metal pattern 43, and the third metal pattern 44 may be less than a fourth height H4 of the upper surface of the insulating interlayer 20.

[0046] Alternatively, refer to Figure 6, each of the first metal pattern 42 , the second metal pattern 43 , and the third metal pattern 44 may have a flat upper surface, and a third height H3 of the upper surfaces of the first metal pattern 42 , the second metal pattern 43 , and the third metal pattern 44 may be greater than a fourth height H4 of the upper surface of the insulating interlayer 20 .

[0047] although Figure 5 and Figure 6 It is illustrated that the third height H3 is different from the fourth height H4 , but the inventive concept is not limited thereto, and the third height H3 may be substantially equal to the fourth height H4 .

[0048] As shown above, the insulating interlayer 20 may include the protruding portion 25, and therefore, the third opening 34 at the region where the first opening 32 and the second opening 33 having the first width W1 cross each other may have a second width W2 equal to or less than the first width W1. Therefore, when the metal layer 40 is formed in the first opening 32, the second opening 33, and the third opening 34, the metal layer 40 formed in the third opening 34 may not have a void therein, and there is no such void. Therefore, the wiring structure including the first metal pattern 42, the second metal pattern 43, and the third metal pattern 44 in the first opening 32, the second opening 33, and the third opening 34, respectively, may not have a malfunction or have a reduced malfunction due to the presence of such a void, and may have improved electrical characteristics.

[0049] Figures 7 to 9 1 is a plan view and a cross-sectional view showing a wiring structure according to some example embodiments. Figure 7 It is a floor plan. Figure 8 and Fig. 9 is along Figure 7 A cross-sectional view taken along line BB'. Figure 7 The first part of the line BB' extends in the third direction, Figure 7 The second portion of the line BB' extends in the fourth direction. In addition to some elements described in more detail below, the wiring structure can be Figures 4 to 6 Therefore, the same reference numerals represent the same elements, and for the sake of brevity, the detailed description of the aforementioned elements is not repeated herein.

[0050] Reference Figure 7 and Figure 8 , the insulating spacer 27 may be formed in the fourth opening 36 at a region where the first opening 32 and the second opening 33 cross each other. Figure 7 When viewed in a plan view, the fourth opening 36 may have a rectangular shape or a substantially rectangular shape.

[0051] In some example embodiments, the insulating spacer 27 may be formed in a central portion of the fourth opening 36, and thus the insulating spacer 27 may be positioned at a third width W3 from each vertex of the fourth opening 36 in each of the fourth and fifth directions. In some example embodiments, the third width W3 may be equal to or less than the first width W1 of each of the first opening 32 and the second opening 33. The third width may be defined as the minimum distance between the insulating spacer 27 and the insulating interlayer 20 in the fourth and fifth directions. When viewed in a plan view, the insulating spacer 27 may have a circular, elliptical, polygonal, or other shape. In some example embodiments, the insulating spacer 27 may be formed when the insulating interlayer 20 is formed, and thus the insulating spacer 27 may include a material substantially the same as that of the insulating interlayer 20. As best in Figure 8 As seen in FIG. 1 , the upper surface of the insulating spacer 27 may have a fourth height H4, which is the height of the upper surface of the insulating interlayer 20. In other words, the upper surface of the insulating spacer 27 may be as far from the upper surface of the substrate 10 as the upper surface of the insulating interlayer 20.

[0052] If the insulating spacer 27 is not formed in the fourth opening 36, the fourth opening 36 may have a rectangular shape (with round vertices in some cases) in a plan view, and thus, the width of the fourth opening 36 in each of the fourth and fifth directions may be greater than the first width W1. However, the insulating spacer 27 may be formed in the fourth opening 36, and thus, the width of the fourth opening 36 in each of the fourth and fifth directions may be equal to or less than the first width W1.

[0053] In some example embodiments, a first angle θ1 of a sidewall of each of the first opening 32 and the second opening 33 (e.g., a sidewall of an opening having a relatively larger width or the first width W1) relative to the upper surface of the substrate 10 may be greater than a third angle θ3 of a sidewall of the fourth opening 36 (e.g., a sidewall of an opening having a relatively smaller width or the third width W3) relative to the upper surface of the substrate 10.

[0054] In some example embodiments, the first metal pattern 42 and the second metal pattern 43 respectively located in the first opening 32 and the second opening 33 may have a first boundary surface 52 and a second boundary surface (not shown), respectively. Each of the first boundary surface 52 and the second boundary surface may extend in the first direction. The fourth metal pattern 46 in the fourth opening 36 may have a fourth boundary surface 56, for example, a seam extending in the first direction. In some example embodiments, a first height H1 of the bottom of the first boundary surface 52 or the second boundary surface in the first direction may be greater than a second height H2 of the bottom of the fourth boundary surface 56 in the first direction.

[0055] In some example embodiments, the insulating spacer 27 may be formed in the fourth opening 36, and thus, the third width W3 of the fourth opening 36 in each of the fourth and fifth directions may be smaller than the first width W1. Therefore, the fourth metal pattern 46 may fill (e.g., completely fill) the fourth opening 36 without forming a void therein.

[0056] In some example embodiments, each of the first metal pattern 42, the second metal pattern 43, and the fourth metal pattern 46 may have a flat upper surface, and a third height H3 of the upper surfaces of the first metal pattern 42, the second metal pattern 43, and the fourth metal pattern 46 may be less than a fourth height H4 of the upper surface of the insulating interlayer 20.

[0057] Alternatively, refer to Fig. 9 , each of the first metal pattern 42 , the second metal pattern 43 and the fourth metal pattern 46 may have a flat upper surface, and a third height H3 of the upper surfaces of the first metal pattern 42 , the second metal pattern 43 and the fourth metal pattern 46 may be greater than a fourth height H4 of the upper surface of the insulating interlayer 20 .

[0058] although Figure 8 and Fig. 9 The third height H3 is shown to be different from the fourth height H4, but the inventive concept is not limited thereto, and the third height H3 of the upper surfaces of the first, second and fourth metal patterns 42 , 43 and 46 may be substantially equal to the fourth height H4 of the upper surface of the insulating interlayer 20 .

[0059] As shown above, the insulating spacer 27 may be formed in the fourth opening 36, and therefore, the fourth opening 36 at the region where the first opening 32 and the second opening 33 having the first width W1 cross each other may have a third width W3 equal to or less than the first width W1. Therefore, the first opening 32, the second opening 33, and the fourth opening 36 may be filled (e.g., completely filled) with the first metal pattern 42, the second metal pattern 43, and the fourth metal pattern 46, respectively, and no void may be formed therein, and the wiring structure including the first metal pattern 42, the second metal pattern 43, and the fourth metal pattern 46 may have improved electrical characteristics.

[0060] Fig. 10A , Fig. 10B , Fig.11 and Fig.12 1 is a plan view and a cross-sectional view showing a wiring structure according to some example embodiments. Fig. 10A and Fig. 10B It is a floor plan. Fig.11 and Fig.12 is along Fig. 10A or Fig. 10BA cross-sectional view taken along line CC'. Fig. 10A and Fig. 10B The first part of the line C-C' extends in the third direction, Fig. 10A and Fig. 10B The second part of the line CC' extends in the fourth direction. In addition to some elements described in more detail below, these wiring structures can be connected with Figures 4 to 6 Therefore, the same reference numerals represent the same elements, and for the sake of brevity, the detailed description of the aforementioned elements is not repeated herein.

[0061] Reference Fig. 10A and Fig.11 The fifth opening 38 may be formed at a region where an end of the first opening 32 extending in the second direction and an end of the second opening 33 extending in the third direction meet each other. The fifth opening 38 may be connected to both the first opening 32 and the second opening 33.

[0062] In some example embodiments, when viewed in a plan view, the fifth opening 38 may have a triangular shape (with a rounded vertex in some cases), and the fifth opening 38 may have a fourth width W4 in the fourth direction, which extends from the vertex to the opposite side or edge of the fifth opening 38. The opposite edge may be the hypotenuse of the triangular shape of the fifth opening 38. The fourth width W4 may be equal to or less than the first width W1. The fourth width W4 may be defined as the minimum distance between the insulating interlayer 20 and the opposite edge of the fifth opening 38. That is, if the fifth opening 38 is, for example, a rectangular shape, the width of the fifth opening 38 in the fourth direction may be greater than the first width W1, however, in some example embodiments, the fifth opening 38 may have a triangular shape, which may have a reduced area compared to a rectangle, and therefore, the width of the fifth opening 38 in the fourth direction may be equal to or less than the first width W1.

[0063] In some example embodiments, a first angle θ1 of a sidewall of each of the first opening 32 and the second opening 33 (e.g., a sidewall of an opening having a relatively larger width or the first width W1) relative to the upper surface of the substrate 10 may be greater than a fourth angle θ4 of a sidewall of the fifth opening 38 (e.g., a sidewall of an opening having a relatively smaller width or the fourth width W4) relative to the upper surface of the substrate 10.

[0064] In some example embodiments, the first metal pattern 42 and the second metal pattern 43 respectively located in the first opening 32 and the second opening 33 may have a first boundary surface 52 and a second boundary surface (not shown), respectively. Each of the first boundary surface 52 and the second boundary surface may extend in the first direction. The fifth metal pattern 48 in the fifth opening 38 may have a fifth boundary surface 58, for example, a seam extending in the first direction. In some example embodiments, a first height H1 of the bottom of the first boundary surface 52 or the second boundary surface in the first direction may be greater than a fifth height H5 of the bottom of the fifth boundary surface 58 in the first direction.

[0065] In some example embodiments, the fifth opening 38 may have a triangular shape, and thus the fifth opening 38 may have a fourth width W4 less than the first width W1 in the fourth direction. Therefore, the fifth metal pattern 48 may fill (eg, completely fill) the fifth opening 38, and no void may be formed therein.

[0066] In some example embodiments, each of the first metal pattern 42, the second metal pattern 43, and the fifth metal pattern 48 may have a flat upper surface, and a third height H3 of the upper surfaces of the first metal pattern 42, the second metal pattern 43, and the fifth metal pattern 48 may be less than a fourth height H4 of the upper surface of the insulating interlayer 20.

[0067] Alternatively, refer to Fig.12 , each of the first metal pattern 42 , the second metal pattern 43 and the fifth metal pattern 48 may have a flat upper surface, and a third height H3 of the upper surface of the first metal pattern 42 , the second metal pattern 43 and the fifth metal pattern 48 may be greater than a fourth height H4 of the upper surface of the insulating interlayer 20 .

[0068] although Fig.11 and Fig.12 The third height H3 is shown to be different from the fourth height H4, but the inventive concept is not limited thereto, and the third height H3 of the upper surfaces of the first, second and fifth metal patterns 42 , 43 and 48 may be substantially equal to the fourth height H4 of the upper surface of the insulating interlayer 20 .

[0069] Reference Fig. 10B When viewed in a plan view, the fifth opening 38 may have a substantially triangular shape having at least one nonlinear segment between two vertices thereof, and the triangular shape may be similar to a rectangle from which a portion is removed. The fourth width W4 may extend from the vertex to the opposite side in the fourth direction, and the fourth width W4 may be equal to or less than the first width W1.

[0070] As shown above, the fifth opening 38 at the region where the first opening 32 and the second opening 33 meet each other may have a triangular shape or a substantially triangular shape, and may have a fourth width W4 that is equal to or less than the width (e.g., first width W1) of the first opening 32 and the second opening 33. Therefore, the first opening 32, the second opening 33, and the fifth opening 38 may be filled (e.g., completely filled) with the first metal pattern 42, the second metal pattern 43, and the fifth metal pattern 48, respectively, and may not have a void formed therein, and a wiring structure including the first metal pattern 42, the second metal pattern 43, and the fifth metal pattern 48 may have improved electrical characteristics.

[0071] Fig.13A and Fig. 13B 10 to 11 are plan views showing wiring structures according to some example embodiments. In addition to some elements described in more detail below, these wiring structures may be similar to those shown in FIG. Fig.12 or Figures 4 to 6 Therefore, the same reference numerals represent the same elements, and for the sake of brevity, the detailed description of the aforementioned elements is not repeated herein.

[0072] Reference Fig.13A , the insulating interlayer 20 may include a protruding portion 29 that protrudes toward the center of a sixth opening (not shown) at an area where the first opening 32 and the second opening 33 extending in the second direction and the third direction meet each other. The sixth opening may be filled with a sixth metal pattern 49. The sixth opening may have a rectangular shape having a recess in one corner thereof. In some example embodiments, the recess may be defined by a concave curve, edge, or arc segment that may be an ellipse or a partial ellipse. The concave curve, edge, or arc segment may start at a point adjacent to the first opening 32 and may extend to a point adjacent to the second opening 33.

[0073] In some example embodiments, the fifth width W5, which is the minimum width from the recess to the vertex of the sixth opening opposite to the recess in the fourth direction, may be equal to or less than the first width W1. That is, if the insulating interlayer 20 does not include the protruding portion 29, the width of the sixth opening in the fourth direction may be greater than the first width W1. In some example embodiments, the insulating interlayer 20 includes the protruding portion 29, and therefore, the minimum width of the sixth opening in the fourth direction may be equal to or less than the first width W1. Therefore, the sixth opening may be filled (e.g., completely filled) with the sixth metal pattern 49, and no void may be formed therein.

[0074] The wiring structure may have the following characteristics: for example, the height of the bottom of the sixth boundary surface (not shown) in the sixth metal pattern 49, the fifth angle (relative to the upper surface of the substrate 10) of each of the opposite side walls forming the minimum width, and the height of the sixth metal pattern 49, which may be the same as the reference Fig. 10A , Fig. 10B , Fig.11 and Fig.12 The wiring structures shown are substantially the same as those.

[0075] Reference Fig. 13B ,like Fig.13A Like the insulating interlayer 20 , the insulating interlayer 20 may include a protruding portion 29 protruding from the center of the sixth opening toward an area where the first opening 32 and the second opening 33 extending in the second direction and the third direction, respectively, meet each other.

[0076] and Fig.13A The first opening 32 and the second opening 33 are different, Fig. 13B The first opening 32 and the second opening 33 may intersect each other at the sixth opening, and may also extend in the second direction and the third direction, respectively. Fig. 13B The first opening 32 and the second opening 33 may be Figure 1 The sixth opening 32 and the second opening 33 are similar. Therefore, when viewed in a plan view, the sixth opening may have a rectangular shape with a recess in one corner thereof. In some example embodiments, the recess may be defined by a concave curve, edge, or arc segment that may be an ellipse or a partial ellipse. The concave curve, edge, or arc segment may start at a point adjacent to the first opening 32 and may extend to a point adjacent to the second opening 33.

[0077] The wiring structure may have the following characteristics: for example, the height of the bottom of the sixth boundary surface in the sixth metal pattern 49, the fifth angle (relative to the upper surface of the substrate 10) of each of the opposite side walls forming the minimum width, and the height of the sixth metal pattern 49, which may be the same as those of the reference Fig.13A The wiring structures shown are substantially the same as those.

[0078] As shown above, refer to Figures 1 to 13BEach of the wiring structures shown may include: a first metal pattern 42 extending in the second direction and having a first width W1 in the third direction; a second metal pattern 43 extending in the second direction and having a first width W1 in the second direction (or having different widths in the second direction as discussed above); and one of a third metal pattern 44, a fourth metal pattern 46, a fifth metal pattern 48, and a sixth metal pattern 49 formed at a region where the first metal pattern 42 and the second metal pattern 43 meet or intersect each other. The one of the third metal pattern 44, the fourth metal pattern 46, the fifth metal pattern 48, and the sixth metal pattern 49 has a minimum width in the fourth direction between opposing portions, the opposing portions having an angle of 45 degrees with respect to each of the second direction and the third direction, and the minimum width may be equal to or less than the first width W1. An angle of the sidewall of the first metal pattern 42 in the third direction and / or the sidewall of the second metal pattern in the second direction relative to the upper surface of the substrate 10 may be greater than an angle of each of the opposing sidewalls forming the minimum width of a corresponding one of the third metal pattern 44, the fourth metal pattern 46, the fifth metal pattern 48, and the sixth metal pattern 49 relative to the upper surface of the substrate 10. In other words, the first angle θ1 may be greater than a corresponding one of the second angle θ2, the third angle θ3, the fourth angle θ4, and the fifth angle.

[0079] In some example embodiments, the height of the bottom of the first boundary surface 52 and the second boundary surface respectively located in the first metal pattern 42 and the second metal pattern 43 may be greater than the height of the bottom of the third boundary surface 54, the fourth boundary surface 56, the fifth boundary surface 58 and the corresponding one of the sixth boundary surface, and the third boundary surface 54, the fourth boundary surface 56, the fifth boundary surface 58 and the corresponding one of the sixth boundary surface may be formed at the center portion of the portion with the minimum width forming the corresponding one of the third metal pattern 44, the fourth metal pattern 46, the fifth metal pattern 48 and the sixth metal pattern 49 in the fourth direction.

[0080] Fig.14 , Fig.15A , Fig. 15B , Fig.16 , Fig.17A and Fig. 17B 1 is a plan view and a cross-sectional view showing a wiring structure according to some example embodiments. Fig.14 and Fig.16 It is a floor plan. Fig.15A and Fig. 15B is along Fig.14 A cross-sectional view taken along line D-D', Fig.17A and Fig. 17B is along Fig.16 A cross-sectional view taken along line EE'. Fig.14A first portion of the line D-D' extends in the second direction, Fig.14 The second portion of the line D-D' extends in the third direction. Fig.16 A first portion of the line EE' extends in the second direction, Fig.16 The second part of the line EE' extends in the fifth direction. In addition to some elements described in more detail below, these wiring structures can be connected with Figures 1 to 3 Therefore, the same reference numerals represent the same elements, and for the sake of brevity, the detailed description of the aforementioned elements is not repeated herein.

[0081] Reference Fig.14 and Fig.15A The seventh opening 31 may be formed at a region where a central portion of the first opening 32 extending in the second direction and an end portion of the second opening 33 extending in the third direction meet each other. The seventh opening 31 may be connected to the first opening 32 and the second opening 33.

[0082] In some example embodiments, when viewed in a plan view, the seventh opening 31 may have a rectangular shape having a recessed portion at an upper portion thereof, and thus, a sixth width W6 in the third direction may be equal to or less than the first width W1. The sixth width W6 may be defined as a minimum width between the recessed portion of the seventh opening 31 and the insulating interlayer 20 in the third direction. In some example embodiments, a first angle θ1 of a sidewall of each of the first opening 32 and the second opening 33 (e.g., an opening having a relatively large width) with respect to an upper surface of the substrate 10 may be greater than a sixth angle θ6 of a sidewall of the seventh opening 31 (e.g., an opening having a relatively small width) with respect to an upper surface of the substrate 10.

[0083] In some example embodiments, the first metal pattern 42 and the second metal pattern 43 respectively located in the first opening 32 and the second opening 33 may have a first boundary surface 52 and a second boundary surface (not shown) each extending in the first direction, and the seventh metal pattern 41 in the seventh opening 31 may have a seventh boundary surface 51, for example, a seam extending in the first direction. In some example embodiments, a first height H1 of the bottom of the first boundary surface 52 or the second boundary surface in the first direction may be greater than a sixth height H6 of the bottom of the seventh boundary surface 51 in the first direction.

[0084] In some example embodiments, when viewed in a plan view, the seventh opening 31 may have a rectangular shape partially recessed thereon, and thus may have a sixth width W6 smaller than the first width W1 in the third direction. Therefore, the seventh opening 31 may be filled (e.g., completely filled) with the seventh metal pattern 41 without forming a void therein.

[0085] In some example embodiments, each of the first metal pattern 42, the second metal pattern 43, and the seventh metal pattern 41 may have a flat upper surface, and a third height H3 of the upper surfaces of the first metal pattern 42, the second metal pattern 43, and the seventh metal pattern 41 may be less than a fourth height H4 of the upper surface of the insulating interlayer 20.

[0086] Alternatively, each of the first metal pattern 42, the second metal pattern 43 and the seventh metal pattern 41 may have a flat upper surface, however, a third height H3 of the upper surfaces of the first metal pattern 42, the second metal pattern 43 and the seventh metal pattern 41 may be greater than or equal to a fourth height H4 of the upper surface of the insulating interlayer 20.

[0087] Reference Fig. 15B In some example embodiments, the second depth D2 of the seventh opening 31 may be greater than the first depth D1 of the first opening 32 and the second opening 33 , and thus the thickness of the seventh metal pattern 41 may be greater than the thickness of the first metal pattern 42 and the second metal pattern 43 .

[0088] In some example embodiments, the first metal pattern 42, the second metal pattern 43 and the seventh metal pattern 41 respectively located in the first opening 32, the second opening 33 and the seventh opening 31 may have any one of a variety of shapes. The seventh metal pattern 41 may be formed in a region where the central portion of the first metal pattern 42 extending in the second direction and the end portion of the second metal pattern 43 extending in the third direction meet each other. For example, when viewed in a plan view, the seventh metal pattern 41 may have a rectangular shape, the rectangle including a first side or a first edge and a second side or a second edge opposite to each other in the third direction. The second side (which may not contact the second metal pattern 43) may not be a straight line, and may be a concave curve in some embodiments. The sixth width W6 between the first side and the second side of the seventh metal pattern 41 may be equal to or less than the first width W1 of each of the first metal pattern 42 and the second metal pattern 43.

[0089] Additionally, an insulating layer including an insulating material (eg, silicon oxide) instead of a metal may be formed in at least one of the first opening 32 , the second opening 33 , and the seventh opening 31 (eg, in the seventh opening 31 ).

[0090] Reference Fig.16 and Fig.17A ,and Fig.14 and Fig.15ALike the seventh opening 31, the eighth opening 39 can be formed in an area where the center portion of the first opening 32 extending in the second direction meets the end portion of the second opening 33 extending in the third direction, and can have a concave edge located at the upper side in a plan view.

[0091] Additionally, the insulating interlayer 20 may include at least one protrusion portion 28 protruding toward the center of the eighth opening 39. For example, when viewed in a plan view, the eighth opening 39 may have a rectangular shape having a recess in at least one corner thereof. Fig.16 Two recesses are shown. In some example embodiments, the recess may be defined by a concave curve, edge, or arc segment that may be elliptical or partially elliptical. The concave curve, edge, or arc segment may start at a point adjacent to the first opening 32 and may extend to a point adjacent to the second opening 33.

[0092] In some example embodiments, a seventh width W7 in the fourth direction or the fifth direction from a point closest to the center of the eighth opening 39 along the concave curve defining the concave portion to the concave edge at the upper side of the rectangle may be equal to or less than the first width W1. Thus, the eighth opening 39 may be completely filled with the eighth metal pattern 45 without a void therein.

[0093] In some example embodiments, a first angle θ1 of a sidewall of each of the first opening 32 and the second opening 33 (i.e., an opening having a relatively larger width) relative to the upper surface of the substrate 10 may be greater than a seventh angle θ7 of a sidewall of the eighth opening 39 (i.e., an opening having a relatively smaller width) relative to the upper surface of the substrate 10.

[0094] In some example embodiments, first metal pattern 42 and second metal pattern 43 respectively located in first opening 32 and second opening 33 may have first boundary surface 52 and second boundary surface each extending in the first direction, and eighth metal pattern 45 in eighth opening 39 may have eighth boundary surface 55, for example, a seam extending in the first direction. In some example embodiments, a first height H1 of a bottom of first boundary surface 52 or second boundary surface in the first direction may be greater than a seventh height H7 of a bottom of eighth boundary surface 55 in the first direction.

[0095] Reference Fig. 17B , the second depth D2 of the eighth opening 39 may be greater than the first depth D1 of the first opening 32 and the second opening 33 , and thus, the thickness of the eighth metal pattern 45 may be greater than the thickness of the first metal pattern 42 and the second metal pattern 43 .

[0096] In some example embodiments, the first metal pattern 42, the second metal pattern 43, and the eighth metal pattern 45, which are respectively located in the first opening 32, the second opening 33, and the eighth opening 39, may have any one of a variety of shapes. The eighth metal pattern 45 may be formed at a region where the center portion of the first metal pattern 42 extending in the second direction and the end portion of the second metal pattern 43 extending in the third direction meet in the third direction. The eighth metal pattern 45 may have a rectangular shape, the rectangle including a first edge and a second edge opposite to each other in the third direction in a plan view, however, the second edge that does not contact the second metal pattern 43 may be a concave curve, rather than a straight line. Additionally, a concave portion may exist at the opposite ends of the first edge of the rectangle. The seventh width W7 may be equal to or less than the first width W1, and the seventh width W7 may be the minimum distance between a concave portion at one of the opposite ends of the first side of the rectangle and a concave portion of the second side in the fourth direction or the fifth direction.

[0097] Additionally, an insulating layer including an insulating material (eg, silicon oxide) instead of metal may be formed in at least one of the first opening 32 , the second opening 33 , and the eighth opening 39 (eg, in the eighth opening 39 ).

[0098] References can be formed through damascene processes or operations Figures 1 to 17B The wiring structure described can be manufactured by one or more methods including reference Figures 1 to 17B A vertical memory device of a wiring structure is described, and some example embodiments of a method of manufacturing the vertical memory device will be described hereinafter.

[0099] In the following description (not necessarily in the claims), a direction substantially perpendicular to the upper surface of the first substrate may be defined as a first direction, and two directions substantially parallel to the upper surface of the first substrate and intersecting each other may be defined as a second direction and a third direction, respectively. In some example embodiments, the second direction and the third direction may be substantially perpendicular to each other.

[0100] Fig.18 and Fig.19 is a cross-sectional view showing a vertical memory device according to some example embodiments. Specifically, Fig.18 is a cross-sectional view taken along the second direction, Fig.19 It is a cross-sectional view taken along the third direction.

[0101] Reference Fig.18 and Fig.19, the vertical memory device may include a lower circuit pattern on the first substrate 100, a second substrate 250 on the lower circuit pattern, a channel connection pattern 480, a support layer 320, a support pattern 322, a sacrificial layer structure 300 and a memory cell on the second substrate 250, contact plugs 542, 543, 544 on the second substrate 250 and the lower circuit pattern, and an upper circuit pattern. The vertical memory device may also include a separation structure, a first insulating interlayer 160, a second insulating interlayer 230 and a third insulating interlayer 240, a fourth insulating interlayer pattern 260, and fifth to thirteenth insulating interlayers 350, 360, 440, 560, 580, 600, 620, 640, and 660.

[0102] Each of the first substrate 100 and the second substrate 250 may include a semiconductor material (e.g., silicon, germanium, silicon germanium, etc.) or a III-V compound (e.g., GaP, GaAs, GaSb, etc.). In some example embodiments, each of the first substrate 100 and the second substrate 250 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. In some example embodiments, the second substrate 250 may include polysilicon doped with n-type impurities.

[0103] The first substrate 100 may include a field region on which an insulating pattern 110 is formed, and an active region 105 on which no insulating pattern is formed. The insulating pattern 110 may include an oxide, for example, silicon oxide.

[0104] In some example embodiments, the first substrate 100 may include a first region I, a second region II, and a third region III. Hereinafter, each of the first region I, the second region II, and the third region III of the first substrate 100 may indicate not only a portion of the first substrate 100 but also an area or space above the first substrate 100.

[0105] The first region I may be a cell array region in which a memory cell is formed; the second region II may be an extension region or a pad region at least partially surrounding the first region I in which a contact plug is formed, the contact plug being configured to transmit an electrical signal to the memory cell and some upper circuit patterns electrically connected to the contact plug; and the third region III may be a peripheral circuit region, which at least partially surrounds the second region II, and a contact plug is formed in the third region III, the contact plug being configured to transmit an electrical signal to a lower circuit pattern and some upper circuit patterns electrically connected to the contact plug.

[0106] The first region I and the second region II may form a cell region, and thus the peripheral circuit region may at least partially surround the cell region. Fig.18A portion of each of the first region I, the second region II, and the third region III of the first substrate 100 is shown.

[0107] In some example embodiments, the vertical memory device may have a cell-overperiphery (COP) structure. That is, a lower circuit pattern may be formed on the first substrate 100, and a memory cell, a contact plug, and an upper circuit pattern may be formed above the lower circuit pattern. The memory cell may be formed on the second substrate 250 in the first region I of the first substrate 100, and the contact plug and the upper circuit pattern may be formed on the second substrate 250 in the second region II of the first substrate 100, or formed on the lower circuit pattern in the third region III of the first substrate 100.

[0108] The lower circuit pattern may include a transistor, a lower contact plug, a lower wiring, a lower via, etc. In some example embodiments, a first transistor in the first region I of the first substrate 100 and a second transistor in the third region III of the first substrate 100 may be formed, the first transistor including a first lower gate structure 152 and a first impurity region 102 located at an upper portion of the active region 105 adjacent to the first lower gate structure 152, and the second transistor including a second lower gate structure 158 and a second impurity region 108 located at an upper portion of the active region 105 adjacent to the second lower gate structure 158. However, the inventive concept is not limited thereto, and the lower gate structure and the impurity region may be formed in the second region II of the first substrate 100 to form an additional transistor.

[0109] The first lower gate structure 152 may include a first lower gate insulating pattern 122, a first lower gate electrode 132 and a first lower gate mask 142 sequentially stacked on the first substrate 100, and the second lower gate structure 158 may include a second lower gate insulating pattern 128, a second lower gate electrode 138 and a second lower gate mask 148 sequentially stacked on the first substrate 100.

[0110] A first insulating interlayer 160 may be formed on the first substrate 100 to cover the first and second transistors, and first and second lower contact plugs 172 and 178 may be formed through the first insulating interlayer 160 to contact the first and second impurity regions 102 and 108 , respectively.

[0111] The lower wiring structure may include first to sixth lower wirings 182, 188, 202, 208, 222, and 228. The first lower wiring 182 and the second lower wiring 188 may be formed on the first insulating interlayer 160 to contact upper surfaces of the first lower contact plug 172 and the second lower contact plug 178, respectively. The first lower via 192, the third lower wiring 202, the third lower via 212, and the fifth lower wiring 222 may be sequentially stacked on the first lower wiring 182, and the second lower via 198, the fourth lower wiring 208, the fourth lower via 218, and the sixth lower wiring 228 may be sequentially stacked on the second lower wiring 188.

[0112] In some example embodiments, at least one of the first to sixth lower wirings 182, 188, 202, 208, 222, and 228 may have a Figures 1 to 17B One of the wiring structures shown has substantially the same structure and thus may have improved electrical characteristics without voids therein.

[0113] The first to second lower contact plugs 172 and 178, the first to fourth lower vias 192, 198, 212, and 218, and the first to sixth lower wirings 182, 188, 202, 208, 222, and 228 may include a conductive material, for example, metal, metal nitride, metal silicide, doped polysilicon, or the like.

[0114] The second insulating interlayer 230 may be formed on the first insulating interlayer 160 to cover the first to fourth lower wirings 182, 188, 202, and 208 and the first to fourth lower vias 192, 198, 212, and 218 to surround the sidewalls of the fifth and sixth lower wirings 222 and 228. The third insulating interlayer 240 may be formed on the second insulating interlayer 230 and the fifth and sixth lower wirings 222 and 228. The first insulating interlayer 160, the second insulating interlayer 230, and the third insulating interlayer 240 may form a lower insulating interlayer structure, and in some cases, may include a single layer because the first insulating interlayer 160, the second insulating interlayer 230, and the third insulating interlayer 240 may include the same material (e.g., silicon oxide) and may be merged with each other.

[0115] The second substrate 250 may be formed on the third insulating interlayer 240 in the first region I and the second region II of the first substrate 100, and the sidewalls of the second substrate 250 may be covered by the fourth insulating interlayer pattern 260 on the third insulating interlayer 240. The fourth insulating interlayer pattern 260 may include an oxide such as silicon oxide, and thus, may be merged with the third insulating interlayer 240 in some cases.

[0116] The memory cells may be formed on the second substrate 250 in the first region I and the second region II of the first substrate 100. The memory cells may be arranged in the second direction and the third direction to form a memory cell array. The memory cell array may include a plurality of memory cell blocks arranged in the third direction, and the plurality of memory cell blocks may be spaced apart from each other by a partition structure extending in the second direction.

[0117] The separation structure may include a common source pattern (CSP) 530 extending in the second direction on the second substrate 250 and a second spacer 520 on each of opposite sidewalls of the CSP 530. Alternatively, the CSP 530 may not be formed, and the separation structure may include only the second spacer 520. The CSP 530 may include a metal, a metal nitride, a metal silicide, etc., and the second spacer 520 may include an oxide such as silicon oxide.

[0118] In some example embodiments, the CSP 530 and / or the second spacer 520 may have the same Figures 14 to 17B The structure of one of the wiring structures shown is substantially the same structure.

[0119] Each of the memory cell blocks may include a channel block therein. The channel block may include a plurality of channel columns each having a plurality of channels 410 arranged in the second direction.

[0120] Each of the memory cell blocks may include gate electrodes 512, 514 and 516 spaced apart from each other in a first direction, an insulating pattern 335 between adjacent ones of the gate electrodes 512, 514 and 516, pillar structures each extending through the gate electrodes 512, 514 and 516 and the insulating pattern 335, and a capping pattern 430.

[0121] The gate electrodes 512, 514, and 516 may be formed in the first region I and the second region II of the first substrate 100 to be spaced apart from each other in the first direction, and each of the gate electrodes 512, 514, and 516 may extend in the second direction in the first region I and the second region II of the first substrate 100. The extension length of the gate electrodes 512, 514, and 516 in the second direction may decrease from the lowest level toward the highest level, and thus, the gate electrodes 512, 514, and 516 may have a stepped shape.

[0122] The gate electrodes 512, 514, and 516 may include a first gate electrode 512, a second gate electrode 514, and a third gate electrode 516 sequentially stacked in a first direction. The first gate electrode 512 may be used as a ground selection line (GSL), the second gate electrode 514 may be used as a word line, and the third gate electrode 516 may be used as a string selection line (SSL).

[0123] Each of the first gate electrode 512, the second gate electrode 514, and the third gate electrode 516 may be formed at one level or at multiple levels. In some example embodiments, the first gate electrode 512 may be formed at the lowest level, the third gate electrode 516 may be formed at the highest level and the second level from the top, and the second electrode 514 may be formed at multiple levels between the first gate electrode 512 and the third gate electrode 516.

[0124] Each of the gate electrodes 512, 514, and 516 may include a conductive pattern and a barrier pattern covering the lower and upper surfaces and sidewalls of the conductive pattern. The conductive pattern may include a metal having a low resistance, such as tungsten, titanium, tantalum, platinum, etc., and the barrier pattern may include a metal nitride, such as titanium nitride, tantalum nitride, etc.

[0125] The sidewalls of the gate electrodes 512, 514, and 516 having the stepped shape may be covered by the fifth insulating interlayer 350, and the sixth to thirteenth insulating interlayers 360, 440, 560, 580, 600, 620, 640, and 660 may be sequentially stacked on the uppermost one of the insulating patterns 335 and the fifth insulating interlayer 350. The fifth to thirteenth insulating interlayers 350, 360, 440, 560, 580, 600, 620, 640, and 660 may include an oxide such as silicon oxide, and may be merged with each other or may be merged with the fourth insulating interlayer pattern 260 in some example embodiments.

[0126] The lower and upper surfaces of each of the gate electrodes 512, 514, and 516 and the sidewalls facing the channel 410 may be covered by the second barrier layer 500. The second barrier layer 500 may include a metal oxide (eg, aluminum oxide, hafnium oxide, etc.) and may also cover the sidewalls of each of the insulating patterns 335.

[0127] Each of the pillar structures may include a charge storage structure 400 , a channel 410 , and a filling pattern 420 , and a capping pattern 430 may be formed on each of the pillar structures.

[0128] The channel 410 may extend in the first direction on the second substrate 250 and may have a cup shape. The charge storage structure 400 may include an upper portion extending in the first direction to cover most of the outer sidewalls of the channel 410, and a lower portion covering the bottom and lower sidewalls of the channel 410 on the second substrate 250. The filling pattern 420 may have a column shape for filling the inner space formed by the channel 410 having the cup shape.

[0129] The charge storing structure 400 may include a tunnel insulating pattern 390 , a charge storing pattern 380 , and a first barrier pattern 370 sequentially stacked from an outer sidewall of the channel 410 in a horizontal direction substantially parallel to an upper surface of the first substrate 100 .

[0130] The channel 410 may include undoped or doped polysilicon or single crystal silicon. The first barrier pattern 370 may include an oxide such as silicon oxide, the charge storage pattern 380 may include a nitride such as silicon nitride, and the tunnel insulating pattern 390 may include an oxide such as silicon oxide. The filling pattern 420 may include an oxide such as silicon oxide.

[0131] The capping pattern 430 may include, for example, polycrystalline silicon or single crystalline silicon doped with impurities. The capping pattern 430 may extend through an upper portion of an uppermost one of the insulating patterns 335 and the sixth insulating interlayer 360 .

[0132] The channel connection pattern 480 may be formed on the second substrate 250 in the first region I of the first substrate 100 to contact the lower outer sidewall of each of the channels 410 (i.e., the outer sidewall between the lower and upper portions of the charge storage structure 400), and thus, the channels 410 included in each channel block may be connected to each other. The channel connection pattern 480 may include, for example, polysilicon doped with n-type impurities, and may have an air gap 490 therein.

[0133] The sacrificial layer structure 300 may be formed on the second substrate 250 in the second region II of the first substrate 100, and may include a first sacrificial layer 270, a second sacrificial layer 280, and a third sacrificial layer 290 sequentially stacked in a first direction. The first sacrificial layer 270, the second sacrificial layer 280, and the third sacrificial layer 290 may include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), and an oxide (e.g., silicon oxide), respectively.

[0134] In some example embodiments, the channel connection pattern 480 may fill a first gap 470 (see FIG. 4 ) which may be formed by removing a portion of the sacrificial layer structure 300 located in the first region I of the first substrate 100. Fig.26 and Fig. 27 ), and thus may be formed at the same level as the sacrificial layer structure 300.

[0135] The support layer 320 may be formed on the channel connection pattern 480 below the gate electrodes 512, 514, and 516 in the first region I of the first substrate 100. However, a portion of the support layer 320 may extend through the channel connection pattern 480 or the sacrificial layer structure 300 to contact the upper surface of the second substrate 250, which may be referred to as a support pattern 322. In some example embodiments, a plurality of support patterns 322 may be formed in the first region I and the second region II of the first substrate 100, and may have various layouts. For example, a plurality of support patterns 322 may be spaced apart from each other in the second direction and the third direction, and some of the support patterns 322 may extend in the second direction or the third direction.

[0136] The first contact plug 542 can extend through the fifth insulating interlayer 350, the sixth insulating interlayer 360 and the seventh insulating interlayer 440, the insulating pattern 335 and the second barrier pattern 500 to contact a corresponding one of the first gate electrode 512, the second gate electrode 514 and the third gate electrode 516 in the second region II of the first substrate 100, the second contact plug 543 can extend through the fifth insulating interlayer 350, the sixth insulating interlayer 360 and the seventh insulating interlayer 440, the supporting layer 320 and the sacrificial layer structure 300 to contact the upper surface of the second substrate 250 in the second region II of the first substrate 100, and the third contact plug 544 can extend through the fifth insulating interlayer 350, the sixth insulating interlayer 360 and the seventh insulating interlayer 440, the sacrificial layer structure 300, the fourth insulating interlayer pattern 260 and the third insulating interlayer 240 to contact the upper surface of the sixth lower wiring 228 in the third region III of the first substrate 100.

[0137] The third contact plug 544 may extend in the first direction to electrically connect the lower circuit pattern with the upper circuit pattern, and thus may be referred to as a through via (THV).

[0138] The upper circuit pattern may include an upper contact plug, an upper wiring, an upper via, and the like.

[0139] The first upper contact plug 572, the second upper contact plug 573, the third upper contact plug 574 and the fifth upper contact plug 579 may extend through the eighth insulating interlayer 560 on the seventh insulating interlayer 440, the separation structure and the first contact plug 542, the second contact plug 543 and the third contact plug 544 to contact the first contact plug 542, the second contact plug 543 and the third contact plug 544 and the upper surface of the CSP 530, respectively, and the fourth upper contact plug 578 may extend through the seventh insulating interlayer 440 and the eighth insulating interlayer 560 to contact the upper surface of the capping pattern 430.

[0140] The upper wiring structure may include, for example, first to twelfth upper wirings 592, 593, 594, 598, 599, 632, 633, 634, 638, 639, 674, 679. The first to fifth upper wirings 592, 593, 594, 598, 599 may extend through the ninth insulating interlayer 580 on the eighth insulating interlayer 560 and the first to fifth upper contact plugs 572, 573, 574, 578, 579 to contact upper surfaces of the first to fifth upper contact plugs 572, 573, 574, 578, 579, respectively.

[0141] The first upper via to the fifth upper via 612, 613, 614, 618, 619 can extend through the tenth insulating interlayer 600 on the ninth insulating interlayer 580 and the first upper wiring to the fifth upper wiring 592, 593, 594, 598 and 599 to contact the upper surfaces of the first upper wiring to the fifth upper wiring 592, 593, 594, 598 and 599, respectively.

[0142] The sixth to tenth upper wirings 632, 633, 634, 638 and 639 may extend through the eleventh insulating interlayer 620 on the tenth insulating interlayer 600 and the first to fifth upper vias 612, 613, 614, 618 and 619 to contact upper surfaces of the first to fifth upper vias 612, 613, 614, 618 and 619, respectively.

[0143] The sixth upper via 654 and the seventh upper via 659 may extend through the twelfth insulating interlayer 640 on the eleventh insulating interlayer 620 and the sixth to tenth upper wirings 632, 633, 634, 638 and 639 to contact upper surfaces of the sixth to tenth upper wirings 632, 633, 634, 638 and 639, respectively.

[0144] The eleventh and twelfth upper wirings 674 and 679 may extend through the thirteenth insulating interlayer 660 on the twelfth insulating interlayer 640 and the sixth and seventh upper vias 654 and 659 to contact upper surfaces of the sixth and seventh upper vias 654 and 659 , respectively.

[0145] In some example embodiments, the ninth upper wiring 638 may extend in the third direction, and a plurality of ninth upper wirings 638 may be spaced apart from each other in the second direction. The ninth upper wiring 638 may serve as a bit line of a vertical memory device.

[0146] In some example embodiments, at least one of the first to twelfth upper wirings 592, 593, 594, 598, 599, 632, 633, 634, 638, 639, 674, 679 may have the same Figure 1 to Figure 1 7 is substantially the same structure and thus can have improved electrical characteristics without having a void therein.

[0147] Figures 20 to 32 is a cross-sectional view illustrating a method of manufacturing a vertical memory device according to some example embodiments. Specifically, Figure 20 to Figure 24 , Fig.26 , Fig.28 , Fig.30 and Fig.32 is a cross-sectional view taken along the second direction, Fig.25 , Fig. 27 , Fig.29 and Fig.31 It is a cross-sectional view taken along the third direction.

[0148] Reference Fig. 20 , a lower circuit pattern may be formed on the first substrate 100 , and a first insulating interlayer 160 , a second insulating interlayer 230 , and a third insulating interlayer 240 may be sequentially formed on the first substrate 100 to cover the lower circuit pattern.

[0149] An insulating pattern 110 may be formed on the first substrate 100 by a shallow trench isolation (STI) process, and an active region 105 may be defined in the first substrate 100. An ion implantation process may be performed to form a first impurity region 102 and a second impurity region 108 at an upper portion of the active region 105. A first lower gate structure 152 and a second lower gate structure 158, a first lower contact plug 172 and a second lower contact plug 178, first to fourth lower vias 192, 198, 212, and 218, and first to sixth lower wirings 182, 188, 202, 208, 222, and 228, which may form a lower circuit pattern, may be formed by a patterning process or a damascene process. Specifically, the active region 105 may be formed by a patterning process or a damascene process. Figures 1 to 17B The first to sixth lower wirings 182 , 188 , 202 , 208 , 222 , and 228 are formed by the damascene process as shown and thus voids are prevented from being formed therein, which can provide improved electrical characteristics.

[0150] A first insulating interlayer 160 may be formed on the first substrate 100 and may cover the first and second impurity regions 102 and 108 and the first and second lower gate structures 152 and 158 to surround sidewalls of the first and second lower contact plugs 172 and 178. A second insulating interlayer 230 may be formed on the first insulating interlayer 160 and may cover the first to fourth lower vias 192, 198, 212, and 218 and the first to fourth lower wirings 182, 188, 202, and 208 to surround sidewalls of the fifth and sixth lower wirings 222 and 228. A third insulating interlayer 240 may be formed on the fifth and sixth lower wirings 222 and 228.

[0151] The second substrate 250 may be formed on the third insulating interlayer 240 , and a fourth insulating interlayer pattern 260 may be formed on the third insulating interlayer 240 to cover a sidewall of the second substrate 250 .

[0152] The second substrate 250 may be formed on the third insulating interlayer 240 , and may be patterned through an etching process to remain only in the first region I and the second region II of the first substrate 100 .

[0153] The fourth insulating interlayer pattern 260 may be formed by forming a fourth insulating interlayer on the third insulating interlayer 240 to cover the second substrate 250 and planarizing the fourth insulating interlayer until an upper surface of the second substrate 250 is exposed.

[0154] Reference Fig.21 A sacrificial layer structure 300 may be formed on the second substrate 250 and the fourth insulating interlayer pattern 260, the sacrificial layer structure 300 may be partially removed to form a ninth opening 310 exposing the upper surface of the second substrate 250, and a supporting layer 320 may be formed on the second substrate 250 and the fourth insulating interlayer pattern 260 to at least partially fill the ninth opening 310.

[0155] The sacrificial layer structure 300 may include a first sacrificial layer 270 , a second sacrificial layer 280 , and a third sacrificial layer 290 , which are sequentially stacked.

[0156] In some example embodiments, a plurality of ninth openings 310 may be formed in the first region I and the second region II of the first substrate 100, and may have various layouts. For example, a plurality of ninth openings 310 may be formed to be spaced apart from each other in the second direction and the third direction, and some of the ninth openings 310 may extend in the second direction or the third direction.

[0157] The support layer 320 may have a constant thickness, and thus a first recess may be formed on a portion of the support layer 320 located in the ninth opening 310. Hereinafter, the portion of the support layer 320 located in the ninth opening 310 may be referred to as a support pattern 322.

[0158] Portions of the sacrificial layer structure 300 and the support layer 320 located in the third region III of the first substrate 100 may be patterned.

[0159] Reference Fig. 22 , an insulating layer 330 may be formed on the supporting layer 320 , the supporting pattern 322 , and the fourth insulating interlayer pattern 260 to fill the first recess, and an upper portion of the insulating layer 330 may be planarized.

[0160] The fourth sacrificial layer 340 and the insulating layer 330 may be alternately and repeatedly stacked on the insulating layer 330. Thus, a mold layer including a plurality of insulating layers 330 and a plurality of fourth sacrificial layers 340 alternately and repeatedly stacked in the first direction may be formed on the support layer 320, the support pattern 322, and the fourth insulating interlayer pattern 260. The fourth sacrificial layer 340 may include a material having an etching selectivity with respect to the insulating layer 330, for example, a nitride such as silicon nitride.

[0161] Reference Fig.23 , a photoresist pattern (not shown) partially covering the uppermost one of the insulating layers 330 may be formed on the uppermost one of the insulating layers 330, and the uppermost one of the fourth sacrificial layers 340 located below the insulating layer 330 may be etched using the photoresist pattern as a mask pattern. Thus, a portion of one of the insulating layers 330 located directly below the uppermost one of the fourth sacrificial layers 340 may be exposed. After performing a trimming process for reducing the area of ​​the photoresist pattern at a given ratio, an etching process may be performed so that the uppermost one of the insulating layers 330, the uppermost one of the fourth sacrificial layers 340, the exposed one of the insulating layers 330, and the sacrificial layer 340 of the fourth sacrificial layers 340 located below the exposed one of the insulating layers 330 may be etched using the reduced photoresist pattern as an etching mask.

[0162] As the trimming process and the etching process are repeatedly performed, a molded part including a plurality of step layers and having a stepped shape may be formed in the first region I and the second region II of the first substrate 100, and the plurality of step layers may include a fourth sacrificial layer 340 and an insulating layer 330 stacked sequentially. Each of the "step layers" may be considered to include not only an exposed portion but also a portion thereof covered by an upper step layer, and thus may refer to the entire portion of each level of the fourth sacrificial layer 340 and the entire portion of the insulating layer 330. The exposed portion of the step layer that is not covered by the upper step layer may be referred to as a "step". In some example embodiments, steps may be arranged in the second direction and / or in the third direction in the second region II of the first substrate 100.

[0163] When the molding is formed, the fourth insulating interlayer pattern 260 in the third region III of the first substrate 100 may be exposed.

[0164] Reference Fig.24 , a fifth insulating interlayer 350 may be formed on the molding and the fourth insulating interlayer pattern 260 , and may be planarized until an upper surface of an uppermost one of the insulating layers 330 is exposed.

[0165] A sixth insulating interlayer 360 can be formed on the fifth insulating interlayer 350 and the topmost insulating layer 330 among the insulating layers 330, and the sixth insulating interlayer 360, the molding, the supporting layer 320 and the sacrificial layer structure 300 can be etched by an etching process to form a channel hole through which the upper surface of the second substrate 250 in the first region I of the first substrate 100 is exposed.

[0166] In some example embodiments, the etching process may be performed until the upper surface of the second substrate 250 is exposed, and further, the channel hole may extend through the upper portion of the second substrate 250. A plurality of channel holes may be formed to be spaced apart from each other in each of the second direction and the third direction, and the plurality of channel holes may form a channel hole array.

[0167] A charge storage structure 400 , a channel 410 , a filling pattern 420 , and a pad 430 may be formed in the channel hole.

[0168] Specifically, a charge storage structure layer and a channel layer can be formed on the sidewalls of the channel hole, the upper surface of the second substrate 250 exposed by the channel hole, and the sixth insulating interlayer 360, and a filling layer can be formed on the channel layer to fill the channel hole, and the filling layer, the channel layer, and the charge storage structure layer can be planarized until the upper surface of the sixth insulating interlayer 360 is exposed.

[0169] Through a planarization process, the charge storage structure 400 and the channel 410 may be sequentially stacked on the sidewall of the channel hole and the upper surface of the second substrate 250 , and the filling pattern 420 may fill the inner space formed by the channel 410 .

[0170] When the channel holes form a channel hole array, the channels 410 in the channel holes may also form a channel array.

[0171] In some example embodiments, the charge storing structure 400 may include a tunnel insulating pattern 390 , a charge storing pattern 380 , and a first barrier pattern 370 sequentially stacked from outer sidewalls of the channel 410 in a horizontal direction substantially parallel to an upper surface of the first substrate 100 .

[0172] The upper portions of the charge storage structure 400 , the channel 410 , and the filling pattern 420 may be removed to form a second recess, a pad layer may be formed on the sixth insulating interlayer 360 to fill the second recess, and may be planarized until the upper surface of the sixth insulating interlayer 360 is exposed to form a pad 430 .

[0173] Reference Fig.25 , a seventh insulating interlayer 440 can be formed on the sixth insulating interlayer 360 and the pad 430, and a tenth opening 450 can be formed, for example by a dry etching process, to pass through the sixth insulating interlayer 360 and the seventh insulating interlayer 440 and the molding in the first region I and the second region II of the first substrate 100.

[0174] The dry etching process may be performed until the tenth opening 450 exposes the upper surface of the support layer 320 or the support pattern 322, and further, the tenth opening 450 may extend through the upper portion of the support layer 320 or the support pattern 322. When the tenth opening 450 is formed, the insulating layer 330 and the fourth sacrificial layer 340 in the molding may be exposed.

[0175] In some example embodiments, the tenth opening 450 may extend in the second direction in the first region I and the second region II of the first substrate 100, and a plurality of tenth openings 450 may be formed in the third direction. When the tenth opening 450 is formed, the insulating layer 330 may be divided into a plurality of insulating patterns 335 each extending in the second direction, and the fourth sacrificial layer 340 may be divided into a plurality of fourth sacrificial patterns 345 each extending in the second direction.

[0176] The first spacer layer may be formed on the sidewalls of the tenth opening 450 and the upper surface of the seventh insulating interlayer 440 and may be anisotropically etched to form first spacers 460 on the sidewalls of the tenth opening 450. Thus, portions of the support layer 320 and the support pattern 322 may be exposed.

[0177] The exposed portions of the support layer 320 and the support pattern 322 and a portion of the sacrificial layer structure 300 thereunder may be removed to downwardly expand the tenth opening 450. Thus, the tenth opening 450 may expose the upper surface of the second substrate 250 and further extend through the upper portion of the second substrate 250.

[0178] In some example embodiments, the first spacer 460 may include undoped or doped amorphous silicon or polysilicon. When the sacrificial layer structure 300 is partially removed, the sidewalls of the tenth opening 450 may be covered by the first spacer 460, and thus the insulating pattern 335 and the fourth sacrificial pattern 345 in the mold may not be removed.

[0179] Reference Fig.26 and Fig. 27 The portion of the sacrificial layer structure 300 located in the first region I of the first substrate 100 may be removed through the tenth opening 450 , for example, by a wet etching process, thereby forming a first gap 470 .

[0180] For example, HF or H 3 PO 4 to perform a wet etching process.

[0181] When the first gap 470 is formed in the first region I of the first substrate 100, the lower portion of the support layer 320 adjacent to the tenth opening 450 and the upper portion of the second substrate 250 may be exposed. Additionally, a sidewall of a portion of the charge storage structure 400 may be exposed through the first gap 470, and the exposed sidewall of the portion of the charge storage structure 400 may also be removed during the wet etching process to expose a portion of the outer sidewall of the channel 410. Therefore, the charge storage structure 400 may be divided into an upper portion extending through the molding to cover most of the outer sidewall of the channel 410 and a lower portion covering the bottom and outer sidewall of the lower portion of the channel 410 on the second substrate 250.

[0182] When the first gap 470 is formed by the wet etching process, the support layer 320 and the support pattern 322 may not be removed, and thus, the molded part may not fall off.

[0183] Reference Fig.28 and Fig.29 , the first spacer 460 may be removed, and a channel connection layer may be formed on the sidewalls of the tenth opening 450 and in the first gap 470. A portion of the channel connection layer located in the tenth opening 450 may be removed by, for example, an etch-back process to form a channel connection pattern 480 in the first gap 470.

[0184] When the channel connection pattern 480 is formed, the channels 410 of the channels 410 located in the channel array may be connected to each other. An air gap 490 may be formed in the channel connection pattern 480.

[0185] Reference Fig.30 and Fig.31 , the fourth sacrificial pattern 345 exposed by the tenth opening 450 may be removed to form a second gap between the insulating patterns 335 adjacent in the first direction, and the outer sidewall of the first barrier pattern 370 may be partially exposed through the second gap.

[0186] In some example embodiments, the 3 PO 4 or H 2 SO 4 The fourth sacrificial pattern 345 is removed by a wet etching process.

[0187] A second barrier layer 500 may be formed on the exposed outer wall of the first barrier pattern 370, the inner wall of the second gap, the surface of the insulating pattern 335, the side wall and lower surface of a portion of the support layer 320, the side wall of the support pattern 322, the side wall of the channel connection pattern 480, the upper surface of the second substrate 250, and the upper surface of the seventh insulating interlayer 440, and a gate electrode layer may be formed on the second barrier layer 500.

[0188] The gate electrode layer may include a gate barrier layer and a gate conductive layer which are sequentially stacked.

[0189] The gate electrode layer may be partially removed to form a gate electrode in each of the second gaps. In some example embodiments, the gate electrode layer may be partially removed by a wet etching process.

[0190] In some example embodiments, the gate electrode may extend in the second direction, and a plurality of gate electrodes may be stacked in the first direction. In some example embodiments, a plurality of gate electrodes may be formed to be spaced apart from each other in the first direction. Additionally, a plurality of gate electrodes may be formed to be spaced apart from each other in the third direction. That is, a plurality of gate electrodes at the same level may be spaced apart from each other in the third direction through the tenth opening 450. The gate electrode may include a first gate electrode 512, a second gate electrode 514, and a third gate electrode 516 sequentially stacked in the first direction.

[0191] A second spacer 520 may be formed on a sidewall of the tenth opening 450 , and a common source pattern (CSP) 530 may be formed to fill the tenth opening 450 .

[0192] The second spacer 520 may be formed by forming a second spacer layer on the upper surface of the second substrate 250 exposed by the tenth opening 450, the sidewall of the tenth opening 450, and the upper surface of the seventh insulating interlayer 440, and anisotropically etching the second spacer layer; and the CSP 530 may be formed by forming a CSP layer on the upper surface of the second substrate 250 exposed by the tenth opening 450, the second spacer 520, and the seventh insulating interlayer 440; and planarizing the CSP layer until the upper surface of the seventh insulating interlayer 440 is exposed.

[0193] In some example embodiments, the CSP 530 may extend in the second direction, and the CSP 530 and the second spacers 520 on the sidewalls thereof may divide each of the first gate electrode 512 , the second gate electrode 514 , and the third gate electrode 516 in the third direction.

[0194] Reference Fig.32 , a first contact plug 542, a second contact plug 543, and a third contact plug 544 may be formed. The first contact plug 542 may extend through the fifth insulating interlayer 350, the sixth insulating interlayer 360, and the seventh insulating interlayer 440, the insulating pattern 335, and the second barrier layer 500 to contact one of the first gate electrode 512, the second gate electrode 514, and the third gate electrode 516 in the second region II of the first substrate 100. The second contact plug 543 may extend through the fifth insulating interlayer 350, the sixth insulating interlayer 360, and the seventh insulating interlayer 440, the support layer 320, and the sacrificial layer structure 300 to contact the upper surface of the second substrate 250 in the second region II of the first substrate 100. The third contact plug 544 may extend through the fifth, sixth, and seventh insulating interlayers 350 , 360 , and 440 , the fourth insulating interlayer pattern 260 , and the third insulating interlayer 240 to contact an upper surface of the sixth lower wiring 228 in the third region III of the first substrate 100 .

[0195] Reference Fig.18 and Fig.19, eighth to thirteenth insulating interlayers 560 , 580 , 600 , 620 , 640 , and 660 may be formed on the seventh insulating interlayer 440 , the CSP 530 , and the first, second, and third contact plugs 542 , 543 , and 544 . First to fifth upper contact plugs 572, 573, 574, 578 and 579, first to twelfth upper wirings 592, 593, 594, 598, 599, 632, 633, 634, 638, 639, 674, 679 and first to seventh upper vias 612, 613, 614, 618, 619, 654, 659 (which may extend through the eighth to thirteenth insulating interlayers 560, 580, 600, 620, 640 and 660 to be electrically connected to corresponding ones of the first contact plug 542, the second contact plug 543 and the third contact plug 544, the pad 430 and the CSP 530, respectively) may be formed to complete the manufacture of a vertical memory device.

[0196] Specifically, by referring to Figures 1 to 17B The first to twelfth upper wirings 592 , 593 , 594 , 598 , 599 , 632 , 633 , 634 , 638 , 639 , 674 , 679 are formed by the damascene process as shown and thus may have improved electrical characteristics without voids therein.

[0197] As noted above, although the inventive concept has been described with reference to a few example embodiments, those skilled in the art will readily appreciate that many modifications are possible to the various example embodiments without materially departing from the novel teachings and advantages of the inventive concept.

Claims

1. A wiring structure, comprising: a first metal pattern located on a substrate, the first metal pattern extending in a second direction parallel to an upper surface of the substrate and having a first width in a third direction parallel to the upper surface of the substrate and perpendicular to the second direction; a second metal pattern extending in the third direction to intersect the first metal pattern, the second metal pattern having a second width in the second direction; as well as a third metal pattern, which is located on the substrate at a region where the first metal pattern and the second metal pattern intersect each other, the third metal pattern being connected to the first metal pattern and the second metal pattern and having a substantially rectangular shape in a plan view, the third metal pattern having a recess in each corner thereof, the third metal pattern having a third width, the third width being defined as a minimum distance between opposite recesses of the third metal pattern in a fourth direction, the fourth direction being parallel to the upper surface of the substrate and forming an acute angle with each of the second direction and the third direction, wherein the third width is less than or equal to the smaller of the first width and the second width, wherein the first metal pattern has a first boundary surface at a center portion of the first metal pattern in the third direction, the first boundary surface extending in a first direction perpendicular to an upper surface of the substrate, and the third metal pattern has a third boundary surface at a center portion of the third metal pattern in the fourth direction, the third boundary surface extending in the first direction, and The bottom of the first boundary surface is farther away from the substrate than the bottom of the third boundary surface.

2. The wiring structure according to claim 1, wherein: The second metal pattern has a second boundary surface at a center portion of the second metal pattern in the second direction, the second boundary surface extending in the first direction, and The bottom of the second boundary surface is farther away from the substrate than the bottom of the third boundary surface.

3. The wiring structure according to claim 1, wherein: The first width is equal to or smaller than the second width.

4. The wiring structure according to claim 1, wherein: The concave portions of the third metal pattern are each defined by an arc segment.

5. The wiring structure according to claim 1, wherein: An angle of a sidewall of the first metal pattern in the third direction relative to an upper surface of the substrate is greater than an angle of a sidewall of each of the concave portions of the third metal pattern relative to the upper surface of the substrate.

6. The wiring structure according to claim 5, wherein: An angle of a sidewall of the second metal pattern in the second direction relative to an upper surface of the substrate is greater than an angle of a sidewall of each of the concave portions of the third metal pattern relative to the upper surface of the substrate. 7 . The wiring structure according to claim 1 , further comprising an insulating interlayer covering side walls of the first metal pattern to the third metal pattern on the substrate.

8. The wiring structure according to claim 7, in, Upper surfaces of the first to third metal patterns are higher than an upper surface of the insulating interlayer.

9. The wiring structure according to claim 1, wherein: An upper surface of each of the first to third metal patterns is substantially flat.

10. The wiring structure according to claim 1, wherein: The first to third metal patterns include the same material.

11. The wiring structure according to claim 10, wherein: Each of the first to third metal patterns includes tungsten, aluminum, or copper.

12. A wiring structure comprising: a first metal pattern located on a substrate, the first metal pattern extending in a second direction parallel to an upper surface of the substrate and having a first width in a third direction parallel to the upper surface of the substrate and perpendicular to the second direction; a second metal pattern extending in the third direction to intersect the first metal pattern and having a second width in the second direction; a third metal pattern located on the substrate at a region where the first metal pattern and the second metal pattern cross each other, wherein the third metal pattern is connected to the first metal pattern and the second metal pattern and has a substantially rectangular shape in a plan view; and an insulating spacer located on the substrate, wherein the insulating spacer is located at a central portion of the third metal pattern in a plan view and covers a sidewall of the third metal pattern, The third width is less than or equal to a smaller one of the first width and the second width, and the third width is defined as a minimum distance between a vertex of the third metal pattern and the insulating spacer.

13. The wiring structure according to claim 12, wherein: The insulating spacer has a circular or oval shape in a plan view.

14. The wiring structure according to claim 12, further comprising an insulating interlayer covering side walls of the first metal pattern to the third metal pattern on the substrate, in, The insulating spacer includes a same material as that of the insulating interlayer, and an upper surface of the insulating spacer is substantially coplanar with an upper surface of the insulating interlayer.

15. The wiring structure according to claim 14, wherein: An upper surface of each of the first to third metal patterns is substantially flat.

16. The wiring structure according to claim 15, wherein: Upper surfaces of the first to third metal patterns are higher than an upper surface of the insulating interlayer.

17. The wiring structure according to claim 12, wherein: The sidewall of the first metal pattern in the third direction has a first angle relative to the upper surface of the substrate, and the sidewall of the second metal pattern in the second direction has the first angle relative to the upper surface of the substrate, and The sidewall of the third metal pattern contacting the insulating spacer has a second angle relative to the upper surface of the substrate, and the second angle is smaller than the first angle.

18. The wiring structure according to claim 12, wherein: Each of the metal patterns has a boundary surface at a central portion thereof, and each of the boundary surfaces extends in a first direction perpendicular to an upper surface of the substrate.

19. The wiring structure according to claim 18, wherein: A bottom of each of boundary surfaces of the first metal pattern and the second metal pattern is farther from the substrate than a bottom of a boundary surface of the third metal pattern.

20. A wiring structure comprising: a first metal pattern located on a substrate, the first metal pattern extending in a second direction parallel to an upper surface of the substrate and having a first width in a third direction parallel to the upper surface of the substrate and perpendicular to the second direction; a second metal pattern extending in the third direction and having the first width in the second direction; as well as a third metal pattern located at a region where an end of the first metal pattern meets an end of the second metal pattern, the third metal pattern being connected to the first metal pattern and the second metal pattern and having a substantially triangular shape, wherein the second width is equal to or less than the first width, the second width being defined as a minimum distance from a vertex of the third metal pattern to an opposite edge thereof in a fourth direction, the fourth direction being parallel to the upper surface of the substrate and forming an acute angle with each of the second direction and the third direction, Each of the metal patterns has a respective boundary surface at its central portion, the boundary surface extending in a first direction perpendicular to the upper surface of the substrate, and The bottom of the boundary surface between the first metal pattern and the second metal pattern is farther away from the substrate than the bottom of the boundary surface of the third metal pattern.

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