Automatically configure output circuits

Abstract

The present invention provides an output circuit capable of automatic configuration, which includes a voltage driving circuit, a current driving circuit, an isolation circuit and an output stage circuit, wherein the output end of the voltage driving circuit is connected to the input end of the output stage circuit, and the output end of the current driving circuit is connected to the input end of the output stage circuit through an isolation circuit, and the isolation circuit has an input end and an output end. The output circuit of the present invention can automatically select one of the voltage driving circuit and the current driving circuit to work according to the characteristics of the device connected to the output circuit, so as to drive the device in a voltage-type or current-type manner. In addition, the output circuit of the present invention has a simple structure, fewer components, occupies less substrate space, is cheap, and does not require current compensation.

Description

Technical Field

[0001] The present invention relates to an output circuit, and in particular to an output circuit capable of automatically switching between two different output modes. Background Art

[0002] The operation of various devices in industrial control is driven by output circuits. Representative devices include valves, fans, actuators, etc. Due to the characteristics of the devices themselves, some devices in industrial control require voltage output to drive, while others require current output to drive. For the convenience of manufacturing, the output circuits currently provided include both voltage output and current output. In actual operation, the output circuit can select voltage output or current output according to the characteristics of the device. Summary of the invention

[0003] In order to solve the above problems, the present invention provides an output circuit that can be automatically configured, and can select voltage output or current output according to the characteristics of the device. In addition, the output circuit of the present invention has a simple structure, fewer components, occupies less substrate space, is cheap, and does not require current compensation.

[0004] According to one aspect of the present invention, the present invention provides an automatically configured output circuit, the output circuit comprising:

[0005] A voltage driving circuit, the voltage driving circuit is configured to generate a voltage driving signal, the voltage driving circuit having an output terminal;

[0006] A current driving circuit, the current driving circuit is configured to generate a current driving signal, the current driving circuit having an output terminal;

[0007] Isolation circuit;

[0008] The output stage circuit has an input terminal, the output terminal of the voltage driving circuit is connected to the input terminal of the output stage circuit, and the output terminal of the current driving circuit is connected to the input terminal of the output stage circuit through the isolation circuit.

[0009] According to another aspect of the present invention, the present invention provides an automatically configured output circuit, the output circuit comprising:

[0010] A voltage driving circuit, the voltage driving circuit is configured to generate a voltage driving signal, the voltage driving circuit having an output terminal;

[0011] A current driving circuit, the current driving circuit is configured to generate a current driving signal, the current driving circuit having an output terminal;

[0012] Isolation circuit;

[0013] The output stage circuit has an input terminal, the output terminal of the voltage driving circuit is connected to the input terminal of the output stage circuit through the isolation circuit, and the output terminal of the current driving circuit is connected to the input terminal of the output stage circuit.

[0014] In one embodiment, the isolation circuit comprises a two-terminal isolation circuit. In another embodiment, the isolation circuit comprises a unidirectional isolation circuit. In another embodiment, the isolation circuit is a diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1A A block diagram structure of an embodiment of an output circuit according to the present invention is shown;

[0016] Figure 1B A block diagram structure of another embodiment of an output circuit according to the present invention is shown;

[0017] Figure 2A Shown according to Figure 1A Details of an exemplary circuit diagram of each module of an embodiment of an output circuit 100 of the present invention are shown;

[0018] Figure 2B Shown according to Figure 1B Details of an exemplary circuit diagram of each module of an embodiment of an output circuit 100 of the present invention are shown;

[0019] Figure 3A The specific circuit structure of the voltage-dividing offset circuit 201 is shown when the input signal Sin is an analog signal;

[0020] Figure 3B The specific circuit structure of the voltage-dividing offset circuit 201 is shown when the input signal Sin is a changing PWM signal;

[0021] Figure 4A A specific structure of the offset control circuit 202 is shown; and

[0022] Figure 4B Another specific structure of the offset control circuit 202 is shown. DETAILED DESCRIPTION

[0023] Various specific embodiments of the present invention will be described below with reference to the accompanying drawings which constitute a part of this specification. It should be understood that, where possible, the same or similar reference numerals used in the present invention refer to the same components.

[0024] Figure 1Ais a block diagram structure 100 of an embodiment of an output circuit according to the present invention, and Figure 1B FIG. 1 is a block diagram of another embodiment of an output circuit according to the present invention.

[0025] like Figure 1A As shown, the automatically configured output circuit 100 includes an offset configuration circuit 101, a voltage driving circuit 102, a current driving circuit 103, an isolation circuit 104 and an output stage circuit 105. Figure 1A To introduce the functions of each module, as well as the connection and coordination relationships between modules.

[0026] exist Figure 1A In the present application, when the voltage driving circuit 102 operates together with the output stage circuit 105 to control the voltage output to the output device 106, thereby driving the output device 106, it is called a voltage-type driving output device 106; when the current driving circuit 103 operates together with the output stage circuit 105 to control the current output to the output device 106, thereby driving the output device 106, it is called a current-type driving output device 106. In the present application, when the output device 106 is connected to the output stage circuit 105, based on the characteristics of the output device 106 (e.g., resistance) and the feedback received from the output stage circuit 105, one of the voltage driving circuit 102 and the current driving circuit 103 is automatically selected to operate together with the output stage circuit 105 to drive the output device 106. Therefore, the present application relates to automatically selecting a voltage-type driving output device 106 or a current-type driving output device 106.

[0027] In order to realize automatic selection of voltage-type drive output device 106 or current-type drive output device 106, it is necessary to input the input signal to voltage drive circuit 102 and current drive circuit 103 at the same time, because in this way, output circuit 100 can automatically select whether output device 106 is driven by voltage drive circuit 102 or current drive circuit 103 based on the characteristics of output device 106. As known to those skilled in the art, in some applications, power (e.g., voltage or current) varying within a certain range is usually provided to output device 106 to meet the drive required by output device 106, so the input signal output to voltage drive circuit 102 and current drive circuit 103 needs to be limited to change within a certain range accordingly. For voltage-type drive output device 106 and current-type drive output device 106, the power (e.g., voltage or current) required to be provided to output device 106 usually varies within different ranges, so this may make the variation range of the input signal required to be output to voltage drive circuit 102 different from the variation range of the input signal required to be output to current drive circuit 103. For example, if for a voltage-type driven output device 106, it may be necessary to provide a voltage varying in the range of 0-10V to drive the output device 106, and for a current-type driven output device 106, it may be necessary to provide a current varying in the range of 4-20mA to drive the output device 106, then this may result in the need to provide an input voltage varying in the range of 0-5V to the voltage driving circuit 102 when the voltage-type driven output device 106 is used, and the need to provide an input voltage varying in the range of 1-5V to the current driving circuit 103 when the current-type driven output device 106 is used, that is, the variation range of the input voltage is different when the voltage-type driven output device 106 is used and the current-type driven output device 106 is used. Therefore, in order to solve this problem, the present application appropriately offsets the same input signal so that when the voltage-type driving output device 106 is used, the input signals provided to the voltage driving circuit 102 and the current driving circuit 103 at the same time vary within a first range, and when the current-type driving output device 106 is used, the input signals provided to the voltage driving circuit 102 and the current driving circuit 103 at the same time vary within a second range (different from the first range), thereby meeting the different requirements of the voltage-type driving output device 106 and the current-type driving output device 106.

[0028] In one embodiment, in order to solve the above problem, the present application Figure 1AAn offset configuration circuit 101 is provided, and its function is: when the voltage driving circuit 102 drives the output device 106, the offset configuration circuit 101 offsets the input signal Sin that varies within a certain range into a signal that varies within a first range; when the current driving circuit 103 drives the output device 106, the offset configuration circuit 101 offsets the input signal Sin that varies within a certain range into a signal that varies within a second range, and the first range and the second range are different. It should be noted that if the power (for example, voltage or current) required to be provided to the output device 106 by the voltage-type driving output device 106 and the current-type driving output device 106 varies within the same range, then there is no need to provide the offset configuration circuit 101, and it is only necessary to provide the required input signal Sin that varies within the same range to the output device 106.

[0029] like Figure 1A As shown, the offset configuration circuit 101 has an input terminal, a control input terminal and an output terminal. The input terminal of the offset configuration circuit 101 receives an external input signal Sin through a connecting line 111. The input signal Sin can be a changing analog voltage signal or a changing analog current signal. In some embodiments, the external input signal Sin can be generated in the following manner: in an air-conditioning system, a temperature sensor detects the ambient temperature and converts the ambient temperature into a voltage signal, and the MCU receives the voltage signal from the temperature sensor and generates an input control signal based on the voltage signal. The input control signal (which can be the input signal Sin of the present application) is input to the drive circuit to drive the output device 106. It should be noted that the external input signal Sin of the present application can also be generated in other ways.

[0030] The output end of the offset configuration circuit 101 is connected to the input end of the voltage driving circuit 102 via the connection lines 123 and 112 and is connected to the input end of the current driving circuit 103 (i.e., the input end of the current control circuit 107) via the connection lines 123 and 113. When the output device 106 needs the voltage driving circuit 102 to drive, the offset configuration circuit 101 performs a first offset on the input signal Sin that varies within a certain range to output an offset input signal Vin that varies within a first range; when the output device 106 needs the current driving circuit 103 to drive, the offset configuration circuit 101 performs a second offset on the input signal Sin that varies within a certain range to output an offset input signal Vin that varies within a second range, and the first range is different from the second range. The offset configuration circuit 101 outputs the offset input signal Vin to the input end of the voltage driving circuit 102 via the connection lines 123 and 112 and to the input end of the current driving circuit 103 via the connection lines 123 and 113.

[0031] In one embodiment, the control input terminal of the offset configuration circuit 101 is connected to the control output terminal of the voltage driving circuit 102 via the connection line 126, and is used to receive the intermediate voltage driving signal Dr1' output by the voltage driving circuit 102. In addition, the offset configuration circuit 101 performs a first or second offset on the input signal Sin according to the intermediate voltage driving signal Dr1' (which is a high level or a low level) received at the control input terminal. For example, when the intermediate voltage driving signal Dr1' is a high level, the offset configuration circuit 101 performs a first offset on the input signal Sin; when the intermediate voltage driving signal Dr1' is a low level, the offset configuration circuit 101 performs a second offset on the input signal Sin. In another embodiment, when the intermediate voltage driving signal Dr1' is a low level, the offset configuration circuit 101 performs a first offset on the input signal Sin; when the intermediate voltage driving signal Dr1' is a high level, the offset configuration circuit 101 performs a second offset on the input signal Sin.

[0032] In another embodiment, the control input terminal of the offset configuration circuit 101 is connected via the connection line 116 (eg Figure 1A The control input terminal 101 is connected to the output terminal of the current driving circuit 103 (as shown by the dotted line) for receiving the current driving signal Dr2 output by the current driving circuit 103. Furthermore, the offset configuration circuit 101 performs a first or second offset on the input signal Sin according to the current driving signal Dr2 (which is a high level or a low level) received at the control input terminal. The offset of the offset configuration circuit 101 is similar to the working mode of the offset configuration circuit 101 performing a first or second offset on the input signal Sin based on the intermediate voltage driving signal Dr1'. Since the intermediate voltage driving signal Dr1' output by the voltage driving circuit 102 and the current driving signal Dr2 output by the current driving circuit 103 can indicate whether the output device 106 is driven by the voltage driving circuit 102 or the current driving circuit 103, the offset configuration circuit 101 performs a first or second offset on the input signal Sin based on whether the output device 106 needs to be driven by the voltage driving circuit 102 or the current driving circuit 103.

[0033] In some embodiments, the input signal Sin may also be a PWM signal with a voltage change. In this case, the offset configuration circuit 101 further includes a D / A conversion circuit, which converts the PWM signal into an analog signal. In addition, the offset configuration circuit 101 also performs the above-described analog signal offset operation on the converted analog signal. In other embodiments, the input signal Sin may also be a PWM signal with a current change.

[0034] Figure 1AThe voltage driving circuit 102 in the embodiment has an input terminal, a feedback input terminal, a control output terminal and an output terminal. The input terminal of the voltage driving circuit 102 is connected to the output terminal of the offset configuration circuit 101 through connection lines 123 and 112 to receive the offset input signal Vin output by the offset configuration circuit 101; the output terminal of the voltage driving circuit 102 is connected to the input terminal of the output stage circuit 105 through connection line 114. The function of the voltage driving circuit 102 is to receive the offset input signal Vin from the offset configuration circuit 101, generate a voltage driving signal Dr1 based on the offset input signal Vin, and output the voltage driving signal Dr1 to the output stage circuit 105 through connection line 114. The feedback input terminal of the voltage driving circuit 102 receives a voltage-type output feedback signal from the output terminal of the output stage circuit 105 through connection line 120, and the function of the voltage-type output feedback signal is to make the voltage driving circuit 102 work or not work. The operation of the voltage driving circuit 102 means that the voltage driving circuit 102 outputs the voltage driving signal Dr1 to the output stage circuit 105 to control the output stage circuit 105 to provide power output to the output device 106. In one embodiment, if the offset configuration circuit 101 performs the first or second offset on the input signal Sin based on the intermediate voltage driving signal Dr1', the control output terminal of the voltage driving circuit 102 outputs the intermediate voltage driving signal Dr1' to the control input terminal of the offset configuration circuit 101 through the connection line 126 to control the offset configuration circuit 101 to perform the first or second offset on the input signal Sin.

[0035] Figure 1AThe current driving circuit 103 in the embodiment has an input terminal, a feedback input terminal and an output terminal. The input terminal of the current driving circuit 103 is connected to the output terminal of the offset configuration circuit 101 through connecting lines 113 and 123 to receive the offset input signal Vin output by the offset configuration circuit 101; the output terminal of the current driving circuit 103 is connected to the input terminal of the isolation circuit 104 through connecting line 115. The function of the current driving circuit 103 is to generate a current driving signal Dr2 in response to the offset input signal Vin, and output the current driving signal Dr2 to the output stage circuit 105 through the isolation circuit 104. The feedback input terminal of the current driving circuit 103 receives a current-type output feedback signal from the current-type feedback output terminal of the output stage circuit 105 through the connecting line 121, and the function of the current-type output feedback signal is to make the current driving circuit 103 work or not work. The operation of the current driving circuit 103 means that the current driving circuit 103 outputs the current driving signal Dr2 to the output stage circuit 105 to control the output stage circuit 105 to provide power output to the output device 106. In one embodiment, if the offset configuration circuit 101 performs a first or second offset on the input signal Sin based on the current drive signal Dr2, the output end of the current drive circuit 103 outputs the current drive signal Dr2 to the control input end of the offset configuration circuit 101 through the connecting line 116 to control the offset configuration circuit 101 to perform the first or second offset on the input signal Sin.

[0036] and, Figure 1A The current driving circuit 103 in the embodiment includes a current control circuit 107 and a feedback differential amplifier circuit 108. The current control circuit 107 includes an input terminal, a feedback amplifier input terminal and an output terminal. The input terminal of the current control circuit 107 is the input terminal of the current driving circuit 103, and the output terminal of the current control circuit 107 is the output terminal of the current driving circuit 103. The function of the current control circuit 107 is to generate a current driving signal Dr2 in response to the offset input signal Vin, and output the current driving signal Dr2 to the output stage circuit 105 through the isolation circuit 104. The feedback amplifier input terminal of the current control circuit 107 receives an amplified feedback signal from the feedback differential amplifier circuit 108 through the connection line 122, and the function of the amplified feedback signal is to make the current control circuit 107 work or not work.

[0037] The feedback differential amplifier circuit 108 includes a feedback input terminal and a feedback amplifier output terminal. The feedback input terminal of the feedback differential amplifier circuit 108 (i.e., the feedback input terminal of the current driving circuit 103) receives the current-type output feedback signal from the output stage circuit 105 through the connection line 121; the feedback amplifier output terminal of the feedback differential amplifier circuit 108 is connected to the feedback amplifier input terminal of the current control circuit 107. The function of the feedback differential amplifier circuit 108 is to proportionally amplify the received current-type output feedback signal and output the amplified feedback signal to the feedback amplifier input terminal of the current control circuit 107 to control the current control circuit 107 to work or not work.

[0038] Figure 1A The isolation circuit 104 in the embodiment has an input terminal and an output terminal, wherein the input terminal of the isolation circuit 104 is connected to the output terminal of the current driving circuit 103 through the connection line 115 to receive the current driving signal Dr2, and the output terminal of the isolation circuit 104 is connected to the output terminal of the voltage driving circuit 102 through the connection line 114 and is connected to the input terminal of the output stage circuit 105 through the connection line 117. The function of the isolation circuit 104 is: when the current driving circuit 103 is in the working state, the current driving circuit 103 drives the output stage circuit 105 via the isolation circuit 104, and the voltage driving circuit 102 is in the non-working state at this time; when the voltage driving circuit 102 is in the working state, since the output of the current driving circuit 103 is also connected to the input terminal of the output stage circuit 105, the isolation circuit 104 disconnects the output of the current driving circuit 103 from the output stage circuit 105 to prevent the output of the current driving circuit 103 from controlling the driving of the output stage circuit 105. It should be noted that the output of the current driving circuit 103 has the property of low impedance, and the output of the voltage driving circuit 102 has the property of high impedance. Therefore, when the voltage driving circuit 102 is working and the current driving circuit 103 is not working, if the current driving circuit 103 is not disconnected through the isolation circuit 104, the low impedance property of the output of the current driving circuit 103 will make it impossible to disconnect the current driving circuit 103 from the output stage circuit 105. However, when the voltage driving circuit 102 is not working and the current driving circuit 103 is working, the high impedance property of the output of the voltage driving circuit 102 will disconnect the voltage driving circuit 102 from the output stage circuit 105, thereby not affecting the current driving circuit 103 driving the output stage circuit 105. Therefore, in this case, it is not necessary to disconnect the voltage driving circuit 102 through the isolation circuit 104.

[0039] It should be noted that when the current driving circuit 103 is not working and the voltage driving circuit 102 is working, the voltage at the input end of the isolation circuit 104 (i.e., the output end of the current driving circuit 103) is lower than the voltage at the output end of the isolation circuit 104 (i.e., the output end of the voltage driving circuit 102). Because when the output device 106 is driven by the voltage driving circuit 102 but not by the current driving circuit 103, based on the characteristics (e.g., impedance) of the output device 106 connected to the output stage circuit 105, the voltage-type output feedback signal received by the voltage driving circuit 102 from the output stage circuit 105 and the current-type output feedback signal received by the current driving circuit 103 from the output stage circuit 105 will make the voltage output by the current driving circuit 103 always lower than the voltage output by the voltage driving circuit 102. Therefore, the inventors used a unidirectional isolation device, specifically a diode.

[0040] Figure 1A The output stage circuit 105 in the embodiment has an input terminal, a first output terminal (device identification input terminal), a second output terminal (device identification input terminal) and a current type feedback output terminal. The input terminal of the output stage circuit 105 is connected to the output terminal of the voltage driving circuit 102 through a connection line 114 and is connected to the output terminal of the isolation circuit 104 through a connection line 117 to receive the voltage driving signal Dr1 output by the voltage driving circuit 102 or the current driving signal Dr2 output by the current driving circuit 103. The first output terminal of the output stage circuit 105 is connected to the output device 106 through a connection line 118 and the second output terminal of the output stage circuit 105 is connected to the output device 106 through a connection line 119 to output the driving output voltage Vout and the driving output current Iout to the output device 106. When the output device 106 is connected to the output stage circuit 105, the output device 106 can identify the characteristics (e.g., resistance) (device identification information) of the output device 106 through the connection lines 118 and 119, and at this time, the output terminal of the output stage circuit 105 should be called the device identification input terminal. The first output terminal of the output stage circuit 105 is connected to the feedback input terminal of the voltage driving circuit 102 through the connection line 120 to output a voltage-type output feedback signal (Vout) to the voltage driving circuit 102, and the current-type feedback output terminal of the output stage circuit 105 is connected to the feedback input terminal of the current driving circuit 103 through the connection line 121 to output a current-type output feedback signal to the current driving circuit 103. The function of the output stage circuit 105 is: to drive the output device 106 based on the voltage driving signal Dr1 received from the voltage driving circuit 102 or the current driving signal Dr2 received from the current driving circuit 103; and to output a voltage-type output feedback signal to the voltage driving circuit 102 and a current-type output feedback signal to the current driving circuit 103 based on the device identification information received from the output device 106, thereby automatically selecting one of the voltage driving circuit 102 and the current driving circuit 103 to work.

[0041] It should be noted that when the voltage driving circuit 102 drives the output stage circuit 105, the output characteristic of the entire circuit is a voltage-type driving output device 106. When the current driving circuit 103 drives the output stage circuit 105, the output characteristic of the entire circuit is a current-type driving output device 106. Specifically, when the voltage driving circuit 102 drives the output stage circuit 105, the voltage output from the output stage circuit 105 to the output device 106 is controlled by the input voltage Sin and the voltage driving circuit 102, which is called driving the output device 106 in a voltage-type manner; when the current driving circuit 103 drives the output stage circuit 105, the current output from the output stage circuit 105 to the output device 106 is controlled by the input voltage Sin and the current driving circuit 103, which is called driving the output device 106 in a current-type manner.

[0042] Figure 1B The structure of the output circuit 100 is similar to Figure 1A The structure of the output circuit 100 in is basically the same, except that: Figure 1A The isolation circuit 104 is connected between the current driving circuit 103 and the output stage circuit 105, and Figure 1B The isolation circuit 104 in FIG. 1 is connected between the voltage driving circuit 102 and the output stage circuit 105. Therefore, Figure 1B The functions of the modules of the output circuit 100, and the connection and coordination relationships between the modules are similar to Figure 1A Basically the same. The difference is: Figure 1B In one embodiment, the output terminal of the voltage driving circuit 102 is connected to the control input terminal of the offset configuration circuit 101 through the connection line 126 to output the voltage driving signal Dr1 to the offset configuration circuit 101, thereby controlling the offset configuration circuit 101 to perform the first or second offset on the input signal Sin; in another embodiment, the current driving circuit 103 includes a control output terminal (i.e., the control output terminal of the current control circuit 107), which is connected to the control input terminal of the offset configuration circuit 101 through the connection line 116 to output the intermediate current driving signal Dr2' to the offset configuration circuit 101, thereby controlling the offset configuration circuit 101 to perform the first or second offset on the input signal Sin. Another difference is that: in Figure 1BIn the embodiment, the output of the voltage driving circuit 102 has a low impedance property, while the output of the current driving circuit 103 has a high impedance property, so that: when the voltage driving circuit 102 is working and the current driving circuit 103 is not working, the high impedance property of the output of the current driving circuit 103 can disconnect the current driving circuit 103 from the output stage circuit 105; when the current driving circuit 103 is working and the voltage driving circuit 102 is not working, the voltage driving circuit 102 is disconnected from the output stage circuit 105 through the isolation circuit 104.

[0043] Figure 2A Based on Figure 1A Details of an exemplary circuit diagram of each module of an embodiment of an output circuit 100 of the present invention are shown; Figure 2B Based on Figure 1B Detail of an exemplary circuit diagram of each module of an embodiment of the output circuit 100 of the present invention is shown.

[0044] Figure 2A Included Figure 1A All circuit modules of the output circuit 100 automatically configured in the embodiment include the offset configuration circuit 101, the voltage driving circuit 102, the current driving circuit 103, the isolation circuit 104 and the output stage circuit 105. However, each component and the connection relationship between the components are shown in each corresponding block diagram. For the purpose of convenience of explanation, Figure 2A Each element of the offset configuration circuit 101 and the connection relationship between the elements are as follows: Figure 3A , 3B , 4A, and 4B are shown in more detail.

[0045] Figure 2AThe offset configuration circuit 101 in the embodiment includes a voltage-dividing offset circuit 201 and an offset control circuit 202. The voltage-dividing offset circuit 201 has an input terminal, two voltage-dividing control input terminals and an output terminal. The input terminal of the voltage-dividing offset circuit 201 receives an external input signal Sin through a connecting line 111, and the output terminal of the voltage-dividing offset circuit 201 is connected to the input terminal of the voltage driving circuit 102 through connecting lines 123 and 112 and to the input terminal of the current driving circuit 103 through connecting lines 123 and 113. The function of the voltage-dividing offset circuit 201 is to offset the input signal Sin that varies within a certain range to vary within another different range to output an offset input signal Vin through voltage division of resistors, and output the offset input signal Vin to the voltage driving circuit 102 and the current driving circuit 103. The two voltage-dividing control input terminals of the voltage-dividing offset circuit 201 are connected to the two voltage-dividing control output terminals of the offset control circuit 202 through connecting lines 203 and 204, respectively, so as to receive the voltage-dividing control signal from the offset control circuit 202 to generate different voltage-dividing characteristics. In operation, the voltage-dividing offset circuit 201 can perform a first offset on the input signal Sin that varies within the same range based on the received voltage-dividing control signal to generate an offset input signal Vin that varies within a first range, or perform a second offset to generate an offset input signal Vin that varies within a second range, wherein the first range is different from the second range, and the first range and the second range are also different from the same range mentioned above. Figure 1A As described in the description, the offset operation of the offset configuration circuit 101 (i.e., the offset of the voltage divider offset circuit 201) is to offset the input signal Sin that varies within the same range to vary within a different range, so that when the output device 106 is driven by the voltage driving circuit 102 or the current driving circuit 103, the power output to the output device 106 varies within a different range, so as to meet the different power requirements of driving the output device 106 in a voltage-type manner and driving the output device 106 in a current-type manner.

[0046] Figure 2AThe offset control circuit 202 in the embodiment has a control input terminal and two voltage-dividing control output terminals. The control input terminal of the offset control circuit 202 is connected to the control output terminal of the voltage driving circuit 102 through the connection line 126 to receive the intermediate voltage driving signal Dr1' from the voltage driving circuit 102; or the control input terminal of the offset control circuit 202 is connected to the output terminal of the current driving circuit 103 through the connection line 116 to receive the voltage driving signal Dr2 from the current driving circuit 103. The two voltage-dividing control output terminals of the offset control circuit 202 are respectively connected to the two voltage-dividing control input terminals of the voltage-dividing offset circuit 201 through the connection lines 203 and 204. The function of the offset control circuit 202 is to generate a voltage-dividing control signal based on the received intermediate voltage driving signal Dr1' or the voltage driving signal Dr2, and output the voltage-dividing control signal to the voltage-dividing offset circuit 201 to control the voltage-dividing offset circuit 201 to perform the first or second offset on the input signal Sin.

[0047] Figure 2A The voltage division offset circuit 201 of the offset configuration circuit 101 includes Figure 3A and 3B The specific circuit structure shown in Figure 2A The offset control circuit 202 of the offset configuration circuit 101 includes Figure 4A and 4B The specific circuit structure shown. Figure 3A 2 shows the specific circuit structure of the voltage-dividing offset circuit 201 when the input signal Sin is an analog signal. Figure 3B The specific circuit structure of the voltage division offset circuit 201 is shown when the input signal Sin is a changing PWM signal. Figure 4A A specific structure of the offset control circuit 202 is shown. Figure 4B Another specific structure of the offset control circuit 202 is shown.

[0048] Figure 2A The offset configuration circuit 101 in the embodiment includes the following embodiments: In the first embodiment, the offset configuration circuit 101 includes Figure 3A The voltage divider offset circuit 201 shown in FIG. Figure 4A In the second embodiment, the offset configuration circuit 101 includes the following Figure 3A The voltage divider offset circuit 201 shown in FIG. Figure 4B In the third embodiment, the offset configuration circuit 101 includes the following Figure 3B The voltage divider offset circuit 201 shown in FIG. Figure 4A In the fourth embodiment, the offset configuration circuit 101 includes the following Figure 3B The voltage divider offset circuit 201 shown in FIG. Figure 4BThe offset control circuit 202 is shown.

[0049] As mentioned above, in the first embodiment, the offset configuration circuit 101 includes: Figure 3A The voltage divider offset circuit 201 shown in FIG. Figure 4A The offset control circuit 202 shown. Specifically, Figure 3A The input signal Sin in is a changing analog signal, and Figure 3A The voltage-dividing offset circuit 201 in the embodiment includes a resistor R1, a resistor R2, and a resistor R3. The resistors R2, R3, and R1 are connected in series between a power supply and an input signal Sin, wherein a first end of the resistor R2 is connected to the power supply, a second end of the resistor R2 is connected to a first end of the resistor R3, a second end of the resistor R3 is connected to a first end of the resistor R1, and a second end of the resistor R1 (i.e., an input end of the voltage-dividing offset circuit 201) is connected to the input signal Sin via a connecting line 111. The first end and the second end of the resistor R2 (i.e., two voltage-dividing control input ends of the voltage-dividing offset circuit 201) are connected to the input signal Sin via connecting lines 203 and 204, respectively. Figure 4A The source and drain of the switch element Q2 in the embodiment are connected (i.e., the two voltage-dividing control output terminals of the offset control circuit 202) (see Figure 2A ), the connection between the resistor R3 and the resistor R1 (ie, the output end of the voltage-dividing offset circuit 201) outputs the offset input signal Vin to the voltage driving circuit 102 and the current driving circuit 103 through the connecting line 123.

[0050] And, in the first embodiment, Figure 4A The offset control circuit 202 in the voltage-dividing offset circuit 201 includes a switch element Q2, which is a P-channel field effect transistor. The source and drain of the P-channel field effect transistor Q2 are connected to the first end and the second end of the resistor R2 in the voltage-dividing offset circuit 201 through connecting lines 203 and 204, respectively (see Figure 3A The gate of the P-channel field effect transistor Q2 is connected to the control output terminal of the voltage driving circuit 102 through the connection line 126 to receive the intermediate voltage driving signal Dr1′ output by the voltage driving circuit 102.

[0051] In the first embodiment, when the voltage driving circuit 102 is in the working state (at this time, the current driving circuit 103 is in the non-working state), the intermediate voltage driving signal Dr1' output by the voltage driving circuit 102 is at a high level, and the P-channel field effect transistor Q2 is disconnected. Then, the resistors R2, R3, and R1 in the voltage dividing offset circuit 201 are connected in series between the power supply and the input signal Sin (see Figure 3A), at this time, the offset configuration circuit 101 performs a first offset on the input signal Sin to output an offset input signal Vin that varies within a first range. When the voltage driving circuit 102 is in an off-state (at this time, the current driving circuit 103 is in an on-state), the intermediate voltage driving signal Dr1' output by the voltage driving circuit 102 is at a low level, the P-channel field effect transistor Q2 is turned on, and the resistor R2 (see Figure 3A ) is short-circuited, then in the voltage-dividing offset circuit 201, only the resistor R3 and the resistor R1 are connected in series between the power supply and the input signal Sin (see Figure 3A ), at this time, the offset configuration circuit 101 performs a second offset on the input signal Sin to output the offset input signal Vin that varies within the second range. That is, when the voltage driving circuit 102 is in a working or non-working state, the resistor R2 is connected or not connected to the voltage division offset circuit 201, so that the voltage division offset circuit 201 generates different voltage division characteristics to perform different offsets (i.e., the first or second offset) on the input signal Sin.

[0052] In some embodiments, the input signal Sin is an analog voltage signal varying in the range of 0-5V, the power supply provides a voltage of 5V, the resistance of the resistor R2 is 475KΩ, the resistance of the resistor R3 is 20KΩ, and the resistance of the resistor R1 is 4.99KΩ. Therefore, according to the voltage division principle of the resistor, when the voltage driving circuit 102 is in the working state so that the resistors R2, R3 and R1 are connected in series between the power supply and the input signal Sin, the offset (first offset) input voltage Vin output at the connection between the resistor R3 and the resistor R1 is: Vin=0.99Sin+0.05. At this time, the offset configuration circuit 101 performs a first offset on the input signal Sin to output an offset input voltage Vin varying in the range of 0.05-5V. It should be noted that, in an ideal state, the offset configuration circuit 101 may need to perform a first offset on the input signal Sin to output an offset input voltage Vin that varies in the range of 0-5V, but in reality, the offset input voltage Vin that varies in the range of 0.05-5V is output. However, the error generated by the actual value (0.05-5V) is very small, and has little effect on the output of the output stage circuit, which can be ignored. When the voltage driving circuit 102 is in a non-operating state so that the resistors R3 and R1 are connected in series between the power supply and the input signal Sin, the offset (second offset) input voltage Vin output at the connection between the resistor R3 and the resistor R1 is: Vin=0.8Sin+1. At this time, the offset configuration circuit 101 performs a second offset on the input signal Sin to output an offset input voltage Vin that varies in the range of 1-5V.

[0053] As mentioned above, in the second embodiment, the offset configuration circuit 101 includes: Figure 3A The voltage divider offset circuit 201 shown in FIG. Figure 4B The offset control circuit 202 shown. The structure, function, connection and coordination relationship of each element in the second embodiment are the same as those in the first embodiment. The difference is that the offset control circuit 202 used in the first embodiment is a P-channel field effect transistor, and the gate of the P-channel field effect transistor is connected to the control output end of the voltage driving circuit 102 through the connecting line 126 to receive the intermediate voltage driving signal Dr1' output by the voltage driving circuit 102. Therefore, the first embodiment performs the first or second offset on the input signal Sin according to the output of the voltage driving circuit 102. The offset control circuit 202 used in the second embodiment is an N-channel field effect transistor, and the gate of the N-channel field effect transistor is connected to the output end of the current driving circuit 103 through the connecting line 116 to receive the voltage driving signal Dr2 output by the current driving circuit 103. Therefore, the second embodiment performs the first or second offset on the input signal Sin according to the output of the current driving circuit 103.

[0054] More specifically, in the second embodiment, Figure 4B The offset control circuit 202 in the voltage-dividing offset circuit 201 includes a switch element Q2, which is an N-channel field effect transistor. The drain and source of the N-channel field effect transistor Q2 are connected to the first end and the second end of the resistor R2 in the voltage-dividing offset circuit 201 through connecting lines 203 and 204, respectively (see Figure 3A ). The gate of the N-channel field effect transistor Q2 is connected to the output end of the current driving circuit 103 through the connecting line 116 to receive the voltage driving signal Dr2 output by the current driving circuit 103. When the current driving circuit 103 is in the working state (at this time, the voltage driving circuit 102 is in the non-working state), the current driving signal Dr2 output by the current driving circuit 103 is at a high level, and the N-channel field effect transistor Q2 (see Figure 4B ) is turned on, the resistor R2 (see Figure 3A ) is short-circuited, then in the voltage-dividing offset circuit 201, only the resistor R3 and the resistor R1 are connected in series between the power supply and the input signal Sin (see Figure 3A ), at this time, the offset configuration circuit 101 performs a second offset on the input signal Sin to output the offset input signal Vin that varies within the second range. When the current driving circuit 103 is in the non-operating state (at this time, the voltage driving circuit 102 is in the operating state), the current driving signal Dr2 output by the current driving circuit 103 is at a low level, and the N-channel field effect transistor Q2 (see Figure 4B ) is disconnected, the resistors R2, R3 and R1 in the voltage-dividing offset circuit 201 are connected in series between the power supply and the input signal Sin (see Figure 3A), at this time, the offset configuration circuit 101 performs a first offset on the input signal Sin to output an offset input signal Vin that varies within a first range.

[0055] In the third and fourth embodiments, Figure 3B The input signal Sin in is a changing PWM signal, and Figure 4A and Figure 4B The structure and function of the elements and their connection and matching relationships are the same as those in the first and second embodiments. Figure 3B The structure and function of the components in the voltage divider offset circuit 201 and their connection and coordination relationship are similar to Figure 3A Basically the same, except that: Figure 3B The voltage division offset circuit 201 in the embodiment further includes a D / A conversion circuit for converting the input PWM signal into an analog signal. Figure 3A same, Figure 3B The voltage division offset circuit 201 in the embodiment also performs a first or second offset on the input signal to output an offset (analog) input signal Vin that varies within a first or second range.

[0056] and Figure 3A Compared with the voltage divider offset circuit 201, Figure 3B The voltage-dividing offset circuit 201 in the embodiment also includes a resistor R4 and a capacitor C1, wherein the connection between the resistor R3 and the resistor R1 is connected to the first end of the capacitor C1 and the first end of the resistor R4, the second end of the capacitor C1 is grounded, and the second end of the resistor R4 outputs the offset input signal Vin to the voltage driving circuit 102 and the current driving circuit 103 through the connecting line 123. The resistor R1 and the capacitor C1 form a D / A conversion circuit for filtering the inputted changing PWM signal Sin to generate an analog signal. In addition, since the capacitor C1 is connected to the inverting input terminal of the voltage output operational amplifier OA1 of the voltage driving circuit 102 and the current output operational amplifier OA2 of the current driving circuit 103 (see Figure 2A ), so it is easy to cause the outputs of the voltage output operational amplifier OA1 and the current output operational amplifier OA2 to oscillate. In one embodiment, the present invention connects a resistor R4 between the capacitor C1 and the voltage output operational amplifier OA1 and the current output operational amplifier OA2 to prevent the outputs of the voltage output operational amplifier OA1 and the current output operational amplifier OA2 from oscillating. In another embodiment, the resistor R4 may not be connected to reduce the number of components in the output circuit.

[0057] In one embodiment, Figure 3B The high level of the PWM signal Sin input is 5V, the low level is 0V, and the duty cycle is D. Figure 3BIf there is no capacitor C1, the connection between resistor R3 and resistor R1 outputs a PWM signal with an offset (amplitude offset) based on the voltage division principle of the resistor. Figure 3A As mentioned, the input signal Sin is an analog voltage signal that varies in the range of 0-5V, the power supply provides a voltage of 5V, the resistance of resistor R2 is 475KΩ, the resistance of resistor R3 is 20KΩ, and the resistance of resistor R1 is 4.99KΩ. When the voltage driving circuit 102 is in a working state so that resistors R2, R3, and R1 are connected in series between the power supply and the input signal Sin, when the PWM signal Sin outputs a low level (0V), the voltage generated at the connection between resistor R3 and resistor R1 based on the voltage division principle is 0.05V; when the PWM signal Sin outputs a high level (5V), the voltage generated at the connection between resistor R3 and resistor R1 based on the voltage division principle is 5V. In other words, the high level of the offset PWM signal output at the connection between resistor R3 and resistor R1 after the first offset is 5V, the low level is 0.05V, and the duty cycle is D. Figure 3B There is a capacitor C1 therein, so the resistor R1 and the capacitor C1 form a filter circuit to convert the offset PWM signal output from the connection between the resistor R3 and the resistor R1 into an analog voltage signal, and the analog voltage signal is: 0.05×(1-D)+5×D, and the analog voltage signal is limited to change within the range of 0.05-5V (first range). The analog voltage signal output from the connection between the resistor R3 and the resistor R1 outputs the offset input signal Vin via the resistor R4, and the offset input signal Vin output from the second end of the resistor R4 is the same as the analog voltage signal input to the first end of the resistor R4. Because the resistor R4 is connected to the input terminals of the voltage output operational amplifier OA1 in the voltage driving circuit 102 and the current output operational amplifier OA2 in the current driving circuit 103 via the connecting line 123, and according to the virtual short and virtual open characteristics of the operational amplifier, the input resistances of the voltage output operational amplifier OA1 and the current output operational amplifier OA2 are infinite, it can be considered that no current flows through the resistor R4, and thus the voltages at the first and second terminals of the resistor R4 are the same. By adjusting the duty cycle D of the PWM signal, the value of the output offset (analog) input signal Vin can be changed to output the desired analog voltage signal.

[0058] The above description is when the voltage driving circuit 102 is in working state. Figure 3B The voltage-dividing offset circuit 201 in the embodiment performs a first offset on the input signal to output an offset (analog) input signal Vin that varies within a first range. It can be understood that, similar to the working principle, when the voltage driving circuit 102 is in a non-working state, Figure 3BThe voltage-dividing offset circuit 201 in the embodiment can perform a second offset on the input signal to output an offset (analog) input signal Vin that varies within a second range.

[0059] Figure 2A The voltage driving circuit 102 in the embodiment includes a voltage output operational amplifier OA1, a resistor R5, a resistor R6 and a resistor R7. Figure 1A As mentioned above, the function of the voltage driving circuit 102 is to receive the offset input signal Vin from the offset configuration circuit 101, generate a voltage driving signal Dr1 based on the offset input signal Vin, and output the voltage driving signal Dr1 to the output stage circuit 105 through the connecting line 114; and receive a voltage-type output feedback signal from the output stage circuit 105 to make the voltage driving circuit 102 work or not work.

[0060] exist Figure 2AIn the specific structure shown, the Vcc+ pole of the voltage output operational amplifier OA1 is connected to the power supply VCC and the Vcc- pole of the voltage output operational amplifier OA1 is grounded GND, and the voltage output operational amplifier OA1 has a non-inverting input terminal, an inverting input terminal and an output terminal. Resistors R5 and R6 are connected in series, wherein the first end of the resistor R5 is connected to the first end of the output device 106 through the connecting line 120, the second end of the resistor R5 is connected to the first end of the resistor R6, and the second end of the resistor R6 is grounded GND. Since the output stage circuit 105 outputs the driving output voltage Vout to the first end of the output device 106 through the connecting line 118, and the first end of the resistor R5 is connected to the first end of the output device 106 through the connecting line 120, the first end of the resistor R5 receives the driving output voltage Vout (voltage-type output feedback signal) from the output stage circuit 105 through the connecting line 120. Furthermore, the connection between the resistor R5 and the resistor R6 is connected to the non-inverting input terminal of the voltage output operational amplifier OA1, so the voltage VOA1 at the non-inverting input terminal is the voltage value provided to both ends of the resistor R6 by the driving output voltage Vout after the voltage division of the resistor R5 and the resistor R6, that is, VOA1 = Vout*R6 / (R5+R6), where R5 and R6 represent the resistance values ​​of the resistor R5 and the resistor R6 respectively. Assuming R6 / (R5+R6) = L, then VOA1 = Vout*L. The inverting input terminal of the voltage output operational amplifier OA1 is connected to the output terminal of the offset configuration circuit 101 through the connection line 112 to receive the offset input voltage Vin. The output end of the voltage output operational amplifier OA1 is connected to the first end of the resistor R7 to output the intermediate voltage drive signal Dr1′ to the first end of the resistor R7, the second end of the resistor R7 is connected to the input end of the output stage circuit 105 through the connecting line 114 to output the voltage drive signal Dr1 to the input end of the output stage circuit 105, and the second end of the resistor R7 is connected to the output end of the isolation circuit 104 through the connecting lines 114 and 117.

[0061] The voltage output operational amplifier OA1 is used to output an intermediate voltage drive signal Dr1' to the resistor R7 in response to the voltage-type output feedback signal Vout received at the non-inverting input terminal from the output stage circuit 105 and the offset input voltage Vin received at the inverting input terminal from the offset configuration circuit 101, and output the voltage drive signal Dr1 to the output stage circuit 105 via the resistor R7. The voltage-type output feedback signal is used to make the voltage drive circuit 102 work or not work, wherein the work of the voltage drive circuit 102 means that the voltage drive circuit 102 outputs the voltage drive signal Dr1 to the output stage circuit 105 to control the output stage circuit 105 to provide power to the output device 106 (i.e., drive the output device in a voltage-type manner) (see below for details).

[0062] In one embodiment, if the offset configuration circuit 101 performs the first or second offset on the input signal Sin based on the intermediate voltage driving signal Dr1′, then Figure 2A The control output terminal (the second end of the resistor R7) of the voltage driving circuit 102 outputs the intermediate voltage driving signal Dr1' to the control input terminal of the offset control circuit 202 of the offset configuration circuit 101 through the connecting line 126 to control the offset configuration circuit 101 to perform the first or second offset on the input signal Sin.

[0063] Figure 2A The current driving circuit 103 in the embodiment includes a current control circuit 107 and a feedback differential amplifier circuit 108. The function of the feedback differential amplifier circuit 108 is to proportionally amplify the current-type output feedback signal received from the output stage circuit 105, and output the amplified feedback signal V1 to the feedback amplifier input terminal of the current control circuit 107. The function of the current control circuit 107 is to receive the offset input voltage Vin from the output terminal of the offset configuration circuit 101 and the amplified feedback signal V1 from the feedback differential amplifier circuit 108, and generate a current driving signal Dr2 in response to the offset input voltage Vin and the amplified feedback signal V1, and output the current driving signal Dr2 to the output stage circuit 105 through the isolation circuit 104. The function of the current-type output feedback signal is to make the current driving circuit 103 work or not work.

[0064] Figure 2AThe current control circuit 107 in the embodiment includes a current output operational amplifier OA2, a resistor R8 and a resistor R9. The current output operational amplifier OA2 is connected between the working power supply VCC and the ground GND, and the current output operational amplifier OA2 has a non-inverting input terminal, an inverting input terminal and an output terminal. The inverting input terminal of the current output operational amplifier OA2 is connected to the output terminal of the offset configuration circuit 101 to receive the offset input voltage Vin. The resistor R8 and the resistor R9 are connected in series to the output terminal of the feedback differential amplifier circuit 108 to receive the amplified feedback signal V1, wherein the feedback differential amplifier circuit 108 proportionally amplifies the voltage difference (i.e., the current-type output feedback signal) received from both ends of the current detection resistor R15 of the output stage circuit 105 to output the amplified feedback signal V1. The first end of the resistor R9 is connected to the output terminal of the feedback differential amplifier circuit 108 to receive the amplified feedback signal V1, the second end of the resistor R9 is connected to the first end of the resistor R8, and the second end of the resistor R8 is grounded GND. The connection between resistor R8 and resistor R9 is connected to the non-inverting input terminal of the current output operational amplifier OA2, so the voltage (VOA2) of the non-inverting input terminal is the voltage value provided to the two ends of the resistor R8 by the feedback signal V1 after the voltage division of the resistor R8 and the resistor R9, that is, VOA2 = V1 * R8 / (R8 + R9), where R8 and R9 represent the resistance values ​​of the resistor R8 and the resistor R9 respectively. The output terminal of the current output operational amplifier OA2 is connected to the output terminal of the voltage driving circuit 102 and the input terminal of the output stage circuit 105 via the isolation circuit 104.

[0065] The function of the current output operational amplifier OA2 is to output a current drive signal Dr2 in response to the offset input voltage Vin received at the inverting input terminal from the output terminal of the offset configuration circuit 101 and the feedback signal V1 received at the non-inverting input terminal from the output terminal of the feedback differential amplifier circuit 108 after amplifying the current-type output feedback signal, and output the current drive signal Dr2 to the output stage circuit 105 through the isolation circuit 104. The function of the current-type output feedback signal is to make the current drive circuit 103 work or not work, wherein the work of the current drive circuit 103 means that the current drive circuit 103 outputs the current drive signal Dr2 to the output stage circuit 105, so as to control the output stage circuit 105 to provide power to the output device 106 (i.e., drive the output device in a current-type manner) (see below for details).

[0066] Figure 2AThe feedback differential amplifier circuit 108 in the embodiment includes a feedback operational amplifier OA3, a resistor R10, a resistor R11, a resistor R12 and a resistor R13. The feedback operational amplifier OA3 is connected between the working power supply VCC and the ground GND, and the feedback operational amplifier OA3 has a non-inverting input terminal, an inverting input terminal and an output terminal. The first end of the resistor R13 is connected to the first end (the voltage at the end is V2) of the current detection resistor R15 in the output stage circuit 105, the second end of the resistor R13 is connected to the first end of the resistor R12 and the non-inverting input terminal of the feedback operational amplifier OA3, and the second end of the resistor R12 is grounded GND. The first end of the resistor R11 is connected to the second end (the voltage at the end is V3) of the current detection resistor R15 in the output stage circuit 105, the second end of the resistor R11 is connected to the first end of the resistor R10 and the inverting input terminal of the feedback operational amplifier OA3, and the second end of the resistor R10 is connected to the output terminal of the feedback operational amplifier OA3. In the feedback differential amplifier circuit 108, according to the virtual short and virtual open characteristics of the feedback operational amplifier OA3, it can be obtained that: V1 = R12*(R11+R10)*V2 / [R11*(R13+R12)]-R10*V3 / R11, where R10, R11, R12, and R13 are the resistance values ​​of the resistors R10, R11, R12, and R13 respectively. If R10 = R12, R11 = R13, then V1 = R10*(V2-V3) / R11.

[0067] The function of the feedback differential amplifier circuit 108 is as follows: it receives the voltage difference V2 - V3 (current-type output feedback signal) across the current detection resistor R15 from the output stage circuit 105, and proportionally amplifies this voltage difference (current-type output feedback signal) to output an amplified feedback signal V1. If the current flowing through the output device 106 is considered equal to the current flowing through the current detection resistor R15, then V2 - V3 = Iout * R15, where R15 represents the resistance value of the current detection resistor R15. Substituting V2 - V3 = Iout * R15 into the above formula V1 = R10 * (V2 - V3) / R11, we get: V1 = Iout * R10 * R15 / R11. Substituting this V1 into the前述 VOA2 = V1 * R8 / (R8 + R9), we obtain VOA2 = Iout * R10 * R15 * R8 / [(R8 + R9) * R11], where VOA2 is the voltage at the non-inverting input terminal of the current output operational amplifier OA2 of the current control circuit 107 (of the current drive circuit 103). And Iout = Vout / R device, where R device represents the resistance value of the output device 106, then VOA2 = Vout * R10 * R15 * R8 / [(R8 + R9) * R11 * R device]. Assuming R10 * R15 * R8 / [(R8 + R9) * R11 * R device] = M, then VOA2 = Vout * M, where the value of M is related to the resistance value R device of the output device 106. And as mentioned when describing the voltage output operational amplifier OA1 of the voltage drive circuit 102, the voltage VOA1 at the non-inverting input terminal of the voltage output operational amplifier OA1 is VOA1 = Vout * L, where L = R6 / (R5 + R6).

[0068] It should be noted that when the output device 106 is connected to the output stage circuit 105, the voltage-type output feedback signal output from the output stage circuit 105 to the voltage drive circuit 102 and the current-type output feedback signal output to the current drive circuit 103 will cause one of the voltage drive circuit 102 and the current drive circuit 103 to operate. Therefore, in this application, by designing the specific circuit structures of the voltage drive circuit 102, the current drive circuit 103, and the output stage circuit 105, it can be achieved that: when the output device 106 connected to the output stage circuit 105 has a certain resistance value R, L = M, then the voltage VOA1 at the non-inverting input terminal of the voltage output operational amplifier OA1 of the voltage drive circuit 102 is equal to the voltage VOA2 at the non-inverting input terminal of the current output operational amplifier OA2 of the current drive circuit 103 (VOA1 = VOA2); when the output device 106 is less than the resistance value R, L < M, then VOA1 < VOA2; when the output device 106 is greater than the resistance value R, L > M, then VOA1 > VOA2.

[0069] Since the voltages received by the inverting input terminals of the voltage output operational amplifier OA1 of the voltage driving circuit 102 and the current output operational amplifier OA2 of the current driving circuit 103 are the same, both being the biased input voltage Vin, when the voltage VOA1 at the non-inverting input terminal of the voltage output operational amplifier OA1 of the voltage driving circuit 102 is less than the voltage VOA2 at the non-inverting input terminal of the current output operational amplifier OA2 of the current driving circuit 103 (i.e., VOA1 < VOA2), the voltage Dr1' output from the output terminal of the voltage output operational amplifier OA1 of the voltage driving circuit 102 is always less than the voltage Dr2 (current driving signal) output from the output terminal of the current output operational amplifier OA2 of the current driving circuit 103. Therefore, the voltage driving signal Dr1 output from the voltage driving circuit 102 after the voltage drop across the resistor R7 is also always less than the current driving signal Dr2 output from the current driving circuit 103. The potential difference formed by the voltages Dr1 (lower) and Dr2 (higher) is applied to the isolation circuit 104. Thus, the isolation circuit 104 conducts to supply the current driving signal Dr2 output from the current driving circuit 103 to the input terminal of the output stage circuit 105. At the same time, the resistor R7 blocks the voltage Dr1' output from the voltage driving circuit 102 from being supplied to the input terminal of the output stage circuit 105, such that the voltage Dr1' output from the voltage driving circuit 102 does not affect the voltage control function of the current driving signal Dr2 output from the current driving circuit 103 on the output stage circuit 105. At this time, only the current driving signal Dr2 output from the current driving circuit 103 is supplied to the input terminal of the output stage circuit 105 to control the output stage circuit 105 to supply power to the output device 106. This situation is called driving the output device in a current mode. That is to say, when the output device 106 is less than the above-mentioned resistance value R, the characteristic of the output circuit 100 is to drive the output device in a current mode.

[0070] When the voltage VOA1 at the non-inverting input terminal of the voltage output operational amplifier OA1 is greater than the voltage VOA2 at the non-inverting input terminal of the current output operational amplifier OA2 (i.e., VOA1>VOA2), the voltage Dr1' outputted from the output terminal of the voltage output operational amplifier OA1 of the voltage driving circuit 102 is always greater than the voltage Dr2 (current driving signal) outputted from the output terminal of the current output operational amplifier OA2 of the current driving circuit 103. Since the voltage drop across the resistor R7 is very small, the voltage driving signal Dr1 outputted from the voltage driving circuit 102 is also always smaller than the current driving signal Dr2 outputted from the current driving circuit 103. The potential difference formed by the voltage Dr1 (higher) and Dr2 (lower) is applied to the isolation circuit 104, so the isolation circuit 104 is disconnected to isolate the current driving signal Dr2 outputted from the current driving circuit 103 from the input terminal of the output stage circuit 105, and the voltage Dr1' outputted from the voltage driving circuit 102 outputs the voltage driving signal Dr1 to the input terminal of the output stage circuit 105 via the resistor R7. At this time, only the voltage driving signal Dr1 output by the voltage driving circuit 102 is provided to the input end of the output stage circuit 105 to control the output stage circuit 105 to provide power to the output device 106. This situation is called driving the output device in a voltage-type manner. In other words, when the output device 106 is greater than the above resistance value R, the characteristic of the output circuit 100 is to drive the output device in a voltage-type manner. It should be noted that those skilled in the art understand that other circuit designs can also make: when the output device 106 is greater than the above resistance value R, the characteristic of the output circuit 100 is to drive the output device in a current-type manner, and when the output device 106 is less than the above resistance value R, the characteristic of the output circuit 100 is to drive the output device in a voltage-type manner.

[0071] Figure 2A The isolation circuit 104 in the circuit is a diode D1, which has a positive terminal and a negative terminal, wherein the positive terminal of the diode D1 is connected to the output terminal of the current driving circuit 103, and the negative terminal of the diode D1 is connected to the output terminal of the voltage driving circuit 102 and the input terminal of the output stage circuit 105. The diode D1 is preferably a Schottky diode. The function of the isolation circuit 104 is: when the current driving circuit 103 is in a working state, the current driving signal Dr2 output by the current driving circuit 103 drives the output stage circuit 105 via the isolation circuit 104, and the voltage driving circuit 102 is in a non-working state; but when the voltage driving circuit 102 is in a working state, the isolation circuit 104 disconnects the output of the current driving circuit 103 from the output stage circuit 105, because the output of the current driving circuit 103 is also connected to the input terminal of the output stage circuit 105.

[0072] During operation, when the current driving circuit 103 is in a working state, the voltage Dr1' outputted from the output terminal of the voltage output operational amplifier OA1 of the voltage driving circuit 102 is less than the voltage Dr2 (current driving signal) outputted from the output terminal of the current output operational amplifier OA2 of the current driving circuit 103, and the isolation circuit 104 is turned on to provide the voltage current driving signal Dr2 outputted by the current driving circuit 103 to the input terminal of the output stage circuit 105, while the resistor R7 prevents the voltage Dr1' outputted by the voltage driving circuit 102 from being provided to the input terminal of the output stage circuit 105, so that the voltage driving circuit 102 is in a non-working state.

[0073] When the voltage driving circuit 102 is in a working state, the voltage Dr1' outputted from the output terminal of the voltage output operational amplifier OA1 of the voltage driving circuit 102 is greater than the voltage Dr2 (current driving signal) outputted from the output terminal of the current output operational amplifier OA2 of the current driving circuit 103, and the isolation circuit 104 is disconnected to separate the current driving signal Dr2 outputted by the current driving circuit 103 from the input terminal of the output stage circuit 105, so that the current driving circuit 103 is in a non-working state, and the voltage Dr1' outputted by the voltage driving circuit 102 outputs the voltage driving signal Dr1 to the input terminal of the output stage circuit 105 via the resistor R7.

[0074] In one embodiment, a capacitor may be connected between the output terminal and the inverting input terminal of each of the voltage output operational amplifier OA1, the current output operational amplifier OA2, and the feedback operational amplifier OA3 to prevent the phase of the output terminal of these feedback operational amplifiers from lagging behind the phase of their inverting input terminals. The capacitance value of the capacitor is relatively small, for example, 330 pF. In another embodiment, the capacitor may not be connected to reduce the number of components in the output circuit. Figure 2AThe output stage circuit 105 in the embodiment includes a diode D2, a diode D3, a resistor R14, a switch element (e.g., a PNP transistor) Q1, a current sensing resistor R15, a diode D4, and a capacitor C2, which are sequentially connected in series between a power source VCC and a ground GND. The positive end of the diode D2 is connected to the power source VCC, the negative end of the diode D2 is connected to the positive end of the diode D3, the negative end of the diode D3 is connected to the first end of the resistor R14, and the second end of the resistor R14 is connected to the emitter of the transistor Q1. The base of the transistor Q1 is connected to the second end of the resistor R7 of the voltage driving circuit 102 (the output end of the voltage driving circuit 102) through a connecting line 114 and is connected to the negative end of the diode D1 of the isolation circuit 104 (the output end of the isolation circuit 104) through a connecting line 117 to receive the voltage driving signal Dr1 output by the voltage driving circuit 102 or the current driving signal Dr2 output by the current driving circuit 103. The collector of transistor Q1 is connected to the first end of current-sense resistor R15, and the second end of current-sense resistor R15 is connected to the positive end of diode D4. The negative end of diode D4 is connected to the first end of capacitor C2, and the second end of capacitor C2 is grounded GND. The first end of output device 106 is connected to the first end of capacitor C2 via connection line 118, and the second end of output device 106 is connected to the second end of capacitor C2 via connection line 119 (both are grounded). Output stage circuit 105 outputs drive output voltage Vout and drive output current Iout to output device 106 via connection lines 118 and 119. Figure 2A In the embodiment, the negative end of the diode D4 of the output stage circuit 105 is connected to the first end of the capacitor C2, the second end of the capacitor C2 is connected to the ground GND, and the output device 106 is connected in parallel with the capacitor C2. The function of the capacitor C2 is to filter the output voltage Vout and the output current Iout output to the output device 106, so that the output voltage Vout and the output current Iout change slowly when the resistance value of the output device 106 changes greatly.

[0075] exist Figure 2AIn the embodiment, the first end of the output device 106 is connected to the first end of the resistor R5 of the voltage driving circuit 102 (the feedback input end of the voltage driving circuit 102) through the connection line 120 to output a voltage-type output feedback signal (Vout) to the voltage driving circuit 102. In addition, the first end of the current-sensing resistor R15 of the output stage circuit 105 is connected to the first end of the resistor R13 of the feedback differential amplifier circuit 108 of the current driving circuit 103 through the connection line 121, and the second end of the current-sensing resistor R15 is connected to the first end of the resistor R11 of the feedback differential amplifier circuit 108 of the current driving circuit 103 through the connection line 121, so that the voltage difference (Iout*R15, i.e., the current-type output feedback signal) across the current-sensing resistor R15 is output to the current driving circuit 103. The output stage circuit 105 outputs a voltage-type output feedback signal to the voltage driving circuit and outputs a current-type output feedback signal to the current driving circuit 103, which causes one of the voltage driving circuit 102 and the current driving circuit 103 to work, that is, to drive the output device 106 in a voltage-type manner or to drive the output device 106 in a current-type manner (see above for details). At this time, the driving signal Dr1 from the voltage driving circuit 102 or the current driving signal Dr2 from the current driving circuit 103 is output to the base of the transistor Q1 of the output stage circuit 105 to turn on the transistor Q1, so that the circuit of the output stage circuit 105 is turned on to drive the output device 106.

[0076] When the output device 106 is driven in a voltage mode, as shown in FIG. Figure 2A As shown, the voltage output operational amplifier OA1 in the voltage driving circuit 102 has two working states. The first working state is a working state in which the input signal remains unchanged when the output circuit 100 is initially started, and the second working state is a working state in which the input signal changes during the operation of the output circuit 100.

[0077] In the embodiment of the first working state, when the output circuit 100 is initially started, if the input signal Sin is 5V so that the offset input voltage Vin is also 5V, then since the offset input voltage Vin is provided to the inverting input terminal of the voltage output operational amplifier OA1 of the voltage driving circuit 102, the voltage of the inverting input terminal increases to 5V. Since the non-inverting input terminal of the voltage output operational amplifier OA1 of the voltage driving circuit 102 is still 0V at the initial startup of the circuit, the voltage outputted by the output terminal of the voltage output operational amplifier OA1 increases from 0V to slightly greater than 0V, which is a relatively low voltage (low level). This relatively low voltage is outputted to the base of the transistor Q1 of the output stage circuit 105, causing the transistor Q1 to turn on (in an amplified or saturated state), the output stage circuit 105 is turned on, and the output current Iout provided by the output stage circuit 105 to the output device 106 increases from 0A to greater than 0A, and the output voltage Vout provided by the output stage circuit 105 to the output device 106 increases from 0V to greater than 0V. The increase of output voltage Vout also increases the voltage of the non-inverting input terminal of voltage output operational amplifier OA1 from 0V to greater than 0V, so that the voltage outputted from the output terminal of voltage output operational amplifier OA1 further increases, resulting in an increase in the base current of transistor Q1 of output stage circuit 105, a decrease in the voltage between the collector and emitter of transistor Q1, a further increase in output voltage Vout, and a further increase in output current Iout. As the above cycle, the output voltage Vout will continue to increase. When the output voltage Vout increases to a certain value and makes the voltage Vin at the inverting input terminal of voltage output operational amplifier OA1 equal to the voltage VOA1 at the non-inverting input terminal (i.e., Vin=VOA1), due to the virtual short and virtual break characteristics of voltage output operational amplifier OA1, voltage output operational amplifier OA1 reaches a stable state at this time, so the voltage VOA1 outputted to the non-inverting input terminal of voltage output operational amplifier OA1 and the voltage at the output terminal are stable and no longer change. Therefore, the voltage outputted from the voltage output operational amplifier OA1 to the base of the transistor Q1 of the output stage circuit 105 is stable and no longer changes, so the voltage Vout and the current Iout outputted from the output stage circuit 105 to the output device 106 are also stable. As mentioned above, the voltage Vout outputted from the output stage circuit 105 to the output device 106 is fed back to the non-inverting input terminal of the voltage output operational amplifier OA1 of the voltage driving circuit 102, and the voltage VOA1 of the non-inverting input terminal is: VOA1 = Vout*R6 / (R5+R6). When the voltage output operational amplifier OA1 reaches a stable state, Vin = VOA1, so the input signal can control the voltage Vout outputted from the output stage circuit 105 to the output device 106, and the voltage is Vout = Vin*(R5+R6) / R6.

[0078] In the embodiment of the second working state, when the voltage output operational amplifier OA1 reaches a stable state after the first working state, if the input voltage Vin increases to a certain voltage value, the voltage Vin at the inverting input terminal of the voltage output operational amplifier OA1 also increases to the voltage value. At this time, the voltage outputted from the output terminal of the voltage output operational amplifier OA1 decreases, resulting in an increase in the base current of the transistor Q1 of the output stage circuit 105, a decrease in the voltage between the collector and the emitter of the transistor Q1, and an increase in the output voltage Vout, so that the voltage at the non-inverting input terminal of the voltage output operational amplifier OA1 increases. As in the above cycle, the output voltage Vout increases continuously, so that the voltage at the non-inverting input terminal of the voltage output operational amplifier OA1 increases continuously until the voltage VOA1 at the non-inverting input terminal of the voltage output operational amplifier OA1 is equal to the voltage Vin at the inverting input terminal of the voltage output operational amplifier OA1, then the voltage output operational amplifier OA1 reaches a stable state, and the voltage Vout and current Iout outputted from the output stage circuit 105 to the output device 106 also reach stability accordingly. At this time, the input signal still controls the voltage Vout outputted by the output stage circuit 105 to the output device 106 , and the voltage Vout=Vin*( R5+R6 ) / R6 .

[0079] When the voltage output operational amplifier OA1 reaches a stable state after the first working state, if the input voltage Vin decreases to a certain voltage value, the voltage Vin at the inverting input terminal of the voltage output operational amplifier OA1 decreases to the voltage value. At this time, the voltage outputted from the output terminal of the voltage output operational amplifier OA1 increases, resulting in a decrease in the base current of the transistor Q1 of the output stage circuit 105, an increase in the voltage between the collector and the emitter of the transistor Q1, and a decrease in the output voltage Vout, so that the voltage at the non-inverting input terminal of the voltage output operational amplifier OA1 decreases. As in the above cycle, the output voltage Vout keeps decreasing, so that the voltage at the non-inverting input terminal of the voltage output operational amplifier OA1 keeps decreasing until the voltage at the non-inverting input terminal of the voltage output operational amplifier OA1 is equal to the voltage Vin at the inverting input terminal of the voltage output operational amplifier OA1, then the voltage output operational amplifier OA1 reaches a stable state, and the voltage Vout and current Iout outputted from the output stage circuit 105 to the output device 106 also reach stability accordingly. At this time, the input signal still controls the voltage Vout outputted by the output stage circuit 105 to the output device 106 , and the voltage Vout=Vin*( R5+R6 ) / R6 .

[0080] When the output device 106 is driven in a current mode, as shown in FIG. Figure 2AAs shown, the current output operational amplifier OA2 in the current driving circuit 103 works in the above-mentioned manner similar to the voltage output operational amplifier OA1 in the voltage driving circuit 102. The difference is that the voltage difference (Iout*R15) outputted by the output stage circuit 105 to the two ends of the current sensing resistor R15 is fed back to the input end of the feedback differential amplifier circuit 108 of the current driving circuit 103, and the feedback differential amplifier circuit 108 outputs the voltage V1 to the non-inverting input end of the current output operational amplifier OA2 in the current control circuit 107 after proportional amplification, so that the voltage VOA2 at the non-inverting input end is: VOA2=Iout*R10*R15*R8 / [(R8+R9)*R11]. When the current output operational amplifier OA2 reaches a stable state, Vin=VOA2, so the input signal can control the current Iout outputted from the output stage circuit 105 to the output device 106, and the current is Iout=Vin*(R8+R9)*R11 / (R10*R15*R8).

[0081] It should be noted that in Figure 2A In the embodiment, the voltage output operational amplifier OA1 in the voltage driving circuit 102 and the current output operational amplifier OA2 in the current driving circuit 103 are both non-rail-to-rail operational amplifiers. According to the formula Dr1'=A1×(VOA1-Vin)+VCC and the formula Dr2=A2×(VOA2-Vin)+VCC (where A1 and A2 are the amplification factors of the voltage output operational amplifier OA1 and the current output operational amplifier OA2, respectively, and A1 and A2 are both very large values), it can be seen that the actual values ​​of the voltage driving signal Dr1' output by the voltage output operational amplifier OA1 and the current driving signal Dr2 output by the current output operational amplifier OA2 are both smaller than the ideal values. Therefore, the diode D2 and the diode D3 are added to the output stage circuit 105 of the present application, thereby reducing the voltage of the emitter of the transistor Q1, so that the transistor Q1 can still work normally when its base is connected to the voltage driving signal Dr1' and the current driving signal Dr2 that are smaller than the ideal value. Those skilled in the art will appreciate that in other embodiments, the voltage output operational amplifier OA1 and the current output operational amplifier OA2 may use rail-to-rail operational amplifiers without using diodes D2 and D3. Furthermore, it should be noted that rail-to-rail operational amplifiers are much more expensive than non-rail-to-rail operational amplifiers. Figure 2A The solution shown using a non-rail-to-rail op amp and diode combination is less expensive than the solution using a rail-to-rail op amp.

[0082] As can be understood by those skilled in the art, in other embodiments, the transistor Q1 may also be a P-channel field effect transistor Q1, or a PMOS transistor Q1. The source of the P-channel field effect transistor Q1 is connected to the second end of the resistor R14, the gate of the P-channel field effect transistor Q1 is connected to the second end of the resistor R7 of the voltage driving circuit and to the negative end of the diode D1 of the isolation circuit 104 to receive the voltage driving signal Dr1 or the current driving signal Dr2, and the drain of the P-channel field effect transistor Q1 is connected to the first end of the current detection resistor R15 and the second end of the resistor R13 of the feedback differential amplifier circuit 108 of the current driving circuit 103.

[0083] Furthermore, the output circuit of the present invention does not require a current compensation circuit. Specifically, as described above, the present invention considers the output current Iout output to the output device 106 to be equal to the current flowing through the current sensing resistor R15 in the calculation. However, in reality, Figure 2A As shown, when the output stage circuit 105 is driven by the current driving signal Dr2, the current flowing through the current sensing resistor R15 in the output stage circuit 105 is not only output to the output device 106, but also shunted by the resistors R5 and R6 in the voltage driving circuit 102 connected in parallel with the output device 106, so that the output current Iout cannot reach the current flowing through the current sensing resistor R15. However, since the resistance values ​​of the resistors R5 and R6 are much larger than the resistance value of the output device 106, the current shunted from the current sensing resistor R15 by the resistors R5 and R6 is very small, so that the error caused by recognizing the output current Iout output to the output device 106 as equal to the current flowing through the current sensing resistor R15 is very small. For example, in one embodiment, the resistors R5 and R6 are both 20 kΩ, the resistance of the output device 106 is 500 Ω, if the current value output to the output device 106 is in the range of 4-20 mA, then when the current value flowing through the current sensing resistor R15 is, for example, 20 mA, the current value divided by the resistors R5 and R6 is about 0.25 mA, and the final current value output to the output device 106 is about 19.75 mA, with an error of only 1.25%. Since the error of the output current Iout caused by the resistors R5 and R6 is very small and can be ignored, the present invention does not need to use an additional current compensation circuit.

[0084] Figure 2B Based on Figure 1B Detail of an exemplary circuit diagram of each module of an embodiment of the output circuit 100 of the present invention is shown. Figure 2B The structure of the output circuit 100 is similar to Figure 2A The structure of the output circuit 100 in is basically the same, except for the following aspects: Figure 2BIn the embodiment, the output end of the voltage driving circuit 102 (i.e., the output end of the voltage output operational amplifier OA1) is connected to the input end of the isolation circuit 104 (i.e., the positive end of the diode D1) through the connection line 124 to output the voltage driving signal Dr1 to the isolation circuit 104, and the output end of the isolation circuit 104 (i.e., the negative end of the diode D1) is connected to the input end of the output stage circuit 105 (i.e., the base of the transistor Q1) through the connection line 127 to output the voltage driving signal Dr1 output by the voltage driving circuit 102 to the output stage circuit 105. The output end of the voltage driving circuit 102 (i.e., the output end of the voltage output operational amplifier OA1) is also connected to the control input end of the offset configuration circuit 101 through the connection line 126 to output the voltage driving signal Dr1 to the offset configuration circuit 101, thereby controlling the offset configuration circuit 101 to perform the first or second offset on the input signal Sin. In one embodiment, the control output terminal of the current driving circuit 103 (i.e., the output terminal of the current output operational amplifier OA2) is connected to the control input terminal of the offset configuration circuit 101 through the connection line 116 to output the intermediate current driving signal Dr2' to the offset configuration circuit 101, thereby controlling the offset configuration circuit 101 to perform the first or second offset on the input signal Sin. The output terminal of the current output operational amplifier OA2 of the current driving circuit 103 is connected to the first terminal of the resistor R7, and the second terminal of the resistor R7 (i.e., the output terminal of the current driving circuit 103) is connected to the output terminal of the isolation circuit 104 and the input terminal of the output stage circuit 105 through the connection line 125 to output the current driving signal Dr2 to the output stage circuit 105.

[0085] In operation, Figure 2B The voltage output operational amplifier OA1 and the current output operational amplifier OA2 operate with Figure 2A The same difference is: Figure 2BAmong them, the output voltage drive signal Dr1 is output from the output terminal of the voltage output operational amplifier OA1, and the intermediate current drive signal Dr2' is output from the output terminal of the current output operational amplifier OA2. When the voltage VOA1 at the non-inverting input terminal of the voltage output operational amplifier OA1 is less than the voltage VOA2 at the non-inverting input terminal of the current output operational amplifier OA2 (i.e., VOA1 < VOA2), the voltage Dr1 (voltage drive signal) output from the output terminal of the voltage output operational amplifier OA1 of the voltage drive circuit 102 is always less than the voltage Dr2' output from the output terminal of the current output operational amplifier OA2 of the current drive circuit 103. Since the voltage drop across the resistor R7 is very small, the voltage drive signal Dr1 output by the voltage drive circuit 102 is also always less than the current drive signal Dr2 output by the current drive circuit 103. The potential difference formed by the voltages Dr1 (lower) and Dr2 (higher) is applied to the isolation circuit 104. Therefore, the isolation circuit 104 is turned off to isolate the voltage drive signal Dr1 output by the voltage drive circuit 102 from the input terminal of the output stage circuit 105, while the current drive circuit 103 outputs the current drive signal Dr2 to the input terminal of the output stage circuit 105. At this time, only the current drive signal Dr2 output by the current drive circuit 103 is provided to the input terminal of the output stage circuit 105 to control the output stage circuit 105 to supply power to the output device 106. This situation is called driving the output device in a current mode.

[0086] Moreover, when the voltage VOA1 at the non-inverting input terminal of the voltage output operational amplifier OA1 is greater than the voltage VOA2 at the non-inverting input terminal of the current output operational amplifier OA2 (i.e., VOA1 > VOA2), the voltage Dr1 (voltage drive signal) output from the output terminal of the voltage output operational amplifier OA1 of the voltage drive circuit 102 is always greater than the voltage Dr2' output from the output terminal of the current output operational amplifier OA2 of the current drive circuit 103. Therefore, the voltage drive signal Dr1 output by the voltage drive circuit 102 is also always greater than the current drive signal Dr2 output by the current drive circuit 103 after the voltage drop across the resistor R7. The potential difference formed by the voltages Dr1 (higher) and Dr2 (lower) is applied to the isolation circuit 104. Therefore, the isolation circuit 104 is turned on to provide the voltage drive signal Dr1 output by the voltage drive circuit 102 to the input terminal of the output stage circuit 105. At the same time, the resistor R7 prevents the voltage Dr2' output by the current drive circuit 103 from being provided to the input terminal of the output stage circuit 105, so that the voltage Dr2' output by the current drive circuit 103 does not affect the voltage control function of the voltage drive signal Dr1 output by the voltage drive circuit 102 on the output stage circuit 105. At this time, only the voltage drive signal Dr1 output by the voltage drive circuit 102 is provided to the input terminal of the output stage circuit 105 to control the output stage circuit 105 to supply power to the output device 106. This situation is called driving the output device in a voltage mode.

[0087] In one embodiment of the present application, the parameters of each component in the output circuit 100 can be set as shown in Table 1 below:

[0088] Table 1

[0089]

[0090] Those skilled in the art will appreciate that other parameters may also be set for these elements in the output circuit 100 .

[0091] In the present application, when the output device 106 is connected to the output stage circuit 105, the voltage-type output feedback signal output by the output stage circuit 105 to the voltage driving circuit 102 and the current-type output feedback signal output to the current driving circuit 103 will automatically select one of the voltage driving circuit 102 and the current driving circuit 103 to work, thereby automatically selecting to drive the output device 106 in a voltage-type or current-type manner. As can be understood by those skilled in the art, the automatically configured output circuit of the present application can adopt other circuit structures and devices to achieve Figure 1A and 1B The functions of each circuit and device in it.

[0092] For the existing output circuit, some traditional methods use a large number of electronic components and complex circuits to achieve high cost and require current compensation, while other traditional methods cannot achieve automatic selection of voltage output and current output. Compared with the prior art, the output circuit in the present application has the following beneficial technical effects: using an isolation circuit to isolate the voltage driving circuit or the current driving circuit from the output stage circuit to achieve automatic selection of voltage-type driving output devices and current-type driving output devices; the isolation circuit, especially the diode, is simple, fast and economical, making the circuit simple, with fewer components, low price and small substrate space; the circuit structure of the voltage driving circuit and the current driving circuit is simple, with fewer components, low price and small substrate space; the circuit is reasonably designed and the resistance value of each resistor is selected, so that when the current-type output device is driven, no current compensation circuit is required, thereby making the circuit structure simple and with fewer components.

[0093] Although the present invention has been described with reference to the specific embodiments shown in the accompanying drawings, it should be understood that the output circuit of the present invention may have many variations without departing from the spirit and scope and context of the teachings of the present invention. Those skilled in the art will also recognize that there are different ways to change the parameters in the embodiments disclosed by the present invention, such as resistance values, capacitance values, or the type of components, all within the spirit and scope of the present invention and the claims.

Claims

1. An automatically configured output circuit (100), characterized in that include: A voltage driving circuit (102), the voltage driving circuit (102) being configured to generate a voltage driving signal (Dr1), the voltage driving circuit (102) having an output terminal; A current driving circuit (103), the current driving circuit (103) being configured to generate a current driving signal (Dr2), the current driving circuit (103) having an output terminal; Isolation circuit (104); an output stage circuit (105), the output stage circuit (105) having an input end, the output end of the voltage driving circuit (102) being connected to the input end of the output stage circuit (105), and the output end of the current driving circuit (103) being connected to the input end of the output stage circuit (105) via the isolation circuit (104); The voltage driving circuit (102) receives a voltage-type output feedback signal from the output stage circuit (105), and the current driving circuit (103) receives a current-type output feedback signal from the output stage circuit (105).

2. The output circuit (100) according to claim 1, characterized in that: When the current driving signal (Dr2) is always lower than the voltage driving signal (Dr1), the isolation circuit (104) isolates the output end of the current driving circuit (103) from the input end of the output stage circuit (105).

3. An automatically configured output circuit (100), characterized in that include: A voltage driving circuit (102), the voltage driving circuit (102) being configured to generate a voltage driving signal (Dr1), the voltage driving circuit (102) having an output terminal; A current driving circuit (103), the current driving circuit (103) being configured to generate a current driving signal (Dr2), the current driving circuit (103) having an output terminal; Isolation circuit (104); an output stage circuit (105), the output stage circuit (105) having an input end, the output end of the voltage driving circuit (102) being connected to the input end of the output stage circuit (105) via the isolation circuit (104), and the output end of the current driving circuit (103) being connected to the input end of the output stage circuit (105); The voltage driving circuit (102) receives a voltage-type output feedback signal from the output stage circuit (105), and the current driving circuit (103) receives a current-type output feedback signal from the output stage circuit (105).

4. The output circuit (100) according to claim 3, characterized in that: When the voltage driving signal (Dr1) is always lower than the current driving signal (Dr2), the isolation circuit (104) isolates the output end of the voltage driving circuit (102) from the input end of the output stage circuit (105).

5. The output circuit (100) according to claim 1 or 3, characterized in that: The output stage circuit (105) comprises two output terminals, and the two output terminals of the output stage circuit (105) are connected to an output device (106). The output stage circuit (105) is configured to be able to detect a characteristic of the output device (106), the characteristic of the output device (106) being an impedance of the output device (106).

6. The output circuit (100) according to claim 5, characterized in that: The voltage driving signal (Dr1) is always higher than the current driving signal (Dr2); or the voltage driving signal (Dr1) is always lower than the current driving signal (Dr2).

7. The output circuit (100) according to claim 2 or 4, characterized in that: The isolation circuit (104) is a two-terminal isolation circuit.

8. The output circuit (100) according to claim 2 or 4, characterized in that: The isolation circuit (104) is a unidirectional isolation circuit.

9. The output circuit (100) according to claim 7, characterized in that: The isolation circuit (104) is a diode.

10. The output circuit (100) according to claim 1 or 3, characterized in that: The current driving circuit (103) does not include a current compensation circuit.

11. The output circuit (100) according to claim 9, characterized in that: The diode (D1) has a positive end and a negative end, wherein the positive end of the diode (D1) is the input end of the isolation circuit (104), and the negative end of the diode (D1) is the output end of the isolation circuit (104).

12. The output circuit (100) according to claim 1 or 3, characterized in that: The output stage circuit (105) further includes: A switch element (Q1) is configured to receive the voltage drive signal (Dr1) or the current drive signal (Dr2) to be turned on, thereby connecting the circuit of the output stage circuit to drive the output device (106).

13. An automatically configured output circuit (100), characterized in that include: A voltage driving circuit (102), the voltage driving circuit (102) being configured to generate a voltage driving signal (Dr1), the voltage driving circuit (102) having an output terminal; A current driving circuit (103), the current driving circuit (103) being configured to generate a current driving signal (Dr2), the current driving circuit (103) having an output terminal; Isolation circuit (104); an output stage circuit (105), the output stage circuit (105) having an input end, the output end of the voltage driving circuit (102) being connected to the input end of the output stage circuit (105), and the output end of the current driving circuit (103) being connected to the input end of the output stage circuit (105) via the isolation circuit (104); as well as An offset configuration circuit (101) is configured to receive a varying input signal (Sin), and selectively shift the variation range of the input signal (Sin) to a first variation range or a second variation range based on a signal received from the current driving circuit (103) or a signal received from the voltage driving circuit (102) to generate an offset input signal (Vin), wherein the first variation range and the second variation range are different. The offset configuration circuit (101) includes an output terminal, the voltage driving circuit (102) includes an input terminal, and the current driving circuit (103) includes an input terminal. The output end of the offset configuration circuit (101) is connected to the input end of the voltage driving circuit (102) and the input end of the current driving circuit (103) to output the offset input signal (Vin) to the voltage driving circuit (102) and the current driving circuit (103).

14. An automatically configured output circuit (100), characterized in that include: A voltage driving circuit (102), the voltage driving circuit (102) being configured to generate a voltage driving signal (Dr1), the voltage driving circuit (102) having an output terminal; A current driving circuit (103), the current driving circuit (103) being configured to generate a current driving signal (Dr2), the current driving circuit (103) having an output terminal; Isolation circuit (104); an output stage circuit (105), the output stage circuit (105) having an input end, the output end of the voltage driving circuit (102) being connected to the input end of the output stage circuit (105) via the isolation circuit (104), and the output end of the current driving circuit (103) being connected to the input end of the output stage circuit (105); as well as An offset configuration circuit (101) is configured to receive a varying input signal (Sin), and selectively shift the variation range of the input signal (Sin) to a first variation range or a second variation range based on a signal received from the current driving circuit (103) or a signal received from the voltage driving circuit (102) to generate an offset input signal (Vin), wherein the first variation range and the second variation range are different. The offset configuration circuit (101) includes an output terminal, the voltage driving circuit (102) includes an input terminal, and the current driving circuit (103) includes an input terminal. The output end of the offset configuration circuit (101) is connected to the input end of the voltage driving circuit (102) and the input end of the current driving circuit (103) to output the offset input signal (Vin) to the voltage driving circuit (102) and the current driving circuit (103).

15. The output circuit (100) according to claim 13 or 14, characterized in that: The current driving circuit (103) comprises a current control circuit (107) and a feedback differential amplifier circuit (108), wherein the current control circuit (107) and the feedback differential amplifier circuit (108) are connected to each other, wherein the feedback differential amplifier circuit (108) is configured to receive a current-type output feedback signal from the output stage circuit (105) to amplify the current-type output feedback signal, and wherein the current control circuit (107) is configured to generate the current driving signal (Dr2) based on the amplified signal received from the feedback differential amplifier circuit (108).

16. The output circuit (100) according to claim 13 or 14, characterized in that: The offset configuration circuit (101) further includes a voltage-dividing offset circuit (201) and an offset control circuit (202), wherein the offset control circuit (202) is configured to control the voltage-dividing offset circuit (201) to selectively offset the variation range of the input signal (Sin) to the first variation range or the second variation range based on the signal received from the current driving circuit (103) or the signal received from the voltage driving circuit (102).

17. The output circuit (100) according to claim 16, characterized in that: The offset control circuit (202) includes a switching element (Q2).

18. The output circuit (100) according to claim 16, characterized in that: The voltage driving circuit (102) comprises a voltage output operational amplifier (OA1), wherein the voltage output operational amplifier (OA1) has a non-phase input terminal, an inverting input terminal and an output terminal; The inverting input terminal of the voltage output operational amplifier (OA1) is connected to the output terminal of the offset configuration circuit (101), and the non-inverting input terminal of the voltage output operational amplifier (OA1) receives an output voltage signal (Vout) output by the output stage circuit (105) to the output device (106); When the output end of the current driving circuit (103) is connected to the input end of the output stage circuit (105) through the isolation circuit (104), the output end of the voltage output operational amplifier (OA1) is coupled to the output end of the isolation circuit (104) and the input end of the output stage circuit (105); When the output end of the voltage driving circuit (102) is connected to the input end of the output stage circuit (105) through the isolation circuit (104), the output end of the voltage output operational amplifier (OA1) is connected to the input end of the isolation circuit (104).

19. The output circuit (100) according to claim 15, characterized in that: The feedback differential amplifier circuit (108) comprises a feedback operational amplifier (OA3), wherein the feedback operational amplifier (OA3) has a non-inverting input terminal, an inverting input terminal and an output terminal, wherein the non-inverting input terminal and the inverting input terminal of the feedback operational amplifier (OA3) are coupled to the output stage circuit (105), and the output terminal of the feedback operational amplifier (OA3) is connected to the current control circuit (107), wherein the feedback operational amplifier (OA3) is configured to proportionally amplify an output current signal (Iout) outputted by the output stage circuit (105) to an output device (106) to output a feedback amplified voltage signal (V1).

20. The output circuit (100) according to claim 19, characterized in that: The current control circuit (107) comprises a current output operational amplifier (OA2), The current output operational amplifier (OA2) has a non-inverting input terminal, an inverting input terminal and an output terminal, the inverting input terminal of the current output operational amplifier (OA2) is connected to the output terminal of the offset configuration circuit (101), the output terminal of the feedback operational amplifier (OA3) of the feedback differential amplifier circuit (108) is coupled to the non-inverting input terminal of the current output operational amplifier (OA2), and when the output terminal of the current driving circuit (103) is connected to the input terminal of the output stage circuit (105) through the isolation circuit (104), the output terminal of the current output operational amplifier (OA2) is connected to the input terminal of the isolation circuit (104); When the output end of the voltage driving circuit (102) is connected to the input end of the output stage circuit (105) through the isolation circuit (104), the output end of the current output operational amplifier (OA2) is coupled to the output end of the isolation circuit (104) and the input end of the output stage circuit (105).

21. The output circuit (100) according to claim 19, characterized in that: The output stage circuit (105) comprises: A current sensing resistor (R15), wherein two ends of the current sensing resistor (R15) are respectively coupled to the non-inverting input terminal and the inverting input terminal of the feedback operational amplifier (OA3).

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