Semiconductor circuit and method for manufacturing semiconductor circuit

Abstract

The present invention relates to a semiconductor circuit and a method for manufacturing a semiconductor circuit, comprising a heat dissipation substrate, a circuit wiring layer, a plurality of electronic components, a plurality of pins and a sealing layer, wherein the portion of the pin located in the sealing layer is provided with grooves on at least two opposite sides thereof. The thermoplastic resin of the sealing layer can be embedded in these grooves, and after the thermoplastic resin is solidified, the sealing layer will form a boss that matches the groove, and through the close combination of the boss and the groove, the pin and the sealing layer are closely combined, thereby avoiding the prior art that the pin adopts a smooth surface, and during use, due to the external pulling force on the pin, the surface of the pin is easily separated from the sealing layer to produce a small gap, thereby allowing moisture in the surrounding environment to invade the interior of the semiconductor circuit through these gaps, causing the electronic components inside it to leak and eventually fail. Therefore, the stability and reliability of the semiconductor circuit during operation are effectively improved.

Description

Technical Field

[0001] The invention relates to a semiconductor circuit and a method for manufacturing the semiconductor circuit, belonging to the technical field of semiconductor circuit application. Background Art

[0002] Semiconductor circuits are power-driven products that combine power electronics and integrated circuit technology. The surface of semiconductor circuits is generally encapsulated by injection-molded resin materials to form a sealing layer, which seals the internal circuit boards and electronic components, and the pins extend from one or both sides of the sealing layer. Since the surface of the pins is a smooth structure, the bonding strength between the pins and the resin sealing layer is low. When the pins are subjected to external force, it is very easy to cause delamination between the pins and the plastic encapsulation material. When the semiconductor circuit works in harsh environments such as high temperature and high humidity outdoors, external water vapor invades the interior of the semiconductor circuit from the root of the pins along the smooth surface of the pins, causing it to fail. Summary of the invention

[0003] The technical problem to be solved by the present invention is to solve the problem that during the use of the existing semiconductor circuit, due to the easy separation between the pins and the plastic packaging material, external water vapor enters the interior of the semiconductor circuit and causes the semiconductor circuit to fail.

[0004] Specifically, the present invention discloses a semiconductor circuit, comprising:

[0005] A heat dissipation substrate, the heat dissipation substrate comprising a mounting surface and a heat dissipation surface;

[0006] A circuit wiring layer, the circuit wiring layer is arranged on the mounting surface of the heat dissipation substrate, and the circuit wiring layer is provided with a plurality of connection pads;

[0007] A plurality of electronic components are arranged on the pads of the circuit wiring layer, and the plurality of electronic components include power devices and driver chips;

[0008] A plurality of pins, wherein the plurality of pins are arranged on at least one side of the heat dissipation substrate;

[0009] A sealing layer, the sealing layer wraps one side of the heat dissipation substrate on which the electronic component is arranged, and one end of the pin is exposed from the sealing layer;

[0010] The portion of the pin located in the sealing layer is provided with grooves at least on two opposite sides thereof.

[0011] Optionally, the grooves are arranged on four sides of the pin in both the width direction and the thickness direction.

[0012] Optionally, the grooves arranged along the width direction and the thickness direction of the pin are staggered along the length direction of the pin.

[0013] Optionally, four grooves are arranged along the width direction of the pin, namely a first groove group and a second groove group arranged opposite to each other, and four grooves are also arranged along the thickness direction of the pin, namely a third groove group and a fourth groove group arranged opposite to each other. The first groove group, the third groove group, the second groove group and the fourth groove group are arranged sequentially in the length direction of the pin.

[0014] Optionally, the first depth of the grooves of the first groove group and the second groove group is 1 / 20 to 1 / 5 of the width of the pin, and the first width of the grooves of the first groove group and the second groove group is 1 to 4 times the first depth.

[0015] Optionally, the second depth of the grooves of the third groove group and the fourth groove group is 1 / 25 to 1 / 6 of the thickness of the pin, and the second width of the grooves of the third groove group and the fourth groove group is 1 to 4 times the second depth.

[0016] Optionally, the pin includes two bends, which separate the pin into a starting section, a middle section and an ending section arranged in sequence along the length direction, and the groove is arranged in at least one of the starting section, the middle section and the ending section.

[0017] Optionally, the groove is provided in the end section.

[0018] Optionally, a green oil layer is further provided on the surface of the circuit wiring layer for protection.

[0019] The present invention also provides a method for manufacturing the semiconductor circuit, characterized in that the manufacturing method comprises the following steps:

[0020] Arrange a heat dissipation substrate, and sequentially arrange an insulating layer and a circuit wiring layer on the surface of the heat dissipation substrate;

[0021] Arrange electronic components in the circuit wiring layer;

[0022] The pins are configured and shaped to be bent at two positions in the length direction to form a starting section, a middle section and an ending section along the length direction of the pins, and a first groove group, a third groove group, a second groove group and a fourth groove group are sequentially provided near the bending position of the ending section along the length direction of the pins, wherein the first groove group and the second groove group are respectively arranged opposite to each other in the width direction of the pins, and the third groove group and the fourth groove group are respectively arranged opposite to each other in the thickness direction of the pins;

[0023] Electrically connecting electronic components, circuit wiring layers, and pins through bonding wires;

[0024] Injection molding is performed on a heat dissipation substrate provided with electronic components and pins through a packaging mold to form a sealing layer, wherein the sealing layer at least covers a side of the heat dissipation substrate on which the electronic components are installed;

[0025] The leads are cut and formed to form a semiconductor circuit, and the formed semiconductor circuit is tested.

[0026] The semiconductor circuit of the present invention includes a heat dissipation substrate, a circuit wiring layer, a plurality of electronic components, a plurality of pins and a sealing layer, wherein the portion of the pin located in the sealing layer is provided with grooves on at least two opposite sides thereof. The thermoplastic resin of the sealing layer can be embedded in these grooves. After the thermoplastic resin is solidified, the sealing layer will form a boss that matches the groove. Through the close combination of the boss and the groove, the pin and the sealing layer are closely combined, thus avoiding the prior art that the pin adopts a smooth surface. During use, due to the external pulling force on the pin, the surface of the pin is easily separated from the sealing layer to produce a small gap, thereby allowing moisture in the surrounding environment to invade the interior of the semiconductor circuit through these gaps, causing the electronic components inside to leak and eventually fail. Therefore, the stability and reliability of the semiconductor circuit during operation are effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A top view of a semiconductor circuit in the prior art;

[0028] Figure 2 for Figure 1 Sectional view in the XX direction;

[0029] Figure 3 for Figure 2 A magnified view of middle;

[0030] Figure 4 A schematic diagram of the structure of a single pin in an embodiment of the present invention;

[0031] Figure 5 This is a top view of the pins shown in the present invention before installation.

[0032] Reference numerals:

[0033] Sealing layer 002, boss 021, freewheeling diode 003, circuit wiring layer 005, connecting pad 0051, bonding wire 006, insulating layer 007, heat dissipation substrate 008, IGBT 009, pin 100, groove 110, first groove 111, second groove 112, third groove 113, fourth groove 114, fifth groove 115, sixth groove 116, seventh groove 117, eighth groove 118, first bend 101, second bend 102, starting section 103, middle section 104, ending section 105, reinforcing rib 120. DETAILED DESCRIPTION

[0034] It should be noted that, in the case where the structures or functions do not conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below based on examples.

[0035] The semiconductor circuit mentioned in the present invention is a circuit module that integrates power switching devices and high-voltage drive circuits, and is sealed and packaged on the outside. It is widely used in the field of power electronics, such as frequency converters for driving motors, various inverter voltages, variable frequency speed regulation, metallurgical machinery, electric traction, variable frequency home appliances and other fields. The semiconductor circuit here has many other names, such as Modular Intelligent Power System (MIPS), Intelligent Power Module (IPM), or hybrid integrated circuits, power semiconductor modules, power modules and other names. In the following embodiments of the present invention, they are collectively referred to as Modular Intelligent Power System (MIPS).

[0036] The MIPS proposed by the present invention is as follows Figures 1 to 4 As shown, MIPS includes a heat dissipation substrate 008 , a circuit wiring layer 005 , a plurality of electronic components, a plurality of pins 100 , and a sealing layer 002 .

[0037] The heat dissipation substrate 008 is made of metal material, including an upper mounting surface and a lower heat dissipation surface, and can be specifically a rectangular plate made of aluminum such as 1100, 5052, etc.

[0038] An insulating layer 007 is provided on the heat dissipation substrate 008, so that the circuit wiring layer 005 is provided on the insulating layer 007 to realize electrical isolation between the circuit wiring layer 005 and the heat dissipation substrate 008. The insulating layer 007 is formed by covering at least one surface of the heat dissipation substrate 008, and is made of a resin material such as epoxy resin, and fillers such as aluminum oxide and aluminum carbide are filled inside the resin material to improve thermal conductivity. In order to improve thermal conductivity, the shape of these fillers can be angular, and in order to avoid the risk of the fillers damaging the contact surface of the electronic components arranged on the surface thereof, the fillers can be spherical, angular, or a mixed type of angular and spherical. The circuit wiring layer 005 can be formed by etching copper foil, or it can be formed by printing a paste-like conductive medium, and the conductive medium can be a conductive material such as graphene, solder paste, silver glue, etc. The routing of the circuit is formed on the circuit wiring layer 005, and a plurality of connection pads 0051 (not shown in the figure) connecting the routing are provided for mounting electronic components and pins 100. The pin 100 is fixedly and electrically connected to the connection pad 0051 of the heat dissipation substrate 008 near its edge, and has the function of inputting and outputting signals to the external circuit connected to the MIPS. In this embodiment, Figure 1As shown, a plurality of pins 100 are led out from one side of the heat dissipation substrate 008. In other implementations, the pins 100 may also be led out from opposite sides of the heat dissipation substrate 008. The pins 100 are generally made of metals such as copper. A nickel-tin alloy layer is formed on the copper surface by chemical plating and electroplating. The thickness of the alloy layer is generally 5 μm. The plating layer can protect the copper from corrosion and oxidation and improve the weldability.

[0039] Furthermore, a thinner green oil layer (not shown in the figure) can be set on the surface of the circuit wiring layer 005 to prevent damage caused by short circuits between the wirings of the circuit wiring layer 005, and to prevent oxidation and contamination of the surface of the circuit wiring layer 005, thereby playing a protective role.

[0040] The electronic components are arranged on the connection pads 0051 of the circuit wiring layer 005. The electronic components include power devices and driver chips (not shown in the figure). The power devices include switching tubes such as IGBT009 (Insulated Gate Bipolar Transistor) or MOS tubes (metal oxide semiconductor), etc., and also include freewheeling diodes 003. The power consumption of the diodes is large and the heat generated is large during operation. Therefore, the temperature during the operation of MIPS is higher than the room temperature.

[0041] The sealing layer 002 can be formed of resin, and can be molded using thermosetting resin by transfer molding, or can be molded using thermoplastic resin by injection molding. The sealing layer 002 has two packaging structures. One is that the sealing layer 002 covers the upper and lower surfaces of the heat dissipation substrate 008, and covers the electronic components arranged on the heat dissipation substrate 008, and also covers the pins 100 arranged at one end of the heat dissipation substrate 008, which is a full-coverage method of the sealing layer 002; in another packaging method, the sealing layer 002 covers the upper surface of the heat dissipation substrate 008, that is, covers the heat dissipation substrate 008, the electronic components and the pins 100 arranged at one end of the heat dissipation substrate 008, and the lower surface of the heat dissipation substrate 008, that is, the heat dissipation surface, is exposed to the sealing layer 002, thereby forming a semi-coverage method of the sealing layer 002. Figure 2 The semi-encapsulation mode of the sealing layer 002 is shown.

[0042] The portion of the pin 100 located in the sealing layer 002 is provided with grooves 110 at least on two opposite sides thereof. Figure 1 and Figure 2As shown. Grooves 110 are respectively provided on the upper and lower sides of the pin 100 in the thickness direction, so that the thermoplastic resin of the sealing layer 002 can be embedded in these grooves 110. After the thermoplastic resin is cured, the sealing layer 002 will form a boss 021 that matches the groove 110. Through the close combination of the boss 021 and the groove 110, the pin 100 and the sealing layer 002 are closely combined, avoiding the problem that the pin 100 in the prior art uses a smooth surface. During use, due to the external pulling force on the pin 100, the surface of the pin 100 is easily separated from the sealing layer 002 to form a tiny gap, so that the moisture in the surrounding environment invades the inside of the MIPS through these gaps, causing the internal electronic components to leak and eventually fail. Furthermore, grooves 110 are provided on at least two opposite sides of the pin 100, so that at least two opposite sides of the pin 100 have a matching structure of the groove 110 and the boss 021 of the sealing layer 002, thereby further strengthening the firmness and reliability of the combination of the two, further avoiding the occurrence of the separation of the two, and thus effectively improving the stability and reliability of the MIPS during operation.

[0043] In some embodiments of the present invention, Figures 2 to 4 As shown. The groove 110 is provided on two sides of the pin 100 in the thickness direction and on two sides of the pin 100 in the width direction. Figure 4 As shown, a plurality of grooves 110 are provided in the thickness direction of the pin 100, and a plurality of grooves 110 are also provided in the thickness direction of the pin 100, and preferably the number of grooves 110 in the thickness direction and the width direction is the same. That is, grooves 110 are provided on all four surfaces of the pin 100, so that when the sealing layer 002 is formed, the sealing layer 002 is formed with a plurality of bosses 021 respectively engaged with the grooves 110 on the four surfaces of the pin 100, so that the connection between the sealing layer 002 and the pin 100 is further firm and reliable.

[0044] Furthermore, in some embodiments of the present invention, the grooves 110 arranged along the width direction and the thickness direction of the pin 100 are staggered along the length direction of the pin 100. Figure 4 As shown, the grooves 110 arranged in the width direction and the thickness direction are arranged at intervals along the length direction of the pin 100, so that when the sealing layer 002 is formed, the bosses 021 are staggered along the length direction of the pin 100 on the four surfaces of the pin 100 in the thickness and width directions, and the bosses 021 and the grooves 110 are interlocked with each other, so that a firm and reinforced connection structure is uniformly formed on the four surfaces of the pin 100, which helps to further enhance the connection reliability between the pin 100 and the sealing layer 002. The number of the grooves 110 along the width and thickness directions of the pin 100 is preferably greater than or equal to 4.

[0045] Specifically, Figure 4 For example, four grooves, namely groove 111, groove 112, groove 113 and groove 114, are arranged along the width direction of the pin 100, which are respectively the first groove group (groove 111 and groove 112) and the second groove group (groove 113 and groove 114) arranged oppositely, and four grooves 115, groove 116, groove 117 and groove 118 are also arranged along the thickness direction of the pin 100, which are respectively the third groove group (groove 115 and groove 116) and the fourth groove group (groove 117 and groove 118) arranged oppositely, and the first groove group, the third groove group, the second groove group and the fourth groove group are arranged in sequence in the length direction of the pin 100. The first groove group and the second groove group are preferably arranged oppositely in the width direction, and the third groove group and the fourth groove group are also preferably arranged oppositely in the thickness direction, and of course they can also be slightly staggered. Figure 4 In the middle, they are arranged opposite to each other. Because the length of the portion of the pin 100 located in the sealing layer 002 is shorter, the arrangement makes the length of the pin 100 occupied by these groove groups shorter, so that more groove groups can be arranged, thereby further strengthening the firmness of the connection between the pin 100 and the sealing layer 002. The first groove group, the third groove group, the second groove group and the fourth groove group are preferably arranged at equal intervals in the length direction of the pin 100. In order to ensure that the grooves and the bosses 021 of the sealing layer 002 are stably and reliably engaged, while not affecting the toughness of the pin 100 body due to excessive groove depth and width, which may cause easy bending and fracture, the first depth of the grooves of the first groove group and the second groove group is 1 / 20 to 1 / 5 of the width of the pin 100, and the width of the grooves of the first groove group and the second groove group is 1 to 4 times the first depth. The first depth refers to the groove depth in the width direction of the pin 100, and the first width of the groove is the groove length of the groove along the length direction of the pin 100. Since the pin 100 is generally thinner than its width, such as Figure 4 As shown, the end face of the pin 100 in the length direction is rectangular, and the relative size of the grooves in the third groove group and the fourth groove group arranged along the thickness direction of the pin 100 is different from the first groove and the second groove. Specifically, the second depth of the grooves of the third groove group and the fourth groove group is 1 / 25 to 1 / 6 of the thickness of the pin 100, and the second width of the grooves of the third groove group and the fourth groove group is 1 to 4 times the second depth. Preferably, the second depth is less than the first depth, so that the grooves of the third groove group and the fourth groove group in the thickness direction of the pin 100 further reduce the toughness of the pin 100 due to the slotting. Thereby, while ensuring the reliable connection between the pin 100 and the sealing layer 002, the toughness of the pin 100 is not affected. Moreover, the dimensions of the pin 100 in the thickness direction and the width direction are maintained at appropriate sizes, so that the pin 100 maintains a large overcurrent capacity and the design requirements of the entire MIPS are guaranteed.

[0046] In some embodiments of the present invention, Figures 2 to 4 , the pin 100 may include two bends, specifically bends 101 and 102, the two bends divide the pin 100 into a starting section 103, a middle section 104 and an end section 105 arranged in sequence along the length direction, and the groove 110 is arranged in at least one of the starting section 103, the middle section 104 and the end section 105. The starting section 103 is the part of the pin 100 installed on the circuit wiring layer 005. Since the pin 100 is generally fixed by welding to the connection pad 0051 on the circuit wiring layer 005, and the area of ​​the connection pad 0051 is small, the length of the starting section 103 of the pin 100 is short, and the middle section 104 forms the same obtuse angle with the starting section 103 and the end section 105, respectively, so that the starting section 103 and the end section 105 are arranged in parallel, and the end section 105 is located above the starting section 103. Moreover, the middle section 104 is also located in the sealing layer 002, and only a small part of the end section 105 is located in the sealing layer 002, and most of the length is located outside the sealing layer 002. Figure 4 It can be seen that the starting section 103 is the shortest, the middle section 104 is the second shortest, and the ending section 105 is the longest. Because when the pin 100 is pulled by external force during the use of MIPS, the position where the pin 100 is exposed from the sealing layer 002 is subjected to the greatest stress, and the closer to the exposed position, the greater the stress, so the groove 110 is preferably set in the ending section 105, so that the connection force generated by the mutual engagement of the groove 110 and the boss 021 of the sealing layer 002 effectively avoids the risk of separation of the sealing layer 002 and the pin 100 surface due to large stress.

[0047] In some embodiments of the present invention, Figure 2 As shown, MIPS also includes a plurality of bonding wires 006, and the bonding wires 006 are connected between a plurality of electronic components, a circuit wiring layer 005, and a plurality of pins 100. For example, the bonding wires 006 can connect electronic components and electronic components, or can connect electronic components and circuit wiring layer 005, or can connect electronic components and pins 100, and circuit wiring layer 005 and pins 100. The electronic components are the IGBT 009, the driver chip, the freewheeling diode 003, and other components such as resistors and capacitors mentioned in the above embodiments. The bonding wires 006 are usually gold wires, copper wires, gold-copper mixed wires, thin aluminum wires of 38um or less, and thick aluminum wires of 100um or more.

[0048] In some embodiments of the present invention, for the sealing layer 002 of the semi-encapsulated structure, the circuit wiring layer 005 and the insulating layer 007 are provided with openings that penetrate through the thickness thereof, and the surface of the heat dissipation substrate 008 is exposed from the openings, and the openings of the heat dissipation substrate 008 are connected to the ground wire of the circuit wiring layer 005 through bonding wires 006. Because the heat dissipation surface of the heat dissipation substrate 008 is exposed on the surface of the MIPS, in order to prevent leakage, the heat dissipation substrate 008 needs to be electrically connected to the ground wire of the circuit wiring layer 005. For example, holes can be opened in the circuit wiring layer 005 and the insulating layer 007 through a hole-transfer process, so that the side of the heat dissipation substrate 008 in contact with the insulating layer 007 is exposed, and then the metal surface of the heat dissipation substrate 008 is connected to the ground wire of the circuit wiring layer 005 through bonding wires 006, so that the grounding of the heat dissipation substrate 008 is achieved, thereby ensuring the safety of the MIPS during operation.

[0049] The present invention also provides a method for manufacturing the MIPS mentioned in the above embodiment, the manufacturing method comprising the following steps:

[0050] Step S100, configuring a heat dissipation substrate 008, and sequentially configuring an insulating layer 007 and a circuit wiring layer 005 on the surface of the heat dissipation substrate 008;

[0051] Step S200, configuring electronic components on the circuit wiring layer 005;

[0052] Step S300, configuring the pin 100, shaping the pin 100 to bend at two positions in the length direction, so as to form a starting section 103, a middle section 104 and an ending section 105 along the length direction of the pin 100, and sequentially opening a first groove group, a third groove group, a second groove group and a fourth groove group near the bending position of the ending section 105 along the length direction of the pin 100, wherein the first groove group and the second groove group are respectively arranged opposite to each other in the width direction of the pin 100, and the third groove group and the fourth groove group are respectively arranged opposite to each other in the thickness direction of the pin 100;

[0053] Step S400, electrically connecting the electronic component, the circuit wiring layer 005, and the pin 100 through the bonding wire 006;

[0054] Step S500, injection molding the heat dissipation substrate 008 provided with electronic components and pins 100 through a packaging mold to form a sealing layer 002, wherein the sealing layer 002 at least covers the side of the heat dissipation substrate 008 on which the electronic components are installed;

[0055] Step S600 , cutting and molding the pins 100 to form a MIPS, and testing the molded MIPS.

[0056] In step S100, it is a step to manufacture the heat dissipation substrate 008. The heat dissipation substrate 008 of suitable size can be designed according to the required circuit layout. For example, for a general MIPS, the size of one can be selected as 64mm×30mm. Taking the heat dissipation substrate 008 as an aluminum substrate made of metal as an example, the aluminum substrate is formed by directly processing the 1m×1m aluminum material with a gong. The gong uses high-speed steel as the material, the motor uses a speed of 5000 rpm, and the gong is cut at a right angle to the aluminum plane; it can also be formed by stamping. Then, the heat dissipation substrate 008 can be treated with corrosion protection on both sides. For the MIPS with a semi-encapsulated structure, the side of the heat dissipation substrate 008 without electronic components is exposed from the sealing layer 002. At this time, the corrosion protection enhances its corrosion resistance during use and is not easily oxidized. For the MIPS with a fully encapsulated structure, in order to save costs, the corrosion protection can also be omitted.

[0057] Then, an insulating layer 007 is arranged on the surface of the heat dissipation substrate 008, and the insulating layer 007 can be formed on the surface of the aluminum substrate by hot pressing. The insulating layer 007 can be made of a resin material such as epoxy resin, and fillers such as aluminum oxide and aluminum carbide are filled inside the resin material to improve thermal conductivity. In order to improve thermal conductivity, the shape of these fillers can be angular. In order to avoid the risk of the fillers damaging the contact surface of the electronic components arranged on the surface, the fillers can be spherical, angular, or a mixture of angular and spherical. In order to improve the withstand voltage characteristics, the thickness of the insulating layer 007 can be designed to be 110um.

[0058] Next, copper foil is laminated on the surface of the insulating layer 007, and then the copper foil is etched and partially removed to form a circuit wiring layer 005, wherein the circuit wiring layer 005 includes a circuit line, the circuit line includes a wiring forming a circuit, and a plurality of connection pads 0051 (not shown in the figure) are provided to connect the wiring. In order to improve the current carrying capacity, the thickness of the circuit wiring layer 005 can be designed to be 0.07 mm.

[0059] Furthermore, a thinner green oil layer (not shown in the figure) can be set on the surface of the circuit wiring layer 005 to prevent damage caused by short circuits between the wirings of the circuit wiring layer 005, and to prevent oxidation and contamination of the surface of the circuit wiring layer 005, thereby playing a protective role.

[0060] In step S200, the electronic components can be fixed to the connection pads 0051 of the circuit wiring layer 005 by welding. For example, the power devices and resistors and capacitors can be welded to the connection pads 0051 by soldering, and the driver chip can be fixed to the connection pads 0051 by epoxy resin adhesive.

[0061] In step S300, this step includes the process of manufacturing the pin 100 and the process of connecting the pin 100 to the connection pad 0051. The manufacturing process of the pin 100 is as follows: All the pins 100 are made of a metal substrate such as a copper substrate, such as a strip with a length of 25 mm, a width of 1.5 mm, and a thickness of 1 mm. For ease of assembly, one end of the pin 100 can be pressed and shaped to a certain curvature. Specifically, the pin 100 can be bent twice in the length direction to form a starting section 103, a middle section 104, and an end section 105 along the length direction of the pin 100, and the middle section 104 forms the same obtuse angle with the starting section 103 and the end section 105, respectively, so that the starting section 103 and the end section 105 are arranged in parallel, and the end section 105 is located above the starting section 103. Then, the portion of the end section 105 near the bend is punched to sequentially open the first groove group, the third groove group, the second groove group and the fourth groove group in the length direction of the pin 100, wherein the first groove group is composed of grooves 111 and 112, the second groove group is composed of grooves 113 and 114, the third groove group is composed of grooves 115 and 116, and the fourth groove group is composed of grooves 117 and 118. The first groove group and the second groove group are respectively arranged opposite to each other in the width direction of the pin 100, and the third groove group and the fourth groove group are respectively arranged opposite to each other in the length and thickness direction of the pin 100. The first depth of the grooves of the first groove group and the second groove group is 1 / 20 to 1 / 5 of the width of the pin 100, and the width of the grooves of the first groove group and the second groove group is 1 to 4 times of the first depth. Since the pin 100 is generally thinner than wide, the second depth of the grooves of the third and fourth groove groups is 1 / 25 to 1 / 6 of the thickness of the pin 100 , and the second width of the grooves of the third and fourth groove groups is 1 to 4 times the second depth.

[0062] Then, a nickel layer is formed on the surface of the pin 100 by chemical plating: a nickel layer is formed on the surface of the copper material that has been formed into a specific shape by mixing a solution of nickel salt and sodium hypophosphite and adding an appropriate chelating agent. The nickel metal has a strong passivation ability and can quickly form an extremely thin passivation film that can resist corrosion from the atmosphere, alkali and certain acids. The nickel plating crystals are extremely fine, and the thickness of the nickel layer is generally 0.1μm; then, through the acid sulfate process, the copper material that has been formed into a shape and a nickel layer is immersed in a plating solution with positive tin ions at room temperature and electrified to form a nickel-tin alloy layer on the surface of the nickel layer. The thickness of the nickel layer is generally controlled at 5μm. The formation of the nickel layer greatly improves the protection and solderability.

[0063] Furthermore, in order to prevent the electronic components from being damaged by static electricity in subsequent processing steps, specific positions of the pins 100 are connected by reinforcing ribs 120, such as Figure 5 This also facilitates the fixation of the pin 100 during the subsequent connection process with the connection pad 0051.

[0064] The process of installing the connecting pin 100 to the connecting pad 0051 is as follows: one end of the pin 100 is placed on the connecting pad 0051, and the other end needs to be fixed by a carrier, which is made of synthetic stone, stainless steel and other materials. Due to the connection function of the reinforcing rib 120 of the pin 100, it is convenient to fix the pin 100 at the position of the pad. Then, the circuit substrate trace placed on the carrier trace is reflowed, the solder paste or silver paste is solidified, and the pin 100 is fixed to the connecting pad 0051 by welding.

[0065] In step S400, this step is a step of connecting the bonding wire 006. Figure 2 As shown, one of the driving bonding pads of the driving chip routing can be directly connected to the gate bonding area of ​​the IGBT009 routing tube (not shown in the figure) through a bonding wire 006 such as a gold wire, a copper wire, a gold-copper mixed wire, or a thin aluminum wire of 38um or less, and the other driving bonding pads of the driving chip routing can be directly connected to the pin 100 routing or connected to the connection pad 0051 of the circuit wiring layer 005 (not shown in the figure) through a bonding wire 006 such as a gold wire, a copper wire, a gold-copper mixed wire, or a thin aluminum wire of 38um or less. The emitter bonding area of ​​the IGBT009 routing tube is directly connected to the connection of the heat dissipation substrate 008 through a thick aluminum wire of um or more.

[0066] In step S500, this step is a step for realizing the sealing layer 002. First, the heat dissipation substrate 008 on which the electronic components and the pins 100 are installed in the above steps can be baked in an oxygen-free environment. The baking time should not be less than 2 hours, and the baking temperature is selected to be 125°C. Then, the heat dissipation substrate 008 after baking is transported to the packaging mold, wherein the packaging mold includes an upper film and a lower film arranged up and down. The pins 100 fixedly connected to the heat dissipation substrate 008 are contacted with the fixing device located in the lower mold to position the heat dissipation substrate 008 so that the heat dissipation surface of the heat dissipation substrate 008 is fitted with the inner surface of the lower mold. At least two ejector pins are arranged on the upper mold, and the free ends of the ejector pins can abut against the circuit wiring layer 005. Through these two ejector pins, the heat dissipation substrate 008 is fitted with the inner surface of the lower mold. Then, the packaging mold with the heat dissipation substrate 008 placed is molded, and the sealing resin is injected from the gate. The method for sealing can be a transfer mold molding using a thermosetting resin or an injection mold molding using a thermosetting resin. Moreover, the gas inside the cavity of the sealing resin injected from the gate is discharged to the outside through the exhaust port. Finally, demoulding is performed. After demoulding, the sealing resin forms a sealing layer 002. Both ends of the sealing layer 002 are provided with mounting grooves formed by the packaging mold. The free end of the pin 100 routing is exposed from the sealing layer 002. In addition, in the part where the end section 105 of the pin 100 is located inside the sealing layer 002, the sealing layer 002 forms a plurality of bosses 021 that are embedded with the groove 110 in the above-mentioned groove group. The bosses 021 are embedded with the groove 110 to form two tight and reliable parts, which avoids the prior art that the pin 100 uses a smooth surface. During use, due to the external pulling force on the pin 100, the surface of the pin 100 is easily separated from the sealing layer 002 to form a small gap, so that the moisture in the surrounding environment invades the inside of the MIPS from these gaps, causing the internal electronic components to leak and eventually fail.

[0067] In step S600, the pin 100 trace of the semi-finished MIPS forming the sealing layer 002 is sheared and shaped. The pin 100 trace can be shaped and the length of the pin 100 can be sheared according to the length and shape required for use, and the reinforcing ribs can be sheared off; and the MIPS is further tested, such as conventional electrical parameter tests, generally including insulation withstand voltage, static power consumption, delay time and other test items, and appearance AOI tests, generally including assembly hole size, pin 100 trace offset and other test items. The qualified ones are finished products. In this way, the entire MIPS manufacturing process is completed.

[0068] The manufacturing method of MIPS of the present invention comprises the following steps: configuring a heat dissipation substrate 008, sequentially configuring an insulating layer 007 and a circuit wiring layer 005 on the surface of the heat dissipation substrate 008, configuring electronic components and pins 100 on the circuit wiring layer 005, shaping the pins 100 to bend at two positions in the length direction to form a starting section 103, a middle section 104 and an ending section 105 along the length direction of the pins 100, and sequentially opening a first groove group, a third groove group, a second groove group and a fourth groove group near the bending position in the ending section 105 along the length direction of the pins 100, wherein the first groove group and the second groove group are respectively arranged opposite to each other in the width direction of the pins 100, and the third groove group and the fourth groove group are respectively arranged opposite to each other in the length and thickness direction of the pins 100; then, the electronic components, the circuit wiring layer 005 and the pins 100 are electrically connected through bonding wires 006, and then, the heat dissipation substrate 008 provided with the electronic components and the pins 100 is injection molded through a packaging mold to form a sealing layer 002, wherein the sealing layer 002 at least covers the heat dissipation substrate 008 The side where the electronic components are installed is cut off and formed to form MIPS, and the formed MIPS is tested. By sequentially arranging the first to fourth groove groups formed by multiple grooves 110 along the length direction of the pin 100, and these grooves are sequentially staggered on the two opposite sides of the thickness and width of the pin 100, when the sealing layer 002 is formed by injection molding, the injection molding body forms a boss 021 in these grooves 110, and the boss 021 and the groove 110 are tightly combined, so that the pin 100 and the sealing layer 002 are tightly combined, avoiding the prior art that the pin 100 uses a smooth surface. During use, due to the external pulling force on the pin 100, the surface of the pin 100 is easily separated from the sealing layer 002 to produce a small gap, so that the moisture in the surrounding environment invades the inside of the MIPS through these gaps, causing the electronic components inside it to leak and eventually fail. Therefore, the stability and reliability of the MIPS during operation are effectively improved.

[0069] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0070] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0071] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0072] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0073] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0074] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A semiconductor circuit, characterized in that: include: A heat dissipation substrate, the heat dissipation substrate comprising a mounting surface and a heat dissipation surface; A circuit wiring layer, the circuit wiring layer is arranged on the mounting surface of the heat dissipation substrate, and the circuit wiring layer is provided with a plurality of connection pads; A plurality of electronic components are arranged on the pads of the circuit wiring layer, and the plurality of electronic components include power devices and driver chips; A plurality of pins, wherein the plurality of pins are arranged on at least one side of the heat dissipation substrate; A sealing layer, wherein the sealing layer wraps one side of the heat dissipation substrate on which the electronic component is disposed, and one end of the pin is exposed from the sealing layer; The portion of the pin located in the sealing layer is provided with grooves at least on two opposite sides thereof; The grooves are arranged on four sides of the pin in both the width direction and the thickness direction; The grooves arranged along the width direction and the thickness direction of the pin are staggered along the length direction of the pin; Four grooves are arranged along the width direction of the pin, which are a first groove group and a second groove group arranged opposite to each other, and four grooves are also arranged along the thickness direction of the pin, which are a third groove group and a fourth groove group arranged opposite to each other, and the first groove group, the third groove group, the second groove group and the fourth groove group are arranged in sequence in the length direction of the pin; The first depth of the grooves of the first groove group and the second groove group is 1 / 20 to 1 / 5 of the width of the pin, and the first width of the grooves of the first groove group and the second groove group is 1 to 4 times of the first depth; The second depth of the grooves of the third groove group and the fourth groove group is 1 / 25 to 1 / 6 of the thickness of the pin, and the second width of the grooves of the third groove group and the fourth groove group is 1 to 4 times the second depth.

2. The semiconductor circuit according to claim 1, characterized in that The pin comprises two bends, which separate the pin into a starting section, a middle section and an ending section arranged in sequence along the length direction, and the groove is arranged in at least one of the starting section, the middle section and the ending section.

3. The semiconductor circuit according to claim 2, characterized in that The groove is arranged in the end section.

4. The semiconductor circuit according to claim 1, wherein: A green oil layer for protection is also provided on the surface of the circuit wiring layer.

5. A method for manufacturing a semiconductor circuit according to any one of claims 1 to 4, characterized in that: The manufacturing method comprises the following steps: Disposing a heat dissipation substrate, and sequentially disposing an insulating layer and a circuit wiring layer on a surface of the heat dissipation substrate; Arrange electronic components on the circuit wiring layer; The pins are configured, and the pins are shaped to be bent at two positions in the length direction to form a starting section, a middle section and an ending section along the length direction of the pins, and a first groove group, a third groove group, a second groove group and a fourth groove group are sequentially provided near the bending position of the ending section along the length direction of the pins, wherein the first groove group and the second groove group are respectively arranged opposite to each other in the width direction of the pins, and the third groove group and the fourth groove group are respectively arranged opposite to each other in the thickness direction of the pins; Electrically connecting the electronic component, the circuit wiring layer, and the pins through bonding wires; Injection molding the heat dissipation substrate provided with the electronic component and the pins through a packaging mold to form a sealing layer, wherein the sealing layer at least covers a side of the heat dissipation substrate on which the electronic component is mounted; The pins are cut and shaped to form the semiconductor circuit, and the shaped semiconductor circuit is tested.

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