Image Sensor

Abstract

Image sensor. An image sensor is disclosed, which may include: a plurality of photodiodes arranged in a matrix in a first direction and a second direction; a plurality of first isolation layers, each two adjacent first isolation layers arranged in the first direction are spaced apart from each other by a first distance, and each first isolation layer is interposed between adjacent photodiodes arranged in the second direction; and a plurality of second isolation layers, each two adjacent second isolation layers arranged in the second direction are spaced apart from each other by a second distance, and each second isolation layer is interposed between adjacent photodiodes arranged in the first direction. The space between two adjacent first isolation layers arranged in the first direction and the space between two adjacent second isolation layers arranged in the second direction overlap to form a blank area surrounded by two adjacent first isolation layers and two adjacent second isolation layers in a substrate including the first isolation layers and the second isolation layers.

Description

Technical Field

[0001] The techniques and implementations disclosed in this patent document generally relate to image sensors for generating electrical signals corresponding to incident light. Background Art

[0002] Image sensors are devices used to capture optical images by converting light into electrical signals using photosensitive semiconductor materials that react to light. With the recent developments in the automotive, medical, computer, and communications industries, the demand for high-performance image sensors is increasing in various devices such as smartphones, digital cameras, game consoles, the Internet of Things (IoT), robots, surveillance cameras, medical micro cameras, etc.

[0003] Image sensors can be roughly divided into image sensors based on charge coupled devices (CCD) and image sensors based on CMOS (complementary metal oxide semiconductor). Compared with CMOS image sensors, CCD image sensors provide the best available image quality, but they tend to consume more power and are larger in size. Compared with CCD image sensors, CMOS image sensors are smaller in size and consume less power. Many different scanning schemes can be used to implement CMOS image sensors, and because CMOS sensors are manufactured using CMOS manufacturing technology, CMOS image sensors and other signal processing circuits can be integrated in a single chip, enabling small-sized image sensors to be manufactured at a lower cost. For these reasons, CMOS image sensors are being intensively studied and are rapidly entering widespread use. Summary of the invention

[0004] This patent document particularly provides a method for manufacturing an image sensor capable of avoiding potential collapse of a photoresist pattern during a patterning process.

[0005] Embodiments of the disclosed technology can be implemented to improve productivity by minimizing defects and variability in the manufacturing process.

[0006] In one embodiment of the disclosed technology, an image sensor may include: a plurality of photodiodes arranged in a matrix in a first direction and a second direction; a plurality of first isolation layers, each two adjacent first isolation layers arranged in the first direction are spaced apart from each other by a first distance, each first isolation layer is interposed between adjacent photodiodes arranged in the second direction; and a plurality of second isolation layers, each two adjacent second isolation layers arranged in the second direction are spaced apart from each other by a second distance, each second isolation layer is interposed between adjacent photodiodes arranged in the first direction. The space between two adjacent first isolation layers arranged in the first direction and the space between two adjacent second isolation layers arranged in the second direction overlap to form a blank area surrounded by two adjacent first isolation layers and two adjacent second isolation layers in a substrate including the first isolation layers and the second isolation layers.

[0007] According to another embodiment of the disclosed technology, an image sensor may include: a plurality of photodiodes arranged in a matrix shape; a plurality of first isolation layers arranged at regular intervals in a first direction and a second direction, each two adjacent first isolation layers arranged in the first direction are spaced apart from each other by a first distance, and each first isolation layer is interposed between adjacent photodiodes arranged in the second direction; and a plurality of second isolation layers arranged at regular intervals in the first direction and the second direction, each two adjacent second isolation layers arranged in the second direction are spaced apart from each other by a second distance, and each second isolation layer is interposed between adjacent photodiodes arranged in the first direction. A blank area is formed at an area surrounded by four adjacent photodiodes in a substrate including the first isolation layers and the second isolation layers.

[0008] It should be understood that the foregoing general description, the accompanying drawings, and the following detailed description in this patent document are examples and explanations of the technical features and implementations of the disclosed technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating an example of an image sensor based on some implementations of the disclosed technology.

[0010] Figure 2 is an example of Figure 1 A cross-sectional view of an example of a unit pixel taken along line AA′ is shown.

[0011] Figure 3 is a layout diagram illustrating an example of a pixel array according to one embodiment of the disclosed technology.

[0012] Figure 4 is an example for forming Figure 3 A plan view of an example of a first photoresist of a first deep photodiode (DPD) isolation layer is shown.

[0013] Figure 5 is an example for forming Figure 3 A plan view of an example of a second photoresist for a second DPD isolation layer is shown.

[0014] Figure 6 It is an example Figure 4 A perspective view of an example of a first photoresist is shown.

[0015] Figure 7 is a layout diagram illustrating an example of a pixel array according to another embodiment of the disclosed technology.

[0016] Figure 8 is an example for forming Figure 7 A plan view of an example of a first photoresist of a first DPD isolation layer is shown.

[0017] Fig. 9 is an example for forming Figure 7 A plan view of an example of a second photoresist for a second DPD isolation layer is shown.

[0018] Fig.10 It is an example Figure 8 A perspective view of an example of a first photoresist is shown.

[0019] Fig.11A is a layout diagram illustrating an example of a pixel array that may be used in a first manufacturing process based on some implementations of the disclosed technology.

[0020] Fig. 11B is an example of some implementations based on the disclosed technology. Fig.11A An example cross-sectional view of a pixel array taken along a first cutting line is shown.

[0021] Fig. 11C is an example of some implementations based on the disclosed technology. Fig.11A An example cross-sectional view of a pixel array taken along a second cutting line is shown.

[0022] Fig. 12A is a layout diagram illustrating an example of a pixel array that may be used in a second manufacturing process based on some implementations of the disclosed technology.

[0023] Fig. 12B is an example of some implementations based on the disclosed technology. Fig. 12A An example cross-sectional view of a pixel array taken along a first cutting line is shown.

[0024] Fig. 12C is an example of some implementations based on the disclosed technology. Fig. 12A An example cross-sectional view of a pixel array taken along a second cutting line is shown.

[0025] Fig.13A is a layout diagram illustrating an example of a pixel array that may be used in a third manufacturing process based on some implementations of the disclosed technology.

[0026] Fig. 13B is an example of some implementations based on the disclosed technology. Fig.13A An example cross-sectional view of a pixel array taken along a first cutting line is shown.

[0027] Fig. 13C is an example of some implementations based on the disclosed technology. Fig.13A An example cross-sectional view of a pixel array taken along a second cutting line is shown.

[0028] Fig.14A is a layout diagram illustrating an example of a pixel array that can be used in a fourth manufacturing process based on some implementations of the disclosed technology.

[0029] Fig. 14B is an example of some implementations based on the disclosed technology. Fig.14A An example cross-sectional view of a pixel array taken along a first cutting line is shown.

[0030] Fig. 14C is an example of some implementations based on the disclosed technology. Fig.14A An example cross-sectional view of a pixel array taken along a second cutting line is shown.

[0031] Fig.15A is a layout diagram illustrating an example of a pixel array that can be used in a fifth manufacturing process based on some implementations of the disclosed technology.

[0032] Fig. 15B is an example of some implementations based on the disclosed technology. Fig.15A An example cross-sectional view of a pixel array taken along a first cutting line is shown.

[0033] Fig. 15C is an example of some implementations based on the disclosed technology. Fig.15A An example cross-sectional view of a pixel array taken along a second cutting line is shown.

[0034] Fig.16A is a layout diagram illustrating an example of a pixel array that can be used in a sixth manufacturing process based on some implementations of the disclosed technology.

[0035] Fig. 16B is an example of some implementations based on the disclosed technology. Fig.16A An example cross-sectional view of a pixel array taken along a first cutting line is shown.

[0036] Fig. 16C is an example of some implementations based on the disclosed technology. Fig.16A An example cross-sectional view of a pixel array taken along a second cutting line is shown.

[0037] Fig.17A is a layout diagram illustrating an example of a pixel array that can be used in a seventh manufacturing process based on some implementations of the disclosed technology.

[0038] Fig. 17B is an example of some implementations based on the disclosed technology. Fig.17A An example cross-sectional view of a pixel array taken along a first cutting line is shown.

[0039] Fig. 17C is an example of some implementations based on the disclosed technology. Fig.17A An example cross-sectional view of a pixel array taken along a second cutting line is shown. DETAILED DESCRIPTION

[0040] This patent document provides implementations and examples of image sensors that can improve the stability of patterns used to form photodiodes, transistors, interconnects, and other material layers, thereby minimizing defects and variability in the manufacturing process.

[0041] Now with detailed reference to the embodiments of the disclosed technology, examples of the embodiments of the disclosed technology are shown in the accompanying drawings. As much as possible, the same reference numerals will be used throughout the accompanying drawings to represent the same or similar parts. Although the present disclosure is susceptible to various modifications and alternative forms, its specific embodiments are shown by way of example in the accompanying drawings. However, the present disclosure should not be construed as being limited to the embodiments set forth herein, but on the contrary, the present disclosure is intended to cover all modifications, equivalents and substitutions that fall within the spirit and scope of the embodiments. In the accompanying drawings, the size and shape of the elements may be exaggerated for ease of description and clarity.

[0042] Figure 1 is a block diagram illustrating an example of an image sensor 100 based on some implementations of the disclosed technology.

[0043] In some implementations, the image sensor 100 used as a complementary metal oxide semiconductor (CMOS) image sensor may include a pixel array 110, a row decoder 120, a correlated double sampling (CDS) circuit 130, an analog-to-digital converter (ADC) 140, an output buffer 150, a column decoder 160, and a timing controller 170. In this case, the above-mentioned constituent elements of the image sensor 100 are only examples, and at least some of the constituent elements may be added to or omitted from the image sensor 100 as needed.

[0044] The pixel array 110 may include a plurality of unit pixels 200 arranged in rows and columns in a two-dimensional (2D) array in different row and column directions (e.g., orthogonal to each other). A plurality of unit pixels may be arranged so that at least two unit pixels share at least one element. For example, a plurality of unit pixels may be arranged in a shared pixel structure in which at least one element is shared by two or more unit pixels to convert an optical signal or incident light into an electrical signal. In some implementations, each unit pixel or each shared pixel may include more than one transistor and a photodiode. For example, each unit pixel or each shared pixel may correspond to a 3T pixel (3 transistors per pixel), a 4T pixel (4 transistors per pixel), or a 5T pixel (5 transistors per pixel), or may include more than 5 transistors per unit. The pixel array 110 may receive control signals such as a row select signal, a pixel reset signal, and a transmission (Tx) signal from a row decoder 120, and may operate based on the control signal received from the row decoder 120.

[0045] The row decoder 120 may be used to select a desired row of the pixel array 110 based on a control signal generated by the timing controller 170. In some implementations, when selecting a row from the pixel array 110, the row decoder 120 may generate a row selection signal to select at least one of the plurality of rows. The row decoder 120 may sequentially enable a pixel reset signal for resetting pixels corresponding to at least one selected row and a transmission (Tx) signal for the selected pixel to transmit an electrical signal generated by the pixel. In this manner, an analog reference signal and an image signal generated from each pixel of the selected row may be sequentially sent to the CDS circuit 130. In this regard, the reference signal and the image signal may be collectively referred to as a pixel signal as needed.

[0046] The CMOS image sensor may use correlated double sampling (CDS) to remove the undesired offset value of the pixel by sampling the pixel signal twice to remove the difference between the two samples. In one example, correlated double sampling (CDS) may remove the undesired offset value of the pixel by comparing the pixel output voltage obtained before and after the light signal is incident on the pixel, so that only the pixel output voltage based on the incident light may be measured. In some embodiments of the disclosed technology, the CDS circuit 130 may sequentially sample and hold the reference signal and the image signal transmitted from the pixel array 110 to each of the plurality of column lines. That is, the CDS circuit 130 may sample and hold the voltage levels of the reference signal and the image signal corresponding to each column of the pixel array 110.

[0047] Upon receiving a control signal from the timing controller 170 , the CDS circuit 130 may transmit a correlated double sampling (CDS) signal corresponding to the reference signal and the image signal for each column to the ADC 140 .

[0048] ADC 140 is used to convert the analog CDS signal into a digital signal. Examples of ADC 140 may include a ramp comparison ADC that compares the analog pixel signal with a reference signal such as a ramp signal that ramps up or ramps down, and a timer that counts until the voltage of the ramp signal matches the analog pixel signal. In some embodiments of the disclosed technology, ADC 140 may receive a CDS signal for each column from CDS circuit 130, may convert the received CDS signal into a digital signal, and may thus output a digital signal. In some implementations, ADC 400 samples an input signal (e.g., a pixel signal) multiple times using a reference signal, and performs analog-to-digital conversion on the sampled input signal by counting the number of clock pulses before the crossing point. ADC 140 may perform such counting and calculation operations based on the CDS signal for each column and the ramp signal received from timing controller 170, so that ADC 140 may generate digital image data from which noise corresponding to each column (e.g., a unique reset noise for each pixel) is removed.

[0049] ADC 140 may include a plurality of column counters corresponding to respective columns of pixel array 110, and may convert the CDS signal of each column into a digital signal using the column counters, thereby forming image data. In another embodiment, ADC 140 may include a single global counter, and may convert the CDS signal corresponding to each column into a digital signal using a global code received from the global counter.

[0050] The output buffer 150 may receive the image data of each column received from the ADC 140. In addition, the output buffer 150 may capture the received image data and output the captured image data. Upon receiving a control signal from the timing controller 170, the output buffer 150 may temporarily store the image data output from the ADC 140. The output buffer 150 may operate as an interface configured to compensate for a data rate difference or a transmission (Tx) speed difference between the image sensor 100 and another device coupled to the image sensor 100.

[0051] Upon receiving a control signal from the timing controller 170, the column decoder 160 may select a column of the output buffer 150 and may cause the output buffer 150 to sequentially output the temporarily stored image data. In some implementations, the column decoder 160 may receive an address signal from the timing controller 170, may generate a column selection signal based on the received address signal, and may select a column of the output buffer 150 to output the image data of the selected column from the output buffer 150 as the output signal S0.

[0052] The timing controller 170 may control the row decoder 120 , the ADC 140 , the output buffer 150 , and the column decoder 160 .

[0053] The timing controller 170 may transmit a clock signal for operating or synchronizing the constituent elements of the image sensor 100, a control signal for timing control, and an address signal for selecting a row or column to the row decoder 120, the column decoder 160, the ADC 140, and the output buffer 150. In some implementations, the timing controller 170 may include a logic control circuit, a phase-locked loop (PLL) circuit, a timing control circuit, a communication interface circuit, and the like.

[0054] Figure 2 It is an example of Figure 1 A cross-sectional view of an example of a unit pixel 200 taken along line AA′ in the pixel array 110 is shown.

[0055] In some implementations, the unit pixel 200 may refer to any unit pixel in the pixel array 110. Although the line AA' is illustrated as extending along the row direction of the pixel array 110 by way of example, the line AA' may also be along the column direction of the pixel array 110.

[0056] In some implementations, the unit pixel 200 may include a substrate region 300 and a light incident region 400 .

[0057] The substrate region 300 may include one or more photodiodes 310 and one or more isolation layers 340 configured to electrically (and / or optically) isolate the one or more photodiodes 310 from adjacent photodiodes 310. Figure 2 Each of the photodiode 310 and the isolation layer 340 is drawn using a straight line, but it should be noted that the photodiode 310 and the isolation layer 340 are formed by ion implantation (see Fig.11A ), therefore, each of the photodiode 310 and the isolation layer 340 may have a bent shape.

[0058] For example, the substrate region 300 may include a doped region, which may be formed by implanting impurity ions corresponding to the n-type region or the p-type region of the photodiode 310 and the isolation layer 340. In one example, the substrate region 300 doped with impurity ions may include a P-type or N-type bulk substrate, a P-type bulk substrate having a P-type or N-type epitaxial layer grown therein, or an N-type bulk substrate having a P-type or N-type epitaxial layer grown therein.

[0059] Photodiode 310 can generate and accumulate photocharge in response to received incident light. In some implementations, photodiode 310 can be formed as an N-type doped region by ion implantation of N-type ions. Photodiode 310 can be formed by stacking multiple doped regions on top of each other. That is, Figure 2 As shown, the photodiode 310 may include a shallow photodiode (SPD) 320 formed at an upper region of the substrate region 300 and a deep photodiode (DPD) 330 formed at a bottom region of the substrate region 300. Therefore, the SPD 320 and the DPD 330 may form one photodiode 310. The SPD 320 and the DPD 330 are doped with the same conductivity type to generate and accumulate photocharges according to the intensity of the incident light, respectively. In addition, the SPD 320 and the DPD 330 are vertically stacked to increase the photoelectric conversion efficiency, which represents the efficiency with which the incident light is converted into photocharges. In addition, the SPD 320 and the DPD 330 have a potential gradient so that the photocharges accumulated in the SPD 320 and the DPD 330 can be easily transferred to a floating diffusion node for converting a certain amount of photocharges into an electrical signal. That is, the SPD 320 and the DPD 330 may have different doping concentrations from each other. In some implementations, the DPD 330 may be formed by injecting N + ions, and SPD 320 can be formed by implanting N - In other implementations, the SPD 320 and the DPD 330 may also be formed to have the same doping concentration.

[0060] The isolation layer 340 may be formed to extend deeply in the vertical direction in such a manner that the photodiodes 310 of adjacent pixels can be electrically and optically isolated from each other. The isolation layer 340 may include: an SPD isolation layer 350 interposed between adjacent SPDs 320 to isolate the SPD 320 from the adjacent SPDs 320; and a DPD isolation layer 360 interposed between adjacent DPDs 330 to isolate the DPD 330 from the adjacent DPDs 330. Therefore, the SPD isolation layer 350 is formed above the DPD isolation layer 360. Although each of the SPD isolation layer 350 and the DPD isolation layer 360 is described as being formed by implanting P +ions, but the SPD isolation layer 350 and the DPD isolation layer 360 may be N-type doped regions.

[0061] In some implementations, the light incident region 400 may be formed above the substrate region 300, and incident light received from the outside may pass through the light incident region 400 before reaching the photodiode 310 after passing through a main lens (not shown). The light incident region 400 may include a color filter 410, a grid 420, and a microlens 430.

[0062] The color filter 410 may be formed over the substrate region 300. The color filter 410 may selectively transmit light of a certain wavelength (e.g., light of a red wavelength, light of a green wavelength, light of a blue wavelength, light of a magenta wavelength, light of a yellow wavelength, light of a cyan wavelength) while blocking light of other wavelengths. In some implementations, the unit pixel 200 including the depth pixel may be formed without the color filter 410, or the unit pixel 200 including the depth pixel may be formed with an infrared (IR) color filter. In some implementations, an anti-reflective film (not shown) may be disposed between the color filter 410 and the substrate region 300.

[0063] The grid 420 may be disposed between adjacent color filters 410 to prevent optical crosstalk caused by incident light having passed through the color filter 410 from entering another unit pixel. The grid 420 may include a material having a high light absorption rate (e.g., tungsten), or may include a material having a relatively lower refractive index than the color filter 410 (e.g., a silicon insulating layer, air, etc.).

[0064] The microlens 430 may be formed above the color filter 410 and may increase the light-gathering capability of incident light, thereby improving the light receiving (Rx) efficiency of the photodiode 310. In some implementations, a coating layer (not shown) may also be formed to prevent diffuse reflection of incident light received from the outside, thereby suppressing flare characteristics.

[0065] Figure 3 is a layout diagram illustrating an example of a pixel array 500 according to one embodiment of the disclosed technology.

[0066] exist Figure 3 In the illustrated example, the pixel array 500 includes unit pixels arranged in a (5×5) matrix as an example.

[0067] Figure 3 The pixel array 500 shown in FIG. 5 includes a layout including a first DPD spacer 510 , a second DPD spacer 520 , and a DPD 530 in each unit pixel.

[0068] The first DPD isolation layer 510 and the second DPD isolation layer 520 may correspond to Figure 2 The DPD isolation layer 360 is shown. The DPD 530 may correspond to Figure 2 DPD 330 is shown.

[0069] The DPDs 530 may be spaced apart from each other by a predetermined distance and arranged in a (5×5) matrix in the row and column directions of the pixel array 500 .

[0070] The first DPD spacers 510 may be arranged at regular intervals in rows and columns, such that every two adjacent first DPD spacers 510 are spaced apart from each other by a first distance in the first direction (i.e., in the row direction of the pixel array 500), while being interposed between the DPDs 530 in the second direction. In some implementations, a plurality of first DPD spacers 510 may be arranged at regular intervals in the row direction. The horizontal length of the first DPD spacers 510 may be equal to or greater than the horizontal length of the DPDs 530, and the vertical length thereof may be equal to or less than the separation distance between the adjacent DPDs 530 arranged in the column direction. Although the first distance is equal to or less than the distance between the adjacent DPDs 530 arranged in the row direction, it should be noted that the first distance may also be greater than the distance between the adjacent DPDs 530 arranged in the row direction.

[0071] The second DPD spacers 520 may be arranged at regular intervals in rows and columns, so that every two adjacent second DPD spacers 520 are spaced apart from each other by a second distance in the second direction (i.e., in the column direction of the pixel array 500), while being interposed between the DPDs 530 in the first direction. In some implementations, a plurality of second DPD spacers 520 may be arranged at regular intervals in the column direction. The vertical length of each of the second DPD spacers 520 may be equal to or greater than the vertical length of each DPD 530, and the horizontal length thereof may be equal to or less than the separation distance between adjacent DPDs 530 arranged in the row direction. Although the second distance is equal to or less than the separation distance between adjacent DPDs 530 arranged in the column direction, it should be noted that the second distance according to another embodiment may also be greater than the separation distance between adjacent DPDs 530 arranged in the column direction.

[0072] In one implementation, the first distance and the second distance may be the same as each other. In another implementation, the first distance and the second distance may be different from each other.

[0073] Since the first DPD isolation layer 510 and the second DPD isolation layer 520 are arranged at regular intervals in the row direction and the column direction, respectively, the blank area 540 may be provided at an area where a first area between the first DPD isolation layers 510 adjacent to each other overlaps with a second area between the second DPD isolation layers 520 adjacent to each other. In other words, the blank area 540 may be provided at a central portion surrounded by four DPDs 530 arranged in a (2×2) matrix, or the blank area 540 may be provided at an intersection area of ​​a first extension line and a second extension line, the first DPD isolation layers 510 arranged in the first direction are connected to each other through the first extension line, and the second DPD isolation layers 520 arranged in the second direction are connected to each other through the second extension line.

[0074] Neither the first DPD spacer 510 nor the second DPD spacer 520 may be disposed in the blank area 540. In addition, the blank area 540 may have a horizontal length corresponding to the first distance and a vertical length corresponding to the second distance.

[0075] Figure 4 is an example for forming Figure 3 A plan view of an example of a first photoresist 600 of a first DPD spacer layer 510 is shown.

[0076] In some implementations, the first photoresist 600 may be used in an ion implantation process for forming the first DPD isolation layer 510. The first photoresist 600 may be formed of a polymer compound that reacts to light or an electron beam.

[0077] The first photoresist 600 may include a main pattern 610, a support pattern 620, and an open region 630. The first photoresist 600 may be formed in a ladder shape in which all portions of the first photoresist 600 are connected to each other and integrated into one structure.

[0078] The main pattern 610 may be formed as a straight line extending in the first direction, and a width of the main pattern 610 may be equal to a distance between two adjacent first DPD spacers 510 when the first DPD spacers 510 are formed at regular intervals in the column direction.

[0079] The support pattern 620 may be formed in a specific shape by which the main patterns 610 are connected to each other. The horizontal length of the support pattern 620 may be equal to the first distance, and the vertical length of the support pattern 620 may be equal to or similar to the vertical length of the first DPD isolation layer 510. In some implementations, when the support patterns 620 are arranged continuously, the distance between two adjacent support patterns 620 may be equal to or similar to the horizontal length of the first DPD isolation layer 510.

[0080] In the context of this patent document, the word “equal” may indicate not only equal lengths or distances but also similar lengths or distances.

[0081] The open region 630 may be surrounded by a first region between adjacent main patterns 610 and a second region between adjacent support patterns 620. During the ion implantation process, ions for forming the first DPD isolation layer 510 may be implanted through the open region 630.

[0082] Figure 5 is an example for forming Figure 3 A plan view of an example of a second photoresist 700 of a second DPD spacer layer 520 is shown.

[0083] In some implementations, the second photoresist 700 may be used in an ion implantation process for forming the second DPD isolation layer 520. The second photoresist 700 may be formed of a polymer compound that reacts to light or an electron beam.

[0084] The second photoresist 700 may include a main pattern 710, a support pattern 720, and an open region 730. The second photoresist 700 may be formed in a ladder shape in which all portions of the second photoresist 700 are connected to each other and integrated into one structure.

[0085] The main pattern 710 may be formed as a straight line extending in the second direction, and a width of the main pattern 710 may be equal to or similar to a distance between two adjacent second DPD spacers 520 when the second DPD spacers 520 are formed at regular intervals along the row direction.

[0086] The support pattern 720 may be formed into a specific shape by which the adjacent main patterns 710 are connected to each other. The vertical length of the support pattern 720 may be equal to or similar to the second distance, and the horizontal length of the support pattern 720 may be equal to the horizontal length of the second DPD isolation layer 520. In some implementations, the separation distance between adjacent support patterns 720 may be equal to or similar to the vertical length of the second DPD isolation layer 520.

[0087] The open region 730 may be an open region defined not only by a first region between adjacent main patterns 710 but also by a second region between adjacent support patterns 720. During the ion implantation process, ions for forming the second DPD spacer 520 may be implanted through the open region 730.

[0088] Figure 6 It is an example Figure 4 A perspective view of an example of a first photoresist 600 is shown.

[0089] In some implementations, the Figure 4 650 of the first photoresist 600 shown in FIG. Figure 6 Only three main patterns 610 are shown in FIG. 6 , but it should be noted that the remaining main patterns can also be integrated into one structure through the support pattern.

[0090] from Figure 6 It can be seen that the first photoresist 600 may be formed to have a sufficient height to form the first DPD isolation layer 510 .

[0091] The photodiode 310 may be arranged over as large an area as possible to increase the fill factor indicating light receiving (Rx) efficiency. However, as the size of image sensor chips gradually decreases and the demand for high-resolution image sensors rapidly increases, the size of the area occupied by only one pixel gradually decreases. In addition, in order to increase the fill factor and ensure the volume of the photodiode 310, the DPD 330 may also be formed under the substrate area 300.

[0092] However, the ion implantation process requires relatively high energy in order to form the DPD 330 and the DPD isolation layer 360 under the substrate region 300. In order to avoid damage caused by the ion implantation process, it is desirable that the photoresist has a greater thickness.

[0093] In order to form a thicker photoresist required for forming the DPD isolation layer 360, the PR slope of the photoresist (i.e., the slope of the photoresist wall relative to the plane) may be increased. Such an increase in the PR slope may reduce the stability of the photoresist and may cause the collapse or tilt of the photoresist, so that the quality of the DPD 330 may be degraded due to the ion implantation process.

[0094] In addition, a thick photoresist having a narrow pattern may deteriorate a critical dimension (CD) dispersion rate (or may deteriorate uniformity of a target CD), and thus, the quality of the DPD 330 may be deteriorated due to the ion implantation process.

[0095] A double patterning scheme may be implemented using embodiments of the disclosed technology to form the DPD isolation layer 360. In the double patterning scheme, after forming the DPD isolation layer extending in the row direction using a photoresist having an elongated pattern extending in the row direction, instead of using a photoresist having a specific area corresponding to each DPD 330, the DPD isolation layer extending in the column direction is formed using a photoresist having an elongated pattern extending in the column direction.

[0096] However, since each of the elongated patterns has a very small width, the stability of the photoresist is low, causing the photoresist to collapse in a photolithography process including an ion implantation process. For example, unlike the first photoresist 600, in a photolithography process for forming a photoresist consisting of only the main pattern 610 without using the support pattern 620, the main pattern 610 may easily collapse toward an adjacent main pattern 610 adjacent thereto. Such collapse of the main pattern 610 may have a serious adverse effect on the quality of the image sensor and at the same time may reduce productivity.

[0097] However, the first photoresist 600 may include support patterns 620 that are spaced apart from each other by a predetermined distance and maintain a constant interval between the main patterns 610, so that the first photoresist 600 can prevent the collapse of the main pattern 610. In this case, the width (or first distance) of each support pattern 620 may be determined through experiments in such a manner that the first photoresist 600 can prevent the collapse of the main pattern 610 while also ensuring the function of the first DPD isolation layer 510.

[0098] Although a perspective view of the second photoresist 700 is not shown in the drawings, the second photoresist 700 may be formed in the same manner as the first photoresist 600 .

[0099] The blank area 540 is formed in the ion implantation process using the first photoresist 600 and the second photoresist 700. However, if the blank area 540 has a specific size that does not affect the function of physically isolating the adjacent DPDs 530 from each other, the blank area 540 can ensure the manufacturing stability of the semiconductor device without reducing the performance of the image sensor.

[0100] Figure 7 is a layout diagram illustrating an example of a pixel array 800 according to another embodiment of the disclosed technology.

[0101] In some implementations, the pixel array 800 may include a layout structure in each unit pixel, the layout structure including first DPD spacers 810 and 815 , second DPD spacers 820 and 825 , and a DPD 830 .

[0102] The first DPD isolation layers 810 and 815 and the second DPD isolation layers 820 and 825 may correspond to Figure 2 The DPD isolation layer 360 is shown. The DPD 830 may correspond to Figure 2 DPD 330 is shown.

[0103] The DPDs 830 may be spaced apart from each other by a predetermined distance, and may be formed in a (5×5) matrix arranged in the row and column directions of the pixel array 800 .

[0104] The first DPD isolation layers 810 may extend in a first direction (i.e., in the row direction of the pixel array 800) while being interposed between adjacent DPDs 830 and may be connected to each other to form a structure. That is, each of the first DPD isolation layers 810 may be viewed as a solid line connected to each other. The vertical length of each of the first DPD isolation layers 810 may be equal to or less than the separation distance between adjacent DPDs 830 arranged in the column direction. Each of the first DPD isolation layers 810 may also be defined as a third DPD isolation layer in a manner that the first DPD isolation layer 810 may be distinguished from the first DPD isolation layer 815.

[0105] The first DPD spacers 815 may be spaced apart from each other by a first distance in the first direction while being interposed between adjacent DPDs 830, and may be arranged continuously. In some implementations, a plurality of first DPD spacers 815 may be arranged at regular intervals in the row direction. The horizontal length of each of the first DPD spacers 815 may be equal to or greater than the horizontal length of each DPD 830, and the vertical length thereof may be equal to or less than the separation distance between adjacent DPDs 830 arranged in the column direction. Although the first distance may be equal to or less than the separation distance between adjacent DPDs 830 arranged in the row direction, it should be noted that the first distance according to another embodiment may also be greater than the separation distance between adjacent DPDs 830 arranged in the row direction.

[0106] from Figure 7 It can be seen that the row lines corresponding to the first DPD isolation layer 810 and the row lines corresponding to the first DPD isolation layer 815 may be alternately arranged in the second direction.

[0107] Each of the second DPD isolation layers 820 may extend in the second direction (i.e., in the column direction of the pixel array 800) while being interposed between adjacent DPDs 830, so that the second DPD isolation layers 820 may be connected to each other to form a structure. That is, each of the second DPD isolation layers 820 may be viewed as a solid line connected to each other. The horizontal length of each of the second DPD isolation layers 820 may be equal to or less than the separation distance between adjacent DPDs 830 arranged in the row direction. Each of the second DPD isolation layers 820 may also be defined as a fourth DPD isolation layer in a manner that the second DPD isolation layer 820 may be distinguished from the second DPD isolation layer 825.

[0108] The second DPD isolation layers 825 may be spaced apart from each other by a second distance in the second direction while being interposed between adjacent DPDs 830, and may be arranged continuously. In some implementations, a plurality of second DPD isolation layers 825 may be arranged at regular intervals in the column direction. The vertical length of each of the second DPD isolation layers 825 may be equal to or greater than the vertical length of each DPD 830, and the horizontal length thereof may be equal to or less than the separation distance between adjacent DPDs 830 arranged in the row direction. Although the second distance may be equal to or less than the separation distance between adjacent DPDs 830 arranged in the column direction, it should be noted that the second distance according to another embodiment may also be greater than the separation distance between adjacent DPDs 830 arranged in the column direction.

[0109] from Figure 7 It can be seen that the row lines corresponding to the second DPD isolation layer 820 and the row lines corresponding to the first DPD isolation layer 825 may be alternately arranged in the first direction.

[0110] In this case, the first distance and the second distance may be equal to each other, or may be different from each other.

[0111] Since the first DPD spacers 815 and the second DPD spacers 825 are arranged at regular intervals in the row direction and the column direction, respectively, the blank area 840 may be provided at an area where a first area between the first DPD spacers 815 adjacent to each other overlaps with a second area between the second DPD spacers 825 adjacent to each other. In other words, in an area where a first area between the first DPD spacers 810 overlaps with a second area between the second DPD spacers 820, the blank area 840 may be provided at a central portion of a specific area (AR1) composed of four DPD spacers 830 arranged in a (2×2) matrix, or the blank area 840 may be provided at an intersection area between a first extension line through which the first DPD spacers 815 arranged in the first direction are connected to each other and a second extension line through which the second DPD spacers 825 arranged in the second direction are connected to each other.

[0112] Neither the first DPD isolation layers 810 and 815 nor the second DPD isolation layers 820 and 825 may be disposed in the blank area 840 .

[0113] In contrast, the blank area may not be formed at the intersection area between the extension lines through which the first DPD isolation layer 810 and the second DPD isolation layer 825 are connected to each other, or may not be formed at the intersection area between the first DPD isolation layer 810 and the second DPD isolation layer 820 .

[0114] In addition, the blank area may not be formed at the intersection area between the extension lines of the second DPD isolation layer 820 and the first DPD isolation layer 815 for connecting to each other, or may not be formed at the intersection area between the second DPD isolation layer 820 and the first DPD isolation layer 810 .

[0115] Figure 8 is an example for forming Figure 7 A plan view of an example of a first photoresist 900 of first DPD spacer layers 810 and 815 is shown.

[0116] In some implementations, the first photoresist 900 may be used in an ion implantation process for forming the first DPD isolation layers 810 and 815. The first photoresist 900 may be formed of a polymer compound that reacts to light or an electron beam.

[0117] The first photoresist 900 may include a main pattern 910, a support pattern 920, and an opening region 930. Figure 4 different, Figure 8 The first photoresist 900 shown in FIG. 8 may be formed in a ladder shape spaced apart every two main patterns 910 .

[0118] The main pattern 910 may be formed as a straight line extending in the first direction, and a width of the main pattern 910 may be equal to a distance between two adjacent first DPD spacers 810 and 815 when the first DPD spacers 810 and 815 are formed at regular intervals along the column direction.

[0119] The support pattern 920 may be formed into a specific shape by which the adjacent main patterns 910 are connected to each other. The horizontal length of the support pattern 920 may be equal to the first distance, and the vertical length of the support pattern 920 may be equal to the vertical length of the first DPD isolation layer 815. In some implementations, the distance between adjacent support patterns 920 may be equal to or similar to the horizontal length of the first DPD isolation layer 815.

[0120] The open region 930 may be surrounded by a first region between adjacent main patterns 910 and a second region between adjacent support patterns 920. During the ion implantation process, ions for forming the first DPD isolation layer 815 may be implanted through the open region 930.

[0121] In addition, as described above, the first photoresist 900 may be formed in a ladder-like shape spaced apart from adjacent ladder-like photoresist patterns (two main patterns 910 are connected by a plurality of connection patterns 920). Here, the distance between the first photoresists 900 spaced apart from each other and adjacent to each other may be equal to or similar to the vertical length (ie, width) of the first DPD isolation layer 810.

[0122] Fig. 9 is an example for forming Figure 7 A plan view of an example of a second photoresist 1000 with second DPD spacer layers 820 and 825 is shown.

[0123] In some implementations, the second photoresist 1000 may be used in an ion implantation process for forming the second DPD isolation layers 820 and 825. The second photoresist 1000 may be formed of a polymer compound that reacts to light or an electron beam.

[0124] The second photoresist 1000 may include a main pattern 1010, a support pattern 1020, and an opening region 1030. Figure 5 different, Fig. 9 The second photoresist 1000 shown may be formed in a ladder shape spaced apart every two main patterns 1010 .

[0125] The main pattern 1010 may be formed as a straight line extending in the second direction, and a width of the main pattern 1010 may be equal to a distance between two adjacent second DPD spacers 820 and 825 when the two second DPD spacers 820 and 825 are formed at regular intervals along the row direction.

[0126] The support pattern 1020 may be formed into a specific shape by which the adjacent main patterns 1010 are connected to each other. The vertical length of the support pattern 1020 may be the same as the second distance, and the horizontal length of the support pattern 1020 may be equal to or similar to the horizontal length of the second DPD isolation layer 825. In some implementations, the separation distance between adjacent support patterns 1020 may be equal to or similar to the vertical length of the second DPD isolation layer 825.

[0127] The open region 1030 may be surrounded by a first region between adjacent main patterns 1010 and a second region between adjacent support patterns 1020. During the ion implantation process, ions for forming the second DPD spacer 825 may be implanted through the open region 1030.

[0128] In addition, as described above, the second photoresist 1000 may be formed in a ladder shape where every two main patterns 1010 are spaced apart (two main patterns 1010 are connected by a plurality of connection patterns 1020). Here, the distance between the second photoresists 1000 spaced apart and adjacent to each other may be equal to the horizontal length (ie, width) of the second DPD isolation layer 820.

[0129] Fig.10 It is an example Figure 8 A perspective view of an example of a first photoresist 900 is shown.

[0130] Reference Fig.10 , exemplifies Figure 8 A perspective view 950 of the first photoresist 900 is shown.

[0131] from Fig.10 It can be seen that the first photoresist 900 may be formed to have a sufficient height to form the first DPD isolation layers 810 and 815 .

[0132] The first photoresist 900 may include support patterns 920 that are spaced apart from each other by a predetermined distance and maintain a constant interval between adjacent main patterns 910, so that the first photoresist 900 can prevent the main pattern 910 from collapsing. In this case, the width (or first distance) of each support pattern 920 may be determined experimentally in such a manner that the first photoresist 900 can prevent the main pattern 910 from collapsing while also ensuring the function of the first DPD isolation layer 815. Although the support patterns 920 are not provided on both sides of each main pattern 910, the support patterns 920 can provide higher shape stability than other cases where the support patterns 920 are not used.

[0133] That is, linear patterning based on the four photodiodes 830 can be implemented on the outer walls of the four photodiodes 830, and dot-dash line patterning can be implemented at the isolation layer among the four photodiodes 830, so that the dispersion characteristics of the 4-shared pixels can be minimized while ensuring the shape stability of the narrow photoresist.

[0134] Although a perspective view of the second photoresist 1000 is not shown in the drawings, it should be noted that the technical concept described in the first photoresist 900 may also be substantially the same as the technical concept of the second photoresist 1000 .

[0135] The blank area 840 may be formed in an ion implantation process using the first photoresist 900 and the second photoresist 1000. However, if the blank area 840 has a specific size that does not affect the function of physically isolating the adjacent DPDs 830 from each other, the blank area 840 can ensure manufacturing stability of the semiconductor device without reducing the performance of the image sensor.

[0136] Hereinafter, a manufacturing process for forming the image sensor 100 according to one embodiment of the disclosed technology will be described. Although for the sake of convenience of description, only the process for forming the image sensor 100 will be described below with reference to the accompanying drawings. Figure 3 The manufacturing process of the pixel array 500 shown in FIG. 1 is shown in FIG. 1 , but the scope or spirit of the disclosed technology is not limited thereto, and it should be noted that in the process for forming Figure 7 The remaining components to be used in the manufacturing process of the pixel array 800 shown in FIG. 8 are the same as those of the type of photoresist. Figure 3 The components are basically the same.

[0137] Fig.11A is a layout diagram illustrating an example of a pixel array 500 that can be used in the first manufacturing process. Fig. 11B is an example of Fig.11A The cross-sectional view of the example of the pixel array 500 taken along the first cutting line XX′ is shown. Fig. 11C is an example of Fig.11A The cross-sectional view of the example of the pixel array 500 taken along the second cutting line YY′ is shown.

[0138] Reference Fig.11A In a first manufacturing process, a substrate 550 may be disposed above the pixel array 500 .

[0139] Reference Fig. 11B , illustrates a cross-sectional view of the pixel array 500 taken along the first cutting line XX′. Fig. 11B In the cross-sectional view shown, only the substrate 550 may be included.

[0140] Reference Fig. 11C , illustrates a cross-sectional view of the pixel array 500 taken along the second cutting line YY'. Fig. 11C In the cross-sectional view shown, only the substrate 550 may be included.

[0141] Fig. 12A is a layout diagram illustrating an example of a pixel array 500 that can be used in the second manufacturing process. Fig. 12B is an example of Fig. 12A The cross-sectional view of the example of the pixel array 500 taken along the first cutting line XX′ is shown. Fig. 12C is an example of Fig. 12AThe cross-sectional view of the example of the pixel array 500 taken along the second cutting line YY′ is shown.

[0142] Reference Fig. 12A , the pixel array 500 formed for the second manufacturing process may include an impurity layer 560 formed under the substrate 550 by an ion implantation process based on a bottom blanket scheme. In this case, the ion implantation process based on bottom blanket may refer to an ion implantation process for allowing impurities to be implanted into the bottom of the substrate 550. Although the impurity layer 560 is formed of P-type impurities, the scope or spirit of the disclosed technology is not limited thereto. Although Figure 2 The impurity layer is not shown in FIG. 3 , but it should be noted that another impurity layer may be formed below the photodiode 310 and the isolation layer 340 .

[0143] Reference Fig. 12B , illustrates a cross-sectional view of the pixel array 500 taken along the first cutting line XX′. The impurity layer 560 may be formed at a lower portion of the substrate 550 to a predetermined distance.

[0144] Reference Fig. 12C , illustrates a cross-sectional view of the pixel array 500 taken along the second cutting line YY′. Also, the impurity layer 560 may be formed at a lower portion of the substrate 550 to a predetermined thickness.

[0145] Fig.13A is a layout diagram illustrating an example of a pixel array 500 that can be used in the third manufacturing process. Fig. 13B is an example of Fig.13A The cross-sectional view of the example of the pixel array 500 taken along the first cutting line XX′ is shown. Fig. 13C is an example of Fig.13A The cross-sectional view of the example of the pixel array 500 taken along the second cutting line YY′ is shown.

[0146] Reference Fig.13A , the DPDs 530 may be spaced apart from each other by a predetermined distance at preset positions, so that the DPDs 530 may be formed in a matrix shape.

[0147] Reference Fig. 13B , illustrating the Fig.13A 5. The ion implantation process may be performed using the photoresist pattern 1300 for forming the DPD 530 disposed above the substrate 550 as a photomask. In this case, the ion implantation process may be performed with relatively high energy in such a manner that each DPD 530 may be formed to have a predetermined depth from the top surface of the substrate 550.

[0148] Reference Fig. 13C , illustrating the Fig.13A 2 is a cross-sectional view of the pixel array 500 taken along the second cutting line YY′ shown in FIG. 2 . Likewise, each DPD 530 may be formed to have a predetermined depth from a top surface of the substrate 550 at a predetermined position included in the substrate 550 .

[0149] Fig.14A is a layout diagram illustrating an example of a pixel array 500 that can be used in the fourth manufacturing process. Fig. 14B is an example of Fig.14A The cross-sectional view of the example of the pixel array 500 taken along the first cutting line XX′ is shown. Fig. 14C is an example of Fig.14A The cross-sectional view of the example of the pixel array 500 taken along the second cutting line YY′ is shown.

[0150] Reference Fig.14A The pixel array 500 that can be used in the fourth process may include second DPD isolation layers 520 that are spaced apart from each other by a second distance in the second direction (i.e., in the column direction of the pixel array 500) and can be continuously arranged at the same time. That is, the second DPD isolation layers 520 are continuously arranged at regular intervals in the column direction.

[0151] Reference Fig. 14B , illustrating the Fig.14A 5. The ion implantation process may be performed using the second photoresist 700 for forming the second DPD isolation layer 520 disposed above the substrate 550 as a photomask. That is, ions for forming the second DPD isolation layer 520 may be implanted through the opening region 730 between the adjacent main patterns 710. In this case, the ion implantation process may be performed with relatively high energy in such a manner that each second DPD isolation layer 520 may be formed to have a predetermined depth (corresponding to the DPD 530) from the top surface of the substrate 550.

[0152] Reference Fig. 14C , illustrating the Fig.14A 2 is a cross-sectional view of the pixel array 500 taken along the second cutting line YY′ shown in FIG. The main pattern 710 may be disposed across the entire region corresponding to the second cutting line YY′, so that the second DPD isolation layer 520 may not be formed.

[0153] Fig.15A is a layout diagram illustrating an example of a pixel array 500 that can be used in the fifth manufacturing process. Fig. 15B is an example of Fig.15A The cross-sectional view of the example of the pixel array 500 taken along the first cutting line XX′ is shown. Fig. 15C is an example of Fig.15A The cross-sectional view of the example of the pixel array 500 taken along the second cutting line YY′ is shown.

[0154] Reference Fig.15A The pixel array 500 for the fifth process may include first DPD spacers 510 that are spaced apart from each other by a first distance in a first direction (ie, in a row direction of the pixel array 500) and that may be continuously arranged at the same time. That is, the first DPD spacers 510 are continuously arranged at regular intervals in the row direction.

[0155] Reference Fig. 15B , illustrating the Fig.15A 2 is a cross-sectional view of the pixel array 500 taken along the first cutting line XX′ shown in FIG. The main pattern 610 may be disposed across the entire region corresponding to the first cutting line XX′, so that the first DPD isolation layer 510 may not be formed.

[0156] Reference Fig. 15C , illustrating the Fig.15A 5. The ion implantation process may be performed using the first photoresist 600 for forming the first DPD isolation layer 510 disposed above the substrate 550 as a photomask. That is, ions for forming the first DPD isolation layer 510 may be implanted through the opening region 630 between adjacent main patterns 610. In this case, the ion implantation process may be performed with relatively high energy in such a manner that each first DPD isolation layer 510 may be formed to have a predetermined depth (corresponding to the DPD 530) from the top surface of the substrate 550.

[0157] Although the above embodiment exemplarily discloses that the fifth manufacturing process is performed after the fourth manufacturing process is completed for ease of description, the scope or spirit of the disclosed technology is not limited thereto, and it should be noted that the first manufacturing process is performed first, and then the fourth manufacturing process is performed as needed.

[0158] Fig.16A is a layout diagram illustrating an example of a pixel array 500 that can be used in the sixth manufacturing process. Fig. 16B is an example of Fig.16A The cross-sectional view of the example of the pixel array 500 taken along the first cutting line XX′ is shown. Fig. 16C is an example of Fig.16A The cross-sectional view of the example of the pixel array 500 taken along the second cutting line YY′ is shown.

[0159] Reference Fig.16A, the pixel array 500 for the sixth manufacturing process may include the SPDs 570 spaced apart from each other by a predetermined distance at preset positions (corresponding to the DPDs 530) so that the SPDs 570 may be formed in a matrix shape.

[0160] Reference Fig. 16B , illustrating the Fig.16A 5. The cross-sectional view of the pixel array 500 taken along the first cutting line XX′ shown in FIG. 5. The ion implantation process may be performed using the photoresist pattern 1600 for forming the SPD 570 disposed above the substrate 550 as a photomask. In this case, the ion implantation process may be performed at a relatively lower energy than the energy required to form the DPD 530, so that the SPD 570 may be formed to have a predetermined depth closer to the top surface of the substrate 550.

[0161] Reference Fig. 16C , illustrating the Fig.16A 2 is a cross-sectional view of the pixel array 500 taken along the second cutting line YY′ shown in FIG. 2 . Likewise, the SPD 570 may be formed to have a predetermined depth closer to the top surface of the substrate 550 at a preset position included in the substrate 550 .

[0162] Fig.17A is a layout diagram illustrating an example of a pixel array 500 that can be used in the seventh manufacturing process. Fig. 17B is an example of Fig.17A The cross-sectional view of the example of the pixel array 500 taken along the first cutting line XX′ is shown. Fig. 17C is an example of Fig.17A The cross-sectional view of the example of the pixel array 500 taken along the second cutting line YY′ is shown.

[0163] Reference Fig.17A , the pixel array 500 may include an SPS isolation layer 580 extending in the first direction and the second direction.

[0164] Reference Fig. 17B , illustrating the Fig.17A 5. A cross-sectional view of the pixel array 500 taken along the first cutting line XX′ shown in FIG. 5. The ion implantation process may be performed using a photoresist pattern 1700 for forming an SPD isolation layer 580 disposed above the substrate 550 as a photomask. The photoresist pattern 1700 may be disposed at a position corresponding to the SPD 570 so that ions for forming the SPD isolation layer 580 may be implanted through an area in which the photoresist pattern 1700 is not disposed. In this case, the ion implantation process may be performed with relatively low energy in a manner such that each SPD isolation layer 580 may be formed to have a predetermined depth (corresponding to the SPD 570) closer to the top surface of the substrate 550.

[0165] Reference Fig. 17C , illustrating the Fig.17A 5 ′. Similarly, each of the SPD isolation layers 580 can be formed at a preset position included in the substrate 550 to have a predetermined depth closer to the top surface of the substrate 550. Unlike the DPD isolation layers 510 and 520, the SPD isolation layer 580 can be formed using only one round of process. Since the energy of the ion implantation process for forming the SPD isolation layer 580 is at a relatively low energy level, there is no need to increase the thickness of the photoresist pattern 1700, so that no problem occurs in the photoresist pattern for forming the DPD isolation layer.

[0166] According to another embodiment, the SPD spacer layer may be formed twice using a ladder-type photoresist pattern in the same manner as the formation of the DPD spacer layers 510 and 520. Therefore, a blank area may also be formed between adjacent SPD spacer layers.

[0167] According to various embodiments, each of the above-mentioned constituent elements (for example, module or program) may include one or more entities. According to various embodiments, at least one constituent element or at least one operation among the above-mentioned constituent elements may be omitted, or one or more other constituent elements or one or more other operations may be added. Alternatively or additionally, multiple constituent elements (for example, module or program) may be integrated into only one constituent element. In this case, the integrated constituent element may perform one or more functions of each constituent element in multiple constituent elements in the same manner or in a similar manner as the previous operation performed by the corresponding constituent element in multiple constituent elements before implementing this integration. According to various embodiments, the operation performed by a module, program or another constituent element may be performed sequentially, in parallel, repeatedly or tentatively, at least one of the above-mentioned operations may be performed or omitted in different orders, or another operation may be added.

[0168] As apparent from the above description, image sensors based on some implementations of the disclosed technology can provide a manufacturing process for ensuring manufacturing stability without reducing the performance of the image sensor.

[0169] The embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized through the above-mentioned patent documents.

[0170] Those skilled in the art will understand that, without departing from the spirit and essential features of the disclosed technology, the disclosed technology may be implemented in other specific ways than those set forth herein. Therefore, the above embodiments are interpreted in all respects as illustrative and not restrictive. The scope of the disclosed technology should be determined by the attached claims and their legal equivalents, rather than by the above description. In addition, all variations that fall within the meaning and equivalent scope of the attached claims are intended to be included in the present disclosure. In addition, it is obvious to those skilled in the art that claims that are not explicitly referenced to each other in the attached claims may be presented as a combination of embodiments of the disclosed technology, or may be included as new claims through subsequent amendments after the present application is submitted.

[0171] Although a number of exemplary embodiments consistent with the disclosed technology have been described, it will be appreciated that those skilled in the art may devise many other modifications and embodiments that will fall within the spirit and scope of the principles of the present disclosure. Specifically, within the scope of the present disclosure, the drawings, and the appended claims, many variations and modifications may be made in the components and / or arrangements. In addition to variations and modifications in the components and / or arrangements, alternative uses will also be apparent to those skilled in the art.

[0172] CROSS-REFERENCE TO RELATED APPLICATIONS

[0173] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2020-0010887, filed on January 30, 2020, the disclosure of which is incorporated herein by reference in its entirety as a part of the disclosure of this patent document.

Claims

1. An image sensor, comprising: a plurality of photodiodes, the plurality of photodiodes being arranged in a matrix in a first direction and a second direction; a plurality of first isolation layers, wherein every two adjacent first isolation layers arranged in the first direction are spaced apart from each other by a first distance, and each first isolation layer is interposed between adjacent photodiodes arranged in the second direction; as well as a plurality of second isolation layers, each two adjacent second isolation layers arranged in the second direction are spaced apart from each other by a second distance, and each second isolation layer is interposed between adjacent photodiodes arranged in the first direction, The first distance is smaller than the width of the second isolation layer in the first direction, and the second distance is smaller than the width of the first isolation layer in the second direction. wherein a space between two adjacent first isolation layers arranged in the first direction overlaps a space between two adjacent second isolation layers arranged in the second direction to form a blank area surrounded by the two adjacent first isolation layers and the two adjacent second isolation layers in the substrate including the plurality of first isolation layers and the plurality of second isolation layers, and Wherein, both the plurality of first isolation layers and the plurality of second isolation layers are doped with impurities of a predetermined conductive type.

2. The image sensor according to claim 1, wherein: Each of the plurality of photodiodes is formed to have a predetermined depth from a top surface of the substrate.

3. The image sensor according to claim 1, wherein: The first distance is smaller than a distance between adjacent photodiodes arranged in the first direction.

4. The image sensor according to claim 1, wherein: The second distance is smaller than a distance between adjacent photodiodes arranged in the second direction.

5. The image sensor according to claim 1, wherein: A horizontal length of each of the plurality of first isolation layers is greater than a horizontal length of each of the plurality of photodiodes.

6. The image sensor according to claim 1, wherein: A vertical length of each of the plurality of second isolation layers is greater than a vertical length of each of the plurality of photodiodes.

7. The image sensor according to claim 1, wherein: The blank area is formed to have a horizontal length corresponding to the first distance and a vertical length corresponding to the second distance.

8. The image sensor according to claim 1, wherein: The first direction is the row direction of the pixel array, and The second direction is a column direction of the pixel array.

9. The image sensor according to claim 1, wherein: The plurality of first isolation layers and the plurality of second isolation layers are arranged at regular intervals in the first direction and the second direction, respectively.

10. The image sensor according to claim 1, further comprising: a plurality of third isolation layers formed to extend in the first direction when interposed between the adjacent photodiodes and integrated in one structure; as well as A plurality of fourth isolation layers are formed to extend in the second direction while being interposed between the adjacent photodiodes and are integrated in one structure.

11. The image sensor according to claim 10, wherein: The first isolation layers and the third isolation layers are alternately arranged in the second direction.

12. The image sensor according to claim 10, wherein: The second isolation layers and the fourth isolation layers are alternately arranged in the first direction.

13. The image sensor according to claim 10, wherein: The blank area is not formed at a crossing area between extension lines of the third isolation layer and the second isolation layer for coupling to each other, or the blank area is not formed at a crossing area between the third isolation layer and the fourth isolation layer.

14. The image sensor according to claim 10, wherein: The blank area is not formed at a crossing area between extension lines of the fourth isolation layer and the first isolation layer for coupling to each other, or the blank area is not formed at a crossing area between the fourth isolation layer and the third isolation layer.

15. The image sensor according to claim 10, wherein: The photodiode includes a deep photodiode DPD and a shallow photodiode SPD formed above the DPD, Each first isolation layer is interposed between adjacent DPDs arranged in the second direction, and Each second isolation layer is interposed between adjacent DPDs arranged in the first direction.

16. An image sensor, comprising: a plurality of photodiodes, the plurality of photodiodes being arranged in a matrix shape; a plurality of first isolation layers, the plurality of first isolation layers being arranged at regular intervals in a first direction and a second direction, each two adjacent first isolation layers arranged in the first direction being spaced apart from each other by a first distance, and each first isolation layer being interposed between adjacent photodiodes arranged in the second direction; as well as a plurality of second isolation layers, the plurality of second isolation layers being arranged at regular intervals in the first direction and the second direction, each two adjacent second isolation layers arranged in the second direction being spaced apart from each other by a second distance, and each second isolation layer being interposed between adjacent photodiodes arranged in the first direction, The first distance is smaller than the width of the second isolation layer in the first direction, and the second distance is smaller than the width of the first isolation layer in the second direction. wherein a blank area is formed in an area surrounded by the two adjacent first isolation layers and the two adjacent second isolation layers within the substrate including the plurality of first isolation layers and the plurality of second isolation layers, and Wherein, both the plurality of first isolation layers and the plurality of second isolation layers are doped with impurities of a predetermined conductive type.

17. The image sensor according to claim 16, wherein: Each of the plurality of photodiodes includes a deep photodiode DPD and a shallow photodiode SPD formed over the DPD.

18. The image sensor according to claim 16, further comprising: A plurality of optical filters are arranged in an array in a matrix shape above the plurality of photodiodes, and each optical filter is configured to filter incident light to guide the filtered incident light to a corresponding photodiode.

19. The image sensor according to claim 18, further comprising: A plurality of lenses are arranged in an array in a matrix shape, and the plurality of lenses are respectively placed above or below the plurality of optical filters, so that the lenses and the corresponding filters operate to receive incident light to generate filtered light to be received by the corresponding photodiodes.

Images