Semiconductor Devices

Abstract

A semiconductor device includes: a substrate, the substrate including a logic unit region and a connection region; a dummy transistor, the dummy transistor being located on the connection region; an intermediate connection layer, the intermediate connection layer being located on the dummy transistor; a first metal layer, the first metal layer being located on the intermediate connection layer; an etch stop layer, the etch stop layer being located between the intermediate connection layer and the first metal layer; a through contact, the through contact being located below the first metal layer, the through contact penetrating the connection region, the upper portion of the through contact protruding beyond the etch stop layer; and a protective insulating pattern, the protective insulating pattern being located on the etch stop layer, the protective insulating pattern covering the upper portion of the through contact. The protective insulating pattern covers the upper side surface of the through contact and the top surface of the through contact.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the priority benefit of Korean Patent Application No. 10-2020-0013892 filed on February 5, 2020 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a semiconductor device, and in particular to a semiconductor device including a field effect transistor and a semiconductor chip stack. Background Art

[0004] Semiconductor devices include integrated circuits composed of metal oxide semiconductor field effect transistors (MOS-FETs). In order to meet the growing demand for semiconductor devices with small pattern sizes and reduced design rules, the size of MOS-FETs is being reduced. The size reduction of MOS-FETs may lead to a decrease in the operating performance of semiconductor devices. In order to overcome the technical limitations associated with the reduction in the size of semiconductor devices and realize high-performance semiconductor devices, various studies are being conducted. Summary of the invention

[0005] Example embodiments of the inventive concepts provide a semiconductor device and a stack of semiconductor chips having improved reliability.

[0006] According to an example embodiment of the present invention, a semiconductor device may include: a substrate including a logic unit region and a connection region; a dummy transistor located on the connection region; an intermediate connection layer located on the dummy transistor; a first metal layer located on the intermediate connection layer; an etch stop layer located between the intermediate connection layer and the first metal layer; a through contact located below the first metal layer, the through contact penetrating the connection region, and an upper portion of the through contact protruding beyond the etch stop layer; and a protective insulating pattern located on the etch stop layer, the protective insulating pattern covering the upper portion of the through contact. The protective insulating pattern may cover an upper side surface of the through contact and a top surface of the through contact.

[0007] According to an example embodiment of the present invention, a semiconductor device may include: a substrate including a logic cell region and a connection region; a dummy transistor located on the connection region; a first interlayer insulating layer located on the dummy transistor; an intermediate connection layer located in the first interlayer insulating layer; a second interlayer insulating layer located on the first interlayer insulating layer; a first metal layer located in the second interlayer insulating layer; an etch stop layer located between the first interlayer insulating layer and the second interlayer insulating layer; a through contact located below the first metal layer of the connection region and extending from the bottom of the second interlayer insulating layer to the bottom surface of the substrate, the top surface of the through contact being higher than the top surface of the etch stop layer; and a protective insulating pattern disposed on the etch stop layer to cover an upper portion of the through contact. The top surface of the through contact may be higher than the top surface of the etch stop layer. The protective insulating pattern may partially cover the top surface of the etch stop layer. The protection insulating pattern may extend from the top surface of the etch stop layer to the top surface of the through contact.

[0008] According to an example embodiment of the present invention, a semiconductor device may include: a substrate including a logic cell region and a connection region; an active pattern located on each of the logic cell region and the connection region; a device isolation layer covering a lower surface of the active pattern, an upper portion of the active pattern protruding beyond the device isolation layer; a gate electrode intersecting the active pattern; a source / drain pattern adjacent to a side portion of the gate electrode and filling a recess in an upper portion of the active pattern; an intermediate connection layer located on the gate electrode and the source / drain pattern, the intermediate connection layer The intermediate connection layer includes an active contact and a gate contact electrically connected to the source / drain pattern and the gate electrode, respectively; a first metal layer, the first metal layer is located on the intermediate connection layer, the first metal layer includes an interconnection line and a path electrically connecting the interconnection line to the intermediate connection layer; an etch stop layer, the etch stop layer is located between the intermediate connection layer and the first metal layer; a through contact, the through contact is located below the first metal layer, the through contact penetrates the connection area, and the upper part of the through contact protrudes beyond the etch stop layer; and a protective insulating pattern, the protective insulating pattern is located on the etch stop layer to cover the upper part of the through contact. At least one of the paths can penetrate the protective insulating pattern and can be connected to the through contact. At least one of the interconnects can be electrically connected to the through contact through the at least one path.

[0009] According to an example embodiment of the inventive concept, a stack of semiconductor chips may include a memory chip and a logic chip stacked on the memory chip. The logic chip may include: a substrate including an integrated circuit; a metal layer located on the substrate; and a through contact located below the metal layer, the through contact penetrating the substrate. The through contact may be connected to the metal layer of the memory chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings, which illustrate non-limiting example embodiments described herein.

[0011] Figure 1 is a top plan view illustrating a semiconductor device according to example embodiments of the inventive concepts.

[0012] Figure 2 It is shown Figure 1 An enlarged top view of the logic cell area and the connection area.

[0013] FIG. 3A to FIG. 3E Along Figure 2 Cross-sectional views taken along lines AA', BB', CC', DD' and EE'.

[0014] Figure 4 , Figure 6 , Figure 8 and Fig.10 is a top plan view illustrating a method of manufacturing a semiconductor device according to example embodiments of the inventive concepts.

[0015] Figure 5A , Fig. 7A , Fig. 9A and Fig.11A Along Figure 4 , Figure 6 , Figure 8 and Fig.10 A cross-sectional view taken along line AA' in FIG.

[0016] Figure 5B , Figure 7B , Fig. 9B and Fig. 11B Along Figure 4 , Figure 6 , Figure 8 and Fig.10 A cross-sectional view taken along line BB' in FIG.

[0017] Figure 5C , Figure 7C , Fig. 9C and Fig. 11C Along Figure 4 , Figure 6 , Figure 8 and Fig.10 A cross-sectional view taken along line CC'.

[0018] Fig.9D and Fig.11D Along Figure 8 and Fig.10 A cross-sectional view taken along line D-D' in FIG.

[0019] Figures 12 to 17 is a cross-sectional view illustrating a method of forming a through-contact according to an example embodiment of the inventive concept.

[0020] Fig.18 is a cross-sectional view illustrating a stack of semiconductor chips according to example embodiments of the inventive concepts.

[0021] Fig.19 is a cross-sectional view illustrating a semiconductor package according to example embodiments of the inventive concepts.

[0022] FIG. 20A to FIG. 20E Along the Figure 2 2 , cross-sectional views taken along lines AA′, BB′, CC′, DD′, and EE′ in FIG. 1 illustrate semiconductor devices according to example embodiments of the inventive concepts.

[0023] Fig.21 is along Figure 2 A cross-sectional view taken along line EE′ in FIG. 1 illustrates a semiconductor device according to an example embodiment of the inventive concept. DETAILED DESCRIPTION

[0024] Figure 1 is a top plan view illustrating a semiconductor device according to example embodiments of the inventive concepts.

[0025] Reference Figure 1 , a logic chip LGC may be provided. The logic chip LGC may include a logic cell region LCR located on the substrate 100. In example embodiments, the logic cell region LCR may include first to fourth logic cell regions LCR1-LCR4. The first to fourth logic cell regions LCR1-LCR4 may be two-dimensionally arranged on the substrate 100. Each logic cell region LCR may be a region in which a logic cell (e.g., a standard cell) constituting a logic circuit is disposed.

[0026] The logic chip LGC may further include a connection region CNR disposed between the logic cell regions LCR. The first to fourth logic cell regions LCR1-LCR4 may be disposed around the connection region CNR. At least one through contact TCT may be disposed in the connection region CNR.

[0027] Figure 2 It is shown Figure 1 An enlarged top view of the logic cell area and the connection area. FIG. 3A to FIG. 3E Along Figure 2 Cross-sectional views taken along lines AA', BB', CC', DD' and EE'.

[0028] In the following, reference will be made to Figure 2 as well as FIG. 3A to FIG. 3D The logic cell region LCR of the logic chip LGC is described in more detail. The logic cell region LCR may include logic cells (eg, standard cells) constituting a logic circuit. Figure 2 The logic cell region LCR shown in FIG. 4 may be an example of a single logic cell.

[0029] The substrate 100 may include a first active region PR and a second active region NR. In example embodiments, the first active region PR may be a PMOSFET region, and the second active region NR may be an NMOSFET region. The substrate 100 may be a semiconductor substrate (e.g., a semiconductor substrate of silicon, germanium, or silicon germanium) or a compound semiconductor substrate. As an example, the substrate 100 may be a silicon wafer.

[0030] The first active region PR and the second active region NR may be defined by a second trench TR2 formed in an upper portion of the substrate 100. The second trench TR2 may be located between the first active region PR and the second active region NR. The first active region PR and the second active region NR may be spaced apart from each other in the first direction D1, with the second trench TR2 interposed therebetween. The first active region PR and the second active region NR may each extend in a second direction D2 intersecting the first direction D1.

[0031] The first active pattern AP1 and the second active pattern AP2 may be disposed on the first active region PR and the second active region NR, respectively. The first active pattern AP1 and the second active pattern AP2 may extend parallel to each other along the second direction D2. The first active pattern AP1 and the second active pattern AP2 may be portions of the substrate 100 having a vertically protruding shape. A first trench TR1 may be defined between adjacent first active patterns AP1 and between adjacent second active patterns AP2. The first trench TR1 may be shallower than the second trench TR2.

[0032] A device isolation layer ST filling the first trench TR1 and the second trench TR2 may be provided. The device isolation layer ST may include a silicon oxide layer. The upper portion of the first active pattern AP1 and the upper portion of the second active pattern AP2 may vertically protrude beyond the device isolation layer ST (eg, see Figure 3C). The upper portion of the first active pattern AP1 and the upper portion of the second active pattern AP2 may be formed in a fin shape. The device isolation layer ST may not cover the upper portion of the first active pattern AP1 and the upper portion of the second active pattern AP2. The device isolation layer ST may cover the lower side surface of the first active pattern AP1 and the lower side surface of the second active pattern AP2.

[0033] The first source / drain pattern SD1 may be disposed on an upper portion of the first active pattern AP1. The first source / drain pattern SD1 may be an impurity region of a first conductivity type (e.g., p-type). The first channel pattern CH1 may be disposed between each pair of first source / drain patterns SD1. The second source / drain pattern SD2 may be disposed on an upper portion of the second active pattern AP2. The second source / drain pattern SD2 may be an impurity region of a second conductivity type (e.g., n-type). The second channel pattern CH2 may be disposed between each pair of second source / drain patterns SD2.

[0034] The first source / drain pattern SD1 and the second source / drain pattern SD2 may be epitaxial patterns formed by a selective epitaxial growth process. As an example, the first source / drain pattern SD1 and the second source / drain pattern SD2 may have a top surface coplanar with a top surface of the first channel pattern CH1 and the second channel pattern CH2. As another example, the top surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be higher than the top surfaces of the first channel pattern CH1 and the second channel pattern CH2.

[0035] The first source / drain pattern SD1 may include a semiconductor material (e.g., SiGe) having a lattice constant greater than that of the semiconductor material in the substrate 100. In this case, the first source / drain pattern SD1 may apply compressive stress on the first channel pattern CH1. In contrast, the second source / drain pattern SD2 may include, for example, the same semiconductor material (e.g., Si) as the substrate 100.

[0036] The gate electrode GE may be disposed to cross the first active pattern AP1 and the second active pattern AP2 and extend in the first direction D1. The gate electrodes GE may be spaced apart from each other at a certain pitch in the second direction D2. When viewed in a top view, the gate electrode GE may overlap the first channel pattern CH1 and the second channel pattern CH2. Each gate electrode GE may surround the top surface and the side surface of each of the first channel pattern CH1 and the second channel pattern CH2.

[0037] Return to reference Figure 3C, the gate electrode GE may be disposed on the first top surface TS1 of the first channel pattern CH1 and at least one first side surface SW1 of the first channel pattern CH1. The gate electrode GE may be disposed on the second top surface TS2 of the second channel pattern CH2 and at least one second side surface SW2 of the second channel pattern CH2. In other words, the transistor according to some example embodiments may be a three-dimensional field effect transistor (e.g., FinFET) in which the gate electrode GE is disposed to three-dimensionally surround the channel patterns CH1 and CH2.

[0038] Return to reference Figure 2 as well as FIG. 3A to FIG. 3D , a pair of gate spacers GS may be disposed on both side surfaces of each gate electrode GE. The gate spacer GS may extend along the gate electrode GE and in the first direction D1. The top surface of the gate spacer GS may be higher than the top surface of the gate electrode GE. The top surface of the gate spacer GS may be coplanar with the top surface of the first interlayer insulating layer 110 to be described below. The gate spacer GS may be formed of or include at least one of SiCN, SiCON, or SiN. Alternatively, the gate spacer GS may be a multilayer structure including at least two layers formed of at least two of SiCN, SiCON, or SiN.

[0039] The gate capping pattern GP may be disposed on each gate electrode GE. The gate capping pattern GP may extend along the gate electrode GE and in the first direction D1. The gate capping pattern GP may be formed of or include at least one material selected to have an etching selectivity (etching rate ratio) with respect to the first interlayer insulating layer 110 and the second interlayer insulating layer 120 to be described below. For example, the gate capping pattern GP may be formed of or include at least one of SiON, SiCN, SiCON, or SiN.

[0040] The gate dielectric pattern GI may be arranged between the gate electrode GE and the first active pattern AP1 and between the gate electrode GE and the second active pattern AP2. The gate dielectric pattern GI may extend along the bottom surface of the gate electrode GE thereon. As an example, the gate dielectric pattern GI may cover the first top surface TS1 and the first side surface SW1 of the first channel pattern CH1. The gate dielectric pattern GI may cover not only the second top surface TS2 of the second channel pattern CH2 but also the two second side surfaces SW2 of the second channel pattern CH2. The gate dielectric pattern GI may cover the top surface of the device isolation layer ST located below the gate electrode GE (for example, see Figure 3C ).

[0041] In example embodiments, the gate dielectric pattern GI may be formed of or include a high-k dielectric material having a dielectric constant higher than that of silicon oxide. For example, the high-k dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium oxide silicon, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0042] The gate electrode GE may include a first metal pattern and a second metal pattern located on the first metal pattern. The first metal pattern may be disposed on the gate dielectric pattern GI and may be adjacent to the first channel pattern CH1 and the second channel pattern CH2. The first metal pattern may include a work function metal that can be used to adjust the threshold voltage of the transistor. By adjusting the thickness and composition of the first metal pattern, a transistor with a desired threshold voltage may be realized.

[0043] The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W) and molybdenum (Mo) and nitrogen (N). The first metal pattern may also include carbon (C). The first metal pattern may include a plurality of stacked work function metal layers.

[0044] The second metal pattern may include a metal material having a lower resistance than the first metal pattern. For example, the second metal pattern may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta).

[0045] A first interlayer insulating layer 110 may be disposed on the substrate 100. The first interlayer insulating layer 110 may cover the gate spacer GS and the first source / drain pattern SD1 and the second source / drain pattern SD2. A top surface of the first interlayer insulating layer 110 may be substantially coplanar with a top surface of the gate capping pattern GP and a top surface of the gate spacer GS. A second interlayer insulating layer 120 may be disposed on the first interlayer insulating layer 110 to cover the gate capping pattern GP. A third interlayer insulating layer 130 may be disposed on the second interlayer insulating layer 120. A fourth interlayer insulating layer 140 may be disposed on the third interlayer insulating layer 130. In example embodiments, the first to fourth interlayer insulating layers 110-140 may be formed of or include silicon oxide.

[0046] Active contacts AC may be provided to penetrate the first and second interlayer insulating layers 110 and 120 and may be electrically connected to the first and second source / drain patterns SD1 and SD2 , respectively. Each active contact AC may be provided between the pair of gate electrodes GE.

[0047] The active contact AC may be a self-aligned contact. For example, the active contact AC may be formed by a self-aligned process using the gate capping pattern GP and the gate spacer GS. For example, the active contact AC may cover at least a portion of the side surface of the gate spacer GS. Although not shown, the active contact AC may cover a portion of the top surface of the gate capping pattern GP.

[0048] The silicide pattern SC may be disposed between the active contact AC and the first source / drain pattern SD1 and between the active contact AC and the second source / drain pattern SD2. The active contact AC may be electrically connected to the source / drain patterns SD1 and SD2 through the silicide pattern SC. The silicide pattern SC may be formed of or include at least one metal silicide (e.g., titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and / or cobalt silicide).

[0049] The active contact AC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may be formed of or include at least one metal material (e.g., aluminum, copper, tungsten, molybdenum and / or cobalt). The barrier pattern BM may cover the side surface and the bottom surface of the conductive pattern FM. The barrier pattern BM may include a metal nitride layer or may include a metal layer and a metal nitride layer. The metal layer may be formed of or include at least one of titanium, tantalum, tungsten, nickel, cobalt or platinum. The metal nitride layer may be formed of or include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN) or platinum nitride (PtN).

[0050] At least one gate contact GC may be provided to penetrate the second interlayer insulating layer 120 and the gate capping pattern GP and may be electrically connected to the gate electrode GE. When viewed in a top view, the gate contact GC may be provided between the first active region PR and the second active region NR. The gate contact GC may be provided on the device isolation layer ST filling the second trench TR2.

[0051] The gate contact GC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. The conductive pattern FM and the barrier pattern BM of the gate contact GC may be respectively provided to have substantially the same features as those of the active contact AC.

[0052] The connection pattern CNP may be provided in the third interlayer insulating layer 130. The connection pattern CNP may be provided on the active contact AC and the gate contact GC, respectively. The connection pattern CNP may connect the active contact AC and the gate contact GC to a metal layer to be described below. The connection pattern CNP may be provided between the active contact AC and the gate contact GC and the metal layer, which may increase the degree of freedom of the wiring process. For example, referring to Figure 3C , the connection pattern CNP disposed on the gate contact GC may connect the gate contact GC to the interconnection line INL horizontally offset from the gate contact GC. In example embodiments, the connection pattern CNP may be omitted.

[0053] The active contact AC and the gate contact GC in the second interlayer insulating layer 120 and the connection pattern CNP in the third interlayer insulating layer 130 may include an intermediate connection layer MCL. The intermediate connection layer MCL may electrically connect the first metal layer M1 to be described below to the transistor on the substrate 100. The intermediate connection layer MCL may be a layer formed by a middle of the line (MOL) process to be described below.

[0054] The etch stop layer ESL may be disposed between the third interlayer insulating layer 130 and the fourth interlayer insulating layer 140. For example, the etch stop layer ESL may include a silicon oxide layer.

[0055] The first metal layer M1 may be disposed in the fourth interlayer insulating layer 140. The first metal layer may include an interconnection line INL and a via VI. The via VI may be disposed below the interconnection line INL, respectively. For example, the interconnection lines INL may extend parallel to each other in the second direction D2. The interconnection lines INL may be arranged at a constant pitch in the first direction D1. The via VI may be disposed between the interconnection lines INL and the connection pattern CNP, respectively, to electrically connect them to each other. Each via VI may be arranged to penetrate the etch stop layer ESL and contact the top surface of the connection pattern CNP.

[0056] The interconnection line INL and the via VI may be formed of or include the same conductive material. The interconnection line INL and the via VI may be formed of or include at least one metal material such as aluminum, copper, tungsten, molybdenum, ruthenium or cobalt. Although not shown, a metal layer (e.g., a second metal layer, a third metal layer, a fourth metal layer, etc.) may be additionally stacked on the fourth interlayer insulating layer 140. The stacked metal layers may include wiring interconnects for connecting logic units.

[0057] In the following, reference will be made to Figure 2 and Figure 3EThe connection region CNR of the logic chip LGC is described in more detail. The connection region CNR may include at least one dummy cell region DMR and at least one through contact TCT.

[0058] The dummy cell region DMR may have a structure substantially the same as that of the above-mentioned logic cell region LCR. That is, similar to the logic cell region LCR, the dummy cell region DMR may include a first active region PR, a second active region NR, and a three-dimensional field effect transistor located thereon. In the same manner as the active contact AC, the gate contact GC, the connection pattern CNP, and the first metal layer M1 are provided on the dummy cell region DMR, the active contact AC, the gate contact GC, the connection pattern CNP, and the first metal layer M1 may be provided on the dummy cell region DMR.

[0059] However, unlike the logic cell region LCR, the dummy cell region DMR of the connection region CNR may be a dummy region that is not used to implement a logic circuit. In other words, the transistor on the dummy cell region DMR may be a dummy transistor. However, if no pattern is formed on the dummy cell region DMR because the dummy cell region DMR is not used as a valid logic cell, the pattern density of the dummy cell region DMR will be significantly reduced in the photolithography process for forming the logic cell region LCR. This may lead to process failures during the photolithography process. Therefore, the process for forming the logic cell region LCR may also be performed on the dummy cell region DMR in the same manner.

[0060] Return to reference Figure 1 , the through contact TCT may be disposed to be spaced apart from the logic cell region LCR by a certain distance. Therefore, in addition to the logic cell region LCR, the through contact TCT may be locally disposed only on the connection region CNR (ie, the dummy cell region DMR).

[0061] Return to reference Figure 2 and Figure 3E , the third trench TR3 may be formed in the upper portion of the substrate 100 to divide the first active pattern AP1 into two parts in the second direction D2. The device isolation layer ST may fill the third trench TR3.

[0062] The through contact TCT may be disposed on the third trench TR3. The through contact TCT may penetrate the device isolation layer ST filling the third trench TR3 and the substrate 100 thereunder. The through contact TCT may be disposed below the first metal layer M1. The through contact TCT may extend vertically from the bottom of the fourth interlayer insulating layer 140 to the bottom surface of the substrate 100.

[0063] A passivation layer PAV may be disposed on the bottom surface of the substrate 100. The passivation layer PAV may surround the exposed lower portion of the through contact TCT. The upper portion of the through contact TCT may penetrate the etch stop layer ESL and may protrude beyond the etch stop layer ESL. A protection insulating pattern PIP may be provided to cover the protruding upper portion of the through contact TCT. In detail, the protection insulating pattern PIP may cover the top surface TCTt of the through contact TCT and the upper side surface TCTu of the through contact TCT. The protection insulating pattern PIP may be formed of or include at least one of SiN, SiCN, or SiON.

[0064] The top surface TCTt of the through contact TCT may be higher than the top surface ESLt of the etch stop layer ESL. The top surface TCTt of the through contact TCT may be located at a horizontal height between the bottom surface and the top surface of the fourth interlayer insulating layer 140. The protection insulating pattern PIP may cover a portion of the top surface of the etch stop layer ESL adjacent to the through contact TCT. The protection insulating pattern PIP may extend from the top surface of the etch stop layer ESL to the top surface TCTt of the through contact TCT.

[0065] At least one via VI of the first metal layer M1 may penetrate the protection insulation pattern PIP and may contact the top surface TCTt of the through contact TCT. In other words, the interconnection line INL of the first metal layer M1 may be electrically connected to the through contact TCT through the at least one via VI.

[0066] The through contact TCT may include a conductive pattern FM, a barrier pattern BM surrounding the conductive pattern FM, and an insulating spacer SPC. The conductive pattern FM may be a vertically extending columnar pattern. The barrier pattern BM may surround the outer side surface of the conductive pattern FM. The barrier pattern BM may be arranged to expose the top and bottom surfaces of the conductive pattern FM. The insulating spacer SPC may surround the outer side surface of the barrier pattern BM.

[0067] The conductive pattern FM may be formed of or include at least one metal material of aluminum, copper, tungsten, molybdenum, or cobalt. The blocking pattern BM may include a metal nitride layer or may include a metal layer and a metal nitride layer.

[0068] Figure 4 , Figure 6 , Figure 8 and Fig.10 is a top plan view illustrating a method of manufacturing a semiconductor device according to example embodiments of the inventive concepts. Figure 5A , Fig. 7A , Fig. 9A and Fig.11A Along Figure 4 , Figure 6 , Figure 8 and Fig.10 A cross-sectional view taken along line AA' in FIG. Figure 5B , Figure 7B , Fig. 9B and Fig. 11B Along Figure 4 , Figure 6 , Figure 8 and Fig.10 A cross-sectional view taken along line BB' in FIG. Figure 5C , Figure 7C , Fig. 9C and Fig. 11C Along Figure 4 , Figure 6 , Figure 8 and Fig.10 A cross-sectional view taken along line CC'. Fig.9D and Fig.11D Along Figure 8 and Fig.10 A cross-sectional view taken along line D-D' in FIG.

[0069] Reference Figure 4 as well as FIG. 5A to FIG. 5C , a substrate 100 having a logic cell region LCR and a connection region CNR may be provided. For example, the logic cell region LCR may include a first active region PR and a second active region NR.

[0070] The first active pattern AP1 and the second active pattern AP2 may be formed by patterning the substrate 100. The first active pattern AP1 and the second active pattern AP2 may be formed on the logic cell region LCR and the connection region CNR. In detail, the first active pattern AP1 may be formed on the first active region PR of the logic cell region LCR, and the second active pattern AP2 may be formed on the second active region NR of the logic cell region LCR.

[0071] A first trench TR1 may be formed between the first active pattern AP1 and the second active pattern AP2. The first trench TR1 may extend in parallel with the first active pattern AP1 and the second active pattern AP2 in the second direction D2. By patterning the substrate 100, a second trench TR2 may be formed between the first active region PR and the second active region NR of the logic cell region LCR. The second trench TR2 may extend in the second direction D2. The second trench TR2 may be formed to have a depth greater than that of the first trench TR1.

[0072] The substrate 100 may be patterned to form a third trench TR3 intersecting the connection region CNR. The third trench TR3 may extend in the first direction D1. Thus, the third trench TR3 may divide each of the first active pattern AP1 and the second active pattern AP2 into two parts. The depth of the third trench TR3 may be equal to or greater than the depth of the second trench TR2.

[0073] A device isolation layer ST may be formed on the substrate 100 to fill the first to third trenches TR1, TR2, and TR3. The device isolation layer ST may be formed of or include an insulating material (e.g., silicon oxide). The device isolation layer ST may be recessed to expose an upper portion of the first active pattern AP1 and an upper portion of the second active pattern AP2. For example, an upper portion of the first active pattern AP1 and an upper portion of the second active pattern AP2 may vertically protrude beyond the device isolation layer ST.

[0074] Reference Figure 6 as well as 7A to 7C , a sacrificial pattern PP may be formed to intersect the first active pattern AP1 and the second active pattern AP2. The sacrificial pattern PP may be a linear or stripe pattern extending in the first direction D1. In detail, the formation of the sacrificial pattern PP may include: forming a sacrificial layer on the substrate 100; forming a hard mask pattern MA on the sacrificial layer; and patterning the sacrificial layer using the hard mask pattern MA as an etching mask. The sacrificial layer may be formed of or include polysilicon.

[0075] A pair of gate spacers GS may be formed on both side surfaces of each sacrificial pattern PP. The formation of the gate spacers GS may include conformally forming a gate spacer layer on the substrate 100 and anisotropically etching the gate spacer layer. The gate spacer layer may be formed of or include at least one of SiCN, SiCON, or SiN. In some embodiments, the gate spacer layer may be a multilayer formed of at least two of SiCN, SiCON, or SiN.

[0076] Reference Figure 8 as well as 9A to 9D , a first source / drain pattern SD1 may be formed at an upper portion of the first active pattern AP1. A pair of first source / drain patterns SD1 may be formed at two opposite portions of each sacrificial pattern PP.

[0077] In detail, the first recessed region RS1 may be formed by etching the upper portion of the first active pattern AP1 using the hard mask pattern MA and the gate spacer GS as an etching mask. During etching of the upper portion of the first active pattern AP1, the device isolation layer ST between the first active patterns AP1 may be recessed (eg, see Fig. 9C).

[0078] The first source / drain pattern SD1 may be formed by a selective epitaxial growth process in which the inner side surface of the first recessed region RS1 of the first active pattern AP1 is used as a seed layer. Since the first source / drain pattern SD1 is formed, the first channel pattern CH1 may be defined between each pair of the first source / drain patterns SD1. The selective epitaxial growth process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process. The first source / drain pattern SD1 may include a semiconductor material (e.g., SiGe) having a lattice constant greater than that of the semiconductor substrate 100. The first source / drain patterns SD1 may each be a multilayer structure including a plurality of semiconductor layers.

[0079] As an example, during the selective epitaxial growth process, the first source / drain pattern SD1 may be in-situ doped with impurities. As another example, after forming the first source / drain pattern SD1, impurities may be implanted into the first source / drain pattern SD1. The first source / drain pattern SD1 may be doped to have a first conductivity type (e.g., p-type).

[0080] The second source / drain patterns SD2 may be formed on the second active pattern AP2. A pair of the second source / drain patterns SD2 may be formed at both sides of each sacrificial pattern PP.

[0081] In detail, the second recessed region RS2 may be formed by etching an upper portion of the second active pattern AP2 using the hard mask pattern MA and the gate spacer GS as an etching mask (eg, see FIG. 2 ). Fig. 9C ). The second source / drain pattern SD2 may be formed by a selective epitaxial growth process in which the inner side surface of the second recessed region RS2 of the second active pattern AP2 is used as a seed layer. As a result of forming the second source / drain pattern SD2, a second channel pattern CH2 may be defined between each pair of the second source / drain patterns SD2. In example embodiments, the second source / drain pattern SD2 may include the same semiconductor material (e.g., Si) as that of the substrate 100. The second source / drain pattern SD2 may be doped to have a second conductivity type (e.g., n-type).

[0082] The first source / drain pattern SD1 and the second source / drain pattern SD2 may be sequentially formed by different processes. For example, the first source / drain pattern SD1 and the second source / drain pattern SD2 may not be formed at the same time. The first source / drain pattern SD1 and the second source / drain pattern SD2 may be formed on both the logic cell region LCR and the connection region CNR in the same manner.

[0083] Reference Fig.10 as well as FIG. 11A to FIG. 11D , a first interlayer insulating layer 110 may be formed to cover the first and second source / drain patterns SD1 and SD2 , the hard mask pattern MA, and the gate spacer GS. As an example, the first interlayer insulating layer 110 may be formed of or include silicon oxide.

[0084] The first interlayer insulating layer 110 may be planarized to expose the top surface of the sacrificial pattern PP. The planarization of the first interlayer insulating layer 110 may be performed using an etch-back or chemical mechanical polishing (CMP) process. During the planarization process, all of the hard mask patterns MA may be removed. As a result, the top surface of the first interlayer insulating layer 110 may be substantially coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

[0085] The sacrificial pattern PP may be replaced with the gate electrode GE. For example, the exposed sacrificial pattern PP may be selectively removed. As a result of removing the sacrificial pattern PP, an empty space may be formed. A gate dielectric pattern GI, a gate electrode GE, and a gate capping pattern GP may be formed in each empty space. The gate electrode GE may include a first metal pattern and a second metal pattern located on the first metal pattern. The first metal pattern may be formed of a work function metal capable of adjusting a threshold voltage of a transistor, and the second metal pattern may be formed of a low resistance metal.

[0086] A second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 may be formed of or include silicon oxide. An active contact AC may be formed to penetrate the second interlayer insulating layer 120 and the first interlayer insulating layer 110 and be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. A gate contact GC may be formed to penetrate the second interlayer insulating layer 120 and the gate capping pattern GP and be electrically connected to the gate electrode GE.

[0087] Return to reference Figure 2 as well as FIG. 3A to FIG. 3E , a third interlayer insulating layer 130 may be formed on the second interlayer insulating layer 120. A connection pattern CNP may be formed in the third interlayer insulating layer 130. The connection pattern CNP may be formed on the active contact AC and the gate contact GC, respectively.

[0088] A fourth interlayer insulating layer 140 may be formed on the third interlayer insulating layer 130. A first metal layer M1 may be formed in the fourth interlayer insulating layer 140. The formation of the first metal layer M1 may include forming a via VI using a damascene process and forming an interconnection line INL on the via VI using the damascene process.

[0089] Before forming the fourth interlayer insulating layer 140 and the first metal layer M1, at least one through contact TCT may be formed on the connection region CNR. The process of forming the active contact AC, the gate contact GC, and the connection pattern CNP thereon may be a middle-of-line (MOL) process. The process of forming the first metal layer M1 and the additional metal layer thereon may be a back-end-of-line (BEOL) process. The through contact TCT may be formed between the MOL process and the BEOL process.

[0090] Figures 12 to 17 2 is a cross-sectional view showing a method of forming a through contact according to an exemplary embodiment of the inventive concept. Figures 12 to 17 A method of forming a through contact TCT is described in more detail.

[0091] Reference Fig.12 , after the MOL process, an etch stop layer ESL and a planarization stop layer CSL may be sequentially formed on the third interlayer insulating layer 130. The planarization stop layer CSL may be used as a stop layer in a planarization process to be described below, and may be formed of or include at least one of SiN, SiCN, or SiON. The etch stop layer ESL may be formed of or include a material having an etching selectivity relative to the planarization stop layer CSL. For example, the etch stop layer ESL may include a silicon oxide layer.

[0092] Reference Fig.13 , a penetration hole TRH may be formed on the device isolation layer ST of the connection region CNR. In detail, an anisotropic etching process may be performed on the planarization stop layer CSL to form a penetration hole TRH penetrating the first to third interlayer insulating layers 110, 120, and 130 and the device isolation layer ST. The penetration hole TRH may extend toward the bottom surface of the substrate 100 to penetrate the upper portion of the substrate 100. The penetration hole TRH may not completely penetrate the substrate 100.

[0093] Reference Fig.14 , an insulating spacer SPC may be formed on an inner side surface of the penetration hole TRH. In detail, the forming of the insulating spacer SPC may include conformally forming an insulating layer in the penetration hole TRH and anisotropically etching the insulating layer.

[0094] The barrier layer BML and the conductive layer FML may be sequentially formed to fill the penetration hole TRH. The barrier layer BML may be conformally formed in the penetration hole TRH. The barrier layer BML may include a metal nitride layer or may include a metal layer and a metal nitride layer. The conductive layer FML may be formed to completely fill the penetration hole TRH. The conductive layer FML may be formed of or include a low resistance metal (e.g., copper).

[0095] Reference Fig.15 , a through contact TCT may be formed by performing a planarization process on the conductive layer FML. The planarization process may be performed to expose the planarization stop layer CSL. As a result of the planarization process, the barrier layer BML and the conductive layer FML on the planarization stop layer CSL may be completely removed.

[0096] The insulating spacer SPC, the blocking pattern BM, and the conductive pattern FM may remain in the penetration hole TRH. They may include a through contact TCT. Through the planarization process, the top surface of the insulating spacer SPC, the top surface of the blocking pattern BM, the top surface of the conductive pattern FM, and the top surface of the planarization stop layer CSL may be coplanar with each other.

[0097] Reference Fig.16 , a protection insulating layer PIL may be formed on the planarization stop layer CSL and the through contact TCT. The protection insulating layer PIL may include at least one of SiN, SiCN, or SiON. In example embodiments, the protection insulating layer PIL may be formed of or include the same material as the planarization stop layer CSL.

[0098] A photoresist pattern PRP may be formed to vertically overlap the through contact TCT. The photoresist pattern PRP may partially cover a region of the protection insulating layer PIL on the through contact TCT and may expose other regions of the protection insulating layer PIL.

[0099] Reference Fig.17 , the protective insulating layer PIL and the planarization stop layer CSL may be etched using the photoresist pattern PRP as an etching mask. An etching process may be performed to expose the etching stop layer ESL. A portion of the protective insulating layer PIL located below the photoresist pattern PRP and a portion of the planarization stop layer CSL located below the photoresist pattern PRP may not be etched during the etching process. The remainder of the protective insulating layer PIL and the remainder of the planarization stop layer CSL may include a protective insulating pattern PIP. The protective insulating pattern PIP may cover the top surface TCTt of the through contact TCT and the upper side surface TCTu of the through contact TCT. The protective insulating pattern PIP may passivate the exposed portion of the through contact TCT.

[0100] Thereafter, a BEOL process may be performed on the etch stop layer ESL to form at least one metal layer (eg, a first metal layer M1 ). After the BEOL process, the substrate 100 may be reversed, and then a planarization process may be performed on the bottom surface SBS of the substrate 100 .

[0101] As a result of the planarization process, the thickness of the substrate 100 may be reduced. The planarization process may be performed to expose the through contacts TCT. As a result of the planarization process, the conductive pattern FM of the through contacts TCT may be exposed through the bottom surface SBS of the substrate 100.

[0102] Afterwards, if Figure 3E As shown, a passivation process may be performed on the through contact TCT exposed through the bottom surface SBS of the substrate 100 to form a passivation layer PAV.

[0103] In the method of forming a through contact TCT according to an example embodiment of the present invention, the through contact TCT can be stably formed or the risk of process defect problems can be reduced by the combination of the etching stop layer ESL and the planarization stop layer CSL. In particular, during the formation of the through contact TCT, the etching stop layer ESL can protect the connection pattern CNP thereunder. In addition, the remaining portion of the planarization stop layer CSL can be used as a protective insulating pattern PIP to protect the upper portion of the through contact TCT.

[0104] Fig.18 is a cross-sectional view showing a stack of semiconductor chips according to an exemplary embodiment of the inventive concept. Figure 1 , Figure 2 as well as FIG. 3A to FIG. 3E The described elements will be identified with the same reference numerals and their repeated description will not be repeated, and features different from those of the previous embodiment will be described in more detail below.

[0105] Reference Fig.18 , a memory chip MEC and a logic chip LGC stacked on the memory chip MEC can be provided. Fig.18 The logic chip LGC can be referenced Figure 1 , Figure 2 and FIG. 3A to FIG. 3E The logic chip LGC described. The logic chip LGC may include a substrate 100 on which an integrated circuit is formed, and a metal layer ML disposed on the substrate 100. The metal layer ML may include a plurality of metal layers, and may include, for example, the first metal layer M1 described above. The logic chip LGC may include at least one through contact TCT extending downward from the metal layer ML to penetrate the substrate 100.

[0106] Similar to the logic chip LGC, the memory chip MEC may include a substrate 100 on which memory cells are disposed and a metal layer ML disposed on the substrate 100. For example, the memory chip MEC may be a DRAM chip or an SRAM chip. The metal layer ML of the memory chip MEC may be electrically connected to the through contact TCT.

[0107] A connection layer CNL may be provided between the memory chip MEC and the logic chip LGC. The connection layer CNL may attach the memory chip MEC to the logic chip LGC. Although not shown, a connection pad (e.g., a microbump) may be provided in the connection layer CNL to connect the through contact TCT of the logic chip LGC to the metal layer ML of the memory chip MEC.

[0108] Fig.19 is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the inventive concept. Fig.18 The described elements will be identified by the same reference numerals without repeating their repeated description, and features that differ from those of the previous embodiment will be described in more detail below.

[0109] Reference Fig.19 The semiconductor package may include a logic chip LGC disposed on a package substrate PKS and a memory stack MES stacked on the logic chip LGC. For example, the memory stack MES may include first to third memory chips MEC1, MEC2, and MEC3 stacked on the logic chip LGC.

[0110] The logic chip LGC and the first memory chip MEC1 may be connected to each other through at least one through contact TCT penetrating the substrate 100 of the logic chip LGC, as previously described with reference to FIG. Fig.18 as described.

[0111] At least one first penetration via TSV1 penetrating the first memory chip MEC1 may be provided. At least one second penetration via TSV2 penetrating the second memory chip MEC2 may be provided. The first to third memory chips MEC1, MEC2, and MEC3 may be connected to each other through the first penetration via TSV1 and the second penetration via TSV2. A penetration via may not be provided in the uppermost memory chip (e.g., the third memory chip MEC3).

[0112] Bonding pads BP may be provided between the through-contact TCT and the first memory chip MEC1 , between the first through-via TSV1 and the second memory chip MEC2 , and between the second through-via TSV2 and the third memory chip MEC3 , respectively.

[0113] A connection member CM may be disposed between the package substrate PKS and the metal layer ML of the logic chip LGC to electrically connect the package substrate PKS and the metal layer ML to each other.

[0114] In some example embodiments, a memory stack MES may be disposed on the logic chip LGC, and they may be vertically connected to each other through a through contact TCT, a first through via TSV1, and a second through via TSV2. Since the logic chip LGC and the memory stack MES are vertically and directly connected to each other, a signal path therebetween may be relatively shortened. Therefore, according to some example embodiments, the operating speed of the semiconductor package may be increased.

[0115] FIG. 20A to FIG. 20E are respectively along Figure 2 The cross-sectional views taken along the lines A-A', B-B', C-C', D-D' and EE' in FIG. 1 show a semiconductor device according to an exemplary embodiment of the present invention. For the sake of simplicity, the previously referenced Figure 1 , Figure 2 and FIG. 3A to FIG. 3E The described elements will be identified by the same reference numerals without repeating their repeated description, and features different from those of the previous embodiment will be described in more detail below.

[0116] Reference Figure 2 as well as FIG. 20A to FIG. 20E , a substrate 100 including a logic cell region LCR and a connection region CNR may be provided. For example, the logic cell region LCR may include a first active region PR and a second active region NR.

[0117] The device isolation layer ST may be disposed on the substrate 100. The device isolation layer ST may define first and second active patterns AP1 and AP2 at an upper portion of the substrate 100. The first and second active patterns AP1 and AP2 may be defined on the first and second active regions PR and NR, respectively.

[0118] The first active pattern AP1 and the second active pattern AP2 may include a first channel pattern CH1 and a second channel pattern CH2, respectively. In detail, the first channel pattern CH1 may include a plurality of first semiconductor patterns SP1 stacked vertically. The stacked first semiconductor patterns SP1 may be spaced apart from each other in a third direction D3. When viewed in a top view, the stacked first semiconductor patterns SP1 may overlap each other. The second channel pattern CH2 may include a plurality of second semiconductor patterns SP2 stacked vertically. The stacked second semiconductor patterns SP2 may be spaced apart from each other in a third direction D3. When viewed in a top view, the stacked second semiconductor patterns SP2 may overlap each other. The first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be formed of or include at least one of silicon (Si), germanium (Ge), or silicon germanium (SiGe).

[0119] The first active pattern AP1 may further include a first source / drain pattern SD1. A first semiconductor pattern SP1 that may be stacked to include a first channel pattern CH1 may be disposed between each adjacent pair of first source / drain patterns SD1. The stack of first semiconductor patterns SP1 may connect adjacent pairs of first source / drain patterns SD1 to each other.

[0120] The second active pattern AP2 may further include a second source / drain pattern SD2. A second semiconductor pattern SP2 that may be stacked to include a second channel pattern CH2 may be disposed between each adjacent pair of second source / drain patterns SD2. The stack of second semiconductor patterns SP2 may connect adjacent pairs of second source / drain patterns SD2 to each other.

[0121] The gate electrode GE may be disposed to cross the first channel pattern CH1 and the second channel pattern CH2 and extend in the first direction D1. When viewed in a top view, the gate electrode GE may overlap the first channel pattern CH1 and the second channel pattern CH2. A pair of gate spacers GS may be disposed on both side surfaces of the gate electrode GE. A gate capping pattern GP may be disposed on the gate electrode GE.

[0122] Return to reference Fig. 20C , the gate electrode GE may surround each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2. For example, the gate electrode GE may be disposed on the top surface TS, at least one side surface SW, and the bottom surface BS of the uppermost first semiconductor pattern SP1. For example, the gate electrode GE may surround the top surface, the bottom surface, and both side surfaces of each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2. The transistor according to some example embodiments may be a three-dimensional field effect transistor (e.g., a multi-bridge channel field effect transistor (MBCFET)) in which the gate electrode GE is disposed to three-dimensionally surround the channel patterns CH1 and CH2.

[0123] Return to reference Figure 2 as well as FIG. 20A to FIG. 20E The gate dielectric pattern GI may be disposed between each of the first and second channel patterns CH1 and CH2 and the gate electrode GE. The gate dielectric pattern GI may surround each of the first and second semiconductor patterns SP1 and SP2.

[0124] On the second active region NR, the insulating pattern IP may be disposed between the gate dielectric pattern GI and the second source / drain pattern SD2. The gate electrode GE may be spaced apart from the second source / drain pattern SD2 by the gate dielectric pattern GI and the insulating pattern IP. In contrast, the insulating pattern IP on the first active region PR may be omitted.

[0125] The first interlayer insulating layer 110 and the second interlayer insulating layer 120 may be disposed on the substrate 100. An active contact AC penetrating the first interlayer insulating layer 110 and the second interlayer insulating layer 120 and connected to the first source / drain pattern 110 and the second source / drain pattern 120, respectively, may be disposed. A gate contact GC penetrating the second interlayer insulating layer 120 and the gate capping pattern GP and electrically connected to the gate electrode GE may be disposed. The active contact AC and the gate contact GC may be configured to have the same structure as the reference electrode GE. Figure 2 as well as FIG. 3A to FIG. 3D Features that are essentially the same as those described.

[0126] The third interlayer insulating layer 130 may be disposed on the second interlayer insulating layer 120. The connection pattern CNP may be disposed in the third interlayer insulating layer 130. The fourth interlayer insulating layer 140 may be disposed on the third interlayer insulating layer 130. The first metal layer M1 may be disposed in the fourth interlayer insulating layer 140.

[0127] The through contact TCT may be disposed on the connection region CNR. The through contact TCT may penetrate the device isolation layer ST filling the third trench TR3 and the substrate 100 thereunder. The through contact TCT may extend vertically from the bottom of the fourth interlayer insulating layer 140 to the bottom surface of the substrate 100. The through contact TCT may be configured to have a thickness similar to that of the reference Figure 2 and Figure 3E Features that are essentially the same as those described.

[0128] Fig.21 is along Figure 2 A cross-sectional view taken along line EE' in FIG. 1 shows a semiconductor device according to an exemplary embodiment of the present invention. Figure 1 , Figure 2 and FIG. 3A to FIG. 3E The described elements will be identified by the same reference numerals without repeating their repeated description, and features different from those of the previous embodiment will be described in more detail below.

[0129] Reference Figure 2 and Fig.21 , the bottom surface TCTb of the through contact TCT may be located at a level higher than the bottom surface SBS of the substrate 100. That is, the bottom surface TCTb of the through contact TCT may be covered by the substrate 100. The barrier pattern BM and the insulating spacer SPC may be arranged between the bottom surface FMb of the conductive pattern FM of the through contact TCT and the substrate 100. The barrier pattern BM may directly cover the bottom surface FMb of the conductive pattern FM. The insulating spacer SPC may be arranged between the barrier pattern BM covering the bottom surface FMb of the conductive pattern FM and the substrate 100.

[0130] According to an example embodiment of the present invention, a semiconductor device may include a through contact configured to penetrate a substrate of a logic chip and used to implement a chip stack in which a logic chip and a memory chip are stacked and connected to each other. In the semiconductor device, process defects that may occur when forming a through contact can be prevented, and the reliability of the semiconductor device can be improved. Since the metal layer of the logic chip is directly connected to the metal layer of the memory chip through the through contact, the signal path between the logic chip and the memory chip can be shortened, thereby realizing a semiconductor device with a fast operating speed.

[0131] While example embodiments of the inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: A substrate, the substrate comprising a logic unit region and a connection region; a dummy transistor, the dummy transistor being located on the connection region; an intermediate connection layer, the intermediate connection layer being located on the dummy transistor; a first metal layer, the first metal layer being located on the intermediate connection layer; an etch stop layer, the etch stop layer being located between the intermediate connection layer and the first metal layer; A through contact, the through contact being located below the first metal layer, the through contact penetrating the connection region, and an upper portion of the through contact protruding beyond the etching stop layer; as well as a protective insulating pattern, wherein the protective insulating pattern is located on the etch stop layer, the protective insulating pattern partially covers the top surface of the etch stop layer and covers the upper portion of the through contact, and the protective insulating pattern extends from the top surface of the etch stop layer to the top surface of the through contact to cover the upper side surface of the through contact and the top surface of the through contact.

2. The semiconductor device according to claim 1, further comprising: a logic transistor, the logic transistor being located on the logic cell region, Wherein, the logic transistor and the dummy transistor are both three-dimensional field effect transistors.

3. The semiconductor device according to claim 1, wherein: The intermediate connection layer comprises: an active contact electrically connected to a source / drain pattern of the dummy transistor; and A gate contact is electrically connected to a gate electrode of the dummy transistor.

4. The semiconductor device according to claim 3, wherein: The intermediate connection layer also includes: A connection pattern is located on the active contact and the gate contact.

5. The semiconductor device according to claim 1, wherein The dummy transistor comprises: an active pattern, wherein the active pattern is located on the connection area; a device isolation layer, the device isolation layer filling the groove dividing the active pattern into two parts; a gate electrode intersecting the active pattern; and a source / drain pattern, the source / drain pattern being adjacent to a side portion of the gate electrode, Wherein, the through contact penetrates the device isolation layer.

6. The semiconductor device according to claim 1, wherein: The first metal layer comprises: a via penetrating the protection insulating pattern and connected to the top surface of the through contact; and An interconnect line is located on the via.

7. The semiconductor device according to claim 1, wherein The through-contact comprises: Columnar conductive pattern; a barrier pattern surrounding an outer side surface of the conductive pattern; and An insulating spacer surrounds an outer side surface of the barrier pattern.

8. The semiconductor device according to claim 1, wherein The first metal layer is located in an interlayer insulating layer on the etch stop layer, and The top surface of the through contact is located at a level between a bottom surface and a top surface of the interlayer insulating layer.

9. The semiconductor device according to claim 1, wherein: The etch stop layer has an etch selectivity with respect to the protection insulating pattern.

10. The semiconductor device according to claim 1, wherein The protection insulating pattern covers a portion of the top surface of the etch stop layer adjacent to the through contact.

11. A semiconductor device, comprising: A substrate, the substrate comprising a logic unit region and a connection region; a dummy transistor, the dummy transistor being located on the connection region; a first interlayer insulating layer, wherein the first interlayer insulating layer is located on the dummy transistor; an intermediate connection layer, wherein the intermediate connection layer is located in the first interlayer insulating layer; a second interlayer insulating layer, the second interlayer insulating layer being located on the first interlayer insulating layer; a first metal layer, wherein the first metal layer is located in the second interlayer insulating layer; an etch stop layer, the etch stop layer being located between the first interlayer insulating layer and the second interlayer insulating layer; a through contact, the through contact being located below the first metal layer of the connection region and extending from the bottom of the second interlayer insulating layer to the bottom surface of the substrate, the top surface of the through contact being higher than the top surface of the etching stop layer; as well as A protective insulating pattern is disposed on the etch stop layer to cover an upper portion of the through contact, the protective insulating pattern partially covers the top surface of the etch stop layer, and the protective insulating pattern extends from the top surface of the etch stop layer to the top surface of the through contact.

12. The semiconductor device according to claim 11, further comprising: a logic transistor, the logic transistor being located on the logic cell region, Wherein, the logic transistor and the dummy transistor are both three-dimensional field effect transistors.

13. The semiconductor device according to claim 11, wherein The dummy transistor comprises: an active pattern, wherein the active pattern is located on the connection area; a device isolation layer, the device isolation layer filling the groove dividing the active pattern into two parts; a gate electrode intersecting the active pattern; and a source / drain pattern, the source / drain pattern being adjacent to a side portion of the gate electrode, Wherein, the through contact penetrates the device isolation layer.

14. The semiconductor device according to claim 11, wherein: The first metal layer comprises: a via penetrating the protection insulating pattern and connected to the top surface of the through contact; and An interconnect line is located on the via.

15. The semiconductor device according to claim 11, wherein The top surface of the through-contact is located at a level between a bottom surface and a top surface of the second interlayer insulating layer.

16. A semiconductor device, comprising: A substrate, the substrate comprising a logic unit region and a connection region; an active pattern located on each of the logic cell region and the connection region; a device isolation layer, the device isolation layer covering the lower surface of the active pattern, the upper portion of the active pattern protruding beyond the device isolation layer; a gate electrode, the gate electrode intersecting the active pattern; a source / drain pattern adjacent to a side of the gate electrode and filling a recess in the upper portion of the active pattern; an intermediate connection layer, the intermediate connection layer being located on the gate electrode and the source / drain pattern, the intermediate connection layer comprising an active contact and a gate contact electrically connected to the source / drain pattern and the gate electrode, respectively; a first metal layer, the first metal layer being located on the intermediate connection layer, the first metal layer comprising interconnection lines and vias electrically connecting the interconnection lines to the intermediate connection layer; an etch stop layer, the etch stop layer being located between the intermediate connection layer and the first metal layer; A through contact, the through contact being located below the first metal layer, the through contact penetrating the connection region, and an upper portion of the through contact protruding beyond the etching stop layer; as well as a protective insulating pattern located on the etch stop layer, the protective insulating pattern covering an upper portion of the through contact, at least one of the vias penetrating the protective insulating pattern and connected to the through contact, and at least one of the interconnects being electrically connected to the through contact through the at least one via.

17. The semiconductor device according to claim 16, wherein: The protection insulating pattern covers an upper side surface of the through contact and a top surface of the through contact.

18. The semiconductor device according to claim 16, wherein: The protection insulating pattern covers a portion of a top surface of the etch stop layer adjacent to the through contact.

19. The semiconductor device according to claim 16, wherein: The intermediate connection layer also includes: A connection pattern is located between the active contact and the gate contact and the first metal layer.

20. The semiconductor device according to claim 16, wherein The through contact penetrates the device isolation layer on the connection region.

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