A current sampling circuit for buck converter

Abstract

The present invention provides a current sampling circuit for a buck converter, comprising: a first subcircuit, the first subcircuit comprising a first buffer and a second buffer, the input ends of the first buffer and the second buffer being respectively connected to a signal input end; a second subcircuit, the second subcircuit being connected to the first subcircuit, the second subcircuit comprising an operational amplifier; a third subcircuit, the third subcircuit being connected to the first subcircuit, and the third subcircuit being respectively connected to a positive input end and a negative input end of the operational amplifier, the third subcircuit comprising an inductor. The present invention is cleverly designed, and the same operational amplifier is used under the full application output voltage, so that the continuity of the sampling current can be ensured without switching the operational amplifier.

Description

Technical Field

[0001] The present invention relates to the field of circuits, and more particularly to a current sampling circuit applied to a buck converter. Background Art

[0002] The existing high-precision output current sampling circuit uses a sampling resistor to collect the differential voltage. However, due to the uncertainty of the bias voltage, that is, the output voltage, two OPAs, namely a high-side and a low-side detection amplifier, are required. At the same time, due to factors such as the offset of different OPAs, the actual use will result in non-smooth switching, and the sampling current will be distorted at the switching point.

[0003] like Figure 1 As shown in the figure, due to the different voltages of VOUT in the actual process, two opas are generally required. When the output voltage VOUT is less than a certain threshold, LS_OPA is used, where LS_OPA is powered by the low-voltage power supply VDD; when the output voltage VOUT is higher than the threshold, HS_OPA is used; due to the different offsets of the two opas, the current sampling will not be smooth during the switching process, which will have a bad impact on the system operation. Summary of the invention

[0004] The object of the present invention is to provide a current sampling circuit applied to a buck converter.

[0005] The present invention aims to solve the problems existing in the existing current sampling circuit.

[0006] Compared with the prior art, the technical solution of the present invention and its beneficial effects are as follows:

[0007] A current sampling circuit applied to a buck converter comprises: a first sub-circuit, the first sub-circuit comprises a first buffer and a second buffer, the input ends of the first buffer and the second buffer are respectively connected to a signal input end; a second sub-circuit, the second sub-circuit is connected to the first sub-circuit, the second sub-circuit comprises an operational amplifier; a third sub-circuit, the third sub-circuit is connected to the first sub-circuit, and the third sub-circuit is respectively connected to a non-phase input end and an inverting input end of the operational amplifier, and the third sub-circuit comprises an inductor.

[0008] As a further improvement, the first sub-circuit further includes: a first MOS transistor, wherein the drain of the first MOS transistor is connected to the voltage input end, the gate of the first MOS transistor is connected to the output end of the first buffer, and the source of the first MOS transistor is connected to the second end of the first buffer; a second MOS transistor, wherein the drain of the second MOS transistor is connected to the source of the first MOS transistor, the gate of the second MOS transistor is connected to the output end of the second buffer, and the source of the second MOS transistor is grounded; and a first capacitor, wherein one end of the first capacitor is connected to the first end of the first buffer, and the other end of the first capacitor is connected to the source of the first MOS transistor.

[0009] As a further improvement, a first terminal of the second buffer is connected to a working voltage terminal, and a second terminal of the second buffer is grounded.

[0010] As a further improvement, the second sub-circuit further includes: a first diode, the anode of the first diode is connected to the voltage input terminal, and the cathode of the first diode is connected to the control terminal of the operational amplifier; a second diode, the anode of the second diode is connected to the first terminal of the first buffer, and the cathode of the second diode is connected to the cathode of the first diode; a second capacitor, one end of the second capacitor is connected to the cathode of the first diode, and the other end of the second capacitor is grounded; a third MOS tube, the source of the third MOS tube is connected to the cathode of the first diode, and the gate of the third MOS tube is connected to the cathode of the third MOS tube. a drain; a fourth MOS tube, the source of the fourth MOS tube is connected to the cathode of the first diode, the gate of the fourth MOS tube is connected to the gate of the third MOS tube, and the drain of the fourth MOS tube is connected to the signal output end; a fifth MOS tube, the drain of the fifth MOS tube is connected to the drain of the third MOS tube, the gate of the fifth MOS tube is connected to the output end of the operational amplifier, and the source of the fifth MOS tube is connected to the inverting input end of the operational amplifier; a first resistor, the first resistor is connected to the inverting input end of the operational amplifier; and a second resistor, the second resistor is connected to the non-inverting input end of the operational amplifier.

[0011] As a further improvement, one end of the inductor is connected to the source of the first MOS tube; the third sub-circuit also includes a third resistor, one end of the third resistor is connected to the other end of the inductor, one end of the third resistor is connected to the second resistor, and the other end of the third resistor is connected to the first resistor.

[0012] As a further improvement, the first MOS transistor, the second MOS transistor, the third MOS transistor and the fourth MOS transistor are N-channel MOS transistors.

[0013] As a further improvement, the fifth MOS tube is a P-channel MOS tube.

[0014] As a further improvement, one end of the inductor is connected to the source of the first MOS tube, and the other end of the inductor is connected to the voltage output end; the third sub-circuit also includes a third resistor, one end of the third resistor is grounded and connected to the first resistor, and the other end of the third resistor is connected to the second resistor.

[0015] The beneficial effects of the present invention are as follows: the present invention is cleverly designed, and a single operational amplifier is used to implement current sampling at the output sampling resistor without a switching point; the sampling circuit is powered by connecting diodes in series with VIN and BST and placing energy storage capacitors, respectively, to meet the normal and smooth operation of the current sampling circuit under all application conditions of the buck converter, and the continuity of the sampling current can be guaranteed without switching the operational amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a circuit diagram provided by the background technology.

[0017] Figure 2 This is a current sampling circuit diagram applied to a buck converter provided in Embodiment 1 of the present invention.

[0018] Figure 3 It is a structural diagram provided by Embodiment 1 of the present invention.

[0019] Figure 4 A current sampling circuit applied to a buck converter is provided in the second embodiment of the present invention.

[0020] In the figure:

[0021] 1. First sub-circuit 2. Second sub-circuit 3. Third sub-circuit

[0022] 31. First buffer 32. Second buffer 4. Operational amplifier DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the invention claimed for protection, but merely represents the selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0024] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0025] Reference Figure 2 As shown, a current sampling circuit applied to a buck converter comprises: a first subcircuit 1, the first subcircuit 1 comprises a first buffer 31 and a second buffer 32, the input ends of the first buffer 31 and the second buffer 32 are respectively connected to the signal input end; a second subcircuit 2, the second subcircuit 2 is connected to the first subcircuit 1, the second subcircuit 2 comprises an operational amplifier 4; a third subcircuit 3, the third subcircuit 3 is connected to the first subcircuit 1, and the third subcircuit 3 is respectively connected to the non-inverting input end and the inverting input end of the operational amplifier 4. A single operational amplifier 4 is used to implement current sampling at the output end sampling resistor, and no switching point will occur; the sampling circuit is powered by connecting a diode in series with VIN and BST and placing an energy storage capacitor, respectively, so as to meet the normal and smooth operation of the current sampling circuit under all application conditions of the buck converter, and can ensure the continuity of the sampling current without switching the operational amplifier 4.

[0026] The first sub-circuit 1 further includes: a first MOS transistor M1, wherein the drain of the first MOS transistor M1 is connected to the voltage input end, the gate of the first MOS transistor M1 is connected to the output end of the first buffer 31, and the source of the first MOS transistor M1 is connected to the second end of the first buffer 31; a second MOS transistor M2, wherein the drain of the second MOS transistor M2 is connected to the source of the first MOS transistor M1, the gate of the second MOS transistor M2 is connected to the output end of the second buffer 32, and the source of the second MOS transistor M2 is grounded; and a first capacitor C1, wherein one end of the first capacitor C1 is connected to the first end of the first buffer 31, and the other end of the first capacitor C1 is connected to the source of the first MOS transistor M1.

[0027] A first terminal of the second buffer 32 is connected to the working voltage terminal, and a second terminal of the second buffer 32 is grounded.

[0028] The second sub-circuit 2 further includes: a first diode D1, wherein the anode of the first diode D1 is connected to the voltage input terminal, and the cathode of the first diode D1 is connected to the control terminal of the operational amplifier 4; a second diode D2, wherein the anode of the second diode D2 is connected to the first terminal of the first buffer 31, and the cathode of the second diode D2 is connected to the cathode of the first diode D1; a second capacitor C2, wherein one end of the second capacitor C2 is connected to the cathode of the first diode D1, and the other end of the second capacitor C2 is grounded; a third MOS transistor M3, wherein the source of the third MOS transistor M3 is connected to the cathode of the first diode D1, and the gate of the third MOS transistor M3 is connected to the drain of the third MOS transistor M3; and a third MOS transistor M3. A fourth MOS tube M4, wherein the source of the fourth MOS tube M4 is connected to the cathode of the first diode D1, the gate of the fourth MOS tube M4 is connected to the gate of the third MOS tube M3, and the drain of the fourth MOS tube M4 is connected to the signal output end; a fifth MOS tube M5, wherein the drain of the fifth MOS tube M5 is connected to the drain of the third MOS tube M3, the gate of the fifth MOS tube M5 is connected to the output end of the operational amplifier 4, and the source of the fifth MOS tube M5 is connected to the inverting input end of the operational amplifier 4; a first resistor R1, wherein the first resistor R1 is connected to the inverting input end of the operational amplifier 4; and a second resistor R2, wherein the second resistor R2 is connected to the non-inverting input end of the operational amplifier 4.

[0029] The third sub-circuit 3 includes: an inductor L, one end of which is connected to the source of the first MOS tube M1; a third resistor R3, one end of which is connected to the other end of the inductor L, and one end of which is connected to the second resistor R2, and the other end of which is connected to the first resistor R1.

[0030] The first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 are N-channel MOS transistors.

[0031] The fifth MOS transistor M5 is a P-channel MOS transistor.

[0032] As Figure 2 shown, an operational amplifier 4 is used. The sum and auxiliary current mirror of the operational amplifier 4 adopt a separate power supply rail VP, which is formed by connecting one diode each of VIN and BST. At the same time, a storage capacitor C2 is placed between VP and ground; the BST voltage is equal to Vsw + Vbst-sw when the upper drive is turned on, and Vsw ≈ Vin. Therefore, the BST voltage can supply power to C2, enabling VP to always be greater than or equal to VIN, while VOUT is always less than VIN. So VP can always supply power to the sampling OPA to ensure the normal operation of the sampling current.

[0033] That is, when VOUT / VIN is relatively small, VP ≥ VIN, VOUT << VIN, and the sampling operational amplifier 4 can operate;

[0034] When VOUT / VIN is relatively high, VP ≈ Vbst-sw + VIN >> VIN, and the sampling operational amplifier 4 can still maintain operation;

[0035] Referring to Figure 3 shown, as the duty cycle increases, VOUT increases and VP also increases. The voltage difference between VP and VOUT always satisfies the power supply for the current sampling OPA and the auxiliary circuit.

[0036] Embodiment 2

[0037] Referring to Figure 4 shown, the difference between this embodiment and Embodiment 1 is that the third sub-circuit 3 includes: an inductor L, one end of the inductor L is connected to the source of the first MOS transistor M1, and the other end of the inductor L is connected to the voltage output terminal; a third resistor R3, one end of the third resistor R3 is grounded and connected to the first resistor R1, and the other end of the third resistor R3 is connected to the second resistor R2.

[0038] The working principle and working process of this embodiment and other contents can refer to the corresponding contents of the foregoing embodiment.

[0039] The above embodiments are only used to explain and illustrate the technical solutions of the present invention rather than to limit them. Those skilled in the art should understand that any modification and equivalent replacement without departing from the spirit and scope of the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. A current sampling circuit for a buck converter, characterized in that: include: A first sub-circuit, the first sub-circuit comprising a first buffer and a second buffer, wherein input ends of the first buffer and the second buffer are respectively connected to the signal input end; a second sub-circuit, the second sub-circuit being connected to the first sub-circuit, the second sub-circuit comprising an operational amplifier; a third sub-circuit, the third sub-circuit being connected to the first sub-circuit, and the third sub-circuit being respectively connected to the non-inverting input terminal and the inverting input terminal of the operational amplifier, and the third sub-circuit comprising an inductor; The first sub-circuit further includes: a first MOS transistor, wherein a drain of the first MOS transistor is connected to a voltage input terminal, a gate of the first MOS transistor is connected to an output terminal of the first buffer, and a source of the first MOS transistor is connected to a second terminal of the first buffer; a second MOS tube, wherein the drain of the second MOS tube is connected to the source of the first MOS tube, the gate of the second MOS tube is connected to the output end of the second buffer, and the source of the second MOS tube is grounded; a first capacitor, wherein one end of the first capacitor is connected to the first end of the first buffer, and the other end of the first capacitor is connected to the source of the first MOS transistor; A first terminal of the second buffer is connected to the working voltage terminal, and a second terminal of the second buffer is grounded; The second sub-circuit further includes: a first diode, wherein an anode of the first diode is connected to the voltage input terminal, and a cathode of the first diode is connected to the control terminal of the operational amplifier; a second diode, wherein an anode of the second diode is connected to the first end of the first buffer, and a cathode of the second diode is connected to the cathode of the first diode; a second capacitor, one end of the second capacitor being connected to the cathode of the first diode, and the other end of the second capacitor being grounded; a third MOS tube, wherein the source of the third MOS tube is connected to the cathode of the first diode, and the gate of the third MOS tube is connected to the drain of the third MOS tube; a fourth MOS tube, wherein a source of the fourth MOS tube is connected to the cathode of the first diode, a gate of the fourth MOS tube is connected to the gate of the third MOS tube, and a drain of the fourth MOS tube is connected to the signal output end; a fifth MOS tube, wherein the drain of the fifth MOS tube is connected to the drain of the third MOS tube, the gate of the fifth MOS tube is connected to the output end of the operational amplifier, and the source of the fifth MOS tube is connected to the inverting input end of the operational amplifier; a first resistor connected to an inverting input terminal of the operational amplifier; A second resistor is connected to the non-inverting input terminal of the operational amplifier.

2. The current sampling circuit for a buck converter according to claim 1, characterized in that: One end of the inductor is connected to the source of the first MOS tube; the third sub-circuit also includes a third resistor, one end of the third resistor is connected to the other end of the inductor, one end of the third resistor is connected to the second resistor, and the other end of the third resistor is connected to the first resistor.

3. The current sampling circuit for a buck converter according to claim 1, characterized in that: The first MOS transistor, the second MOS transistor, the third MOS transistor and the fourth MOS transistor are N-channel MOS transistors.

4. The current sampling circuit for a buck converter according to claim 1, characterized in that: The fifth MOS tube is a P-channel MOS tube.

5. The current sampling circuit for a buck converter according to claim 1, characterized in that: One end of the inductor is connected to the source of the first MOS tube, and the other end of the inductor is connected to the voltage output end; the third sub-circuit also includes a third resistor, one end of the third resistor is grounded and connected to the first resistor, and the other end of the third resistor is connected to the second resistor.

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