Semiconductor crystal grain and method for forming fan-out integrated structure

Abstract

A semiconductor die and a method for forming a fan-out integrated structure are disclosed. The semiconductor die includes a bonding pad and a hole formed in the bonding pad, a passivation layer formed on a portion of the bonding pad, and a protection layer formed on the hole in the bonding pad.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to semiconductor dies and methods of forming fan-out integrated structures. Background Art

[0002] As semiconductor manufacturing technology and processes develop, semiconductor wafer / die size is shrinking. In addition, the number and complexity of functions integrated into semiconductor dies and the transistor density of semiconductor wafers / dies are increasing. As a result, semiconductor dies have more and more I / O pads formed in a smaller area, and the density of I / O pads increases rapidly over time. As a result, packaging of semiconductor dies becomes more difficult, which will adversely affect the yield of packaging.

[0003] Typically, dies (chips) are cut from a wafer before packaging them, and only "known good dies" are packaged. An advantageous feature of this packaging technology is the possibility of forming an integrated fan-out (InFO) package. In an InFO package, the I / O pads on the die can be redistributed to an area larger than the die, and thus the number of I / O pads formed on the surface of the die can be increased.

[0004] In conventional integrated circuit manufacturing techniques, testing is typically the last step used to detect defects that may have been created during the integrated circuit manufacturing process. In conventional methods, semiconductor dies are often inspected and tested after the formation of conductive (e.g., copper) pillars, just prior to packaging. Because semiconductor dies are tested late in the manufacturing process, even though such testing may detect defects and even determine the cause of the defects, corrective and mitigation measures may not be taken to repair such defects because testing does not occur until the manufacturing process is nearly complete. Summary of the invention

[0005] Some embodiments of the present disclosure provide a semiconductor die including: a bonding pad including a hole formed in the bonding pad; a passivation layer formed over a portion of the bonding pad; and a protection layer formed over the hole in the bonding pad.

[0006] Some embodiments of the present disclosure provide a semiconductor die, including: a bonding pad, the bonding pad including a hole formed in the bonding pad, wherein the hole is formed with a diameter in a range of 0.01 microns to 50 microns and a depth of 0.01 microns to 5 microns; a passivation layer formed over a portion of the bonding pad; a protective layer formed over the hole in the bonding pad; and a first seed layer formed over the hole in the bonding pad, wherein a top surface of the first seed layer is contoured over the hole in the bonding pad.

[0007] Some embodiments of the present disclosure provide a method of forming a fan-out integrated structure on a semiconductor die, comprising: forming a bonding pad on the semiconductor die; depositing a passivation layer over multiple portions of the bonding pad; and forming a hole in the bonding pad by applying pressure to the bonding pad with a wafer probe. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1A A vertical cross-sectional view illustrating a step of forming a hole in a contact pad of a semiconductor die in a method for manufacturing a semiconductor device according to some embodiments;

[0010] Figure 1B A vertical cross-sectional view illustrating a step of depositing a seed layer and a protection layer in a hole in a method for manufacturing a semiconductor device according to some embodiments;

[0011] Figure 1C According to some embodiments, a method for manufacturing a semiconductor device is shown. Figure 1B A vertical cross-sectional view of a step of depositing an under bump metallization (UBM) layer on a surface of the intermediate structure shown in FIG.

[0012] Figure 1D A vertical cross-sectional view illustrating the steps of depositing and patterning a photoresist layer and depositing a copper pillar in the patterned photoresist layer above an under bump metallization layer in a method for manufacturing a semiconductor device according to some embodiments;

[0013] Figure 1E A vertical cross-sectional view illustrating the steps of patterning an under bump metallization layer and removing a photoresist layer in a method for manufacturing a semiconductor device according to some embodiments;

[0014] Figure 1F According to some embodiments, a method for manufacturing a semiconductor device is shown. Figure 1E A vertical cross-sectional view of the steps of disposing a series of polymer layers, redistribution layers and solder balls on the intermediate structure shown in FIG.

[0015] Figure 2 A vertical cross-sectional view illustrating a step of depositing a seed layer and a protection layer in an off-center hole in a method for manufacturing a semiconductor device according to another embodiment;

[0016] Figure 3A flowchart illustrating a method of forming a semiconductor device according to various embodiments of the present disclosure;

[0017] Figure 4 The flowchart is a method for testing a semiconductor device according to various embodiments of the present disclosure.

[0018]

Explanation of symbols

[0019] 100: Fan-out integrated structure

[0020] 102: Semiconductor grains

[0021] 104:Jointing pad

[0022] 106: passivation layer

[0023] 108a: Hole

[0024] 108b: Hole

[0025] 109: Wafer probe

[0026] 110: Seed layer

[0027] 112: Protective layer

[0028] 114: first under-bump metallization layer

[0029] 116: first diffusion barrier layer

[0030] 118: The Second Crystal Layer

[0031] 120: Conductive column

[0032] 121: Photoresist layer

[0033] 124: Second under-bump metallization layer

[0034] 126: Second diffusion barrier layer

[0035] 128: The Third Crystal Layer

[0036] 130:Solder ball

[0037] 300: Methods

[0038] 302: Steps

[0039] 304: Steps

[0040] 305: Steps

[0041] 306: Steps

[0042] 307: Steps

[0043] 308: Steps

[0044] 310: Steps

[0045] 312: Steps

[0046] 314: Steps

[0047] 316: Steps

[0048] 318: Steps

[0049] 320: Steps

[0050] 322: Steps

[0051] 324: Steps

[0052] 400: Method

[0053] PM0: first polymer layer

[0054] PM1: Second polymer layer

[0055] PM2: The third polymer layer

[0056] RDL: Redistribution Layer

[0057] x: diameter

[0058] y: depth DETAILED DESCRIPTION

[0059] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. The following describes specific examples of components and arrangements to simplify the present disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, a first feature is formed on or on a second feature, which may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat element symbols and / or letters in various examples. This repetition is for simplification and clarity purposes, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0060] Additionally, for simplicity of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another (additional) element or feature as depicted in the figures. Such spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0061] As described above, in integrated circuit manufacturing technology, testing is usually the last step for detecting defects in the wafer and / or circuit generated during the integrated circuit manufacturing process. In some methods, after forming a conductive (e.g., copper) pillar, just before packaging, the semiconductor grain is inspected. In these methods, a bonding pad can be formed. A passivation layer can be deposited on the bonding pad. The passivation layer can be etched in a later stage in the manufacturing process to form an opening on the bonding pad. An under bump metallization (UBM) layer can be deposited on the bonding pad / passivation layer structure within the opening in the passivation layer. Copper pillars can be formed on the bonding pads. Solder bumps can be formed on the copper pillars to provide connection nodes for the wafer probe. The solder bumps can be removed by top grain polishing after the wafer probe is completed. The solder can act as a sacrificial layer after the wafer probe.

[0062] Wafer probe testing can determine the root cause(s) of defects in manufactured wafers and / or circuits. However, because testing is delayed until later or at the end of the manufacturing process, even if the cause of the defect can be determined, corrective or mitigating measures may not be taken in a timely manner.

[0063] In various embodiments disclosed herein, circuit probe testing can be performed between wafers to verify that each semiconductor die / wafer meets product specifications at an earlier stage in the manufacturing process. In various embodiments, the finished die can be inspected after the bonding pads are formed but before the packaging process. Therefore, the inspection of the semiconductor die can be performed several days earlier in the manufacturing process. In the event that the cause of the defect is determined during the test process, corrective or mitigation measures are taken to repair the defect of the subsequently manufactured semiconductor die before the packaging process can be initiated. Various embodiments disclosed herein can allow manufacturers to obtain a date for wafer detection at an earlier time without incurring additional financial or opportunity costs. In addition, the cost of additionally forming solder bumps on copper pillars for wafer detection (which are subsequently grounded) can be avoided.

[0064] refer to Figure 1A, a semiconductor die 102 on which a circuit element (not shown) is formed may be provided. The semiconductor die 102 may include a bonding pad 104 and a passivation layer 106. The passivation layer 106 may protect the top surface of the semiconductor die 102 and a portion of the bonding pad 104. The bonding pad 104 may be made of aluminum, copper, or an alloy thereof. The bonding pad 104 may be formed by any suitable method. For example, a layer of bonding pad material may be deposited by physical vapor deposition (PVD), such as sputtering deposition using a sputtering target made of aluminum, copper, or an alloy thereof. Alternatively, the bonding pad material may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), or any epitaxial deposition method. After depositing the bonding pad material, the deposited layer of the bonding pad material may be patterned by photolithography and etching processes.

[0065] The passivation layer 106 may be made of silicon oxide, silicon oxynitride, and / or a low-k dielectric material such as organosilicate glass. The passivation layer 106 may be formed by depositing a photoresist layer (not shown) and patterning the photoresist layer so that the central portion of the bonding pad 104 may be masked. The passivation layer 106 may be deposited on the surface of the semiconductor die 102 and on the bonding pad 104. Next, the photoresist layer may be removed by a stripping process so that the central portion of the bonding pad 104 is exposed. Alternatively, the passivation layer 106 may be deposited on the surface of the semiconductor die 102 and on the entire bonding pad 104. Next, a photoresist layer (not shown) may be deposited on the passivation layer 106 and patterned so that a portion of the passivation layer 106 above the central portion of the bonding pad 104 is exposed. Next, the exposed portion of the passivation layer 106 above the central portion of the bonding pad 104 may be removed by, for example, an etching process. Finally, the photoresist layer may be removed, such as by ashing or by dissolving in a solution.

[0066] Next, the wafer probe 109 can be pressed against the exposed surface of the bonding pad 104. Applying the wafer probe 109 to the exposed surface of the bonding pad 104 can form a hole 108a in the exposed surface of the bonding pad 104. The hole 108a does not need to penetrate the entire thickness of the bonding pad 104. The depth of the hole 108a can be deep enough to accommodate the tip portion of the wafer probe 109. During the wafer manufacturing process (and before the packaging process), the wafer probe 109 can be used for testing to determine whether the wafer being manufactured is acceptable and meets the product specifications. In the case where the wafer being manufactured does not meet the product specifications, this wafer can be discarded. Therefore, only known good wafers or dies can be transferred to further processing operations. In various embodiments, the wafer probe 109 may have a diameter "x" in the range of 0.01 microns to 50 microns, such as 1 micron to 25 microns, although larger or smaller diameters can be used. Thus, in various embodiments, the hole 108a may have a diameter in the range of 0.01 microns to 50 microns, such as 1 micron to 25 microns, although larger or smaller diameters may be used. In various embodiments, the hole 108a may have a depth "y" in the range of 0.01 microns to 5 microns, such as 1 micron to 3 microns, although larger or smaller depths may be used. After forming the hole 108a in the bonding pad 104 (i.e., after forming the hole 108a with the wafer probe 109), the semiconductor die 102 may be tested by the wafer probe 109 to find potential defects.

[0067] refer to Figure 1B , a seed layer 110 may be deposited over the surface of the bonding pad 104 that may be exposed through the passivation layer 106. The seed layer 110 is a layer that assists in forming subsequent layers. In various embodiments, the seed layer 110 may be deposited using an electroless plating process. In an electroless plating process, a seed material may be electroplated using a chemical reaction without applying an external current (i.e., without electricity). The electroless plating process forms a conformal layer of seed material that follows the contours of the bonding pad 104 and the hole 108a. In various embodiments, the seed layer 110 may include nickel (Ni). Other suitable materials for the seed layer 110 are within the contemplated scope of the present disclosure. The seed layer 110 may have a thickness in the range of 0.01 microns to 5 microns, such as 1 micron to 3 microns, although greater or lesser thicknesses may be used.

[0068] Next, a protective layer 112 may be grown using deposition of a seed layer 110 to assist growth in areas exposed to the passivation layer 106. The protective layer 112 may be deposited to prevent oxidation of the seed layer 110. In various embodiments, the protective layer 112 includes gold (Au). However, other suitable materials within the intended scope of the present disclosure may be used. The protective layer may have a thickness in the range of 0.01 microns to 0.2 microns, although greater or lesser thicknesses may be used. The protective layer 112 may be formed by any suitable method. For example, in various embodiments, the protective layer 112 may be formed by immersion plating the protective layer 112 on the seed layer 110. In this way, the protective layer 112 may form a conformal layer that follows the contour of the bonding pad 104 having the formed hole 108a and the seed layer 110. Thus, the contour (recess) of the hole 108a may be present in the final product. In a case where the semiconductor die 102 is not tested by the wafer prober 109 , the bonding pad 104 , the seed layer 110 , and the protection layer 112 may be substantially coplanar because the hole 108 a may not be formed in the bonding pad 104 .

[0069] refer to Figure 1C , a first under bump metallization (UBM) layer 114 may be conformally deposited on the surface of the passivation layer 106 and the protective layer 112. In some embodiments, the first UBM layer 114 may include multiple layers. For example, in various embodiments, the first UBM layer 114 may include a first diffusion barrier layer 116 and a second seed layer 118. As discussed in more detail below, the second seed layer 118 may assist in forming the conductive pillar 120. In various embodiments, the first diffusion barrier layer 116 may include Ti, TiN, or Ta. Other suitable materials are within the intended scope of the present disclosure. In various embodiments, the second seed layer 118 may include Cu or a Cu alloy. However, other suitable materials within the intended scope of the present disclosure may be used. The first diffusion barrier layer 116 may have a thickness in the range of 10 nanometers to 50 nanometers, such as 15 nanometers to 40 nanometers, although greater or lesser thicknesses may be used. The second seed layer 118 may have a thickness in a range of 10 nanometers to 150 nanometers, such as 15 nanometers to 100 nanometers, although greater or lesser thicknesses may be used.

[0070] refer to Figure 1D, the first UBM layer 114 may be covered by the photoresist layer 121. The photoresist layer 121 may then be patterned to provide an opening (not shown) in the photoresist layer 121, exposing a portion of the first UBM layer 114 located above the seed layer 110 and the protection layer 112. In various embodiments, the upper surface of the first UBM layer 114 above the seed layer 110 and the protection layer 112 may have a concave portion due to the underlying seed layer 110 and the protection layer 112 filling the hole 108a. Next, copper may be deposited in the opening in the photoresist layer 121 above the first UBM layer 114 to form the conductive pillar 120. Other suitable materials within the intended scope of the present disclosure may be deposited to form the conductive pillar 120.

[0071] refer to Figure 1E , the photoresist layer 121 may be removed, for example, by ashing. Using the conductive pillars 120 as a mask, the exposed portions of the first UBM layer 114 may be removed. The exposed UBM material of the first UBM layer 114 may be removed, for example, by selective etching, such as by reactive ion etching.

[0072] In an alternative embodiment, the conductive pillars 120 may be deposited on Figure 1C . In this way, the recess in the first UBM layer 114 formed above the hole 108a can be filled with the conductive pillar 120 material. A photoresist layer can be formed over the conductive pillar 120 material to mask a portion of the conductive pillar 120 material overlying the bonding pad 104. The exposed portion of the conductive pillar 120 material can be removed (e.g., via an etching process). In various embodiments, the bottom surface of the conductive pillar 120 can have a convex surface that follows the contours of the hole 108a and the overlying layers (i.e., the seed layer 110, the protection layer 112, and the first UBM layer 114).

[0073] refer to Figure 1F , a first polymer layer PM0 may be formed on the passivation layer 106 and the conductive pillars 120. Next, a chemical-mechanical polishing (CMP) step may be performed to planarize the upper surface of the element (i.e., the conductive pillars 120) and the first polymer layer PM0 so as to remove excess portions of the first polymer layer PM0 and expose the top surface of the conductive pillars 120. The top surface of the first polymer layer PM0 and the top surface of the conductive pillars 120 may be formed to be coplanar.

[0074] Next, a second polymer layer PM1 may be formed on the first polymer layer PM0. A photoresist layer (not shown) may be deposited on the second polymer layer PM1. The photoresist layer (not shown) may be patterned using photolithography to form a mask on the second polymer layer PM1. The second polymer layer PM1 may be etched to expose a portion of the conductive pillar 120 in the opening of the second polymer layer PM1.

[0075] Next, a redistribution layer RDL may be deposited over the second polymer layer PM1 and in the etched openings in the second polymer layer PM1 so that the redistribution layer RDL may be in electrical contact with the conductive pillars 120. As the name implies, a redistribution layer is an additional metal layer on the wafer that redistributes the input-output pads of the integrated circuit so that electrical connections can be made at another location on the die. In this way, the redistribution layer RDL may provide more convenient access to the input-output pads. Another example of the use of the redistribution layer RDL may be to spread (i.e., distribute) contact points around the die so that solder balls may be applied and the thermal stress of the installation may be spread (i.e., distributed) throughout the die. The redistribution layer RDL may be patterned so that undesired redistribution layer RDL material may be removed from the top surface of the second polymer layer PM1, leaving only the desired traces on the surface of the second polymer layer PM1.

[0076] Next, a third polymer layer PM2 may be deposited on the surface of the second polymer layer PM1 and the redistribution layer RDL. A photoresist layer (not shown) may be deposited on the third polymer layer PM2. The photoresist layer (not shown) may be patterned using photolithography to form a mask on the third polymer layer PM2. The third polymer layer PM2 may be etched to expose a portion of the redistribution layer RDL in the opening of the third polymer layer PM2.

[0077] A second UBM layer 124 may be deposited in the holes in the third polymer layer PM2, thereby forming an electrical contact with the redistribution layer RDL. Therefore, the fan-out integrated structure 100 may include two UBM layers (a first UBM layer 114, a second UBM layer 124). Just like the first UBM layer 114, the second UBM layer 124 may include a second diffusion barrier layer 126 and a third seed layer 128. The third seed layer 128 may assist in the formation and bonding of the solder balls 130. In various embodiments, the second diffusion barrier layer 126 may be made of Ti, TiN or Ta. Other suitable materials are within the intended scope of the present disclosure. The second diffusion barrier layer 126 may have a thickness in the range of 10 nanometers to 50 nanometers, such as 20 nanometers to 40 nanometers, although smaller or larger thicknesses may be used. The third seed layer 128 may be made of copper. Other suitable materials are within the intended scope of the present disclosure. The third seed layer 128 may have a thickness in the range of 10 nanometers to 300 nanometers, such as 20 nanometers to 200 nanometers, although greater or lesser thicknesses may be used. As depicted, due to the additional process steps and the layers formed between the second UBM layer 124 and the first UBM layer 114, the second UBM layer 124 may be located at a different vertical distance from the top surface of the semiconductor die 102 than the first UBM layer 114. Next, solder balls 130 may be deposited on the second UBM layer 124, thereby completing the fan-out integrated structure 100. Figure 1F As shown in FIG. 1 , the solder ball 130 may be laterally spaced from the conductive pillar 120. That is, in contrast to known fan-out integrated structures, the solder ball 130 may not be directly above and in contact with the conductive pillar 120. The solder ball 130 may be offset from the conductive pillar 120.

[0078] The polymer layers (first polymer layer PM0, second polymer layer PM1, third polymer layer PM2) may be made of the same or different polymers. Exemplary polymers include, but are not limited to, polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), and combinations thereof. Other suitable polymer materials are within the contemplated scope of the present disclosure.

[0079] refer to Figure 2, an embodiment is provided in which the hole 108b in the bonding pad 104 is located at a position offset from the center of the bonding pad 104. That is, the hole 108b in the bonding pad 104 is laterally offset from the center of the bonding pad 104. As described above, before the packaging process, a circuit probe test can be performed between wafers to verify that each die meets the product specifications. In order to ensure that the wafer probe 109 is properly aligned, a probe mark check can be performed to determine whether a position shift of the probe mark (e.g., hole 108a, hole 108b) may occur. Probe mark shift refers to the shift of the probe mark on the bonding pad 104, which indicates that the probe mark has exceeded the safety range of the bonding pad. The current embodiment reflects the effect of probe shift on the position of the hole 108b (i.e., probe mark) in the bonding pad 104.

[0080] Figure 3 Flowchart 300 is a diagram illustrating a general method 300 for forming a fan-out integrated structure 100 on a semiconductor die 102 according to various embodiments. Referring to step 302, the method includes forming a bonding pad 104 on the semiconductor die 102. Referring to step 304, the method includes applying a wafer probe 109 to the bonding pad 104 to form holes 108a, 108b in the bonding pad 104. Thus, the size of the wafer probe 109 may affect the size of the holes 108a, 108b formed. Referring to step 306, a seed layer 110 may be deposited on the surface of the bonding pad 104 and the holes 108a, 108b formed in the bonding pad. Referring to step 308, a protective layer 112 may be formed on the seed layer 110. Referring to step 310, a first UBM layer 114 may be formed on the surface of the seed layer 112 and the passivation layer 106. Referring to step 312, a conductive pillar 120 may be formed on the first UBM layer 114. Referring to step 314, a first polymer layer PM0 may be formed around the conductive pillar 120. Referring to step 316, a second polymer layer PM1 may be formed on the first polymer layer PM0. The second polymer layer PM1 may be etched to form an opening to expose the top surface of the conductive pillar 120. Referring to step 318, a redistribution layer (RDL) may be formed on the second polymer layer PM1 and in the opening in the second polymer layer PM1 to contact the top surface of the conductive pillar 120. Referring to step 320, a third polymer layer PM2 may be formed on the RDL. The third polymer layer PM2 may also contact a portion of the second polymer layer PM1. The third polymer layer PM2 may be etched to form an opening that exposes the top surface of the RDL. Referring to step 322, a second UBM layer 124 may be formed on the third polymer layer PM2 and in the etched opening to contact the top surface of the RDL. Referring to step 324, a solder ball 130 may be deposited on the second UBM layer 124.

[0081] Figure 4A flow chart is provided for illustrating a general method 400 of a method for testing a semiconductor die 102 according to various embodiments. As discussed above with respect to method 300, referring to step 302, the method includes forming a bonding pad 104 on the semiconductor die 102. Referring to step 304, the method includes applying a wafer probe 109 to the bonding pad 104 to form holes 108a, 108b in the bonding pad 104. Referring to step 305, the method includes positioning the wafer probe 109 in the holes 108a, 108b in the bonding pad 104, and determining whether the semiconductor die 102 meets product specifications. In response to determining that the semiconductor die 102 meets product specifications (i.e., determination step 305 = yes), the semiconductor die 102 may be indicated as an acceptable semiconductor die 102, and the above steps with respect to testing may be performed. Figure 3 The remaining processing steps 306 through 324 of method 300 are described in detail in FIG. 1. In response to determining that semiconductor die 102 does not meet product specifications (ie, determination step 305 = No), semiconductor die 102 may be discarded as unacceptable.

[0082] In general, the structures and methods of the present disclosure may be used to form a fan-out integrated structure 100 on a semiconductor die 102 and test the semiconductor die 102. As described above, in conventional integrated circuit manufacturing techniques, testing is typically the last step used to detect defects that may have occurred during the integrated circuit manufacturing process. In conventional methods, the semiconductor die 102 is inspected after forming the conductive (e.g., copper) pillars 120 and just before packaging.

[0083] However, testing may determine the root cause(s) of such defects. Because testing is delayed until a later stage or at the end of the manufacturing process, even if the cause of the defect can be determined, corrective or mitigation measures may not be taken. In various embodiments disclosed herein, circuit probe testing may be performed between wafers to verify that each semiconductor die (wafer) 102 meets product specifications at an earlier stage in the manufacturing process. In various embodiments, the semiconductor die 102 may be inspected after the bonding pads 104 are formed but before the packaging process. Thus, inspection of the semiconductor die 102 may be performed several days earlier in the manufacturing process. In the event that the cause of the defect is determined during the testing process, corrective or mitigation measures may be taken to repair the defect of the subsequently manufactured semiconductor die 102 before the packaging process can be initiated.

[0084] With reference to all figures and in accordance with various embodiments of the present disclosure, a semiconductor die 102 is provided. The semiconductor die 102 may include a bonding pad 104 and holes 108a, 108b formed in the bonding pad 104. The embodiment semiconductor die 102 may further include a passivation layer 106 formed over a portion of the bonding pad 104. The embodiment semiconductor die 102 may further include a protective layer 112 formed over the holes 108a, 108b in the bonding pad 104. In an embodiment, the semiconductor die 102 may also include a first seed layer 110 formed over the holes 108a, 108b in the bonding pad 104, wherein a top surface of the first seed layer 110 is contoured over the holes 108a, 108b in the bonding pad 104. In an embodiment, the holes 108b in the bonding pad 104 may be laterally offset from the center of the bonding pad 104. In an embodiment semiconductor die 102, the first seed layer 110 may include electroless nickel plating and may be formed to a thickness in a range of 0.01 microns to 5 microns, and the protective layer 112 may include gold plating and may be formed to a thickness in a range of 0.01 microns to 0.2 microns. In an embodiment semiconductor die 102, a top surface of the protective layer 112 is contoured over the holes 108a, 108b in the bonding pads 104. In another embodiment, the semiconductor die 102 may include a first under bump metallization layer 114 covering the protective layer 112, and a top surface of the first under bump metallization layer 114 includes a recessed portion located over the holes 108a, 108b in the bonding pads 104. In another embodiment, the semiconductor die 102 may include a first under bump metallization layer 114 and a second under bump metallization layer 124 covering the protection layer 112, wherein the first under bump metallization layer 114 and the second under bump metallization layer 124 are located at different vertical distances from the top surface of the semiconductor die 102. In another embodiment, the semiconductor die 102 further includes a conductive pillar 120 located on the first under bump metallization layer 114; and a solder ball 130 located on the second under bump metallization layer 124, wherein the solder ball 130 is laterally spaced from the conductive pillar 120.

[0085] Another embodiment semiconductor die 102 is provided. The embodiment semiconductor die 102 may include a bonding pad 104 and holes 108a, 108b formed in the bonding pad 104, wherein the holes are formed with a diameter in a range of 0.01 microns to 50 microns and a depth of 0.01 microns to 5 microns. The embodiment semiconductor die 102 may further include a passivation layer 106 formed over a portion of the bonding pad 104. The embodiment semiconductor die 102 may further include a protective layer 112 formed over the holes 108a, 108b in the bonding pad 104. In an embodiment, the semiconductor die 102 may also include a first seed layer 110 formed over the holes 108a, 108b in the bonding pad 104, wherein a top surface of the first seed layer 110 is contoured over the holes 108a, 108b in the bonding pad 104. In one embodiment, a first under bump metallization layer 114 covering the protection layer 112 is further included. The first under bump metallization layer 114 includes a first diffusion barrier layer 116 and a second seed layer 118 .

[0086] One embodiment is directed to a method 300 of forming a fan-out integrated structure 100 on a semiconductor die 102, which includes forming a bonding pad 104 on the semiconductor die 102, depositing a passivation layer 108 on the bonding pad 104, and forming holes 108a and 108b in the bonding pad 104 by applying pressure with a wafer probe 109.

[0087] In the embodiment method, the holes 108a, 108b are formed with a diameter in the range of 0.01 micron to 50 microns and a depth of 0.01 micron to 5 microns. The embodiment method further includes the step of testing the semiconductor die 102 by contacting the bonding pad 104 in the holes 108a, 108b formed in the bonding pad 104 by a wafer prober 109 to determine whether the semiconductor die 102 meets the product specification. The embodiment method may further include the step of forming a first seed layer (seed layer 110) in the holes 108a, 108b in response to the semiconductor die 102 meeting the product specification. The embodiment method further includes the step of forming a protective layer 112 on the first seed layer (seed layer 110). In the embodiment method, forming the first seed layer (seed layer 110) includes electroless nickel plating on the bonding pad 104; and forming the protective layer 112 includes immersion gold plating on the first seed layer (seed layer 110). The method of this embodiment further includes the steps of: forming a first under bump metallization layer 114 on the protective layer 112; forming a conductive pillar 120 on the first under bump metallization layer 114; forming a redistribution layer on the first under bump metallization layer 114; forming a second under bump metallization layer 124 on the redistribution layer; and forming a solder ball 130 on the second under bump metallization layer 124. The method of this embodiment, wherein the solder ball 130 is formed to be laterally spaced from the conductive pillar 120. The method of this embodiment, wherein the second under bump metallization layer 124 is formed at a different vertical distance from the top surface of the semiconductor die 102 than the first under bump metallization layer 114. The method of this embodiment, wherein forming the first under bump metallization layer 114 includes forming a first diffusion barrier layer 116 and a second seed layer 118; and forming the second under bump metallization layer 124 includes forming a second diffusion barrier layer 126 and a third seed layer 128.

[0088] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and replacements herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor crystal grain, characterized in that: include: a bonding pad including a hole formed therein; a first seed layer formed over the hole in the bond pad, wherein a top surface of the first seed layer is contoured over the hole in the bond pad; a passivation layer formed over a portion of the bonding pad; as well as A protection layer is formed over the hole in the bonding pad.

2. The semiconductor crystal grain according to claim 1, characterized in that: The invention further comprises a first under-bump metallization layer covering the protection layer, wherein the first under-bump metallization layer comprises a first diffusion barrier layer and a second seed crystal layer.

3. The semiconductor crystal grain according to claim 1, characterized in that: The hole in the bonding pad is laterally offset from a center of the bonding pad.

4. The semiconductor crystal grain according to claim 1, characterized in that: The first seed layer includes electroless nickel plating and is formed to a thickness in a range of 0.01 microns to 5 microns; and The protective layer includes gold electroplating and is formed to have a thickness in a range of 0.01 microns to 0.2 microns.

5. The semiconductor crystal grain according to claim 1, characterized in that: A top surface of the protective layer is contoured over the hole in the bond pad.

6. The semiconductor crystal grain according to claim 5, characterized in that: A first under bump metallization layer covering the protection layer is further included, and a top surface of the first under bump metallization layer includes a concave portion located above the hole in the bonding pad.

7. The semiconductor crystal grain according to claim 1, characterized in that: The invention further comprises a first under bump metallization layer and a second under bump metallization layer covering the protection layer, wherein the first under bump metallization layer and the second under bump metallization layer are located at different vertical distances from a top surface of the semiconductor die.

8. The semiconductor crystal grain according to claim 7, characterized in that: Further including: a conductive column located on the first under bump metallization layer; and A solder ball is located on a second under bump metallization layer, wherein the solder ball is laterally spaced from the conductive post.

9. A semiconductor crystal grain, characterized in that: include: a bonding pad including a hole formed therein, wherein the hole is formed with a diameter in a range of 0.01 micrometers to 50 micrometers and a depth of 0.01 micrometers to 5 micrometers; a passivation layer formed over a portion of the bonding pad; a protective layer formed over the hole in the bonding pad; as well as A first seed layer is formed over the hole in the bonding pad, wherein a top surface of the first seed layer is contoured over the hole in the bonding pad.

10. The semiconductor crystal grain according to claim 9, characterized in that: The invention further comprises a first under-bump metallization layer covering the protection layer, wherein the first under-bump metallization layer comprises a first diffusion barrier layer and a second seed crystal layer.

11. A method for forming a fan-out integrated structure on a semiconductor die, characterized in that: include: forming a bonding pad on the semiconductor die; depositing a passivation layer over portions of the bond pad; forming a hole in the bond pad by applying pressure to the bond pad with a wafer probe; testing the semiconductor die by contacting the bonding pad through the hole formed in the bonding pad with the wafer probe to determine whether the semiconductor die meets product specifications; and A first crystal layer is formed in the hole in response to the semiconductor grain meeting product specifications.

12. The method according to claim 11, characterized in that The hole is formed with a diameter in a range of 0.01 micrometers to 50 micrometers and a depth of 0.01 micrometers to 5 micrometers.

13. The method according to claim 11, characterized in that A top surface of the first seed layer is contoured over the hole in the bond pad.

14. The method according to claim 11, characterized in that The hole in the bonding pad is laterally offset from a center of the bonding pad.

15. The method according to claim 11, characterized in that The method further includes forming a protective layer on the first seed crystal layer.

16. The method according to claim 15, characterized in that Forming the first seed layer includes electroless plating nickel over the bonding pad; and Forming the protective layer includes immersion electroplating gold on the first seed layer.

17. The method according to claim 16, characterized in that Further including: forming a first under bump metallization layer on the protective layer; forming a conductive pillar on the first under bump metallization layer; forming a redistribution layer on the first under bump metallization layer; forming a second under bump metallization layer on the redistribution layer; and A solder ball is formed on the second under bump metallization layer.

18. The method according to claim 17, characterized in that The solder ball is formed to be laterally spaced from the conductive post.

19. The method according to claim 17, characterized in that The second under bump metallization layer is formed at a different vertical distance from a top surface of the semiconductor die than the first under bump metallization layer.

20. The method according to claim 17, characterized in that Forming the first under bump metallization layer includes forming a first diffusion barrier layer and a second seed layer; and Forming the second under-bump metallization layer includes forming a second diffusion barrier layer and a third seed crystal layer.

Images