Semiconductor structure and method for forming semiconductor structure

Abstract

A semiconductor structure and a method for forming the semiconductor structure, the method comprising: providing a substrate; forming an initial fin structure on the substrate, the initial fin structure comprising a multi-layered initial sacrificial layer and a nanowire located on the initial sacrificial layer; forming source and drain openings at both ends of the initial fin structure in the extension direction, the source and drain openings exposing the sidewall surface of the initial fin structure; removing a portion of the initial sacrificial layer exposed by the source and drain openings to form a sacrificial layer, and forming a first groove on the sidewall of the sacrificial layer between adjacent nanowires; forming a first sidewall material layer in the first groove and on the sidewall of the nanowire, the first sidewall material layer having first ions; annealing the first sidewall material layer to diffuse the first ions into the nanowire to form a modified nanowire, the modified nanowire having the first ions. The performance of the semiconductor structure formed by the method is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] With the development of semiconductor technology, the electrical control ability of the traditional planar metal-oxide-semiconductor field-effect transistor (MOSFET) over the channel has weakened, and the leakage current problem has become increasingly prominent. Fin field effect transistor (FinFET) is an emerging multi-gate device, which generally includes a fin protruding from the surface of the semiconductor substrate, a gate structure covering part of the top surface and sidewall of the fin, and a source-drain doped region in the fin on both sides of the gate structure. In the traditional planar metal-oxide semiconductor field effect transistor structure, the gate that controls the current passing through can only control the connection and disconnection of the circuit on one side of the gate, which belongs to a planar architecture; while in the architecture of the fin field effect transistor, the gate is a forked 3D architecture similar to a fish fin, which can control the connection and disconnection of the circuit on both sides of the circuit. This design enables the fin field effect transistor to have a stronger short channel suppression capability, which can improve circuit control and reduce leakage current, shorten the gate length of the transistor, and have a stronger working current and better electrical control of the channel.

[0003] With the further development of semiconductor technology, the size of integrated circuit devices is getting smaller and smaller, and traditional fin field effect transistors are limited in further increasing the operating current. Specifically, since only the area close to the top surface and the sidewall of the fin is used as the channel area, the volume of the fin used as the channel area is small, which limits the increase in the operating current of the fin field effect transistor. Therefore, a fin field effect transistor (GAAFinFET) with a gate-all-around (GAA) structure is proposed, which increases the volume used as the channel area, further increasing the operating current of the fin field effect transistor with a gate-all-around structure.

[0004] However, the performance of the FinFET with a trench gate-around structure in the prior art needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the performance of a fin field effect transistor with a channel gate surrounding structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate; a fin structure located on the substrate, the fin structure includes a plurality of layers of modified nanowires, and the modified nanowires have first ions therein.

[0007] Optionally, the first ions include fluorine ions, carbon ions or nitrogen ions.

[0008] Optionally, it also includes: a gate structure surrounding the modified nanowires; and a first sidewall disposed on the sidewall of the gate structure between the modified nanowires, wherein the first sidewall has first ions.

[0009] Optionally, the material of the first spacer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide and silicon oxynitride and carbonitride.

[0010] Optionally, it also includes: a second side wall located on the side wall surface of the first side wall, and the second side wall exposes the side wall surface of the modified nanowire.

[0011] Optionally, the material of the second spacer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide and silicon oxynitride and carbonitride.

[0012] Optionally, the material of the second side wall is different from that of the first side wall.

[0013] Optionally, it further includes: source-drain doped layers located on both sides of the fin structure in the extension direction; and a dielectric layer located on the substrate, wherein the source-drain doped layers and the gate structure are located in the dielectric layer.

[0014] The technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming an initial fin structure on the substrate, the initial fin structure comprising a multi-layered initial sacrificial layer and a nanowire located on the initial sacrificial layer; forming source and drain openings at both ends of the extension direction of the initial fin structure, the source and drain openings exposing the side wall surface of the initial fin structure; removing a portion of the initial sacrificial layer exposed by the source and drain openings to form a sacrificial layer, and forming a first groove on the side wall of the sacrificial layer between adjacent nanowires; forming a first sidewall material layer in the first groove and on the sidewall of the nanowire, the first sidewall material layer having first ions; annealing the first sidewall material layer to diffuse the first ions into the nanowire to form a modified nanowire, the modified nanowire having the first ions.

[0015] Optionally, after forming the modified nanowire, the method further includes: removing a portion of the first spacer material layer until the surface of the modified nanowire sidewall is exposed, and forming a first spacer in the first groove.

[0016] Optionally, the formation process of the first side wall material layer includes a chemical vapor deposition process; the parameters of the chemical vapor deposition process include: the gas includes a mixed gas of N(SiH3)3, ammonia, oxygen and silicon tetrafluoride; the total flow rate of N(SiH3)3, ammonia and oxygen includes 500 standard milliliters per minute to 3000 standard milliliters per minute, and the flow rate of silicon tetrafluoride includes 20 standard milliliters per minute to 400 standard milliliters per minute; the temperature is 200 degrees Celsius to 600 degrees Celsius; the pressure is 1 millitorr to 100 millitorr.

[0017] Optionally, the material of the first spacer material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide and silicon oxynitride and carbonitride.

[0018] Optionally, the first ions include fluorine ions, carbon ions or nitrogen ions.

[0019] Optionally, the parameters of the annealing process include: a temperature of 850 degrees Celsius to 1050 degrees Celsius; and a time of 1 second to 50 seconds.

[0020] Optionally, after forming the first sidewall, the method further includes: forming a second sidewall on the sidewall of the first sidewall, wherein the second sidewall exposes the sidewall surface of the modified nanowire.

[0021] Optionally, the material of the second sidewall spacer is different from that of the first sidewall spacer; the material of the second sidewall spacer includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide and silicon oxynitride and carbonitride.

[0022] Optionally, before forming the initial fin structure, the method further includes: forming a dummy gate structure on the substrate, wherein the dummy gate structure spans across the initial fin structure, and the source and drain openings are located on both sides of the dummy gate structure.

[0023] Optionally, after forming the modified nanowires, it also includes: forming a source-drain doping layer in the source-drain opening; after forming the source-drain doping layer, forming a dielectric layer on the substrate, the pseudo gate structure and the source-drain doping layer are located in the dielectric layer; removing the pseudo gate structure, forming a gate opening in the dielectric layer, the gate opening exposing the side wall surface of the sacrificial layer; removing the sacrificial layer to form a fin structure, the fin structure includes a number of modified nanowires; forming a gate structure in the gate opening, the gate structure surrounds the modified nanowire, and the first side wall is located on the side wall surface of the gate structure.

[0024] Optionally, after forming the modified nanowire and before forming the source-drain doping layer in the source-drain opening, it also includes: cleaning the source-drain opening, the modified nanowire side wall surface and the first side wall surface; the cleaning process includes a combination of one or more of a dry etching process and a wet etching process.

[0025] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0026] The semiconductor structure in the technical solution of the present invention has a first ion in the modified nanowire, and the first ion can form a stable chemical bond with the dangling bond on the surface of the nanowire, thereby forming a modified nanowire with a stable surface state, thereby improving the stability of the electrical properties of the semiconductor structure and further improving the reliability of the semiconductor structure.

[0027] The method for forming a semiconductor structure in the technical solution of the present invention forms a first sidewall material layer having a first ion on the sidewall of the nanowire, and then anneals the first sidewall material layer to diffuse the first ion into the nanowire to form a modified nanowire having the first ion, so that the process of doping the first ion into the nanowire is simple, thereby simplifying the process flow and improving production efficiency. The formed modified nanowire has the first ion, and the first ion can form a stable chemical bond with the dangling bond on the surface of the nanowire, thereby forming a modified nanowire with a stable surface state, thereby improving the stability of the electrical performance of the semiconductor structure, and further improving the reliability of the semiconductor structure.

[0028] Furthermore, the first ions include fluorine ions, carbon ions or nitrogen ions, and the fluorine ions, carbon ions or nitrogen ions can form stable chemical bonds with the dangling bonds on the surface of the nanowires, thereby forming modified nanowires with stable surface states, thereby improving the stability of the electrical properties of the semiconductor structure and further improving the reliability of the semiconductor structure.

[0029] Furthermore, the first side wall is formed on the side wall surface of the gate structure, and the first side wall can reduce the parasitic capacitance of the semiconductor structure, thereby improving the performance of the semiconductor structure and avoiding the gate structure directly contacting the source and drain doping layer to generate a large parasitic capacitance, thereby reducing the current of the semiconductor structure and slowing down the reaction speed of the semiconductor structure.

[0030] Furthermore, a second side wall is formed on the surface of the first side wall, and the second side wall can protect the first side wall to avoid damage to the first side wall during the cleaning process of forming the source and drain doping layer, so that the thickness of the first side wall and the second side wall can be controlled, and the degree to which the first side wall and the second side wall reduce the parasitic capacitance of the semiconductor structure can be controlled, which is beneficial to improving the uniformity of the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1is a schematic cross-sectional structure diagram of a gate-around-channel fin field effect transistor (GAAFinFET) in one embodiment;

[0032] Figures 2 to 11 It is a schematic cross-sectional structure diagram of the semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION

[0033] As described in the background art, the performance of the existing FinFET with a trench gate-around structure needs to be improved.

[0034] Figure 1 It is a schematic cross-sectional structure diagram of a fin field effect transistor with a channel gate wrap-around structure in one embodiment.

[0035] Please refer to Figure 1 The channel gate surround structure fin field effect transistor includes: a substrate 100; a nanowire 101 located on the substrate 100; a gate structure 103 surrounding the nanowire 101; a sidewall 104 located on the sidewall of the gate structure 103; a source-drain doped layer 102 located on both sides of the gate structure 103; and a dielectric layer 105 located on the substrate 100, wherein the dielectric layer 105 covers the gate structure 103 and the source-drain doped layer 102.

[0036] In the structure of the trench gate wrap-around fin field effect transistor, the material of the nanowire 101 includes single crystal silicon. Because the lattice of the single crystal silicon crystal suddenly stops growing at the surface of the nanowire 101, each atom in the outermost layer of the surface of the nanowire 101 will have an unpaired electron, thereby forming a dangling bond on the surface of the nanowire 101. The dangling bond is unstable and easily gains or loses electrons, so that the surface state of the nanowire 101 is charged, which affects the electrical performance of the trench gate wrap-around fin field effect transistor, reduces the reliability of the trench gate wrap-around fin field effect transistor, and shortens the service life of the device.

[0037] In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming a semiconductor structure, by forming an initial first sidewall with a first ion on the sidewall of a nanowire, and then annealing the initial first sidewall to diffuse the first ion into the nanowire to form a modified nanowire with the first ion, so that the process of doping the first ion into the nanowire is simple, thereby simplifying the process flow and improving production efficiency. The formed modified nanowire has the first ion, and the first ion can form a stable chemical bond with the dangling bond on the surface of the nanowire, thereby forming a modified nanowire with a stable surface state, thereby improving the stability of the electrical performance of the semiconductor structure, and further improving the reliability of the semiconductor structure.

[0038] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] Figures 2 to 11 It is a schematic cross-sectional structure diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0040] Please refer to Figure 2 , providing a substrate 200.

[0041] In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the material of the substrate includes silicon germanium, germanium, silicon on insulator or germanium on insulator.

[0042] Next, an initial fin structure is formed on the substrate 200 , wherein the initial fin structure includes multiple stacked initial sacrificial layers and nanowires located on the initial sacrificial layers.

[0043] In this embodiment, when the initial fin structure is formed on the substrate, source and drain openings are formed at both ends of the initial fin structure in an extending direction, and the source and drain openings expose the sidewall surfaces of the initial fin structure.

[0044] Please refer to Figure 3 , a fin structure material layer is formed on a substrate 200 , wherein the fin structure material layer includes a sacrificial material layer 201 stacked multiple times and a nanowire material layer 202 located on the sacrificial material layer.

[0045] The method for forming the fin structure material layer includes: forming an initial fin structure material layer on a substrate 200, the initial fin structure material layer including a multi-layered initial sacrificial material layer (not shown) and an initial nanowire material layer (not shown) located on the initial sacrificial material layer; forming a patterned mask layer (not shown) on the initial fin structure material layer; etching the initial fin structure material layer using the patterned mask layer as a mask until the surface of the substrate 200 is exposed to form the fin structure material layer.

[0046] The nanowire material layer 202 is used to form the nanowires; the sacrificial material layer 201 is used to form the initial sacrificial layer. The nanowire material layer 202 includes single crystal silicon or single crystal silicon germanium; the sacrificial material layer 201 includes single crystal silicon or single crystal silicon germanium.

[0047] In this embodiment, the material of the sacrificial material layer 201 includes silicon germanium, and the material of the nanowire material layer 202 includes single crystal silicon. The silicon germanium and single crystal silicon have a large etching selectivity, so that when the initial sacrificial layer is subsequently removed, the nanowire will not be damaged by the etching process.

[0048] After the fin structure material layer is formed, an isolation layer (not shown) is formed on the substrate 200 , and a top surface of the isolation layer is lower than or flush with a bottom surface of the fin structure material layer.

[0049] The material of the isolation layer includes silicon oxide, silicon nitride, silicon oxynitride or silicon carbide nitride. In the present embodiment, the material of the isolation layer includes silicon oxide.

[0050] Please continue to refer to Figure 3 After forming the isolation layer, a dummy gate structure is formed on the substrate 200, and the dummy gate structure spans the fin structure material layer; a third sidewall (not shown) is formed on the sidewall of the dummy gate structure.

[0051] The dummy gate structure includes a dummy gate dielectric layer (not shown) and a dummy gate layer 203 located on the dummy gate dielectric layer.

[0052] The method for forming the pseudo gate structure includes: forming a pseudo gate dielectric material layer (not shown) on the surface of the substrate 200; forming a pseudo gate material layer (not shown) on the pseudo gate dielectric material layer; forming a patterned mask layer (not shown) on the pseudo gate material layer; etching the pseudo gate material layer and the pseudo gate dielectric material layer using the patterned mask layer as a mask until the surface of the isolation layer is exposed to form the pseudo gate structure.

[0053] The material of the pseudo gate dielectric layer includes silicon oxide, low-K (less than 3.9) dielectric material or high-K (greater than 3.9) dielectric material; the material of the pseudo gate layer 203 includes polysilicon or metal; the process of forming the pseudo gate dielectric material layer includes atomic layer deposition (ALD) process or chemical vapor deposition (CVD) process, heat treatment process, etc.; the process of forming the pseudo gate material layer includes physical vapor deposition (PVD) process or atomic layer deposition (ALD) process; the process of etching the pseudo gate material layer and the pseudo gate dielectric material layer includes dry etching process or wet etching process.

[0054] In this embodiment, the material of the pseudo gate dielectric layer includes silicon oxide; the material of the pseudo gate layer 203 includes polysilicon; the process of forming the pseudo gate dielectric material layer includes an atomic layer deposition (ALD) process, and the atomic layer deposition (ALD) process can form a pseudo gate dielectric material layer with a thin thickness and a dense structure; the process of forming the pseudo gate material layer includes a physical vapor deposition (PVD) process, and the physical vapor deposition (PVD) process can form a pseudo gate material layer with a thick thickness and a dense structure; the process of etching the pseudo gate material layer and the pseudo gate dielectric material layer includes a dry etching process, and the dry etching process can form a pseudo gate structure with a better sidewall morphology.

[0055] The method for forming the third sidewall spacer includes: forming a sidewall material layer (not shown) on the substrate 200, the top surface and the sidewall surface of the dummy gate structure; etching back the sidewall material layer until the surface of the isolation layer is exposed, and forming a third sidewall spacer on the sidewall of the dummy gate structure.

[0056] The material of the third sidewall spacer includes silicon oxide, silicon nitride, silicon oxynitride or silicon carbide nitride; the process of forming the sidewall material layer includes chemical vapor deposition (CVD) process, atomic layer deposition (ALD) process or thermal treatment process, etc.

[0057] In this embodiment, the material of the third sidewall spacer includes silicon nitride, and the material of the third sidewall spacer is different from the material of the isolation layer, so that the etching of the third sidewall spacer can stop on the isolation layer; the process of forming the sidewall material layer includes a chemical vapor deposition (CVD) process.

[0058] Please refer to Figure 4 An initial fin structure is formed on the substrate 200, wherein the initial fin structure includes a multi-stacked initial sacrificial layer 205 and a nanowire 206 located on the initial sacrificial layer 205; source and drain openings 204 are formed at both ends of the initial fin structure in an extension direction, wherein the source and drain openings 204 expose the sidewall surface of the initial fin structure, and the source and drain openings 204 are located in the fin structure material layer.

[0059] In this embodiment, while the initial fin structure is formed on the substrate, source and drain openings 204 are formed at both ends of the initial fin structure in the extension direction, and the source and drain openings 204 expose the sidewall surface of the initial fin structure.

[0060] The method for forming the initial fin structure and the source-drain openings 204 includes: etching the fin structure material layer using the dummy gate structure as a mask until the surface of the substrate 200 is exposed, thereby forming the initial fin structure and the source-drain openings 204 in the fin structure material layer on both sides of the initial fin structure.

[0061] The process of etching the fin structure material layer includes a dry etching process.

[0062] Please refer to Figure 5 , removing a portion of the initial sacrificial layer 205 exposed by the source / drain openings 204 to form a sacrificial layer 305 , and forming a first groove 207 on the sidewalls of the sacrificial layer 305 between adjacent nanowires 206 and between the nanowire 206 and the substrate.

[0063] The process of removing part of the initial sacrificial layer 205 includes a combination of one or more of a dry etching process and a wet etching process.

[0064] In this embodiment, the process of removing part of the initial sacrificial layer 202 includes a wet etching process, which has a large etching selectivity ratio for the initial sacrificial layer 205 and the nanowire 206, so that the nanowire 206 can be damaged less while removing part of the initial sacrificial layer 205.

[0065] Please refer to Figure 6 A first spacer material layer 208 is formed in the first groove 207 and on the sidewall of the nanowire 206 , and the first spacer material layer 208 contains first ions.

[0066] The first ions include fluorine ions, carbon ions or nitrogen ions.

[0067] In this embodiment, the first ions include fluorine ions.

[0068] The first sidewall material layer 208 contains first ions. After subsequent annealing treatment, the first ions can diffuse into the nanowires 206 through heat to form modified nanowires containing the first ions, making the process of doping the first ions into the nanowires 206 simple, thereby simplifying the process flow and improving production efficiency.

[0069] The first ions include fluorine ions, carbon ions or nitrogen ions, and the fluorine ions, carbon ions or nitrogen ions can form stable chemical bonds with the dangling bonds on the surface of the nanowires 206, thereby forming modified nanowires with stable surface states, thereby improving the stability of the electrical properties of the semiconductor structure and further improving the reliability of the semiconductor structure.

[0070] The material of the first sidewall material layer 208 includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide and silicon nitride-carbon oxynitride; the formation process of the first sidewall material layer 208 includes a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process or a heat treatment process, etc.

[0071] In this embodiment, the material of the first side wall material layer 208 includes silicon oxide; the formation process of the first side wall material layer 208 includes a chemical vapor deposition (CVD) process, and the parameters of the chemical vapor deposition (CVD) process include: the gas includes a mixed gas of N(SiH3)3, ammonia, oxygen and silicon tetrafluoride; the total flow rate range of the N(SiH3)3, ammonia and oxygen is 500 standard milliliters per minute to 3000 standard milliliters per minute, and the flow rate range of silicon tetrafluoride is 20 standard milliliters per minute to 400 standard milliliters per minute; the temperature is 200 degrees Celsius to 600 degrees Celsius; the gas pressure is 1 millitorr to 100 millitorr.

[0072] The material of the first spacer material layer 208 includes silicon oxide, and the formation process of the silicon oxide is simple and easy to operate. It is easy to introduce a gas containing the first ion into the process gas for forming the first spacer material layer 208 to form the first spacer material layer 208 containing the first ion. The first spacer material layer 208 containing the first ion is a doping solid source for the subsequent formation of modified nanowires. Therefore, in the subsequent annealing treatment of the first spacer material layer 208, the first ion diffuses into the nanowire 206 to form the modified nanowire with the first ion, which makes the process of doping the first ion into the nanowire 206 simple, thereby simplifying the process flow and improving production efficiency.

[0073] Please refer to Figure 7 The first spacer material layer 208 is annealed to diffuse the first ions into the nanowire 206 to form a modified nanowire 306 , wherein the modified nanowire 306 has the first ions.

[0074] The process parameters of the annealing treatment include: a temperature of 850 degrees Celsius to 1050 degrees Celsius; and a time of 1 second to 50 seconds.

[0075] The annealing treatment under the temperature conditions allows the first ions to diffuse into the nanowires 206 through heat to form modified nanowires 306 having the first ions, making the process of doping the first ions into the nanowires 206 simple, thereby simplifying the process flow and improving production efficiency.

[0076] The formed modified nanowire 306 has a first ion therein, and the first ion can form a stable chemical bond with the dangling bond on the surface of the nanowire 206, thereby forming a modified nanowire 306 with a stable surface state, thereby improving the stability of the electrical performance of the semiconductor structure and further improving the reliability of the semiconductor structure.

[0077] In this embodiment, the process of forming the modified nanowires 306 includes a solid-state source doping process.

[0078] By first forming a first sidewall material layer 208 having a first ion, the first sidewall material layer 208 is a solid-state doping source having a first ion, and then annealing is performed to diffuse the first ion in the first sidewall material layer 208 into the nanowire 206 to form a modified nanowire 306 having the first ion. The process flow is simple and the work efficiency is improved. At the same time, the first ion in the nanowire 206 is distributed more evenly through thermal diffusion movement, which can react with the dangling bonds on the surface of the nanowire 206 to the maximum extent to form stable chemical bonds, thereby improving the performance of the semiconductor structure.

[0079] In other embodiments, the process of forming the modified nanowires includes an ion implantation process.

[0080] Please refer to Figure 8 After the modified nanowire 306 is formed, a portion of the first spacer material layer 208 is removed until the sidewall surface of the modified nanowire 306 is exposed, and a first spacer 209 is formed in the first groove 207 .

[0081] The method for removing part of the first side wall material layer 208 includes: etching back the first side wall material layer 208 until the surface of the substrate 200 is exposed, and forming an initial first side wall (not shown) in the first groove 207 and the side wall of the modified nanowire 306; etching the side wall of the initial first side wall until the side wall surface of the modified nanowire 306 is exposed, and forming a first side wall 209 in the first groove 207.

[0082] The process of etching the sidewall of the initial first sidewall includes an isotropic dry etching process, and the isotropic dry etching process can etch the initial first sidewall along a direction perpendicular to the sidewall of the initial first sidewall to form a first sidewall 209 with uniform thickness in the first groove 207.

[0083] The parameters of the isotropic dry etching process include: the etching gas is a mixed gas of monofluoromethane, nitrogen and oxygen; the flow range of monofluoromethane is 8 standard ml / min to 100 standard ml / min, the flow range of nitrogen is 80 standard ml / min to 200 standard ml / min, and the flow range of oxygen is 10 standard ml / min to 50 standard ml / min; the RF source power is 100 W to 300 W; the cavity gas pressure is 10 mTorr to 200 mTorr; and the DC bias is 0.

[0084] In this embodiment, the side wall surface of the modified nanowire 306 protrudes relatively from the side wall surface of the first side wall 209, and a second groove 210 is provided between the side wall of the first side wall 209 and the adjacent modified nanowire 306, and between the first side wall 209 and the adjacent modified nanowire 306 and the substrate. The second groove 210 is used to subsequently form a second side wall in the second groove 210.

[0085] The first sidewall 209 formed is located on the sidewall surface of the sacrificial layer 305. After the sacrificial layer 305 is subsequently removed, a gate structure surrounding the modified nanowire 306 is formed. The first sidewall 209 is located on the sidewall surface of the gate structure portion, so that the first sidewall 209 can reduce the parasitic capacitance of the semiconductor structure, thereby improving the performance of the semiconductor structure and avoiding the subsequent gate structure directly contacting the source and drain doping layers to generate a large parasitic capacitance, thereby reducing the current of the semiconductor structure and slowing down the reaction speed of the semiconductor structure.

[0086] In other embodiments, the sidewall surface of the modified nanowire is flush with the sidewall surface of the first sidewall, and the second sidewall may not be formed on the sidewall surface of the first sidewall.

[0087] Please refer to Fig. 9 A second sidewall 211 is formed in the second groove 210 on the sidewall of the first sidewall 209 , and the second sidewall 211 exposes the sidewall surface of the modified nanowire 306 .

[0088] The method for forming the second sidewall 211 includes: forming a second sidewall material layer (not shown) in the second groove 210 and on the sidewall surface of the modified nanowire 306; etching back the second sidewall material layer until the surface of the substrate 200 is exposed, and forming an initial second sidewall (not shown) in the second groove 210 and on the sidewall surface of the modified nanowire 306; etching the sidewall of the initial second sidewall until the sidewall surface of the modified nanowire 306 is exposed, and forming a second sidewall 211 in the second groove 210 on the side wall of the first sidewall 209.

[0089] The process of forming the second spacer material layer includes a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. In this embodiment, the process of forming the second spacer material layer includes a chemical vapor deposition (CVD) process.

[0090] The process of etching the sidewall of the initial second sidewall includes an isotropic dry etching process, and the isotropic dry etching process can etch the initial second sidewall along a direction perpendicular to the sidewall of the initial second sidewall to form a second sidewall 211 with uniform thickness in the second groove 210.

[0091] The second sidewall 211 and the first sidewall 209 are made of different materials.

[0092] The material of the second spacer 211 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide and silicon oxynitride and carbonitride.

[0093] In this embodiment, the material of the second sidewall spacer 211 includes silicon nitride.

[0094] A second side wall 211 is formed on the side wall surface of the first side wall 209. The second side wall 211 can protect the first side wall 209 and prevent the first side wall 209 from being damaged during the cleaning process of forming the source and drain doping layer. This makes the thickness of the first side wall 209 and the second side wall 211 controllable, and the degree to which the first side wall 209 and the second side wall 211 reduce the parasitic capacitance of the semiconductor structure is controllable, which is beneficial to improving the uniformity of the performance of the semiconductor structure.

[0095] Please continue to refer to Fig. 9 After forming the first sidewall 209 and the second sidewall 211 , the source / drain opening 204 , the sidewall surface of the modified nanowire 306 , and the sidewall surface of the second sidewall 211 are cleaned.

[0096] The cleaning process is to prepare for the subsequent formation of source-drain doping layers in the source-drain openings 204. The cleaning process can remove the natural oxide layer formed on the inner wall surface of the source-drain openings 204 and the side wall surface of the modified nanowires 306 after contacting oxygen during the process flow, so that when the source-drain doping layers are subsequently formed by the epitaxial growth process, the seed layer of the epitaxial growth process can grow on the inner wall surface of the source-drain openings 204 and the side wall surface of the modified nanowires 306, avoiding the situation where the formed source-drain doping layers are blocked by the natural oxide layer and have poor contact with the modified nanowires 306, affecting the performance of the semiconductor structure.

[0097] The cleaning process includes a combination of one or more of a dry etching process and a wet etching process.

[0098] In this embodiment, the cleaning process includes a dry etching process.

[0099] The process parameters of the dry etching process include: the gas includes a mixed gas of helium, ammonia and nitrogen trifluoride; the flow range of the helium is 600 standard milliliters per minute to 2000 standard milliliters per minute, the flow range of the ammonia is 100 standard milliliters per minute to 500 standard milliliters per minute, and the flow range of the nitrogen trifluoride is 20 standard milliliters per minute to 300 standard milliliters per minute; the gas pressure is 2 torr to 100 torr.

[0100] In other embodiments, the cleaning process includes a wet etching process, and an etching solution of the wet etching process includes hydrogen fluoride.

[0101] Please refer to Fig.10 , a source-drain doping layer 212 is formed in the source-drain opening 204 ; after the source-drain doping layer 212 is formed, a dielectric layer 213 is formed on the substrate 200 , and the dummy gate structure and the source-drain doping layer 212 are located in the dielectric layer 213 .

[0102] The process of forming the source-drain doping layer 212 in the source-drain opening 204 includes an epitaxial growth process.

[0103] When the semiconductor structure is of N type, the material of the source-drain doping layer 212 includes phosphorus silicon; when the semiconductor structure is of P type, the material of the source-drain doping layer 212 includes silicon germanium.

[0104] The method for forming the dielectric layer 213 includes: forming a dielectric material layer (not shown) on the substrate; and planarizing the dielectric material layer until the top surface of the dummy gate structure is exposed to form the dielectric layer 213 .

[0105] The process of forming the dielectric material layer includes a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process; the material of the dielectric layer 213 includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide and silicon oxynitride and carbonitride.

[0106] In this embodiment, the process of forming the dielectric material layer includes a chemical vapor deposition (CVD) process, and the chemical vapor deposition (CVD) process can quickly form a dielectric material layer with a relatively thick thickness and a dense structure; the material of the dielectric layer 213 includes silicon oxide.

[0107] Please refer to Fig.11 , remove the pseudo gate structure, form a gate opening (not shown) in the dielectric layer 213, the gate opening exposes the side wall surface of the sacrificial layer 305; remove the sacrificial layer 305 to form a fin structure, the fin structure includes a plurality of modified nanowires 306; form a gate structure in the gate opening, the gate structure surrounds the modified nanowires, and the first sidewall 209 is located on the side wall surface of the gate structure.

[0108] The gate structure includes a gate dielectric layer (not shown), a work function layer (not shown) located on the gate dielectric layer, and a gate layer 214 located on the work function layer.

[0109] In other embodiments, the gate structure may not include the work function layer.

[0110] The material of the gate dielectric layer includes a high-K (greater than 3.9) dielectric material, and the high-K dielectric material includes hafnium oxide or aluminum oxide; the material of the work function layer includes a P-type work function material or an N-type work function material, and the P-type work function material includes titanium nitride or tantalum nitride, and the N-type work function material includes titanium aluminum; the material of the gate layer 214 includes a metal, and the metal includes copper or tungsten.

[0111] In this embodiment, the material of the gate dielectric layer includes hafnium oxide; the material of the gate layer 214 includes tungsten.

[0112] At this point, the semiconductor structure is formed, and the modified nanowire 306 has a first ion, which can form a stable chemical bond with the dangling bond on the surface of the nanowire, thereby forming a modified nanowire 306 with a stable surface state, thereby improving the stability of the electrical performance of the semiconductor structure, and further improving the reliability of the semiconductor structure.

[0113] The present invention also provides a semiconductor structure. Fig.11 ,include:

[0114] Substrate 200;

[0115] The fin structure is located on the substrate 200 , and the fin structure includes a plurality of modified nanowires 306 . The modified nanowires 306 have first ions therein.

[0116] In this embodiment, the first ions include fluorine ions, carbon ions or nitrogen ions.

[0117] In this embodiment, the present invention further includes: a gate structure surrounding the modified nanowires 306 ; and a first sidewall spacer 209 located on the sidewall of the gate structure between the modified nanowires 306 , wherein the first sidewall spacer 209 has first ions.

[0118] In this embodiment, the material of the first spacer 209 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon oxynitride and carbonitride.

[0119] In this embodiment, the present invention further includes: a second sidewall 211 located on the sidewall surface of the first sidewall 209 , wherein the second sidewall 211 exposes the sidewall surface of the modified nanowire 306 .

[0120] In this embodiment, the material of the second spacer 211 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon oxynitride and carbonitride.

[0121] In this embodiment, the material of the second sidewall 211 is different from the material of the first sidewall 209 .

[0122] In this embodiment, it also includes: source-drain doped layers 212 located on both sides of the fin structure in the extension direction; and a dielectric layer 213 located on the substrate 200 , wherein the source-drain doped layers 212 and the gate structure are located in the dielectric layer 213 .

[0123] The semiconductor structure has a first ion in the modified nanowire 306, and the first ion can form a stable chemical bond with the dangling bond on the surface of the nanowire, thereby forming a modified nanowire 306 with a stable surface state, thereby improving the stability of the electrical performance of the semiconductor structure and further improving the reliability of the semiconductor structure.

[0124] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming an initial fin structure on the substrate, wherein the initial fin structure includes a multi-stacked initial sacrificial layer and a nanowire located on the initial sacrificial layer; forming source and drain openings at two ends of the initial fin structure in an extending direction, wherein the source and drain openings expose sidewall surfaces of the initial fin structure; Removing a portion of the initial sacrificial layer exposed by the source / drain openings to form a sacrificial layer, and forming a first groove on the sidewall of the sacrificial layer between adjacent nanowires; forming a first spacer material layer in the first groove and on the sidewall of the nanowire, wherein the first spacer material layer has first ions, and the first ions include carbon ions or nitrogen ions; Annealing the first spacer material layer to diffuse the first ions into the nanowires to form modified nanowires, wherein the modified nanowires contain the first ions; A portion of the first sidewall material layer is removed until the surface of the modified nanowire sidewall is exposed, thereby forming a first sidewall in the first groove.

2. The method for forming a semiconductor structure according to claim 1, wherein: The formation process of the first side wall material layer includes a chemical vapor deposition process; the parameters of the chemical vapor deposition process include: the gas includes a mixed gas of N(SiH3)3, ammonia, oxygen and silicon tetrafluoride; the total flow rate of N(SiH3)3, ammonia and oxygen includes 500 standard milliliters per minute to 3000 standard milliliters per minute, and the flow rate of silicon tetrafluoride includes 20 standard milliliters per minute to 400 standard milliliters per minute; the temperature is 200 degrees Celsius to 600 degrees Celsius; the pressure is 1 millitorr to 100 millitorr.

3. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first spacer material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide and silicon oxynitride and carbonitride.

4. The method for forming a semiconductor structure according to claim 1, wherein: The first ions also include fluoride ions.

5. The method for forming a semiconductor structure according to claim 1, wherein: The parameters of the annealing process include: a temperature of 850 degrees Celsius to 1050 degrees Celsius; and a time of 1 second to 50 seconds.

6. The method for forming a semiconductor structure according to claim 1, wherein: After forming the first sidewall spacer, the method further includes: forming a second sidewall spacer on the sidewall of the first sidewall spacer, wherein the second sidewall spacer exposes the sidewall surface of the modified nanowire.

7. The method for forming a semiconductor structure according to claim 6, wherein: The material of the second sidewall spacer is different from that of the first sidewall spacer; the material of the second sidewall spacer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide and silicon oxynitride and carbonitride.

8. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the initial fin structure, the method further includes: forming a dummy gate structure on the substrate, wherein the dummy gate structure spans across the initial fin structure, and the source and drain openings are located on both sides of the dummy gate structure.

9. The method for forming a semiconductor structure according to claim 8, wherein: After the modified nanowires are formed, the method further includes: forming a source-drain doping layer in the source-drain opening; after the source-drain doping layer is formed, forming a dielectric layer on the substrate, wherein the pseudo gate structure and the source-drain doping layer are located in the dielectric layer; removing the pseudo gate structure, forming a gate opening in the dielectric layer, wherein the gate opening exposes the side wall surface of the sacrificial layer; removing the sacrificial layer, forming a fin structure, wherein the fin structure includes a plurality of modified nanowires; forming a gate structure in the gate opening, wherein the gate structure surrounds the modified nanowire, and wherein the first side wall is located on the side wall surface of the gate structure.

10. The method for forming a semiconductor structure according to claim 9, wherein: After forming the modified nanowires and before forming the source-drain doping layer in the source-drain openings, the method further includes: cleaning the source-drain openings, the modified nanowire sidewall surfaces and the first sidewall surface; the cleaning process includes a combination of one or more dry etching processes and wet etching processes.

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