Semiconductor device and method for manufacturing the same

Abstract

Disclosed are the structure of a semiconductor device having a passivation layer on an active region of a FET device and a method for manufacturing the semiconductor device. The semiconductor device includes a substrate, a first and a second source / drain (S / D) region disposed on the substrate, a channel region of a nanostructure disposed between the first and second S / D regions, a passivation layer, and a nanosheet (NS) structure wrapping the channel region of the nanostructure. Each S / D region has a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of the first and second semiconductor layers. A first portion of the passivation layer is disposed between the epitaxial region and the stack of the first and second semiconductor layers, and a second portion of the passivation layer is disposed on the sidewall of the channel region of the nanostructure. Embodiments of the present invention also relate to semiconductor devices and methods for manufacturing the same.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] As semiconductor technology advances, the demand for higher storage capacity, faster processing systems, and higher performance continues to grow. To meet these demands, the semiconductor industry continues to scale down the size of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs and fin field effect transistors (finFETs). This scaling down has increased the complexity of semiconductor manufacturing processes. Summary of the invention

[0003] An embodiment of the present invention provides a semiconductor device, comprising: a substrate; a first source / drain (S / D) region and a second source / drain (S / D) region, which are arranged on the substrate, wherein each of the first source / drain region and the second source / drain region includes a stack of first semiconductor layers and second semiconductor layers arranged in an alternating configuration, and an epitaxial region arranged on the stack of the first semiconductor layers and the second semiconductor layers; a channel region of a nanostructure, which is arranged between the first source / drain region and the second source / drain region; a passivation layer, wherein a first portion of the passivation layer is arranged between the epitaxial region and the stack of the first semiconductor layer and the second semiconductor layer, and a second portion of the passivation layer is arranged on the sidewall of the channel region of the nanostructure; and a nanosheet (NS) structure, which wraps the channel region of the nanostructure.

[0004] Another embodiment of the present invention provides a semiconductor device, comprising:

[0005] A first field effect transistor (FET) comprises: a first fin structure arranged on a substrate, a first passivation layer wrapping the fin structure, and a first epitaxial region of a first conductivity type arranged on the first passivation layer; and a second field effect transistor comprises: a second fin structure arranged on the substrate adjacent to the first fin structure, a second passivation layer wrapping the second fin structure, and a second epitaxial region of a second conductivity type arranged on the second passivation layer, wherein the first conductivity type and the second conductivity type are different from each other.

[0006] Another embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: forming a fin structure, the fin structure having a stack of a first semiconductor layer and a second semiconductor layer arranged in an alternating configuration on a substrate; depositing a passivation layer on the fin structure and the substrate; forming an epitaxial region on a first portion of the fin structure; forming a channel region of a nanostructure in a second portion of the fin structure; and forming a nanosheet (NS) structure wrapping the channel region of the nanostructure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1A and Figures 1B to 1D An isometric view and a cross-sectional view are respectively shown of a semiconductor device having a passivation layer according to some embodiments.

[0009] Figure 1E and Figure 1F to Figure 1G An isometric view and a cross-sectional view are respectively shown of a semiconductor device having a passivation layer according to some embodiments.

[0010] FIG. 2A to FIG. 2H Cross-sectional views illustrating different configurations of a channel region of a semiconductor device having a passivation layer according to some embodiments.

[0011] Figure 3 is a flow chart of a method for fabricating a semiconductor device having a passivation layer according to some embodiments.

[0012] FIG. 4A to FIG. 13A Isometric views of a semiconductor device with a passivation layer at various stages of its fabrication process are shown in accordance with some embodiments.

[0013] FIG. 4B to FIG. 13B Cross-sectional views of a semiconductor device having a passivation layer at various stages of its manufacturing process are shown according to some embodiments.

[0014] Exemplary embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. As used herein, forming a first component on a second component means that the first component is formed to be in direct contact with the second component. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or process of operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0017] Note that references in the specification to "one embodiment," "an embodiment," "an example embodiment," "exemplary," etc. indicate that the described embodiment may include a particular component, structure, or characteristic, but not every embodiment necessarily includes the particular component, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular component, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of those skilled in the art to implement such component, structure, or characteristic in conjunction with other embodiments.

[0018] It should be understood that the phraseology or terminology herein is for the purpose of description rather than limitation, so that the phraseology or terminology of this specification will be interpreted by those skilled in the relevant art based on the teachings herein.

[0019] As used herein, the term "etch selectivity" refers to the ratio of the etching rates of two different materials under the same etching conditions.

[0020] As used herein, the term "deposition selectivity" refers to the ratio of deposition rates on two different materials or surfaces under the same deposition conditions.

[0021] As used herein, the term "high-k" refers to a high dielectric constant. In the field of semiconductor device structure and manufacturing process, high-k refers to a dielectric constant greater than the dielectric constant of SiO2 (eg, greater than 3.9).

[0022] As used herein, the term "p-type" defines a structure, layer, and / or region as being doped with a p-type dopant, such as boron.

[0023] As used herein, the term "n-type" defines a structure, layer, and / or region as being doped with an n-type dopant, such as phosphorus.

[0024] In some embodiments, the terms "about" and "substantially" may indicate a value of a given quantity that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). Of course, these values ​​are merely examples and are not intended to be limiting. It should be understood that the terms "about" and "substantially" may refer to a percentage of a value as interpreted by a person skilled in the relevant art in accordance with the teachings herein.

[0025] The fin structures disclosed herein can be patterned by any suitable method. For example, the fin structure can be patterned using one or more photolithography processes, including a double patterning process or a multiple patterning process. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, allowing the creation of patterns having, for example, a pitch that is smaller than that obtainable using a single direct photolithography process. For example, in some embodiments, a sacrificial layer is formed above a substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin structure.

[0026] The present invention provides example structures and methods for reducing resistance in active regions (e.g., channel regions and / or source / drain regions) of FET devices (e.g., finFETs, all-around gate FETs, MOSFETs, etc.) Reducing resistance in the active regions can increase the drive current of the FET device, thereby resulting in improved FET device performance.

[0027] Example structures and methods provide a passivation layer on the active area of ​​a FET device to improve the surface quality of the active area. The surface quality can be improved by reducing surface defects with a passivation layer. The surface defects on the active area can be in the form of vacancies caused by dangling bonds on the surface of the active area. Vacancies can capture charge carriers that travel through the active area of ​​the FET device during operation and reduce the drive current of the FET device. The passivation layer can react with these dangling bonds to reduce or eliminate the surface defects caused by dangling bonds on the active area. Compared with the drive current of FET devices without such passivation layers on their active areas, eliminating such surface defects on the active area of ​​FET devices with the passivation layer disclosed herein can increase the drive current of the FET device by, for example, about 20% to about 50%. In some embodiments, the passivation layer may include fluorine, nitrogen, hydrogen and / or chlorine atoms that can react with dangling bonds on the surface of the active area to reduce or eliminate defects caused by vacancies on the surface of the active area.

[0028] According to some embodiments, reference Figures 1A to 1D A semiconductor device 100 having FETs 102A- 102B is depicted. Figure 1A An isometric view of a semiconductor device 100 is shown in accordance with some embodiments. Figures 1B to 1D The following diagrams are respectively shown according to some embodiments. Figure 1A BB, CC and DD of the semiconductor device 100. In some embodiments, the FETs 102A-102B may all be p-type FETs (PFETs) or all be n-type FETs (NFETs) or one of each conductivity type. Figures 1A to 1D Two FETs are discussed, and semiconductor device 100 may have any number of FETs. Discussions of elements of FETs 102A-102B with the same annotations apply to each other unless otherwise noted. Isometric and cross-sectional views of semiconductor device 100 are shown for illustration purposes and may not be drawn to scale.

[0029] refer to Figures 1A to 1DFETs 102A-102B may be formed on substrate 106. Substrate 106 may be a semiconductor material such as, but not limited to, silicon. In some embodiments, substrate 106 may include a crystalline silicon substrate (e.g., a wafer). In some embodiments, substrate 106 may include (i) an elemental semiconductor such as germanium (Ge); (ii) a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or a III-V semiconductor material; (iii) an alloy semiconductor including silicon germanium (SiGe), silicon germanium carbide, germanium tin, silicon germanium tin, gallium arsenide phosphide, gallium indium phosphide, gallium indium arsenide, gallium indium arsenide phosphide, aluminum indium arsenide, and / or aluminum gallium arsenide; (iv) a silicon on insulator (SOI) structure; (v) a silicon germanium (SiGe) on insulator structure (SiGeOI); (vi) a germanium on insulator (GeOI) structure; or (vii) a combination thereof. In addition, substrate 106 may be doped (e.g., a p-type substrate or an n-type substrate) according to design requirements. In some embodiments, substrate 106 may be doped with a p-type dopant (eg, boron, indium, aluminum, or gallium) or an n-type dopant (eg, phosphorus or arsenic).

[0030] The FETs 102A-102B may include a fin structure 108A-108B disposed on a substrate 106, a passivation layer 109A-109B disposed on the fin structure 108A-108B, an epitaxial fin region 110A-110B disposed on the passivation layer 109A-109B, a gate structure 112A-112B (also referred to as a gate-all-around (GAA) structure 112A-112B or a nanosheet (NS) structure 112A-112B) disposed on a portion of the fin structure 108A-108B not covered by the epitaxial fin region 110A-110B, and spacers 114A-114B disposed on the passivation layer 109A-109B and the gate structure 112A-112B, respectively.

[0031] like Figure 1C to Figure 1DAs shown, the fin structures 108A-108B may include fin base portions 108A1-108B1 and fin top portions 108A2-108B2 respectively disposed on the fin base portions 108A1-108B1. In some embodiments, the fin base portions 108A1-108B1 may include a material similar to the substrate 106. The fin base portions 108A1-108B1 may be formed by photolithographic patterning and etching of the substrate 106. The fin top portions 108A2-108B2 may include first semiconductor layers 120 and second semiconductor layers 122 stacked in an alternating configuration. Each first semiconductor layer 120 may have (i) a first fin region 120A located below the epitaxial fin regions 110A-110B, and (ii) a second fin region 120B located in the FET 102A below the gate structure 112A and in the FET 102B before being etched to form the gate structure 112B ( Figures 1A to 1D Not shown in; Figure 5A Similarly, each second semiconductor layer 122 may have (i) a first fin region 122A located below the epitaxial fin regions 110A-110B, and (ii) a second fin region 122B located in the FET 102A below the gate structure 112B and in the FET 102A before being etched to form the gate structure 112A. Figures 1A to 1D Not shown in; Figure 5A As shown in Figure 2), as described in further detail below. Figures 1B to 1D As shown, after forming the gate structures 112A- 112B, the second fin regions 120B and 122B may be referred to as channel regions 120B and 122B of the nanostructures of the FETs 102A- 102B, respectively.

[0032] The first and second semiconductor layers 120 and 122 may be epitaxially grown and may include semiconductor materials that are different from each other. In some embodiments, the first and second semiconductor layers 120 and 122 may include semiconductor materials having oxidation rates and / or etching selectivities that are different from each other. In some embodiments, the first and second semiconductor layers 120 and 122 may include semiconductor materials that are similar to or different from the substrate 106. The first and second semiconductor layers 120 and 122 may include (i) elemental semiconductors such as silicon or germanium; and (ii) compound semiconductors containing III-V semiconductor materials; (iii) alloy semiconductors including SiGe, germanium tin, or silicon germanium tin; or (iv) combinations thereof. In some embodiments, the first semiconductor layer 120 may include Si for the n-type FET 102A and SiGe for the p-type FET 102B, or the first semiconductor layer 120 may include SiGe for the p-type FET 102A and Si for the n-type FET 102B if the semiconductor device 100 is a complementary metal oxide semiconductor (CMOS) device. In some embodiments, both the first semiconductor layer 120 and the second semiconductor layer 122 may include Si for n-type FETs 102A-102B or SiGe for p-type FETs 102A-102B. In some embodiments, the first semiconductor layer 120 and the second semiconductor layer 122 may include SiGe with Ge in a range from about 25 atomic percent to about 50 atomic percent, with any remaining atomic percent being Si, or may include Si without any substantial amount of Ge. The semiconductor materials of the first and / or second semiconductor layers 120 and 122 may be undoped or may be in-situ doped during their epitaxial growth process using the following dopants: (i) p-type dopants, such as boron, indium, or gallium; and / or (ii) n-type dopants, such as phosphorus or arsenic.

[0033] refer to Figure 1B , the corresponding vertical dimensions H1 and H2 (e.g., thickness or diameter) of the channel regions 120B and 122B of the nanostructures along the Z axis may be in the range of about 5 nm to about 30 nm, and the corresponding horizontal dimensions W1 and W2 (e.g., width or diameter) along the Y axis may be in the range of about 5 nm to about 30 nm. The ratios of H1 / W1 and H2 / W2 may be in the range of about 0.2 to about 5. Although the rectangular cross-sections of the channel regions 120B and 122B of the nanostructures are Figure 1B , but the channel regions 120B and 122B of the nanostructures may have cross-sections of other geometric shapes (e.g., circular, elliptical, triangular, or polygonal). In addition, the channel regions 120B and 122B of the nanostructures may have respective horizontal dimensions L1 ( L1 ) in the range of about 10 nm to about 100 nm along the X-axis. Figure 1D ) and L2( Figure 1C). The ratio of L1 / H1 and L2 / H2 can be in the range of about 2 to about 20. In some embodiments, the dimensions H1 and H2, W1 and W2, and L1 and L2 can be equal to or different from each other. In some embodiments, the ratio of H1 / W1 and H2 / W2 and the ratio of L1 / H1 and L2 / H2 can be equal to or different from each other.

[0034] In some embodiments, the fin base portions 108A1-108B1 and the fin top portions 108A2-108B2 may have a vertical dimension (e.g., height) along the Z-axis, each ranging from about 40 nm to about 60 nm. The vertical dimensions of the fin base portions 108A1-108B1 and the fin top portions 108A2-108B2 may be equal to or different from each other, and may have values ​​such that the total height of the fin structures 108A-108B, respectively, ranges from about 80 nm to about 120 nm.

[0035] refer to Figures 1A to 1D , the passivation layers 109A-109B may be disposed on the surfaces of the fin top portions 108A2-108B2 below the epitaxial fin regions 110A-110B, respectively, and on the side surfaces of the fin base portions 108A1-108B1, respectively. In addition, the passivation layers 109A-109B may be disposed on the side surfaces of the channel regions 120B and 122B of the nanostructures, respectively. In some embodiments, the passivation layer 109A may be disposed on the top surface of the topmost first semiconductor layer 120, such as Figure 1D As shown, the passivation layer 109B may be disposed on the top surface of the topmost fin region 120A, as shown in FIG. Figure 1C As shown. The passivation layers 109A-109B can improve the surface quality of the surfaces covered by these passivation layers of the fin structures 108A-108B by reducing or eliminating vacancies caused by dangling bonds on these surfaces. The vacancies can trap charge carriers and reduce the drive current of the FETs 102A-102B during their operation. Reducing or eliminating these vacancies can increase the drive current of the FETs 102A-102B by about 20% to about 50% compared to FETs without passivation layers such as the passivation layers 109A-109B.

[0036] In some embodiments, the passivation layers 109A-109B may be nitride, oxide, fluoride, chloride, and / or sulfide films. In some embodiments, the passivation layers 109A-109B may include fluorine, chlorine, nitrogen, oxygen, hydrogen, deuterium, and / or sulfur atoms that may bond with dangling bonds to reduce or eliminate vacancies on the above-mentioned surfaces of the fin structures 108A-108B. The passivation layers 109A-109B may be substantially conformally deposited on these surfaces of the fin structures 108A-108B and may have a thickness in a range of about 5 angstroms to about 5 nm.

[0037] refer to Figure 1A and Figure 1C to Figure 1D , epitaxial fin regions 110A-110B may be grown on regions of fin top portions 108A2-108B2 that are not below gate structures 112A-112B, respectively. Figure 1E to Figure 1G As shown, epitaxial fin regions 110B-110A may be epitaxially grown on fin base portions 108B1-108A1 after removing fin top portions 108B2-108A2 that are not under gate structures 112B-112A. Epitaxial fin regions 110A-110B may include epitaxially grown semiconductor materials that are similar to or different from each other. In some embodiments, the epitaxially grown semiconductor material may include the same material as or a different material from that of substrate 106. The thickness of epitaxial fin regions 110A-110B along side surfaces of fin top portions 108A2-108B2 may be in a range of about 3 nm to about 6 nm. Although in Figure 1C and Figure 1D , the epitaxial fin regions 110A- 110B are shown to have triangular cross-sections, and the epitaxial fin regions 110A- 110B may have cross-sections of other geometric shapes (eg, rectangular, semicircular, or polygonal).

[0038] The epitaxial fin regions 110A-110B may be p-type or n-type for PFETs 102A-102B or NFETs 102A-102B, respectively. In some embodiments, the epitaxial fin regions 110A-110B of the respective FETs 102A-102B may be the same or opposite doping type with respect to each other.

[0039] The P-type epitaxial fin regions 110A-110B may include SiGe, SiGeB, GeB, SiGeSnB, III-V semiconductor compounds, or combinations thereof, and the dopant concentration is about 1×10 20 Atom / cm 3 About 1x10 21 Atom / cm 3In some embodiments, each p-type epitaxial fin region 110A-110B may have multiple sub-regions (not shown), which may include SiGe and may be different from each other based on, for example, doping concentration, epitaxial growth process conditions, and / or relative concentrations of Ge relative to Si. Each sub-region may have a thickness that is similar or different from each other, and the thickness may be in the range of about 0.5nm to about 5nm. In some embodiments, the Ge atomic percentage in the sub-region closest to the fin top portion 108A2-108B2 may be less than the Ge atomic percentage in the sub-region farthest from the fin top portion 108A2-108B2. In some embodiments, the sub-region closest to the fin top portion 108A2-108B2 may include about 15 atomic percent to about 35 atomic percent Ge, while the sub-region farthest from the fin top portion 108A2-108B2 may include about 25 atomic percent to about 50 atomic percent Ge. The remaining atomic percentages in the sub-regions are Si.

[0040] According to some embodiments, multiple sub-regions of the p-type epitaxial fin regions 110A-110B may have different p-type dopant concentrations relative to each other. For example, the sub-region closest to the fin top portion 108A2-108B2 may be undoped or may have a dopant concentration (e.g., about 1×10 20 Atom / cm 3 To about 3x10 22 atom / atom / cm 3 The dopant concentration is within the range of ) and the dopant concentration is low (for example, the dopant concentration is less than about 8×10 20 Atom / cm 3 ).

[0041] In some embodiments, the n-type epitaxial fin regions 110A-110B may have multiple n-type sub-regions (not shown). The first n-type sub-region closest to the fin top portion 108A2-108B2 may have the following materials: SiAs, SiC, or SiCP, with a dopant concentration ranging from about 1×10 20 Atom / cm 3 To about 1x10 21 Atom / cm 3 and a thickness in the range of about 1 nm to about 3 nm. The second n-type sub-region disposed on the first n-type sub-region may have a material with SiP and a dopant concentration in the range of about 1×10 20 Atom / cm 3 About 1x10 22 Atom / cm 3The third n-type sub-region disposed on the second n-type sub-region may have a material with a similar material composition and thickness as the first n-type sub-region. Other materials, thicknesses, and dopant concentrations of the plurality of n-type and / or p-type sub-regions are within the scope and spirit of the present invention.

[0042] The epitaxial fin regions 110A-110B together with the first fin regions 120A and 122A thereunder may form source / drain (S / D) regions of the FETs 102A-102B. The nanostructured channel regions 120B and 122B may be respectively disposed between a pair of S / D regions of the FETs 102A-102B. Figure 1C to Figure 1D shown.

[0043] refer to Figures 1B to 1D , the gate structures 112A-112B may be multi-layer structures and may be disposed on the top surface and sidewall areas of the fin top portions 108A2-108B2 that are not covered by the epitaxial fin regions 110A-110B. In some embodiments, the channel regions 120B and 122B of each nanostructure may wrap around the gate structures 112A-112B, respectively, or wrap around one or more layers of the gate structures 112A-112B, respectively, for which the gate structures 112A-112B may be referred to as full-all-around gate (GAA) structures or horizontal full-all-around gate (HGAA) structures, and the FETs 102A-102B may be referred to as GAA FETs 102A-102B. The spacing 111 between the gate structures 112A-112B is not drawn to scale, and the gate structures 112A-112B may be separated from each other by any distance. In some embodiments, similar to gate structures 112A- 112B, FETs 102A- 102B may have a common gate structure disposed on fin top portions 108A2 - 108B2 .

[0044] The gate structures 112A-112B may include gate dielectric layers 128A-128B, gate work function metal layers 130A-130B, and gate metal filling layers 132A-132B, respectively. Figure 1BAs shown, the gate dielectric layer 128A may wrap the channel region 120B of each nanostructure to fill the space between the channel regions 120B of adjacent nanostructures, thereby electrically isolating the channel regions 120B of the nanostructures from each other and from the conductive gate work function metal layer 130A and the gate metal filling layer 132A to prevent short circuits between the gate structure 112A and the S / D regions of the FET 102A during operation. Similarly, the gate dielectric layer 128B may wrap the channel region 122B of each nanostructure to fill the space between the channel regions 122B of adjacent nanostructures, and electrically isolate the channel regions 122B of the nanostructures from each other and from the conductive gate work function metal layer 130B and the gate metal filling layer 132B to prevent short circuits between the gate structure 112B and the S / D regions 102B of the FET 102B during operation.

[0045] Each gate dielectric layer 128A-128B may have a thickness in the range of about 1 nm to about 5 nm and may include (i) a layer of silicon oxide, silicon nitride, and / or silicon oxynitride, (ii) a high-k dielectric material such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), zirconium silicate (ZrSiO2), (ii) a dielectric layer of ... i) an oxide of lithium (Li), beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), scandium (Sc), yttrium (Y), zirconium (Zr), aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) or lutetium (Lu), or (iv) a combination thereof.

[0046] like Figure 1BAs shown, one or more of the nanostructured channel regions 120B and 122B may wrap the work function metal layers 130A-130B and the gate metal filling layers 132A-132B. The gate work function metal layers 130A-130B may include a single metal layer or a stack of metal layers. The stack of metal layers may include metals with work function values ​​equal to or different from each other. In some embodiments, each gate work function metal layer 130A-130B may include aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), silver (Ag), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tantalum carbon nitride (TaCN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN, tungsten nitride (WN), metal alloys and / or combinations thereof. In some embodiments, each gate work function metal layer 130A-130B may include an Al-doped metal, such as Al-doped Ti, Al-doped TiN, Al-doped Ta, or Al-doped TaN. In some embodiments, the thickness of each gate work function metal layer 130A-130B may be in the range of about 2 nm to about 15 nm.

[0047] In some embodiments, a gate barrier layer (not shown) may be disposed between the gate dielectric layers 128A-128B and the gate work function metal layers 130A-130B, respectively. The gate barrier layer may be used as a nucleation layer for the subsequent formation of the gate work function metal layers 130A-130B and / or may help prevent a large amount of metal (e.g., Al) from the gate work function metal layers 130A-130B from diffusing into the underlying layers (e.g., the gate dielectric layers 128A-128B). The gate barrier layer may include titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other suitable diffusion barrier materials. In some embodiments, the gate barrier layer may include a substantially fluorine-free metal or metal-containing film. The substantially fluorine-free metal or fluorine-free metal-containing film may include less than 5 atomic percent of fluorine contaminants in the form of ions, atoms, and / or molecules. In some embodiments, the thickness of the gate barrier layer may be in the range of about 1 nm to about 10 nm.

[0048] Each gate metal filling layer 132A-132B may include a single metal layer or a stack of metal layers. The stack of metal layers may include metals that are different from each other. In some embodiments, each gate metal filling layer 132A-132B may include a suitable conductive material, such as Ti, silver (Ag), Al, titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium, titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten nitride (WN), copper (Cu), tungsten (W), cobalt (Co), nickel (Ni), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), metal alloys and / or combinations thereof. Although the gate structures 112A-112B are shown as similar, the FETs 102A-102B may have gate structures with different materials and / or electrical characteristics (e.g., threshold voltage, work function value) from each other. Likewise, although the gate structures 112A- 112B are shown as having a horizontal GAA structure, other gate structures (eg, a vertical GAA structure or a gate structure without a GAA structure) are also within the scope and spirit of the present invention.

[0049] According to some embodiments, the spacers 114A-114B may be disposed on the corresponding passivation layers 109A-109B and may form sidewalls of the corresponding gate structures 112A-112B and be in physical contact with the gate dielectric layers 128A-128B. The spacers 114A-114B may include an insulating material such as silicon oxide, silicon nitride, silicon carbon nitride (SiCN), silicon carbon oxynitride (SiOCN), a low-k material, or a combination thereof. The spacers 114A-114B may have a low-k material having a dielectric constant less than about 3.9 (e.g., about 3.5, about 3.0, or about 2.8). In some embodiments, each of the spacers 114A-114B may have a thickness in a range from about 2 nm to about 10 nm.

[0050] The FETs 102A- 102B may be combined into an integrated circuit using other structural components, such as gate contact structures, S / D contact structures, conductive vias, conductive lines, interconnect metal layers, etc., which are not shown here for clarity.

[0051] refer to Figures 1A to 1D, the semiconductor device 100 may further include an etch stop layer (ESL) 116, an interlayer dielectric (ILD) layer 118, and a shallow trench isolation (STI) region 138. The ESL 116 may be configured to protect the gate structures 112A-112B and / or the epitaxial fin regions 110A-110B. Such protection may be provided, for example, during the formation of the ILD layer 118 and / or the S / D contact structure (not shown). The ESL 116 may be disposed on the sidewalls of the spacers 114A-114B and on the epitaxial regions 110A-110B. In some embodiments, the ESL 116 may include, for example, silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), boron nitride (BN), silicon boron nitride (SiBN), silicon boron carbonitride (SiCBN), or a combination thereof. In some embodiments, the ESL 116 may have a thickness in a range of about 3 nm to about 30 nm.

[0052] ILD layer 118 may be disposed on ESL 116 and may include a dielectric material deposited using a deposition method suitable for a flowable dielectric material (e.g., flowable silicon oxide, flowable silicon nitride, flowable silicon oxynitride, flowable silicon carbide, or flowable silicon oxycarbide). In some embodiments, the dielectric material is silicon oxide. In some embodiments, the thickness of ILD layer 118 may be in a range of about 50 nm to about 200 nm.

[0053] The STI regions 138 may be configured to provide electrical isolation between the FETs 102A-102B and adjacent FETs (not shown) on the substrate 106 and / or adjacent active and passive components (not shown) integrated with or deposited on the substrate 106. In some embodiments, the STI regions 138 may include multiple layers, such as a nitride layer and / or an oxide layer 138A and an insulating layer 138B disposed on the nitride and / or oxide layer 138A. In some embodiments, the nitride and / or oxide layer 138A may prevent oxidation of the sidewalls of the fin top portions 108A2-108B2 during the formation of the STI regions 138. In some embodiments, the insulating layer 138B may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, and / or other suitable insulating materials. In some embodiments, the vertical dimension of the STI regions 138 along the Z-axis may be in the range of about 40 nm to about 200 nm.

[0054] Based on the disclosure herein, it will be appreciated that semiconductor device 100 and elements thereof (eg, fin structures 108A- 108B, gate structures 112A- 112B, epitaxial fin regions 110A- 110B, spacers 114A- 114B, and / or STI regions 138 ) are exemplary and are not intended to be limiting.

[0055] FIG. 2A to FIG. 2F FETs 102A-102B with different configurations of the channel regions of passivation layers 109A-109B are shown along Figure 1A In addition, FIG. 2A to FIG. 2F The region of the fin top portions 108A2-108B2, which form a channel region with the passivation layer 109A-109B located below the gate structures 112A-112B, is shown for clarity. Figures 1A to 1D The above discussion of FETs 102A-102B applies to FIG. 2A to FIG. 2F FETs 102A-102B.

[0056] In some embodiments, instead of Figure 1B Each of the channel regions of the FETs 102A-102B may include a single fin structure etched from the substrate 106 ( Figure 2A ) or may be an epitaxially grown fin structure grown on the corresponding fin base portion 108A1-108B1 ( Figure 2B ). Instead of Figure 2A The etched fin structure shown or Figure 2B The epitaxial fin structure forms the channel region of the FET 102A-102B, such as Figure 2C As shown, the channel region of one FET (e.g., FET 102A) may include an etched fin structure, and the channel region of another FET (e.g., FET 102B) may include an epitaxial fin structure. In some embodiments, each of the channel regions of FETs 102A-102B may include a stack of second fin regions 120B and 122B, such as Figure 2D In some embodiments, FIG. 2E to FIG. 2F As shown, the channel region of one of the FETs 102A to 102B may include a stack of second fin regions 120B and 122B, such as 2E to 120B. Figure 2F As shown, the channel region of another of the FETs 102A-102B may include a nanostructured channel region 120B or 122B. In some embodiments, instead of Figure 1BThe FETs 102A-102B shown have different nanostructured channel regions 120B and 122B. The FETs 102A-102B may have different nanostructures. Figure 2G The channel region 120B of the nanostructure shown or Figure 2H The channel region 122B of the nanostructure is shown.

[0057] Figure 3 1 is a flow chart of an exemplary method 300 for manufacturing a semiconductor device 100 according to some embodiments. For purposes of illustration, reference will be made to a method for manufacturing a semiconductor device 100. FIG. 4A to FIG. 13A and FIG. 4B to FIG. 13B The operations shown in FIG. 300 are described with reference to an example manufacturing process of the semiconductor device 300 shown. FIG. 4A to FIG. 13A are isometric views of semiconductor device 100 at various stages of its fabrication. FIG. 4B to FIG. 13B According to some embodiments, FIG. 4A to FIG. 13A BB is a cross-sectional view of the structure of FIG. Depending on the specific application, the operations may be performed in a different order or not performed at all. It should be noted that method 300 may not produce a complete semiconductor device 100. Therefore, it should be understood that additional processes may be provided before, during, and after method 300, and only some other processes are briefly described herein. FIG. 4A to FIG. 13A and FIG. 4B to FIG. 13B With Figures 1A to 1D The same annotation as the element in the element.

[0058] In operation 305, a fin structure is formed on a substrate. For example, fin structures 108A-108B (in FIG. 5A to FIG. 5B ) may be formed on the substrate 106, as shown in FIG. 4A to FIG. 5B The process for forming the fin structures 108A-108B may include forming a stacked layer 108* on the substrate 106, such as FIG. 4A to FIG. 4B The stacked layer 108* may include first semiconductor layers 120* and second semiconductor layers 122* stacked in an alternating configuration. The first semiconductor layers 120* and the second semiconductor layers 122* may have respective vertical dimensions H1 and H2 in the range of about 5 nm to about 30 nm along the Z axis.

[0059] Each of the first semiconductor layer 120* and the second semiconductor layer 122* may be epitaxially grown on its underlying layer and may include semiconductor materials that are different from each other. In some embodiments, the first semiconductor layer 120* and the second semiconductor layer 122* may include semiconductor materials that have different oxidation rates and / or etching selectivities from each other. In some embodiments, the first and second semiconductor layers 120* and 122* may include semiconductor materials that are similar to or different from the substrate 106. The first and second semiconductor layers 120* and 122* may include (i) an elemental semiconductor such as silicon or germanium; (ii) a compound semiconductor including a III-V semiconductor material; (iii) an alloy semiconductor including SiGe, germanium tin, or silicon germanium tin; or (iv) a combination thereof. In some embodiments, the first semiconductor layer 120* may include Si, and the second semiconductor layer 122* may include SiGe. In some embodiments, the first semiconductor layer 120* and the second semiconductor layer 122* may include SiGe having Ge in a range of about 25 atomic percent to about 50 atomic percent, with any remaining atomic percent being Si, or may include Si without any substantial amount of Ge.

[0060] The first and / or second semiconductor layers 120* and 122* may be undoped or may be in-situ doped using the following dopants during their epitaxial growth process: (i) p-type dopants (such as boron, indium or gallium); and / or (ii) n-type dopants, such as phosphorus or arsenic. For p-type in-situ doping, p-type doping precursors such as diborane (B2H6), boron trifluoride (BF3) and / or other p-type doping precursors may be used. For n-type in-situ doping, n-type doping precursors such as phosphine (PH3), arsine (AsH3) and / or other n-type doping precursors may be used.

[0061] The process for forming the fin structures 108A-108B may also include forming Figure 4A The patterned hard mask layer (not shown) on the stacked layer 108* is etched Figure 4A In some embodiments, the hard mask layer may include, for example, a silicon oxide layer formed using a thermal oxidation process and / or a silicon nitride layer formed using, for example, low pressure chemical vapor deposition (LPCVD) or plasma enhanced CVD (PECVD). Figure 4A The etching of the structure may include dry etching, wet etching processes, or a combination thereof.

[0062] The dry etching process may include using an etchant having the following substances: an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, NF3 and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, HCl and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an ammonia gas (NH3), an iodine-containing gas, other suitable etching gases and / or plasmas, or a combination thereof. The dry etching process may be performed at a high bias voltage of about 150V to about 350V, at a radio frequency power of about 10W to about 50W, at a pressure of about 5Torr to about 50Torr, at a temperature range of from about 25°C to about 40°C, for a duration of about 10 seconds to about 40 seconds.

[0063] The wet etching process may include etching in dilute hydrofluoric acid (DHF), potassium hydroxide (KOH) solution, ammonia (NH 3 ), a solution containing hydrofluoric acid (HF), nitric acid (HNO 3 ), acetic acid (CH 3 COOH), or a combination thereof.

[0064] like Figure 5A and Figure 5B As shown, after etching the stacked layer 108*, a fin structure 108A-108B having a fin base portion 108A1-108B1 and a fin top portion 108A2-108B2 may be formed, and the fin structure 108A-108B has a corresponding vertical dimension in the range of about 40nm to about 60nm along the Z axis. The first semiconductor layer 120 and the second semiconductor layer 122 formed in the fin top portion 108A2-108B2 may have corresponding vertical dimensions H3 and H4 in the range of about 5nm to about 30nm along the Z axis, and corresponding horizontal dimensions W3 and W4 in the range of about 5nm to about 50nm along the Y axis. The ratio of H1 / W1 and H2 / W2 may be in the range of about 0.2 to about 5. In some embodiments, the dimensions H3 and H4 and W3 and W4 may be equal to or different from each other, respectively. In some embodiments, the ratios of H1 / W1 and H2 / W2 may be equal to or different from each other, respectively.

[0065] refer to Figure 3 In operation 310, a passivation layer is formed on the fin structure. For example, the passivation layers 109A-109B may be formed on the fin structures 108A-108B, respectively, as shown in FIG. FIG. 6A to FIG. 6B The process of forming the passivation layer 109A-109B on the fin structure 108A-108B may include using one or more precursor gases having fluorine, chlorine, nitrogen, oxygen, hydrogen, deuterium, NH3 and / or hydrogen sulfide (H2S) in an ALD or CVD process. Figure 5AThe passivation layer 109 is blanket deposited on the fin structures 108A-108B. During the blanket deposition process, the flow rate of the one or more precursor gases may be in the range of about 10 sccm to about 1500 sccm. The blanket deposition process may be performed at a pressure of about 10 Torr to about 20 atmospheres, at a temperature of about 100° C. to about 300° C., for a duration in the range of about 10 seconds to about 120 minutes. The portions of the blanket deposited passivation layer 109 on the fin structures 108A-108B may be referred to as passivation layers 109A-109B, respectively.

[0066] refer to Figure 3 In operation 315, an STI region is formed on the passivation layer. For example, the STI region 138 may be formed on the passivation layer 109A-109B, as shown in FIG. FIG. 7A to FIG. 7B The formation of the STI region 138 may include (i) Fig. 6A The steps of: (i) depositing a nitride material layer (not shown) on the structure of the present invention; (ii) depositing an oxide material layer (not shown) on the nitride material layer; (iii) depositing an insulating material layer (not shown) on the oxide material layer; (iv) annealing the insulating material layer; (v) chemically mechanically polishing (CMP) the nitride material layer and the oxide material layer and the annealed insulating material layer; and (vi) etching back the polished structure to form Fig. 7A STI region 138 .

[0067] The nitride material layer and the oxide material layer may be deposited using a suitable method for depositing oxide and nitride materials such as ALD or CVD. These oxide material layers and nitride material layers may prevent oxidation of the sidewalls of the fin top portions 108A2-108B2 during deposition and annealing of the insulating material.

[0068] In some embodiments, the insulating material layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), or a low-k dielectric material. In some embodiments, the insulating material layer may be deposited using a CVD process, a high-density plasma (HDP) CVD process, using silane (SiH4) and oxygen (O2) as reaction precursors. In some embodiments, a sub-atmospheric pressure CVD (SACVD) process or a high aspect ratio process (HARP) may be used to form the insulating material layer, wherein the process gas may include tetraethoxysilane (TEOS) and / or ozone (O3).

[0069] In some embodiments, the insulating material layer may be formed by depositing flowable silicon oxide using a flowable CVD (FCVD) process. A wet annealing process may be performed after the FCVD process. The wet annealing process may include annealing the deposited insulating material layer in steam at a temperature of about 200° C. to about 700° C. for a time of about 30 minutes to about 120 minutes. The wet annealing process may be followed by a CMP process to remove portions of the nitride layer, the oxide layer, and the insulating material layer so that the top surfaces of the nitride layer, the oxide layer, and the insulating material layer are substantially coplanar with the top surfaces of the fin structures 108A-108B. The CMP process may be followed by an etching process to etch back the nitride layer, the oxide layer, and the insulating material layer to form Fig. 7A STI region 138 .

[0070] The nitride layer, the oxide layer and the insulating material layer may be etched back by a dry etching process, a wet etching process or a combination thereof. In some embodiments, the dry etching process may include plasma dry etching in a pressure range of about 1 mTorr to about 5 mTorr using a gas mixture having octafluorocyclobutane (C4F8), argon (Ar), oxygen (O2) and helium (He), fluoroform (CHF3) and helium, carbon tetrafluoride (CF4), difluoromethane (CH2F2), chlorine (Cl2) and O2, hydrogen bromide (HBr), O2 and He or a combination thereof. In some embodiments, the wet etching process may include treatment with dilute hydrofluoric acid (DHF), ammonium peroxide mixture (APM), sulfur peroxide mixture (SPM), hot deionized water (DI water) or a combination thereof. In some embodiments, the wet etching process may include the use of ammonia (NH3) and hydrofluoric acid (HF) and an inert gas (such as Ar, xenon (Xe), He or a combination thereof) as an etchant. In some embodiments, the flow rates of HF and NH3 used in the wet etching process may be in the range of about 10 sccm to about 100 sccm, respectively. In some embodiments, the wet etching process may be performed at a pressure of about 5 mTorr to about 100 mTorr and a high temperature in the range of about 50°C to about 120°C.

[0071] refer to Figure 3 In operation 320, a protective oxide layer is formed on the passivation layer, and a polysilicon structure is formed on the protective oxide layer and the STI region. For example, the protective oxide layers 740A-740B may be formed on the corresponding passivation layers 109A-109B, and the polysilicon structures 112A*-112B* may be formed on the corresponding protective oxide layers 740A-740B and the STI region 138, as shown in FIG. FIG. 7A to FIG. 7B as described.

[0072] The process for forming the protective oxide layers 740A-740B may include: Fig. 6A An oxide material layer (not shown) is blanket deposited on the structure, followed by a high temperature annealing process and an etching process. The oxide material layer may include silicon oxide and may be blanket deposited using a suitable deposition process such as CVD, ALD, plasma enhanced ALD (PEALD), physical vapor deposition (PVD) or electron beam evaporation. In some embodiments, PEALD may be used to blanket deposit the oxide material layer at an energy of about 400 W to about 500 W and a temperature of about 300° C. to about 500° C. The blanket deposition of the oxide material layer may be performed by a dry annealing process in a temperature range of about 800° C. to about 1050° C. under an oxygen flow. The oxygen precursor concentration may be in the range of about 0.5% to about 5% of the total gas flow rate. In some embodiments, the annealing process may be a flash evaporation process, wherein the annealing time may be between about 0.5 s and about 5 s. The etching process to form protective oxide layers 740A- 740B may not follow the annealing process and may be performed during the formation of polysilicon structures 112A*- 112B* described below, or may be a separate etching process after forming polysilicon structures 112A*- 112B*.

[0073] After annealing of the blanket deposited layer of oxide material for protecting oxide layers 740A-740B, a FIG. 7A to FIG. 7B The formation of polysilicon structures 112A*-112B* shown. During subsequent processing, the polysilicon structures 112A*-112B* may be replaced in a gate replacement process to form gate structures 112A-112B, respectively. In some embodiments, the process for forming the polysilicon structures 112A*-112B* may include blanket depositing a polysilicon material layer on an annealed oxide material layer for protecting oxide layers 740A-740B, and etching the blanket deposited polysilicon material layer through a patterned hard mask layer 742A-742B formed on the polysilicon material layer. In some embodiments, the polysilicon material may not be doped, and the hard mask layer 742A-742B may include an oxide layer and / or a nitride layer. The oxide layer may be formed using a thermal oxidation process, and the nitride layer may be formed by LPCVD or PECVD. The hard mask layers 742A- 742B may protect the polysilicon structures 112A*- 112B* from subsequent processing steps (eg, during formation of the spacers 114A- 114B, the epitaxial fin regions 110A- 110B, the ILD layer 118 , and / or the ESL 116 ).

[0074] The blanket deposition of the polysilicon material layer may include CVD, PVD, ALD or other suitable deposition processes. In some embodiments, etching the blanket-deposited polysilicon material layer may include a dry etching process, a wet etching process or a combination thereof. In some embodiments, etching of the blanket-deposited polysilicon material layer may include four etching steps. The first polysilicon etching step may include using a gas mixture with hydrogen bromide (HBr), oxygen (O2), fluoroform (CHF3) and chlorine (Cl2). The second polysilicon etching step may include using a gas mixture with HBr, O2, Cl2 and nitrogen (N2) at a pressure of about 45mTorr to about 60mTorr. The third polysilicon etching step may include using a gas mixture with HBr, O2, Cl2, N2 and argon (Ar) at a pressure of about 45mTorr to about 60mTorr. The fourth polysilicon etching step may include using a gas mixture with HBr, O2, Cl2 and N2 at a pressure of about 45mTorr to about 60mTorr. According to some embodiments, along with the polysilicon material, the fourth polysilicon etching step may remove portions of the annealed blanket-deposited oxide material layer for protecting oxide layers 740A-740B that are not covered by polysilicon structures 112A*-112B*. The first polysilicon etching step may have a higher polysilicon etching rate than the second, third, and / or fourth polysilicon etching steps. The first polysilicon etching step is used to etch unwanted portions of the blanket-deposited polysilicon material layer over fin structures 108A*-108B*. The second, third, and fourth polysilicon etching steps are used to etch unwanted portions of the blanket-deposited polysilicon material layer within high aspect ratio spaces 743.

[0075] In some embodiments, a vertical dimension of the polysilicon structures 112A*-112B* along the Z-axis on the top surface of the fin structures 108A-108B may be in a range of about 40 nm to about 60 nm. The polysilicon structures 112A*-112B* may have an aspect ratio equal to or greater than about 9 (e.g., about 10, about 12, about 15, about 18, or about 20), where the aspect ratio is a ratio of a vertical dimension along the Z-axis to a horizontal dimension along the Y-axis of the polysilicon structures 112A*-112B*. In some embodiments, a horizontal dimension (e.g., a pitch) along the Y-axis between centerlines of adjacent polysilicon structures 112A*-112B* may be in a range of about 30 nm to about 70 nm.

[0076] After forming the polysilicon structures 112A*-112B*, portions of the blanket deposited oxide layer not covered by the polysilicon structures 112A*-112B* may be removed by a dry or wet etching process if not removed during the fourth polysilicon etching step. In some embodiments, the protective oxide layers 740A-740B may have a vertical dimension along the Z-axis (e.g., thickness on the top surface of the fin structures 108A-108B) and a horizontal dimension along the Y-axis (e.g., thickness on the sidewalls of the fin top portions 108A2-108B2) in the range of about 1 nm to about 3 nm. In some embodiments, the vertical dimension may be equal to or greater than the horizontal dimension. The presence of protective oxide layers 740A- 740B allows etching of polysilicon material from high aspect ratio spaces 743 (eg, aspect ratios greater than 1:15, 1:18, or 1:20) without substantially etching and / or damaging fin structures 108A- 108B during formation of polysilicon structures 112A*- 112B*.

[0077] refer to Figure 3 In operation 325, spacers are formed on the sidewalls of the polysilicon structures and on the passivation layer. For example, the spacers 114A-114B may be formed on the sidewalls of the polysilicon structures 112A*-112B* and on portions of the passivation layers 109A-109B not covered by the polysilicon structures 112A*-112B*, as described in reference to FIG. 8A to FIG. 8B The process for forming the spacers 114A-114B may include forming the spacers 114A-114B by CVD, PVD or ALD process. Fig. 7A An insulating material layer (e.g., an oxide or nitride material) is blanket deposited on the structure, followed by a photolithography and etching process (e.g., reactive ion etching or other dry etching process using a chlorine or fluorine-based etchant). An additional process may be performed to selectively remove the insulating material from portions of the passivation layers 109A-109B that are not covered by the polysilicon structures 112A*-112B*. The additional etching process may be a dry etching process using an etchant having CH4, oxygen, and / or CH3F. The ratio of the flow rates of CH4, oxygen, and CH3F may be in the range of about 1:1:1 to about 1:2:4. The dry etching process may be performed at a bias voltage of about 300V to about 450V.

[0078] refer to Figure 3 In operation 330, epitaxial fin regions are formed on the passivation layer. For example, the epitaxial fin regions 110A-110B may be formed on portions of the passivation layers 109A-109B that are not covered by the polysilicon structures 112A*-112B*, as shown in FIG. FIG. 9A to FIG. 9BAs described. The epitaxial fin regions 110A-110B may be formed simultaneously or may be formed sequentially. In some embodiments, epitaxial fin regions 110A-110B having the same conductivity type (e.g., n-type or p-type) may be formed simultaneously, and epitaxial fin regions 110A-110B having conductivity types different from each other may be formed sequentially. In order to sequentially form the epitaxial fin regions 110A-110B, a photoresist layer (not shown) or other suitable protective layer may be used to protect the FET 102B, and the epitaxial fin region 110A may be formed on the passivation layer 109A of the unprotected FET 102A. After the epitaxial fin region 110A is formed, the photoresist layer or other suitable protective layer may be removed from the FET 102B, and the FET 102A may be protected with another photoresist layer (not shown) or other suitable protective layer, after which the epitaxial fin region 110B may be grown on the passivation layer 109B of the unprotected FET 102B.

[0079] In some embodiments, the epitaxial fin regions 110A-110B may be grown by: (i) CVD, such as low pressure CVD (LPCVD), atomic layer CVD (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), or any suitable CVD; (ii) a molecular beam epitaxy (MBE) process; (iii) any suitable epitaxial process; or (iv) a combination thereof. In some embodiments, the epitaxial fin regions 110A-110B may be grown by an epitaxial deposition / partial etching process that repeats the epitaxial deposition / partial etching process at least once. In some embodiments, the epitaxial fin regions 110A-110B may be p-type or n-type. P-type epitaxial fin regions 110A-110B may include SiGe and may be in-situ doped with a p-type dopant such as boron, indium, or gallium during the epitaxial growth process. For p-type in-situ doping, a p-type doping precursor may be used, such as but not limited to diborane (B2H6), boron trifluoride (BF3), and / or other p-type doping precursors. The N-type epitaxial fin regions 110A-110B may include Si without any substantial amount of Ge, and may be in-situ doped with an n-type dopant such as phosphorus or arsenic during the epitaxial growth process. For n-type in-situ doping, an n-type doping precursor may be used, such as but not limited to phosphine (PH3), arsine (AsH3), and / or other n-type doping precursors.

[0080] refer to Figure 3 In operation 335, a nanostructured channel region is formed in the fin structure. For example, the nanostructured channel regions 120B and 122B may be sequentially formed in the region of the fin top portions 108A2-108B2 below the polysilicon structures 112A*-112B*, as shown in FIG. FIG. 10A to FIG. 13BBefore forming the nanostructured channel regions 120B and 122B, Fig. 9A An ESL 116 is deposited on the structure of FIG. 1 , and an ILD 118 may be deposited on the ESL 116 .

[0081] In some embodiments, the ESL 116 may be made of SiN x 、SiO x , SiON, SiC, SiCN, BN, SiBN, SiCBN or a combination thereof. The formation of the ESL 116 may include using PECVD, sub-atmospheric chemical vapor deposition (SACVD), LPCVD, ALD, high density plasma (HDP), plasma enhanced atomic layer deposition (PEALD), molecular layer deposition (MLD), plasma pulse chemical vapor deposition (PICVD) or other suitable deposition methods. Fig. 9A A material layer of ESL 116 is blanket deposited on the structure.

[0082] The blanket deposition of the material layer for ESL 116 may be followed by blanket deposition of the dielectric material layer for ILD 118. In some embodiments, the dielectric material may be silicon oxide. The dielectric material layer may be deposited using a deposition method suitable for a flowable dielectric material (e.g., flowable silicon oxide, flowable silicon nitride, flowable silicon oxynitride, flowable silicon carbide, or flowable silicon oxycarbide). For example, the flowable silicon oxide may be deposited using an FCVD process. The blanket deposition process may be followed by thermal annealing of the deposited dielectric material layer in steam at a temperature of about 200° C. to about 700° C. for a period of about 30 minutes to about 120 minutes. Fig. 10A As shown, a CMP process may be performed after the thermal annealing to make the top surfaces of the ESL 116 , ILD 118 , spacers 114A- 114B, and polysilicon structures 112A*- 112B* coplanar with each other. During the CMP process, the hard mask layers 742A- 742B may be removed.

[0083] After the CMP process, Fig. 11B The process for forming the nanostructured channel region 120B of the FET 102A may include the following sequential steps: (i) FIG. 10A to FIG. 10B A photoresist layer 1046 is formed on the FET 102B shown in FIG. Fig. 10A The polysilicon structure 112A* and the protective oxide layer 740A are etched from Fig. 10AThe second fin region 122B of the fin top portion 108A2 can be etched from the structure. In some embodiments, the polysilicon structure 112A* and the protective oxide layer 740A can be etched using the first, second, third, and / or fourth polysilicon etching steps described in operation 320. In some embodiments, the second fin region 122B can include SiGe, and etching the second fin region 122B can include using a dry etching process that has a higher etching selectivity for silicon germanium than for silicon. For example, a halogen-based chemistry has a higher etching selectivity for Ge than for Si. Therefore, the halogen gas can etch SiGe faster than Si. In some embodiments, the halogen-based chemistry can include fluorine-based and / or chlorine-based gases. Optionally, the etching of the second fin region 122B can include using a wet etching process that has a higher selectivity for SiGe than for Si to form Fig. 11B For example, the wet etching process may include using a mixture (SPM) of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) and / or a mixture (APM) of ammonium hydroxide (NH4OH) with H2O2 and deionized (DI) water. Parameters and etchants used to etch the second fin region 122B may be controlled so that the fin regions 120A and 122A located below the epitaxial fin region 110A are not removed.

[0084] After etching the second fin region 122B of the fin top portion 108A2, the Fig. 12B The process for forming the nanostructured channel region 122B of the FET 102B may include the following sequential steps: (i) removing the photoresist layer 1046, (ii) forming a nanostructured channel region 122B in the opening 1148 (eg, Fig. 11B A photoresist layer 1250 is formed inside the nanostructure to protect the channel region 120A. Fig. 12B As shown, (iii) etching the polysilicon structure 112B* and the protective oxide layer 740B, and (iv) etching the second fin region 120B of the fin top portion 108B2. Similar to the etching of the polysilicon structure 112A*, the polysilicon structure 112B* and the protective oxide layer 740B may be etched using the first, second, third, and / or fourth polysilicon etching steps described in operation 320. In some embodiments, the second fin region 120B may include Si without any substantial amount of Ge, and may be etched in a wet etching process using an etchant including NH4OH and HCl, which has a higher etching selectivity to Si than SiGe to form Fig. 12BThe parameters and etchant used to etch the fin region 120B may be controlled so that the fin regions 120A and 122A located below the epitaxial fin region 110B are not removed. After forming the channel region 122B of the nanostructure of the FET 102B, the photoresist layer 1250 may be removed from the opening 1148 to form FIG. 13A to FIG. 13B structure.

[0085] refer to Figure 3 In operation 340, a gate-all-around (GAA) structure or a nanosheet (NS) structure is formed on the channel region of the nanostructure. For example, the gate structures 112A-112B may be formed to wrap around the channel regions 120B and 122B of the nanostructure, as shown in FIG. FIG. 13A to FIG. 13B and Figures 1B to 1D The process for forming the gate structures 112A-112B may include the following sequential steps: (i) Fig.13A (ii) blanket depositing a dielectric material layer for gate dielectric layers 128A-128B on the structure of (i) a work function metal layer for gate work function metal layers 130A-130B on the dielectric material layer, and (iii) blanket depositing a conductive material layer for gate metal filling layers 132A-132B on the work function metal layer until the openings 1148 and 1352 are filled. In some embodiments, as Figure 1B As shown, each of the dielectric material layer and the work function metal layer may be formed in the openings 1148 and 1352 (eg, Fig. 13B A conformal layer is formed inside the substrate.

[0086] The dielectric material layer for the gate dielectric layers 128A-128B may include silicon oxide and may be formed by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), electron beam evaporation, or other suitable processes. In some embodiments, the dielectric material layer may include (i) a silicon oxide layer, a silicon nitride layer, and / or a silicon oxynitride layer, (ii) a high-k dielectric material such as hafnium oxide (HfO2), TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, (iii) a high-k dielectric material having Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu, or (iv) a combination thereof. The high-k dielectric layer may be formed by ALD and / or other suitable methods.

[0087] The work function metal layer for the work function metal layer 130A-130B may include Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, Ag, TaC, TaSiN, TaCN, TiAl, TiAlN, WN, metal alloys and / or combinations thereof. In some embodiments, the work function metal layer may include a metal doped with aluminum, such as Al-doped Ti, Al-doped TiN, Al-doped Ta, or Al-doped TaN. The work function metal layer may be deposited using a suitable process such as ALD, CVD, PVD, plating, or a combination thereof. The conductive material layer for the gate electrode 132 may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, Cu, W, Co, Ni, TiC, TiAlC, TaAlC, metal alloys and / or combinations thereof, and may be formed by ALD, PVD, CVD, or other suitable deposition processes. The deposited dielectric material layer, work function metal layer and conductive material layer can be planarized by a CMP process to form Figure 1A The CMP process can make the top surfaces of the gate dielectric layers 128A-128B, the gate work function metal layers 130A-130B and the gate metal filling layers 132A-132B substantially coplanar with the top surface of the ILD layer 118, such as Figures 1A to 1D shown.

[0088] After the gate structures 112A- 112B are formed, other elements such as S / D contacts, gate contacts, vias, interconnect metal layers, dielectric layers, passivation layers, etc. may be formed, which are not shown in the drawings for clarity.

[0089] The present invention provides example structures and methods for reducing resistance in active regions (e.g., channel regions 120B and 122B of nanostructures) of FET devices (e.g., FETs 102A-102B). Reducing resistance in active regions can increase the drive current of FET devices, thereby resulting in improved FET device performance.

[0090] Example structures and methods provide a passivation layer 109A-109B on the active region of the FET device to improve the surface quality of the active region. The surface quality can be improved by reducing surface defects with the passivation layer 109A-109B. The surface defects on the active region can be in the form of vacancies caused by dangling bonds on the surface of the active region. The vacancies can capture charge carriers traveling through the active region of the FET device during operation and reduce the drive current of the FET device. The passivation layer 109A-109B can react with these dangling bonds to reduce or eliminate surface defects caused by dangling bonds on the active region. Eliminating such surface defects on the active region of the FET device with the passivation layer 109A-109B can increase the drive current of the FET device by about 20% to about 50% compared to the drive current of the FET device without a passivation layer on their active region.

[0091] In some embodiments, a semiconductor device includes: a substrate; a first source / drain (S / D) region and a second source / drain (S / D) region disposed on the substrate; a channel region of a nanostructure disposed between the first and second S / D regions; a passivation layer; and a nanosheet (NS) structure wrapping the channel region of the nanostructure. Each S / D region has a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of the first and second semiconductor layers. A first portion of the passivation layer is disposed between the epitaxial region and the stack of the first and second semiconductor layers, and a second portion of the passivation layer is disposed on a sidewall of the channel region of the nanostructure.

[0092] In the above semiconductor device, the first portion of the passivation layer wraps the stack of the first semiconductor layer and the second semiconductor layer.

[0093] In the above semiconductor device, the epitaxial region wraps around the stack of the first semiconductor layer and the second semiconductor layer.

[0094] In the above semiconductor device, it further includes a spacer disposed on a sidewall of the nanosheet structure, wherein the first portion of the passivation layer extends below the spacer.

[0095] In the above semiconductor device, the first portion of the passivation layer extends between the nanosheet structure and a channel region of at least one of the nanostructures.

[0096] In the above semiconductor device, the second portion of the passivation layer is disposed between the channel region of the nanostructure and the gate dielectric layer of the nanosheet structure that wraps the channel region of the nanostructure.

[0097] In the above semiconductor device, a shallow trench isolation (STI) region is further included, wherein the third portion of the passivation layer is disposed between the shallow trench isolation region and the substrate.

[0098] In the above semiconductor device, the passivation layer includes a nitride layer, a fluoride layer, a chloride layer or a sulfide layer.

[0099] In some embodiments, a semiconductor device includes: a first field effect transistor (FET) having a first fin structure disposed on a substrate; a first passivation layer wrapping the fin structure; a first epitaxial region of a first conductivity type disposed on the first passivation layer. The semiconductor device also includes: a second FET having a second fin structure disposed adjacent to the first fin structure on the substrate; a second passivation layer wrapping the second fin structure; and a second epitaxial region of a second conductivity type disposed on the second passivation layer, wherein the first and second conductivity types are different from each other.

[0100] In the above semiconductor device, the first passivation layer and the second passivation layer are parts of a passivation layer.

[0101] In the above semiconductor device, the first field effect transistor further includes a channel region having a first nanostructure of a first semiconductor material, and the second field effect transistor further includes a channel region having a second nanostructure of a second semiconductor material different from the first semiconductor material.

[0102] In the above-mentioned semiconductor device, wherein the first field effect transistor also includes a channel region having a first nanostructure of a first semiconductor material, wherein the second field effect transistor also includes a channel region having a second nanostructure of a second semiconductor material different from the first semiconductor material, wherein the first field effect transistor also includes a first nanosheet (NS) structure wrapping the channel region of the first nanostructure, and wherein the second field effect transistor also includes a second full-ring gate structure wrapping the channel region of the second nanostructure.

[0103] In the above-mentioned semiconductor device, wherein the first field effect transistor also includes a channel region having a first nanostructure of a first semiconductor material, wherein the second field effect transistor also includes a channel region having a second nanostructure of a second semiconductor material different from the first semiconductor material, wherein the first field effect transistor also includes a first nanosheet (NS) structure wrapping the channel region of the first nanostructure, and wherein the second field effect transistor also includes a second full-ring gate structure wrapping the channel region of the second nanostructure, the first passivation layer is arranged between the first nanosheet structure and the channel region of the first nanostructure.

[0104] In the above-mentioned semiconductor device, wherein the first field effect transistor also includes a channel region having a first nanostructure of a first semiconductor material, wherein the second field effect transistor also includes a channel region having a second nanostructure of a second semiconductor material different from the first semiconductor material, and each of the first fin structure and the second fin structure includes a stack of the first semiconductor material and the second semiconductor material.

[0105] In some embodiments, a method for manufacturing a semiconductor device includes: forming a fin structure, wherein a stack of first and second semiconductor layers is arranged in an alternating configuration on a substrate; depositing a passivation layer on the fin structure and the substrate; forming an epitaxial region on a first portion of the fin structure, forming a nanostructured channel region in a second portion of the fin structure, and forming a nanosheet (NS) structure wrapping the channel region of the nanostructure.

[0106] In the above method, depositing the passivation layer includes blanket depositing a nitride layer, a fluoride layer, a chloride layer or a sulfide layer on the top surface and the side surface of the stack of the first semiconductor layer and the second semiconductor layer.

[0107] In the above method, wherein forming a channel region of the nanostructure in the second portion of the fin structure includes etching a portion of the second semiconductor layer in the second portion of the fin structure.

[0108] In the above method, wherein forming the epitaxial region includes growing the epitaxial region on a top surface and a side surface of the stack of the first semiconductor layer and the second semiconductor layer not covered by the nanosheet structure.

[0109] In the above method, it also includes blanket depositing a protective oxide layer on the passivation layer.

[0110] In the above method, it also includes blanket depositing a protective oxide layer on the passivation layer, and forming a polysilicon structure on the protective oxide layer.

[0111] The present invention summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a substrate to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also be aware that this equivalent configuration is not directed away from the spirit and scope of the present invention, and in the case of not directed away from the spirit and scope of the present invention, they can make multiple changes, replacements and changes herein.

Claims

1. A semiconductor device, comprising: substrate; a first source / drain (S / D) region and a second source / drain (S / D) region disposed on the substrate, wherein each of the first source / drain region and the second source / drain region includes a stack of first and second semiconductor layers arranged in an alternating configuration and in contact with each other, and an epitaxial region disposed on the stack of the first and second semiconductor layers; A nanostructured channel region is disposed between the first source / drain region and the second source / drain region; a passivation layer, wherein a first portion of the passivation layer is conformally deposited on the stack of the first and second semiconductor layers and disposed between the epitaxial region and the stack of the first and second semiconductor layers, and a second portion of the passivation layer is disposed on a sidewall of a channel region of the nanostructure; and A nanosheet structure wraps the channel region of the nanostructure.

2. The semiconductor device according to claim 1, wherein The first portion of the passivation layer wraps around the stack of the first and second semiconductor layers.

3. The semiconductor device according to claim 1, wherein The epitaxial region wraps around the stack of the first and second semiconductor layers.

4. The semiconductor device according to claim 1, further comprising a spacer disposed on a sidewall of the nanosheet structure, wherein: The first portion of the passivation layer extends under the spacer.

5. The semiconductor device according to claim 1, wherein The first portion of the passivation layer extends between the nanosheet structure and a channel region of at least one of the nanostructures.

6. The semiconductor device according to claim 1, wherein The second portion of the passivation layer is disposed between the channel region of the nanostructure and the gate dielectric layer of the nanosheet structure that wraps the channel region of the nanostructure.

7. The semiconductor device according to claim 1, further comprising a shallow trench isolation (STI) region, wherein: A third portion of the passivation layer is disposed between the shallow trench isolation region and the substrate.

8. The semiconductor device according to claim 1, wherein The passivation layer includes a nitride layer, a fluoride layer, a chloride layer or a sulfide layer.

9. A semiconductor device comprising: A first field effect transistor (FET) comprising: A first fin structure is disposed on a substrate, a first passivation layer, wrapping the first fin structure, and A first epitaxial region of a first conductivity type is disposed on the first passivation layer; and a second field effect transistor comprises: A second fin structure is disposed on the substrate adjacent to the first fin structure, a second passivation layer, wrapping the second fin structure, and A second epitaxial region of a second conductivity type is disposed on the second passivation layer, wherein the first conductivity type and the second conductivity type are different from each other.

10. The semiconductor device according to claim 9, wherein The first passivation layer and the second passivation layer are parts of a passivation layer.

11. The semiconductor device according to claim 9, wherein: The first field effect transistor further comprises a channel region having a first nanostructure of a first semiconductor material, The second field effect transistor further includes a channel region of a second nanostructure having a second semiconductor material different from the first semiconductor material.

12. The semiconductor device according to claim 11, wherein The first field effect transistor further includes a first nanosheet structure encapsulating a channel region of the first nanostructure, and The second field effect transistor further includes a second full-ring gate structure wrapping a channel region of the second nanostructure.

13. The semiconductor device according to claim 12, wherein: The first passivation layer is disposed between the first nanosheet structure and a channel region of the first nanostructure.

14. The semiconductor device according to claim 11, wherein Each of the first fin structure and the second fin structure includes a stack of a first semiconductor material and a second semiconductor material.

15. A method for manufacturing a semiconductor device, comprising: forming a fin structure having a stack of first and second semiconductor layers arranged in an alternating configuration on a substrate; depositing a passivation layer on the fin structure and the substrate; forming an epitaxial region on a first portion of the fin structure; forming a nanostructured channel region in a second portion of the fin structure; as well as A nanosheet structure is formed that wraps around the channel region of the nanostructure.

16. The method according to claim 15, wherein: Depositing the passivation layer includes blanket depositing a nitride layer, a fluoride layer, a chloride layer, or a sulfide layer on a top surface and side surfaces of the stack of the first semiconductor layer and the second semiconductor layer.

17. The method according to claim 15, wherein: Forming a channel region of the nanostructure in the second portion of the fin structure includes etching a portion of the second semiconductor layer in the second portion of the fin structure.

18. The method according to claim 15, wherein: Forming the epitaxial region includes growing the epitaxial region on a top surface and side surfaces of the stack of the first and second semiconductor layers not covered by the nanosheet structure.

19. The method of claim 15, further comprising blanket depositing a protective oxide layer over the passivation layer.

20. The method of claim 19, further comprising forming a polysilicon structure on the protective oxide layer.

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