A P-type back-contact crystalline silicon solar cell, its fabrication method, and its module

Abstract

This invention relates to the field of solar cell processing technology, and provides a P-type back-contact crystalline silicon solar cell, its fabrication method, and a cell module. The P-type back-contact crystalline silicon solar cell includes a P-type silicon wafer with a passivation anti-reflection layer on its front side. The back side of the silicon wafer substrate has P+ doped regions, N+ doped regions, a back passivation layer, a positive electrode, and a negative electrode, with the P+ and N+ doped regions alternating. The N+ doped regions include a tunneling oxide layer on the back side of the P-type silicon wafer and N+ doped polycrystalline silicon on top of the tunneling oxide layer. A textured structure is provided on the back side of the P-type silicon wafer corresponding to the negative electrode, and a rough textured structure is provided on the back side of the negative electrode corresponding to the textured structure to form an ohmic contact with the N+ doped polycrystalline silicon. The P-type back-contact crystalline silicon solar cell provided by this invention can effectively improve the ohmic contact between the negative electrode and the N+ doped polycrystalline silicon, improve cell efficiency, and is simple and low-cost to implement.

Description

Technical Field

[0001] This invention relates to the field of solar cell processing technology, specifically to a P-type back-contact crystalline silicon solar cell, its preparation method, and its battery module. Background Technology

[0002] Currently, with the gradual depletion of fossil fuels, solar cells are becoming increasingly widely used as a new energy alternative. A solar cell is a device that converts solar energy into electrical energy. Solar cells utilize the photovoltaic principle to generate charge carriers, which are then extracted using electrodes, thus facilitating the efficient use of electrical energy. A typical P-type back-contact crystalline silicon solar cell includes a P-type silicon wafer. The front side of the P-type silicon wafer has a passivation anti-reflection layer, while the back side has a tunneling oxide layer, N+-doped polycrystalline silicon disposed on the tunneling oxide layer, P+-doped regions alternately distributed on the back side of the P-type silicon wafer and the N+-doped polycrystalline silicon, and a back passivation layer covering the N+-doped polycrystalline silicon. The N+-doped polycrystalline silicon region has a negative electrode, and the P+-doped region has a positive electrode.

[0003] In the prior art, P-type back-contact crystalline silicon solar cells require polishing before the tunneling oxide layer is prepared. The back side of the P-type silicon wafer, corresponding to the negative electrode, contacts the tunneling oxide layer through the polished surface. Thus, the N+ doped polycrystalline silicon prepared on the tunneling oxide layer and the back passivation layer prepared on the N+ doped polycrystalline silicon are both planar structures. The negative electrode obtained by printing and sintering achieves ohmic contact with the N+ doped polycrystalline silicon through planar contact. The poor ohmic contact between the negative electrode and the N+ doped polycrystalline silicon affects the cell efficiency. Summary of the Invention

[0004] This invention provides a P-type back-contact crystalline silicon solar cell, aiming to solve the problem of poor ohmic contact between the negative electrode and N+-doped polycrystalline silicon in existing P-type back-contact crystalline silicon solar cells, which affects the cell efficiency.

[0005] The present invention is implemented as follows: a P-type back-contact crystalline silicon solar cell is provided, comprising a P-type silicon wafer, wherein a passivation anti-reflection layer is disposed on the front side of the P-type silicon wafer;

[0006] The back side of the P-type silicon wafer is provided with a P+ doped region, an N+ doped region, a back passivation layer, a positive electrode, and a negative electrode. The P+ doped region and the N+ doped region are distributed alternately. The back passivation layer covers the P+ doped region and the N+ doped region.

[0007] The N+ doped region includes a tunneling oxide layer disposed on the back side of the P-type silicon wafer and N+ doped polysilicon disposed on the tunneling oxide layer. The positive electrode forms an ohmic contact with the P+ doped region, and the negative electrode forms an ohmic contact with the N+ doped polysilicon. The back side of the P-type silicon wafer is provided with a textured structure corresponding to the position of the negative electrode, and the negative electrode is provided with a rough textured structure corresponding to the position of the textured structure to form an ohmic contact with the N+ doped polysilicon.

[0008] Preferably, the width of the velvet structure is 80-200 μm.

[0009] Preferably, the sheet resistance of the N+ doped polycrystalline silicon is 50-200 Ω / sqr.

[0010] Preferably, the back side of the P-type silicon wafer is provided with grooves corresponding to the number of P+ doped regions, and each P+ doped region is disposed at the bottom of one of the grooves.

[0011] Preferably, the bottom of the groove is provided with a textured surface, the positive electrode is disposed on the textured surface, and the back passivation layer covers the textured surface.

[0012] Preferably, the width of the groove is 300-600 μm, the depth of the groove is 0.3-10 μm, and the distance between two adjacent grooves is 20-500 μm.

[0013] Preferably, the thickness of the tunneling oxide layer is 1-5 nm.

[0014] Preferably, the passivation antireflection layer and the back passivation layer are one or more combinations of aluminum oxide film, silicon nitride film, and silicon oxynitride film.

[0015] This invention also provides a method for fabricating a P-type back-contact crystalline silicon solar cell, comprising the following steps:

[0016] Polishing: P-type silicon wafers are selected and polished.

[0017] First texturing: Texturing is performed on the back of the P-type silicon wafer at the location where the negative electrode is prepared to form a textured surface structure;

[0018] Preparation of tunneling oxide layer: A tunneling oxide layer is prepared on the back side of the P-type silicon wafer;

[0019] Preparation of N+-doped polycrystalline silicon: N+-doped polycrystalline silicon is prepared on the back side of the P-type silicon wafer;

[0020] Second texturing: Texturing is performed on the front side of the P-type silicon wafer to form a textured surface;

[0021] Fabrication of passivation antireflection layer and back passivation layer: A passivation antireflection layer is fabricated on the front side of the P-type silicon wafer, and a back passivation layer is fabricated on the back side of the P-type silicon wafer;

[0022] Laser grooving: Laser grooving is performed on the back of the P-type silicon wafer at the position where the positive electrode is formed, so as to expose the P-type silicon wafer;

[0023] Printing and sintering of positive and negative electrodes: A negative electrode is printed using silver paste at the first texturing position on the back of the P-type silicon wafer, and a positive electrode is printed using aluminum paste at the laser grooving position on the back of the P-type silicon wafer. The electrodes are then sintered and dried to form a P+ doped region between the positive electrode and the P-type silicon wafer. The negative electrode forms a rough textured structure that forms an ohmic contact with the N+ doped polysilicon.

[0024] Preferably, the polishing process of the P-type silicon wafer specifically includes:

[0025] The P-type silicon wafer is polished using an alkaline solution with a concentration of 1.5-15%, and the reflectivity of the polished P-type silicon wafer is controlled at 38%-45%.

[0026] Preferably, the first fleece forming step includes:

[0027] A mask is fabricated on the back side of the P-type silicon wafer;

[0028] A laser ablation etching mask is applied to the back of the P-type silicon wafer at the location where the negative electrode is fabricated, to expose the P-type silicon wafer.

[0029] A texturing structure is formed in the laser ablation area on the back of the P-type silicon wafer, and the mask in the non-laser ablation area is removed by acid washing.

[0030] Preferably, the thickness of the tunneling oxide layer is controlled to be 1-5 nm.

[0031] Preferably, the thickness of the N+ doped polycrystalline silicon is controlled between 50-350 nm.

[0032] Preferably, the second flocking step further includes:

[0033] A texturing process is performed on the back side of the P-type silicon wafer at the location where the positive electrode is fabricated to form a textured surface.

[0034] Preferably, the second flocking step specifically includes:

[0035] A mask is fabricated on the back side of the P-type silicon wafer;

[0036] A laser-guided local ablation etching mask is used to expose the P-type silicon wafer at the location corresponding to the positive electrode on the back side.

[0037] Texturing is performed on the laser ablation areas of the front and back sides of the P-type silicon wafer to form a textured surface, and the mask in the non-laser ablation areas is removed by acid washing.

[0038] Preferably, the step of preparing N+-doped polycrystalline silicon specifically includes:

[0039] N+-doped amorphous silicon is deposited on the back side of a P-type silicon wafer, and the N+-doped amorphous silicon is then crystallized at high temperature into N+-doped polycrystalline silicon; or,

[0040] Intrinsic amorphous silicon is deposited on the back side of a P-type silicon wafer, and phosphorus diffusion is performed on the intrinsic amorphous silicon to obtain N+-doped amorphous silicon. At the same time, the N+-doped amorphous silicon is crystallized at high temperature to form N+-doped polycrystalline silicon.

[0041] Preferably, the thickness of the back passivation layer is controlled at 60-150 nm, and the refractive index is controlled at 2-2.5.

[0042] The present invention also provides a solar cell module, including the above-described P-type back-contact crystalline silicon solar cell.

[0043] This invention provides a P-type back-contact crystalline silicon solar cell by creating a textured structure on the back of the P-type silicon wafer corresponding to the negative electrode position. This allows the printed and sintered negative electrode to form a rough textured structure corresponding to the textured structure, creating an ohmic contact with N+-doped polycrystalline silicon. This rough textured structure increases the contact area between the negative electrode and the N+-doped polycrystalline silicon, resulting in a good ohmic contact and improved cell efficiency. Furthermore, by adding a texturing process before preparing the tunneling oxide layer, textured structures can be formed on the back of the P-type silicon wafer, the tunneling oxide layer, the N+-doped polycrystalline silicon, and the back passivation layer corresponding to the negative electrode position. This allows the printed and sintered negative electrode to form a rough textured structure to achieve a good ohmic contact with the N+-doped polycrystalline silicon. The implementation method is simple and low-cost. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the structure of a P-type back-contact crystalline silicon solar cell provided in Embodiment 1 of the present invention;

[0045] Figure 2 This is a flowchart illustrating a method for fabricating a P-type back-contact crystalline silicon solar cell according to Embodiment 2 of the present invention. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0047] This invention provides a P-type back-contact crystalline silicon solar cell by creating a textured structure on the back of the P-type silicon wafer corresponding to the negative electrode position. This allows the printed and sintered negative electrode to form a rough textured structure corresponding to the textured structure, creating an ohmic contact with N+-doped polycrystalline silicon. This rough textured structure increases the contact area between the negative electrode and the N+-doped polycrystalline silicon, resulting in a good ohmic contact and improved cell efficiency. Furthermore, by simply adding a texturing process before preparing the tunneling oxide layer, textured structures can be formed on the back of the P-type silicon wafer, the tunneling oxide layer, the N+-doped polycrystalline silicon, and the back passivation layer corresponding to the negative electrode position. This allows the printed and sintered negative electrode to form a rough textured structure to achieve a good ohmic contact with the N+-doped polycrystalline silicon. The implementation method is simple and low-cost.

[0048] Example 1

[0049] Please refer to Figure 1 This embodiment provides a P-type back-contact crystalline silicon solar cell, including a P-type silicon wafer 1, with a passivation antireflection layer 2 disposed on the front side of the P-type silicon wafer 1.

[0050] The back side of the P-type silicon wafer 1 is provided with a P+ doped region 3, an N+ doped region 4, a back passivation layer 5, a positive electrode 6, and a negative electrode 7. The P+ doped region 3 and the N+ doped region 4 are distributed alternately, and the back passivation layer 5 covers the P+ doped region 3 and the N+ doped region 4.

[0051] The N+ doped region 4 includes a tunneling oxide layer 41 disposed on the back side of the P-type silicon wafer 1 and an N+ doped polysilicon 42 disposed on the tunneling oxide layer 41. The positive electrode 6 forms an ohmic contact with the P+ doped region 3, and the negative electrode 7 forms an ohmic contact with the N+ doped polysilicon 42. A textured structure 10 is provided on the back side of the P-type silicon wafer 1 at the position corresponding to the negative electrode 7, and a rough textured structure 71 is provided on the negative electrode 7 at the position corresponding to the textured structure 10 to form an ohmic contact with the N+ doped polysilicon 42.

[0052] As an embodiment of the present invention, the passivation antireflection layer 2 and the back passivation layer 5 are one or more combinations of aluminum oxide film, silicon nitride film, and silicon oxynitride film.

[0053] As an embodiment of the present invention, the passivation antireflection layer 2 includes a passivation film 21 disposed on the front side of the P-type silicon wafer 1 and an antireflection film 22 disposed on the passivation film 21, so as to effectively reduce surface recombination of the silicon wafer and reduce the reflection of sunlight on the front side of the silicon wafer. Preferably, the passivation film 21 is an aluminum oxide film and the antireflection film 22 is a silicon nitride film.

[0054] As an embodiment of the present invention, the thickness of the passivation antireflection layer 2 is 80-150nm, so that the passivation antireflection layer 2 has good passivation and antireflection effects.

[0055] In a preferred embodiment of the present invention, the back passivation layer 5 is a silicon nitride film. By utilizing the good stability and passivation effect of the silicon nitride film, the back of the silicon wafer can be better passivated.

[0056] As an embodiment of the present invention, the thickness of the back passivation layer 5 is 60-150nm and the refractive index is 2-2.5, so as to achieve better passivation on the back of the silicon wafer and increase the absorption and utilization of light by the silicon wafer.

[0057] In one embodiment of the present invention, the back side of the P-type silicon wafer 1 is provided with grooves 11 corresponding to the number of P+ doped regions 3, with each P+ doped region 3 correspondingly disposed at the bottom of a groove 11. The number of grooves 11 is equal to the number of P+ doped regions 3. Figure 1 The diagram shows four P+ doped regions 3 and four grooves 11. By providing grooves 11 on the back side of the P-type silicon wafer 1, the P+ doped regions 3 are separated from the N+ doped regions 4 by the grooves 11, avoiding contact leakage between the P+ doped regions 3 and N+ doped regions 4, thereby improving battery safety and efficiency.

[0058] In one embodiment of the present invention, the groove 11 is arc-shaped, trapezoidal, or square. For example... Figure 1 As shown, in one specific embodiment, the groove 11 is square. The groove 11 is preferably set as an arc or trapezoid. When the groove 11 is set as an arc or trapezoid, the light reflected by the inner wall of the groove 11 is better. At the same time, when the groove 11 is set as a square, the actual production process is simpler. Therefore, the shape of the groove 11 can be flexibly set according to the actual use requirements, and no specific limitation is made here.

[0059] In one embodiment of the present invention, the bottom of the groove 11 is provided with a textured surface, the positive electrode 6 is disposed on the textured surface, and the back passivation layer 5 covers the textured surface. The textured surface at the bottom of the groove 11 can be obtained by a texturing process. Because the bottom of the groove 11 is provided with a textured surface, the positive electrode 6 forms an ohmic contact with the textured surface, which improves the ohmic contact effect between the positive electrode 6 and the P-type silicon wafer 1; moreover, it allows the back passivation layer 5 covering the P+ doped region 3 to adhere more stably to the P+ doped region 3, achieving a good passivation effect.

[0060] As an embodiment of the present invention, the width of the groove 11 is 300-600um, the depth of the groove 11 is 0.3-10um, and the distance between two adjacent grooves 11 is 20-500um. This ensures that the P+ doped region 3 and the N+ doped region 4 maintain a good isolation effect, avoids contact leakage between the P+ doped region 3 and the N+ doped region 4, and facilitates the processing of the groove 11.

[0061] As an embodiment of the present invention, the velvet structure 10 and the rough texture structure 71 can be irregular sawtooth texture, hemispherical texture or pyramidal texture.

[0062] In this embodiment of the invention, by setting a textured structure 10 on the back side of the P-type silicon wafer 1 at the position corresponding to the negative electrode 7, a textured structure will also be formed at the position of the textured structure on the P-type silicon wafer 1 when the tunneling oxide layer 41 is prepared; when N+ doped polysilicon 42 is prepared on top of the tunneling oxide layer 41, a textured structure will also be formed at the position of the textured structure on the tunneling oxide layer 41; when the back passivation layer 5 is prepared, a textured structure will also be formed at the position of the textured structure on the N+ doped polysilicon 42. That is, a textured structure is set on the back side of the P-type silicon wafer 1, the tunneling oxide layer 41, the N+ doped polysilicon 42, and the back passivation layer 5 at the position corresponding to the negative electrode 7. In this way, after the negative electrode 7 is screen-printed with silver paste, the silver paste is sintered at high temperature, and the silver... The slurry is ablated at high temperature to form a textured back passivation layer 5. This causes the sintered negative electrode 7 to form a rough textured structure 71 at one end inside the N+ doped polycrystalline silicon 42, which is roughly the same shape as the textured structure of the back passivation layer 5. The negative electrode 7 forms an ohmic contact with the N+ doped polycrystalline silicon 42 through the rough textured structure 71, which increases the contact area between the negative electrode 7 and the N+ doped polycrystalline silicon 42, thereby forming a good ohmic contact between the negative electrode 7 and the N+ doped polycrystalline silicon 42 and improving the battery efficiency.

[0063] Moreover, the P-type back-contact crystalline silicon solar cell of this invention only requires adding a texturing process before the preparation of the tunneling oxide layer 41 in the traditional P-type back-contact crystalline silicon solar cell process. This allows the back side of the P-type silicon wafer 1, the tunneling oxide layer 41, the N+ doped polycrystalline silicon 42, and the back passivation layer 5 to all have a texturized structure. This enables the negative electrode 7 after printing and sintering to form a rough textured structure to achieve good ohmic contact with the N+ doped polycrystalline silicon 42. The implementation process is simple and the cost is low.

[0064] As an embodiment of the present invention, the width of the textured structure 10 on the back side of the P-type silicon wafer 1 corresponding to the position of the negative electrode 7 is 80-200um, so that the tunneling oxide layer 41, the N+ doped polysilicon 42 and the back passivation layer 5 are all textured with a width of 80-200um. This allows the negative electrode 7 obtained by printing and sintering to form a rough textured structure 71 of appropriate width at one end inside the N+ doped polysilicon 42, so as to further improve the ohmic contact effect between the negative electrode 7 and the N+ doped polysilicon 42.

[0065] As an embodiment of the present invention, the thickness of N+ doped polycrystalline silicon 42 is controlled at 50-350nm to ensure good battery efficiency.

[0066] As an embodiment of the present invention, the sheet resistance of the N+ doped polysilicon 42 is 50-200Ω / sqr, which can enable the negative electrode 7 to form a good ohmic contact with the N+ doped polysilicon 42.

[0067] In one embodiment of the present invention, the thickness of the tunneling oxide layer 41 is 1-5 nm, which gives the tunneling oxide layer 41 a good passivation effect. The tunneling oxide layer 41 is a silicon oxide layer.

[0068] This invention provides a P-type back-contact crystalline silicon solar cell. By setting a textured structure 10 on the back side of the P-type silicon wafer 1 corresponding to the position of the negative electrode 7, the negative electrode 7, obtained by printing and sintering in the P-type back-contact crystalline silicon solar cell, forms a rough textured structure 71 corresponding to the textured surface, which forms an ohmic contact with the N+ doped polycrystalline silicon 42. This rough textured structure significantly increases the contact area between the negative electrode 7 and the N+ doped polycrystalline silicon 42, thereby forming a good ohmic contact and improving cell efficiency. Furthermore, by simply adding a texturing process before preparing the tunneling oxide layer 41, textured structures can be formed on the back side of the P-type silicon wafer 1, the tunneling oxide layer 41, the N+ doped polycrystalline silicon 42, and the back passivation layer 5 of the P-type back-contact crystalline silicon solar cell. This allows the printed and sintered negative electrode 7 to form a rough textured structure to achieve a good ohmic contact with the N+ doped polycrystalline silicon 42. This method is simple and low-cost.

[0069] Example 2

[0070] Please refer to the reference. Figure 2 This embodiment also provides a method for preparing the P-type back-contact crystalline silicon solar cell of the above embodiment one, comprising:

[0071] Step S1, Polishing: Select P-type silicon wafer 1 and polish it.

[0072] As an embodiment of the present invention, polishing the P-type silicon wafer 1 specifically includes:

[0073] The P-type silicon wafer 1 is polished using an alkaline solution with a concentration of 1.5-15%, and the reflectivity of the polished P-type silicon wafer 1 is controlled at 38%-45%. The alkaline solution can be a KOH solution or a NaOH solution.

[0074] Step S2, First texturing: Texturing is performed on the back of the P-type silicon wafer 1 at the position corresponding to the position where the negative electrode 7 is prepared to form a textured surface structure 10;

[0075] In this embodiment of the invention, a textured structure 10 is formed on the back of the P-type silicon wafer 1 at the location where the negative electrode 7 is prepared. This ensures that the subsequently prepared tunneling oxide layer 41, N+ doped polysilicon 42, and back passivation layer 5 all have textured structures. After the negative electrode 7 is screen-printed with silver paste, the silver paste is sintered at high temperature. After sintering, a rough textured structure 71 with approximately the same textured shape as the back passivation layer 5 is formed at one end of the negative electrode 7 inside the N+ doped polysilicon 42. The negative electrode 7 forms an ohmic contact with the N+ doped polysilicon 42 through the rough textured structure 71, which greatly increases the contact area between the negative electrode 7 and the N+ doped polysilicon 42, thereby forming a good ohmic contact between the negative electrode 7 and the N+ doped polysilicon 42 and improving the battery efficiency.

[0076] In this embodiment of the invention, the weight reduction of the silicon wafer after the first texturing is controlled at 0.1g-0.3g, and the reflectivity is controlled at 8%-12%, so as to facilitate the subsequent preparation of the tunneling oxide layer 41.

[0077] As an embodiment of the present invention, step S2 specifically includes:

[0078] A mask is fabricated on the back side of P-type silicon wafer 1;

[0079] A laser ablation etching mask is applied to the back of the P-type silicon wafer 1 at the location where the negative electrode 7 is fabricated, so as to expose the P-type silicon wafer 1.

[0080] A textured surface structure 10 is formed in the laser ablation area on the back of the P-type silicon wafer 1, and the mask in the non-laser ablation area is removed by acid washing.

[0081] As an embodiment of the present invention, a silicon oxide mask is specifically deposited by PECVD, and the mask thickness is controlled between 80-200nm.

[0082] In this embodiment, a mask is first prepared on the back side of the P-type silicon wafer 1 to protect the non-laser ablation area, ensuring that the non-laser ablation area remains polished. This guarantees that the first texturing process is performed only on the back side of the P-type silicon wafer 1 at the location corresponding to the preparation of the negative electrode 7. Simultaneously, after texturing is completed, the mask on the back side of the silicon wafer is removed using an acidic solution. The mask is a silicon oxide mask. Specifically, the acidic solution can be HF.

[0083] Step S3, prepare tunneling oxide layer 41: prepare tunneling oxide layer 41 on the back side of P-type silicon wafer 1;

[0084] In this step, a tunneling oxide layer 41 is prepared on the back side of the P-type silicon wafer 1. The tunneling oxide layer 41 is used to passivate the back side of the silicon wafer to improve the passivation capability of the battery. Specifically, the tunneling oxide layer 41 can be prepared by oxidizing the surface of the P-type silicon wafer 1 using a wet process or a thermal oxidation technique.

[0085] In one embodiment of the present invention, the thickness of the tunneling oxide layer 41 is controlled to be 1-5 nm. Specifically, the tunneling oxide layer 41 is a silicon oxide layer.

[0086] Step S4, Preparation of N+ doped polycrystalline silicon 42: N+ doped polycrystalline silicon 42 is prepared on the back side of the P-type silicon wafer 1;

[0087] In a preferred embodiment of the present invention, N+ doped polycrystalline silicon 42 is specifically obtained through a deposition process.

[0088] As an embodiment of the present invention, the thickness of N+ doped polycrystalline silicon 42 is controlled between 50-350 nm.

[0089] As an embodiment of the present invention, the sheet resistance of the N+ doped polycrystalline silicon 42 is controlled at 50-200Ω / sqr, which enables the subsequently prepared negative electrode 7 to form a good ohmic contact with the N+ doped polycrystalline silicon 42.

[0090] As an embodiment of the present invention, step S4 specifically includes:

[0091] N+-doped amorphous silicon is deposited on the back side of a P-type silicon wafer 1, and the N+-doped amorphous silicon is crystallized at high temperature into N+-doped polycrystalline silicon 42; or,

[0092] Intrinsic amorphous silicon is deposited on the back side of a P-type silicon wafer 1, and phosphorus diffusion is performed on the intrinsic amorphous silicon to obtain N+ doped amorphous silicon. At the same time, the N+ doped amorphous silicon is crystallized at high temperature to form N+ doped polycrystalline silicon 42.

[0093] In this embodiment, the N+-doped polycrystalline silicon 42 can be prepared by directly depositing N+-doped amorphous silicon on the back side of a P-type silicon wafer 1 using LPCVD or PECVD, and then annealing the wafer at high temperature to crystallize the N+-doped amorphous silicon into N+-doped polycrystalline silicon 42. Alternatively, intrinsic amorphous silicon can be deposited on the back side of a P-type silicon wafer 1 first using LPCVD or PECVD, and then N+-doped amorphous silicon can be obtained by phosphorus diffusion process on the intrinsic amorphous silicon. The wafer can then be annealed at high temperature to crystallize the N+-doped amorphous silicon into N+-doped polycrystalline silicon 42.

[0094] Step S5, Second texturing: Texturing is performed on the front side of the P-type silicon wafer 1 to form a textured surface;

[0095] In this embodiment of the invention, a textured surface is formed on the front side of the P-type silicon wafer 1 to reduce the reflection of sunlight on the front side of the silicon wafer.

[0096] In this embodiment of the invention, the weight reduction of the silicon wafer after the second texturing is controlled at 0.2g-0.5g, and the reflectivity is controlled at 8%-12%.

[0097] As an embodiment of the present invention, the second flocking step further includes:

[0098] A texturing process is performed on the back side of the P-type silicon wafer 1 at the location where the positive electrode 6 is fabricated, forming a textured surface.

[0099] In this embodiment, after the positive electrode 6 is printed and sintered, it forms an ohmic contact with the textured surface on the back of the P-type silicon wafer 1. This can improve the ohmic contact effect between the positive electrode 6 and the P-type silicon wafer 1. Moreover, it can make the back passivation layer 5 covering the P+ doped region 3 more stably attached to the P+ doped region 3, achieving a good passivation effect.

[0100] As an embodiment of the present invention, before the second texturing step, a groove 11 is formed on the back side of the P-type silicon wafer 1 at the position corresponding to the formation of the positive electrode 6. The number of grooves 11 is equal to the number of P+ doped regions 3. The grooves 11 can be formed before the polishing step, or before any step prior to the second texturing step.

[0101] The bottom of the groove 11 is used to set the P+ doped region 3, so that the P+ doped region 3 is separated from the N+ doped region 4 by the groove 11, avoiding contact leakage between the P+ doped region 3 and the N+ doped region 4, thereby improving battery safety and efficiency. The positive electrode 6 is prepared at the bottom of the groove 11. By texturing the bottom of the groove 11 to form a textured surface, the positive electrode 6 can form an ohmic contact with the textured surface after printing and sintering.

[0102] As an embodiment of the present invention, the width of the groove 11 is controlled at 300-600um, the depth of the groove 11 is controlled at 0.3-10um, and the distance between adjacent grooves 11 is 20-500um, which not only maintains a good isolation effect between the P+ doped region 3 and the N+ doped region 4, but also facilitates the processing of the groove 11.

[0103] As an embodiment of the present invention, the second flocking step specifically includes:

[0104] A mask is fabricated on the back side of P-type silicon wafer 1;

[0105] A laser local ablation etching mask is used to expose the P-type silicon wafer 1 by fabricating a corresponding positive electrode on the back side.

[0106] Textured surfaces are formed in the laser ablation areas on the front and back sides of P-type silicon wafer 1, and the mask in the non-laser ablation areas is removed by acid washing.

[0107] Specifically, in the second texturing process, the laser ablation area on the back of the P-type silicon wafer 1 is located at the bottom of the groove 11. That is, the mask is removed by laser ablation at the bottom of the groove 11 so that texturing can be performed in the laser ablation area to form a textured surface, which makes it easier for the positive electrode 6 to be printed on the textured surface at the bottom of the groove 11.

[0108] In this embodiment, a mask is first prepared on the back side of the P-type silicon wafer 1 to protect the areas not covered by the second texturing process. This ensures that the second texturing process is performed only on the laser ablation areas of the front and back sides of the P-type silicon wafer 1. After the second texturing process is completed, a textured surface is formed on the laser ablation areas of the front and back sides of the P-type silicon wafer 1. Simultaneously, after texturing is completed, the mask on the back side of the silicon wafer is removed using an acidic solution. This mask is a silicon oxide mask. Specifically, the acidic solution can be HF.

[0109] Step S6, prepare passivation antireflection layer 2 and back passivation layer 5: prepare passivation antireflection layer 2 on the front side of P-type silicon wafer 1 and prepare back passivation layer 5 on the back side of P-type silicon wafer 1.

[0110] In this embodiment of the invention, by preparing a passivation antireflection layer 2 on the front side of a P-type silicon wafer 1, surface recombination of the silicon wafer is reduced, and the reflection of sunlight is decreased.

[0111] As an embodiment of the present invention, the thickness of the passivation antireflection layer 2 is controlled at 80-150 nm.

[0112] As an embodiment of the present invention, the thickness of the back passivation layer 5 is controlled at 60-150nm and the refractive index is controlled at 2-2.5, so as to achieve better passivation on the back of the silicon wafer and increase the absorption and utilization of light by the silicon wafer.

[0113] Step S7, laser grooving: Laser grooving is performed on the back of the P-type silicon wafer 1 at the position corresponding to the position where the positive electrode 6 is prepared, so as to expose the P-type silicon wafer 1;

[0114] In this step, laser grooving is performed on the back side of the P-type silicon wafer 1 at the location corresponding to the positive electrode 6, and the back passivation layer 5 is etched using laser to expose the back side of the P-type silicon wafer 1. This allows the aluminum paste printed at the laser-grooved location to form an ohmic contact with the P-type silicon wafer 1. The groove width of the laser grooving is 28-45 μm.

[0115] Step S8, positive and negative electrode printing and sintering: a negative electrode 7 is printed using silver paste at the first texturing position on the back of the P-type silicon wafer 1, and a positive electrode 6 is printed using aluminum paste at the laser grooving position on the back of the P-type silicon wafer 1, and then sintered and dried, so that a P+ doped region 3 is formed between the positive electrode 6 and the P-type silicon wafer 1, and a rough textured structure 71 is formed by the negative electrode 7 to form an ohmic contact with the N+ doped polysilicon 42.

[0116] In this step, the negative electrode 7 is screen-printed on the back passivation layer 5 at the first texturing position on the back of the P-type silicon wafer 1 using silver paste. Since a textured structure 10 is formed at the location on the back of the P-type silicon wafer 1 corresponding to the formation of the negative electrode 7, the tunneling oxide layer 41, the N+-doped polycrystalline silicon 42, and the back passivation layer 5 all have textured structures at the corresponding texturing positions on the back of the P-type silicon wafer 1. After screen-printing the negative electrode 7 on the back passivation layer 5 using silver paste, the silver paste is sintered at high temperature. The sintered negative electrode 7 forms a rough textured structure 71 inside the N+-doped polycrystalline silicon 42. This rough textured structure can be an irregular sawtooth pattern, a hemispherical pattern, or a pyramidal pattern. The negative electrode 7 forms an ohmic contact with the N+-doped polycrystalline silicon 42 through the rough textured structure 71, greatly increasing the contact area between the negative electrode 7 and the N+-doped polycrystalline silicon 42, thereby forming a good ohmic contact between the negative electrode 7 and the N+-doped polycrystalline silicon 42 and improving battery efficiency.

[0117] In this step, when the aluminum paste used to print the positive electrode 6 is sintered at high temperature, aluminum atoms in the aluminum paste can be incorporated into the P-type silicon wafer 1 in a certain proportion for doping, so as to form the P+ doped region 3 of aluminum doping in the P-type silicon wafer 1. This can reduce carrier recombination on the back of the cell, increase the open circuit voltage, and thus improve the photoelectric conversion efficiency of the P-type back contact crystalline silicon solar cell.

[0118] As an embodiment of the present invention, the sintering temperature is 300-900℃, which can ensure the sintering of the positive electrode 6 and the negative electrode 7, and avoid the damage of high temperature to the tunneling oxide layer 41 and polycrystalline silicon.

[0119] The method for fabricating a P-type back-contact crystalline silicon solar cell provided in this invention adds a texturing process before fabricating the tunneling oxide layer. This process forms a textured structure on the back of the P-type silicon wafer, the tunneling oxide layer, the N+-doped polycrystalline silicon, and the back passivation layer corresponding to the negative electrode positions. This allows the negative electrode after printing and sintering to form a rough textured structure. The rough textured structure enables the negative electrode to achieve good ohmic contact with the N+-doped polycrystalline silicon, improving the cell efficiency. Furthermore, the process is simple and cost-effective.

[0120] Example 3

[0121] This invention also provides a solar cell module, which includes the P-type back-contact crystalline silicon solar cell described in Embodiment 1 above.

[0122] In this embodiment, the solar cell module is equipped with a P-type back-contact crystalline silicon solar cell as described in Embodiment 1. The negative electrode of the P-type back-contact crystalline silicon solar cell forms an ohmic contact with N+-doped polycrystalline silicon through a rough textured structure, which increases the contact area between the negative electrode and the N+-doped polycrystalline silicon. This results in a good ohmic contact between the negative electrode and the N+-doped polycrystalline silicon, improving cell efficiency and thus enhancing the power generation efficiency of the solar cell module.

[0123] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A P-type back-contact crystalline silicon solar cell, characterized in that, Includes a P-type silicon wafer, wherein a passivation antireflection layer is disposed on the front side of the P-type silicon wafer; The back side of the P-type silicon wafer is provided with a P+ doped region, an N+ doped region, a back passivation layer, a positive electrode, and a negative electrode. The P+ doped region and the N+ doped region are distributed alternately. The back passivation layer covers the P+ doped region and the N+ doped region. The N+ doped region includes a tunneling oxide layer disposed on the back side of the P-type silicon wafer and N+ doped polysilicon disposed on the tunneling oxide layer. The positive electrode forms an ohmic contact with the P+ doped region, and the negative electrode forms an ohmic contact with the N+ doped polysilicon. A textured structure is provided on the back side of the P-type silicon wafer corresponding to the position of the negative electrode. A rough textured structure is provided on the negative electrode corresponding to the position of the textured structure to form an ohmic contact with the N+ doped polysilicon. The width of the textured structure is 80-200 μm, and the sheet resistance of the N+ doped polysilicon is 50-200 Ω / sqr. The back side of the P-type silicon wafer is provided with grooves corresponding to the number of P+ doped regions. Each P+ doped region is disposed at the bottom of a groove. The bottom of the groove is provided with a textured surface. The positive electrode is disposed on the textured surface, and the back passivation layer covers the textured surface.

2. The P-type back-contact crystalline silicon solar cell according to claim 1, characterized in that, The groove has a width of 300-600 μm, a depth of 0.3-10 μm, and a distance of 20-500 μm between two adjacent grooves.

3. A P-type back-contact crystalline silicon solar cell according to claim 1, characterized in that, The thickness of the tunneling oxide layer is 1-5 nm.

4. A P-type back-contact crystalline silicon solar cell according to claim 1, characterized in that, The passivation antireflection layer and the back passivation layer are one or more combinations of aluminum oxide film, silicon nitride film, and silicon oxynitride film.

5. A method for fabricating a P-type back-contact crystalline silicon solar cell, characterized in that, Includes the following steps: Polishing: P-type silicon wafers are selected and polished. First texturing: Texturing is performed on the back of the P-type silicon wafer at the location where the negative electrode is prepared to form a textured surface structure, the width of which is 80-200um; Preparation of tunneling oxide layer: A tunneling oxide layer is prepared on the back side of the P-type silicon wafer; Preparation of N+ doped polycrystalline silicon: N+ doped polycrystalline silicon is prepared on the back side of the P-type silicon wafer, and the sheet resistance of the N+ doped polycrystalline silicon is 50-200Ω / sqr; Second texturing: Texturing is performed on the front side of the P-type silicon wafer to form a textured surface, and texturing is performed on the back side of the P-type silicon wafer at the position corresponding to the preparation of the positive electrode to form a textured surface; Fabrication of passivation antireflection layer and back passivation layer: A passivation antireflection layer is fabricated on the front side of the P-type silicon wafer, and a back passivation layer is fabricated on the back side of the P-type silicon wafer; Laser grooving: Laser grooving is performed on the back of the P-type silicon wafer at the position where the positive electrode is formed, so as to expose the P-type silicon wafer; Printing and sintering of positive and negative electrodes: A negative electrode is printed using silver paste at the first texturing position on the back of the P-type silicon wafer, and a positive electrode is printed using aluminum paste at the laser grooving position on the back of the P-type silicon wafer. The electrodes are then sintered and dried to form a P+ doped region between the positive electrode and the P-type silicon wafer. The negative electrode forms a rough textured structure that forms an ohmic contact with the N+ doped polysilicon.

6. The method for fabricating a P-type back-contact crystalline silicon solar cell according to claim 5, characterized in that, The polishing process of the P-type silicon wafer specifically includes: The P-type silicon wafer is polished using an alkaline solution with a concentration of 1.5-15%, and the reflectivity of the polished P-type silicon wafer is controlled at 38%-45%.

7. The method for fabricating a P-type back-contact crystalline silicon solar cell according to claim 5, characterized in that, The first fabrication process includes: A mask is fabricated on the back side of the P-type silicon wafer; A laser ablation etching mask is applied to the back of the P-type silicon wafer at the location where the negative electrode is fabricated, to expose the P-type silicon wafer. A texturing structure is formed in the laser ablation area on the back of the P-type silicon wafer, and the mask in the non-laser ablation area is removed by acid washing.

8. The method for fabricating a P-type back-contact crystalline silicon solar cell according to claim 5, characterized in that, The thickness of the tunneling oxide layer is controlled between 1 and 5 nm.

9. The method for fabricating a P-type back-contact crystalline silicon solar cell according to claim 5, characterized in that, The thickness of the N+ doped polycrystalline silicon is controlled between 50-350 nm.

10. The method for fabricating a P-type back-contact crystalline silicon solar cell according to claim 5, characterized in that, The second texturing step specifically includes: A mask is fabricated on the back side of the P-type silicon wafer; A laser-guided local ablation etching mask is used to expose the P-type silicon wafer at the location corresponding to the positive electrode on the back side. Texturing is performed on the laser ablation areas of the front and back sides of the P-type silicon wafer to form a textured surface, and the mask in the non-laser ablation areas is removed by acid washing.

11. The method for fabricating a P-type back-contact crystalline silicon solar cell according to claim 5, characterized in that, The specific steps for preparing N+-doped polycrystalline silicon include: N+-doped amorphous silicon is deposited on the back side of a P-type silicon wafer, and the N+-doped amorphous silicon is then crystallized at high temperature into N+-doped polycrystalline silicon; or, Intrinsic amorphous silicon is deposited on the back side of a P-type silicon wafer, and phosphorus diffusion is performed on the intrinsic amorphous silicon to obtain N+-doped amorphous silicon. At the same time, the N+-doped amorphous silicon is crystallized at high temperature to form N+-doped polycrystalline silicon.

12. A solar cell module, characterized in that, Including the P-type back-contact crystalline silicon solar cell as described in any one of claims 1-4.

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