Display device and electronic equipment

Abstract

A display device with low power consumption is provided. The display device includes a circuit that steps up a signal voltage output from a gate driver. Since the signal voltage of the gate driver can be stepped up and supplied to a pixel, driving of a display device with a high threshold voltage is facilitated. Further, by utilizing the step-up function, the output of the gate driver can be reduced to suppress power consumption. In addition, by combining with a pixel having a step-up function of image data, a display device with even lower power consumption can be realized.

Description

Technical Field

[0001] One aspect of the present invention relates to a display device.

[0002] Note that one aspect of the present invention is not limited to the aforementioned technical fields. The technical field of one aspect of the invention disclosed in this specification relates to an object, method, or manufacturing method. Furthermore, one aspect of the present invention relates to a process, machine, manufacture, or composition of matter. Therefore, more specifically, examples of the technical field of one aspect of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, lighting devices, energy storage devices, memory devices, imaging devices, methods of operating these devices, or methods of manufacturing these devices.

[0003] Note that in this specification, etc., a semiconductor device refers to any device capable of operating by utilizing the characteristics of semiconductors. Transistors and semiconductor circuits are one type of semiconductor device. Additionally, storage devices, display devices, imaging devices, and electronic devices sometimes include semiconductor devices. Background Technology

[0004] The operation of pixels in a display device requires a signal voltage with appropriate amplitude, and sometimes a higher voltage is needed to activate the pixel's transistors. For example, Patent Document 1 discloses a technique for boosting the output voltage of a gate driver.

[0005] Techniques for constructing transistors using metal oxides formed on a substrate have attracted attention. For example, Patent Documents 2 and 3 disclose a technique for using transistors using zinc oxide or In-Ga-Zn type oxides as switching elements for pixels in display devices.

[0006] In addition, Patent Document 4 discloses a memory device having a structure that uses transistors with extremely low off-state current in memory cells.

[0007] [Preliminary Technology Documents]

[0008] [Patent Literature]

[0009] [Patent Document 1] Japanese Patent Application Publication No. Hei 5-281517

[0010] [Patent Document 2] Japanese Patent Application Publication No. 2007-123861

[0011] [Patent Document 3] Japanese Patent Application Publication No. 2007-96055

[0012] [Patent Document 4] Japanese Patent Application Publication No. 2011-119674 Summary of the Invention

[0013] The technical problem that the invention aims to solve

[0014] Display devices are used in various electronic devices. One method to achieve low power consumption in electronic devices is to operate the display device at low voltage.

[0015] On the other hand, sometimes high voltages are required depending on the type of display device (also called display element) disposed in the pixel or the driving method. When the voltage of the image data is high, a higher signal voltage needs to be supplied to the gate of the transistor that controls the writing of the image data. In this case, low power consumption is also desired.

[0016] Furthermore, even when image data is written to pixels at a lower voltage, the display device still needs to be properly operated.

[0017] Therefore, one objective of this invention is to provide a low-power display device. Another objective of this invention is to provide a display device capable of supplying a voltage higher than the output voltage of the gate driver to the pixels. Furthermore, one objective of this invention is to provide a display device that operates using a low-cost driver. Additionally, one objective of this invention is to provide a display device capable of improving the brightness of the displayed image.

[0018] Furthermore, one objective of the present invention is to provide a display device with high reliability. Another objective of the present invention is to provide a novel display device, etc. Another objective of the present invention is to provide a method of operating the aforementioned display device. Another objective of the present invention is to provide a novel semiconductor device, etc.

[0019] Note that the description of these objectives does not preclude the existence of other objectives. Note that one embodiment of the invention does not necessarily require achieving all of the above objectives. Note that objectives other than those described above can be understood and extracted from the description, drawings, claims, etc.

[0020] means of solving technical problems

[0021] One aspect of the present invention relates to a low-power display device.

[0022] One aspect of the present invention is a display device comprising: a shift register; a boost circuit; and a pixel, wherein the shift register includes a first output terminal, a second output terminal, and a third output terminal; the boost circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor; the pixel includes a fifth transistor; one of the source and drain of the first transistor is electrically connected to one electrode of the first capacitor; one electrode of the first capacitor is electrically connected to one of the source and drain of the third transistor; one of the source and drain of the third transistor is electrically connected to the gate of the fifth transistor; the other electrode of the first capacitor is electrically connected to one of the source and drain of the second transistor and one of the source and drain of the fourth transistor; the gates of the first transistor and the fourth transistor are electrically connected to the first output terminal; the gate of the second transistor is electrically connected to the second output terminal; and the gate of the third transistor is electrically connected to the third output terminal.

[0023] The shift register can output signal voltages sequentially in the order of the first output terminal, the second output terminal, and the third output terminal.

[0024] The boost circuit may also include a sixth transistor and a second capacitor. One of the source and drain of the sixth transistor may be electrically connected to the first output terminal, and the other of the source and drain of the sixth transistor may be electrically connected to one electrode of the second capacitor and the gate of the first transistor. The other electrode of the second capacitor may be electrically connected to one of the source and drain of the first transistor.

[0025] The boost circuit may also include a seventh transistor, an eighth transistor, and a third capacitor. The gate of the seventh transistor may be electrically connected to the third output terminal. One of the source and drain of the seventh transistor may be electrically connected to one electrode of the third capacitor and one of the source and drain of the eighth transistor. The gate of the eighth transistor may be electrically connected to the first output terminal.

[0026] The other of the source and drain of the third transistor can be electrically connected to the other of the source and drain of the fourth transistor.

[0027] A pixel may include a display element, and the pixel may have the function of generating third data based on first data and second data, and the function of being displayed by the display element based on the third data. A liquid crystal device may be used as a display element.

[0028] Preferably, the boost circuit and the transistors included in the pixel contain metal oxide in the channel forming region, and the metal oxide contains In, Zn, or M (M is Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf).

[0029] Invention Effects

[0030] A low-power display device can be provided by means of the present invention. Furthermore, a display device capable of supplying a voltage higher than the output voltage of the gate driver to the pixels can be provided by means of the present invention. Additionally, a display device operating with a low-cost driver can be provided by means of the present invention. Furthermore, a display device capable of improving the brightness of the displayed image can be provided by means of the present invention.

[0031] Furthermore, a highly reliable display device can be provided by using one aspect of the present invention. Additionally, a novel display device can be provided by using one aspect of the present invention. Furthermore, a method for operating the aforementioned display device can be provided by using one aspect of the present invention. Additionally, an objective of one aspect of the present invention is to provide a novel semiconductor device, etc. Attached Figure Description

[0032] Figure 1 This is a diagram illustrating a display device.

[0033] Figure 2A This is a diagram illustrating a boost circuit. Figure 2B This is a timing diagram illustrating the operation of a boost circuit.

[0034] Figure 3A , Figure 3B This is a diagram illustrating a boost circuit.

[0035] Figure 4 This is a diagram illustrating a boost circuit.

[0036] Figure 5 This is a timing diagram illustrating the operation of a boost circuit.

[0037] Figure 6A This is a diagram illustrating a boost circuit. Figure 6B This is a timing diagram illustrating the operation of a boost circuit.

[0038] Figure 7 This is a diagram illustrating a boost circuit.

[0039] Figures 8A to 8C This diagram illustrates other methods of boost circuit design and other connection methods for boost circuits.

[0040] Figure 9A , Figure 9B This is a diagram illustrating the pixel circuit.

[0041] Figures 10A to 10D It is a diagram illustrating the circuitry, including the display device.

[0042] Figures 11A to 11D It is a diagram illustrating the circuitry, including the display device.

[0043] Figure 12 This is a diagram illustrating other ways of using a transistor.

[0044] Figure 13 It is a diagram illustrating the circuit used for simulation.

[0045] Figure 14 This is a graph illustrating the simulation results.

[0046] Figures 15A to 15C This is a diagram illustrating a display device.

[0047] Figure 16A , Figure 16B This is a diagram illustrating the touch panel.

[0048] Figure 17A , Figure 17B This is a diagram illustrating a display device.

[0049] Figure 18 This is a diagram illustrating a display device.

[0050] Figure 19A , Figure 19B This is a diagram illustrating a display device.

[0051] Figure 20A , Figure 20B This is a diagram illustrating a display device.

[0052] Figures 21A to 21E This is a diagram illustrating a display device.

[0053] Figures 22A1 to 22C2 This is a diagram illustrating a transistor.

[0054] Figures 23A1 to 23C2 This is a diagram illustrating a transistor.

[0055] Figures 24A1 to 24C2 This is a diagram illustrating a transistor.

[0056] Figures 25A1 to 25C2 This is a diagram illustrating a transistor.

[0057] Figures 26A to 26F It is a diagram illustrating an electronic device. Detailed Implementation

[0058] The embodiments will be described in detail with reference to the accompanying drawings. Note that the invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as limited only to the embodiments described below. Note that in the structure of the invention described below, the same reference numerals are used in different drawings to denote the same parts or parts having the same function, and repeated descriptions are omitted. Note that sometimes the shading of the same constituent elements is appropriately omitted or changed in different drawings.

[0059] Furthermore, even if something is considered a single element on a circuit diagram, it can be constructed using multiple elements if there are no functional problems. For example, multiple transistors used as switches can sometimes be connected in series or parallel. Additionally, capacitors are sometimes segmented and configured in multiple locations.

[0060] Furthermore, sometimes a single conductor serves multiple functions, such as wiring, electrodes, and terminals; therefore, multiple names may be used for the same element in this specification. Additionally, even when elements are shown as directly connected in a circuit diagram, they may actually be connected via one or more conductors; this type of connection is also included in the scope of direct connections in this specification.

[0061] (Implementation Method 1)

[0062] In this embodiment, a display device according to one aspect of the present invention will be described with reference to the accompanying drawings.

[0063] One aspect of the present invention is a display device including circuitry that boosts the signal voltage output by the gate driver. Since the signal voltage of the gate driver can be boosted and supplied to the pixels, it is suitable for driving display devices with high threshold voltages. Furthermore, by utilizing the boost function, the output suppression power consumption of the gate driver can be reduced.

[0064] Furthermore, by combining a circuit that boosts the signal voltage output by the gate driver with a pixel that has an image data boosting function, a low-power display device can be realized. This structure allows for the use of universal drivers for both the source and gate drivers, even when the pixel circuitry requires high voltage, thus enabling a low-cost display device.

[0065] <Display Device>

[0066] Figure 1This diagram illustrates a display device according to one aspect of the present invention. The display device includes a plurality of pixels 10, a circuit 13, a source driver 11, and a gate driver 12. The source driver 11 is electrically connected to the pixels 10. The gate driver 12 is electrically connected to the circuit 13. The circuit 13 is electrically connected to the pixels 10.

[0067] Pixel 10 includes transistor 101 and circuit 21. Circuit 21 includes a display device. Furthermore, circuit 21 may also include transistors, capacitors, etc., as needed. The gate of transistor 101 is electrically connected to wiring 125. The wiring connecting transistor 101 and circuit 21 is called node NM. Note that pixel 10 may also employ other structures. Furthermore, multiple pixels 10 are arranged to form a pixel array 18.

[0068] Circuit 13 can be set for each row and can be electrically connected to pixels 10 set in the same row. Figure 1 The diagram shows the pixel 10 (pixel 10[n-1, m], pixel 10[n, m], pixel 10[n+1, m] (m and n are more than one natural number)) arranged in the m column in the nth row and the rows before and after it, and the circuit 13 (circuit 13[n-1], circuit 13[n], circuit 13[n+1]) arranged in each row.

[0069] Circuit 13 is a boost circuit and has the function of boosting the signal voltage supplied from gate driver 12 for pixel driving. Circuit 13 is electrically connected to pixel 10 via wiring 125.

[0070] Timing circuitry such as shift registers can be used in the source driver 11 and gate driver 12. Note that one or both of two or more source drivers 11 and gate drivers 12 can also drive the pixel 10. The source driver 11 is electrically connected to the pixel 10 via wiring 127.

[0071] The gate driver 12 has its output terminal 25a connected to wiring 124[n-1], output terminal 25b connected to wiring 124[n], and output terminal 25c connected to wiring 124[n+1]. The gate driver 12 includes output terminals 25a, 25b, and 25c, and can output signal voltages sequentially in the order of output terminals 25a, 25b, and 25c. Note that output terminals 25a, 25b, and 25c only need to be output terminals in a non-overlapping timing sequence. For example, in addition to the three sequentially output signal voltages, signal voltages can also be output every other output terminal or every two output terminals.

[0072] Circuit 13[n] is electrically connected to wiring 124[n-1] and wiring 124[n+1] in addition to wiring 124[n]. Circuits 13[n-1] and 13[n+1] are also electrically connected to the three output terminals of the gate driver 12 output signal voltage. Note that circuit 13 may also be configured to be electrically connected to four or more output terminals of the gate driver 12.

[0073] <Boost Circuit>

[0074] Figure 2A An example of the structure of circuit 13 is shown. Circuit 13 may include transistor 102, transistor 103, transistor 104, transistor 105, and capacitor 106. Figure 2 shows circuit 13[n] electrically connected to pixel 10 in the nth row.

[0075] One of the source and drain of transistor 102 is electrically connected to one electrode of capacitor 106. One electrode of capacitor 106 is electrically connected to one of the source and drain of transistor 104. The other electrode of capacitor 106 is electrically connected to one of the source and drain of transistor 103 and one of the source and drain of transistor 105.

[0076] The gate of transistor 102 is electrically connected to wiring 124[n-1]. The gate of transistor 103 is electrically connected to wiring 124[n]. The gate of transistor 104 is electrically connected to wiring 124[n+1]. The gate of transistor 105 is electrically connected to wiring 124[n-1]. The other of the source and drain of transistor 102 is electrically connected to wiring 121. The other of the source and drain of transistor 103 is electrically connected to wiring 121. The other of the source and drain of transistor 104 is electrically connected to wiring 122. The other of the source and drain of transistor 105 is electrically connected to wiring 122.

[0077] Wiring 121 and 122 can be used as power lines. For example, wiring 121 and wiring 122 can be used as a high-potential power line and a low-potential power line, respectively.

[0078] Here, the wiring connecting one of the source and drain of transistor 102, one electrode of capacitor 106, and one of the source and drain of transistor 104 is designated as node A. Furthermore, the wiring connecting the other electrode of capacitor 106, one of the source and drain of transistor 103, and one of the source and drain of transistor 105 is designated as node B. Node A is used as an output terminal and is electrically connected to wiring 125[n]. Additionally, the gates of transistor 102 and transistor 105, connected to wiring 124[n-1], are used as first input terminals. The gate of transistor 103, connected to wiring 124[n], is used as a second input terminal. The gate of transistor 104, connected to wiring 124[n+1], is used as a third input terminal.

[0079] <Instructions for boosting voltage>

[0080] In circuit 13, firstly, the first input terminals (the gates of transistor 102 and 105) are input with "V1" (high potential), setting the potential of node A to "V1" and the potential of node B to "V0" (low potential). At this time, capacitor 106 remains "V1-V0".

[0081] Next, the first input terminal is input with “V0”, and the second input terminal (the gate of transistor 103) is input with “V1”, causing node A to float and node B to be input with “V1”.

[0082] At this point, the capacitance value of capacitor 106 is set to C. 106 And set the capacitance value of node A to C. A At that time, the potential of node A is "V1+(C 106 / (C 106 +C A ))×(V1-V0)”. Here, in C 106 The value of C A When the value of C is sufficiently large, 106 / (C 106 +C A When the voltage is close to 1, the potential of node A becomes “2V1-V0”.

[0083] At this point, when "V0" = 0, the potential of node A is approximately the same as "2V1". Therefore, circuit 13 can be said to be able to output a potential that is approximately twice the input potential.

[0084] In summary, circuit 13 can output a boosted potential and switch the pixel's transistor on and off. Furthermore, circuit 13 outputs a potential in the next timing sequence that turns off the pixel's transistor. This potential can be input as "V1" through the third input terminal (the gate of transistor 104) and supplied to node A via wiring 122 through transistor 104.

[0085] Note that since the input of “V1” at node A or node B passes through a transistor, it is actually lower than the transistor’s threshold voltage (V1) than the potential input to the gate. th The potential of V. In this embodiment, for the sake of simplicity, V th The absolute value is assumed to be a sufficiently small value (approximately 0V), and its description is omitted.

[0086] Nodes A and B are used as holding nodes. Data can be written to each node by turning on the transistors connected to them. Furthermore, the data can be held in each node by turning off the transistors. By using transistors with extremely low off-state current, leakage current can be suppressed, thereby enabling the potential of each node to be maintained for a long time. For example, a transistor containing metal oxide in the channel formation region (hereinafter, an OS transistor) can be used.

[0087] Specifically, OS transistors are preferably used as any or all of the transistors included in circuit 13. Furthermore, OS transistors can be used in elements included in circuit 21. Additionally, when operating within an acceptable leakage current range, transistors containing Si in the channel formation region (hereinafter, Si transistors) can be used. Furthermore, OS transistors and Si transistors can be used in combination. Note that examples of Si transistors include transistors containing amorphous silicon and transistors containing crystalline silicon (microcrystalline silicon, low-temperature polycrystalline silicon, monocrystalline silicon). The above-described transistor structure can be applied to other circuits shown in this embodiment.

[0088] As semiconductor materials for OS transistors, metal oxides with a bandgap of 2 eV or higher, preferably 2.5 eV or higher, and more preferably 3 eV or higher, can be used. Typical examples include indium-containing oxide semiconductors, such as CAAC-OS or CAC-OS mentioned later. CAAC-OS has stable atoms constituting the crystal, making it suitable for transistors where reliability is critical. CAC-OS exhibits high mobility, making it suitable for transistors used in high-speed driving.

[0089] Because of the large bandgap in the semiconductor layer of an OS transistor, it exhibits extremely low off-state current characteristics, only a few μA / μm (current value per 1μm channel width). Unlike Si transistors, OS transistors do not experience impact ionization, avalanche breakdown, or short-channel effects, thus enabling the formation of highly reliable circuits. Furthermore, the electrical characteristic deviations caused by crystal inhomogeneities in Si transistors are less likely to occur in OS transistors.

[0090] As the semiconductor layer in an OS transistor, a film labeled "In-M-Zn oxide" can be used, for example, containing indium, zinc, and M (metals such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). In addition to the aforementioned In-M-Zn oxide, In oxide, In-Ga oxide, and In-Zn oxide can also be used as the semiconductor layer in an OS transistor. Note that by using a semiconductor layer with a high indium ratio, the on-state current or field-effect mobility of the OS transistor can be improved. In-M-Zn oxides can be formed, for example, using sputtering, ALD (Atomic layer deposition), or MOCVD (Metal organic chemical vapor deposition).

[0091] When forming an In-M-Zn oxide film using sputtering, it is preferable that the atomic ratio of the metal elements in the sputtering target used to form the In-M-Zn oxide film satisfies In ≥ M and Zn ≥ M. Preferred atomic ratios of the metal elements in such sputtering targets include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, and In:M:Zn = 10:1:3. Furthermore, when the oxide semiconductor constituting the semiconductor layer is an In-Zn oxide, it is preferable that the atomic ratio of the metal elements in the sputtering target used to form the In-Zn oxide film satisfies In ≥ Zn. The preferred atomic ratio of the metal elements in this sputtering target is In:M:Zn = 1:1, In:Zn = 2:1, In:Zn = 5:3, In:Zn = 10:1, In:Zn = 10:3, etc.

[0092] As the semiconductor layer, an oxide semiconductor with a low carrier concentration can be used. For example, a semiconductor layer with a carrier concentration of 1×10⁻⁶ can be used. 17 / cm 3 The following is preferred: 1×10 15 / cm 3 Hereinafter, 1×10 is more preferred. 13 / cm 3 Hereinafter, 1×10 is further preferred. 11 / cm 3 The following is a further preferred option: less than 1×10 10 / cm 3 1×10 -9 / cm 3The above refers to oxide semiconductors. Such oxide semiconductors are called high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. These oxide semiconductors have low defect level densities and are therefore considered to have stable properties.

[0093] Note that the present invention is not limited to the above description, and materials with appropriate compositions can be used according to the desired semiconductor and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. Furthermore, it is preferable to appropriately set the carrier concentration, impurity concentration, defect density, ratio of metal elements to oxygen atoms, interatomic distance, density, etc., of the semiconductor layer to obtain the desired semiconductor characteristics of the transistor.

[0094] When the oxide semiconductor constituting the semiconductor layer contains silicon or carbon, one of Group 14 elements, the oxygen defect increases, causing the semiconductor layer to become n-type. Therefore, the concentration of silicon or carbon in the semiconductor layer (measured by secondary ion mass spectrometry) is set to 2 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 17 atoms / cm 3 the following.

[0095] Furthermore, sometimes when alkali metals and alkaline earth metals bond with oxide semiconductors, charge carriers are generated, increasing the off-state current of the transistor. Therefore, the concentration of the alkali metal or alkaline earth metal in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 16 atoms / cm 3 the following.

[0096] Furthermore, when the oxide semiconductor constituting the semiconductor layer contains nitrogen, electrons are generated as charge carriers, increasing the charge carrier concentration and making it easier to achieve n-type characteristics. As a result, transistors with nitrogen-containing oxide semiconductors tend to become normally-on. Therefore, the nitrogen concentration in the semiconductor layer (the concentration measured using secondary ion mass spectrometry) is preferably 5 × 10⁻⁶. 18 atoms / cm 3 the following.

[0097] Furthermore, when the oxide semiconductor constituting the semiconductor layer contains hydrogen, the hydrogen reacts with the oxygen bonded to the metal atoms to form water, thus sometimes creating oxygen vacancies in the oxide semiconductor. When oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor tends to have always-on characteristics. Moreover, sometimes hydrogen entering the defects in the oxygen vacancies is used as a donor to generate electrons as charge carriers. Additionally, sometimes a portion of the hydrogen bonds with the oxygen bonded to the metal atoms, generating electrons as charge carriers. Therefore, transistors using oxide semiconductors containing more hydrogen tend to have always-on characteristics.

[0098] Defects where hydrogen enters oxygen vacancies can be used as donors in oxide semiconductors. However, it is difficult to quantitatively evaluate these defects. Therefore, in oxide semiconductors, evaluation is sometimes based on carrier concentration rather than donor concentration. Consequently, in this specification and the like, carrier concentration, which is assumed to be in a state where no electric field is applied, is sometimes used as a parameter for oxide semiconductors instead of donor concentration. That is to say, the "carrier concentration" described in this specification and the like can sometimes be referred to as "donor concentration".

[0099] Therefore, it is preferable to minimize the amount of hydrogen in oxide semiconductors. Specifically, in oxide semiconductors, the hydrogen concentration measured by secondary ion mass spectrometry (SIMS) is less than 1 × 10⁻⁶. 20 atoms / cm 3 Preferably less than 1×10 19 atoms / cm 3 More preferably, less than 5×10 18 atoms / cm 3 Further optimization of less than 1×10 18 atoms / cm 3 By using oxide semiconductors with sufficiently reduced impurities such as hydrogen in the channel formation region of transistors, stable electrical characteristics can be imparted.

[0100] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors. Among non-single-crystal structures, amorphous structures have the highest defect state density, while CAAC-OS has the lowest defect state density.

[0101] Amorphous oxide semiconductor films, for example, have a disordered atomic arrangement and lack crystalline components. Alternatively, amorphous oxide films can be, for example, completely amorphous structures without crystalline regions.

[0102] Furthermore, the semiconductor layer can also be a mixture of two or more regions having an amorphous structure, a microcrystalline structure, a polycrystalline structure, a CAAC-OS region, and a single-crystal structure. The mixture sometimes has, for example, a single-layer structure or a stacked structure including two or more of the aforementioned regions.

[0103] The following describes the configuration of a non-single-crystal semiconductor layer, specifically a CAC (Cloud-Aligned Composite)-OS.

[0104] CAC-OS, for example, refers to a configuration in which elements are non-uniformly distributed within an oxide semiconductor, wherein the size of the material containing the non-uniformly distributed elements is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or approximately. Note that, below, the state in which one or more metal elements are non-uniformly distributed within an oxide semiconductor and the regions containing those metal elements are mixed with a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or approximately, is also referred to as mosaic or patch-like.

[0105] The oxide semiconductor preferably contains at least indium. In particular, it preferably contains both indium and zinc. In addition, it may also contain one or more of the following: aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.

[0106] For example, CAC-OS in In-Ga-Zn oxides (in particular, In-Ga-Zn oxides can be referred to as CAC-IGZO) refers to materials that are indium oxides (hereinafter referred to as InO). X1 (X1 is a real number greater than 0) or indium zinc oxide (hereinafter referred to as In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) and gallium oxide (hereinafter referred to as GaO) X3 (X3 is a real number greater than 0) or gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 are real numbers greater than 0) etc., thus forming a mosaic pattern, and the mosaic-shaped InO X1 or In X2 ZnY2 O Z2 The composition (hereinafter also referred to as cloud-like) is uniformly distributed in the membrane.

[0107] In other words, CAC-OS is a system with GaO X3 The region with In as the main component and X2 Zn Y2 O Z2 or InO X1 A composite oxide semiconductor is formed by mixing regions that are the main components together. In this specification, for example, when the ratio of the number of In atoms to the number of elements M in the first region is greater than that in the second region, the In concentration in the first region is higher than that in the second region.

[0108] Note that IGZO is a general term, sometimes referring to compounds containing In, Ga, Zn, and O. A typical example is InGaO3 (ZnO). m1 (m1 is a natural number) or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1≤x0≤1, m0 is any number) represents a crystalline compound.

[0109] The aforementioned crystalline compounds have single-crystal, polycrystalline, or CAAC structures. The CAAC structure is a crystalline structure in which multiple IGZO nanocrystals have c-axis orientation and are connected in a non-oriented manner on the ab plane.

[0110] On the other hand, CAC-OS is related to the material composition of oxide semiconductors. CAC-OS refers to a material composition containing In, Ga, Zn, and O, in which nanoparticle-like regions dominated by Ga and nanoparticle-like regions dominated by In are observed to be randomly dispersed in a mosaic pattern in one part and in another part, respectively. Therefore, in CAC-OS, the crystal structure is a secondary factor.

[0111] CAC-OS does not contain stacked structures consisting of two or more different membranes. For example, it does not contain a structure consisting of two layers: one with In as the main component and the other with Ga as the main component.

[0112] Note that sometimes GaO cannot be observed. X3 Regions with In as the main component X2 Zn Y2 O Z2 or InO X1 Clear boundaries between regions that are the main components.

[0113] In the case where CAC-OS contains one or more of aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium to replace gallium, CAC-OS refers to a composition in which nanoparticle-like regions with the metal element as the main component are observed in one part, and nanoparticle-like regions with In as the main component are observed to be randomly dispersed in a mosaic pattern in another part.

[0114] CAC-OS can be formed, for example, by sputtering without intentionally heating the substrate. When forming CAC-OS by sputtering, one or more gases selected from inert gases (typically argon), oxygen gases, and nitrogen gases can be used as the film-forming gas. Furthermore, the lower the proportion of oxygen gas in the total flow rate of the film-forming gas during film formation, the better; for example, the oxygen gas flow rate ratio is set to 0% or more and less than 30%, preferably 0% or more and less than 10%.

[0115] CAC-OS has the following characteristics: when measured using the out-of-plane method (XRD), one of the methods for X-ray diffraction, with θ / 2θ scanning, no clear peak is observed. In other words, based on X-ray diffraction, it can be determined that there is no orientation in the ab plane direction or the c-axis direction within the measurement region.

[0116] Furthermore, in the electron diffraction pattern of CAC-OS obtained by irradiating it with an electron beam with a diameter of 1 nm (also known as a nanobeam), a ring-shaped region of high brightness (ring region) and multiple bright spots within the ring region were observed. Therefore, based on the electron diffraction pattern, it can be concluded that the crystal structure of CAC-OS has an nc (nano-crystal) structure that is unoriented in both the planar and cross-sectional directions.

[0117] Furthermore, for example, in CAC-OS of In-Ga-Zn oxides, based on EDX surface analysis images (EDX-mapping) obtained by energy dispersive X-ray spectroscopy (EDX), it can be confirmed that: it has GaO X3 Regions with In as the main component and X2 Zn Y2 O Z2 or InO X1 A mixture of components whose main components are unevenly distributed in different regions.

[0118] CAC-OS differs in structure from IGZO compounds, which have a uniform distribution of metallic elements, and thus exhibits different properties. In other words, CAC-OS possesses properties centered around GaO.X3 Regions with In as the main component and In X2 Zn Y2 O Z2 or InO X1 The regions that are the main components are separated from each other, and the regions that are the main components of each element are mosaic-like.

[0119] Here, in In X2 Zn Y2 O Z2 or InO X1 The conductivity of regions with GaO as the main component is higher than that of regions with GaO as the main component. X3 The region is dominated by components such as In. In other words, when charge carriers flow through a region dominated by In X2 Zn Y2 O Z2 or InO X1 When In is the dominant component, it exhibits the conductivity of an oxide semiconductor. Therefore, when In... X2 Zn Y2 O Z2 or InO X1 When the region that is the main component is distributed in a cloud-like manner in an oxide semiconductor, a high field-effect mobility (μ) can be achieved.

[0120] On the other hand, with GaO X3 The insulation of regions with In as the main component is higher than that of regions with In as the main component. X2 Zn Y2 O Z2 or InO X1 The region where GaO is the main component. In other words, when GaO is used... X3 When regions with these as the main components are distributed in an oxide semiconductor, leakage current can be suppressed, thus achieving good switching operation.

[0121] Therefore, when CAC-OS is used in semiconductor devices, it is due to GaO X3 The insulation properties of In and other materials and their causes X2 Zn Y2 O Z2 or InO X1 The complementary effect of conductivity can achieve high on-state current (I) on ) and high field-effect mobility (μ).

[0122] Furthermore, semiconductor components using CAC-OS exhibit high reliability. Therefore, CAC-OS is suitable as a constituent material for a wide variety of semiconductor devices.

[0123] <Example of a boost circuit in operation>

[0124] Reference Figure 2B Timing diagram explanation Figure 2AThis is an example of the operation of circuit 13 shown. Note that in the following description or timing diagram, a low potential is denoted as "L", twice the low potential is denoted as "2L", three times the low potential is denoted as "3L", a high potential is denoted as "H", twice the high potential is denoted as "2H", and three times the high potential is denoted as "3H". Furthermore, wiring 121, wiring 122, and wiring 124 are supplied with conditions of "H", "L", "H", or "L", respectively.

[0125] Note that detailed variations in potential distribution, coupling, or losses due to circuit structure, operating conditions, etc., are not considered here. Furthermore, potential changes resulting from capacitive coupling of a capacitor depend on the capacitance ratio of the capacitor to the element connected to it; however, for ease of explanation, the capacitance of the element is assumed to be sufficiently small.

[0126] At time T1, when the potential of wiring 124[n-1] becomes "H" (the potentials of wiring 124[n] and wiring 124[n+1] are "L"), transistor 102 turns on, and the potential of node A becomes "H". Additionally, transistor 105 turns on, and the potential of node B becomes "L".

[0127] At time T2, when the potential of wiring 124[n-1] becomes “L” (the potentials of wiring 124[n] and wiring 124[n+1] are both “L”), transistor 102 is not turned on, and the potential of node A remains “H”. Furthermore, transistor 105 is not turned on, and the potential of node B remains “L”.

[0128] At time T3, when the potential of wiring 124[n] becomes "H" (the potentials of wiring 124[n-1] and wiring 124[n+1] are "L"), transistor 103 is turned on, and the potential of node B changes from "L" to "H". This change is calculated by adding the capacitance ratio of capacitor 106 and node A to the potential of node A, resulting in the potential of node A becoming "H+(HL)". That is, when "L" = 0, the potential of node A becomes "2H".

[0129] At time T4, when the potential of wiring 124[n] becomes “L” (the potentials of wiring 124[n-1] and wiring 124[n+1] are “L”), transistor 103 is not turned on, and the potential of node A remains “2H”.

[0130] At time T5, when the potential of wiring 124[n+1] becomes “H” (the potentials of wiring 124[n-1] and wiring 124[n] are “L”), transistor 104 is turned on, and the potential of node A becomes “L”.

[0131] At time T6, when the potential of wiring 124[n+1] becomes “L” (the potentials of wiring 124[n-1] and wiring 124[n] are “L”), transistor 104 is not turned on, and the potential of node A remains “L”.

[0132] The writing operation to pixel 10 can be performed during the period when node A (wiring 125[n]) is supplied with a potential of "2A" (after time T3 and before time T5). Furthermore, since the potential of node A remains "L" after T5, the image signal written to pixel 10 can be maintained until the next frame (the next operation).

[0133] <Example 1 of a variation of a boost circuit>

[0134] Figure 3A A modified example of circuit 13 is shown. Figure 3A The circuit 13 shown is Figure 2A The difference in circuit 13 shown is that it includes circuit 14 and another of the source and drain of transistor 102 is electrically connected to wiring 123. Circuit 14 has the function of increasing the voltage output by circuit 13.

[0135] Circuit 14 may include transistor 107 and capacitor 108. One of the source and drain of transistor 107 is electrically connected to wiring 124[n-1]. The other of the source and drain of transistor 107 is electrically connected to one electrode of capacitor 108 and the gate of transistor 102. The other electrode of capacitor 108 is electrically connected to node A. In this configuration, one of the source and drain of transistor 107 is a first input terminal.

[0136] The gate of transistor 107 is electrically connected to wiring 121. The other of the source and drain of transistor 102 is electrically connected to wiring 123. Here, wiring 123 is a power supply line providing a potential above that of wiring 121. Note that the other of the source and drain of transistor 102 may also be electrically connected to wiring 121.

[0137] In one embodiment of the invention, circuit 13 can be given a bootstrap effect by assembling circuit 14. The bootstrap effect allows the output signal voltage to be higher than the input signal voltage.

[0138] The bootstrapping process works as follows. First, when node C (the wiring connecting the source and drain of transistor 107, one electrode of capacitor 108, the gate of transistor 102, and the gate of transistor 105) is input a potential "H" through transistor 107, current flows through transistor 102 until the potential of node A rises from "L" to "H". At this time, the potential of node C rises above "H" through the capacitive coupling of capacitor 108, so transistor 102 allows current to flow further, causing the potential of node A to rise further.

[0139] Note that one of the source and drain terminals and the gate of transistor 107 is supplied with a potential "H", while the potential of the other terminal (node ​​C) of transistor 107 is higher than "H", and no current flows through transistor 107. That is, transistor 107 is used as a diode. The structure including circuit 14 can be applied to other circuits shown in this embodiment.

[0140] Figure 3A The circuit 13 shown can be based on Figure 2B The timing diagram shown is operational. Note that, as described above, the potential of node A can be adjusted from time T1 to T5. Figure 2B Circuit 13 is high.

[0141] <Example 2 of a variation of a boost circuit>

[0142] Figure 3B Other variations of circuit 13 are shown. Figure 3B The circuit 13 shown is Figure 2A The difference in circuit 13 shown is the inclusion of circuit 15. Circuit 15 controls the supply of low potential to wiring 125.

[0143] Circuit 15 may include transistor 109, transistor 110, and capacitor 111. One of the source and drain of transistor 109 is electrically connected to wiring 121. The other of the source and drain of transistor 109 is electrically connected to one of the source and drain of transistor 110, one electrode of capacitor 111, and the gate of transistor 104. The other of the source and drain of transistor 110 is electrically connected to wiring 122. The other electrode of capacitor 111 is electrically connected to wiring 122. The gate of transistor 109 is electrically connected to wiring 124[n+1]. The gate of transistor 110 is electrically connected to wiring 124[n-1]. In this structure, the gates of transistors 102, 105, and 110 are first input terminals, and the gate of transistor 109 is a third input terminal.

[0144] exist Figure 2A In the circuit 13 shown, in Figure 2BAt time T6 in the timing diagram shown, transistor 104 is not conducting, so wiring 125 is in a floating state. At this time, when the leakage current of transistor 102 is high, the potential of wiring 125 sometimes rises, causing pixel 10 to malfunction.

[0145] Circuit 15 is a circuit that maintains the potential of node D (a wiring that connects the gate of transistor 104, one electrode of capacitor 111, the other of the source and drain of transistor 109, and one of the source and drain of transistor 110), and can keep transistor 104 in a conducting or non-conducting state.

[0146] The circuit 15 operates as follows. First, when the first input terminal is supplied with the signal voltage "H", transistor 110 is turned on, and node D is supplied with the potential "L". At this time, transistor 104 is not turned on.

[0147] Next, when the first input terminal is supplied with a signal voltage "L", transistor 110 is not turned on, and node D is supplied with a potential "L". Then, during the boost operation using the signal voltage input to the second input terminal, node D also maintains a potential "L".

[0148] Next, when the third input terminal is supplied with the signal voltage "H", transistor 109 turns on, and the potential of node D becomes "H". At this time, transistor 104 turns on, and the potential of node A becomes "L".

[0149] Then, when the third input terminal is supplied with the signal voltage "L", transistor 109 is not turned on, and the potential of node D remains "H". This state is maintained until the next frame, during which transistor 104 is turned on, and node A is continuously supplied with the potential "L" of wiring 122. Therefore, node A (wiring 125) can maintain a constant potential "L".

[0150] Note that when using an OS transistor as transistor 102, the potential rise of wiring 125 is minimal due to the extremely small off-state current. The structure including circuit 15 can also be applied to other circuits shown in this embodiment.

[0151] <Working Example of Variation 2>

[0152] Figure 3B The circuit 13 shown can be based on Figure 2B The timing diagram shown is operational. Note that even with a high leakage current in transistor 102, the potential of node A can be kept constant after time T6.

[0153] <Example 3 of a variation of a boost circuit>

[0154] Figure 4Other variations of circuit 13 are shown. Note that circuit 13 described above includes three input terminals. Figure 4 The circuit 13 shown includes four input terminals. In this configuration, the boost function can be improved compared to the circuit 13 described above.

[0155] Figure 4 The circuit 13 shown Figure 2A The circuit 13 shown includes transistors 112 and 113, and capacitor 114.

[0156] One of the source and drain terminals of transistor 102 is electrically connected to one electrode of capacitor 106. One electrode of capacitor 106 is electrically connected to one of the source and drain terminals of transistor 104. The other electrode of capacitor 106 is electrically connected to one of the source and drain terminals of transistor 105, one of the source and drain terminals of transistor 112, and one electrode of capacitor 114. The other electrode of capacitor 114 is electrically connected to one of the source and drain terminals of transistor 103 and one of the source and drain terminals of transistor 113.

[0157] The gate of transistor 102 is electrically connected to wiring 124[n-2]. The gate of transistor 112 is electrically connected to wiring 124[n-1]. The gate of transistor 113 is electrically connected to wiring 124[n-1]. The gate of transistor 103 is electrically connected to wiring 124[n]. The gate of transistor 104 is electrically connected to wiring 124[n+1]. The other of the source and drain of transistor 102 is electrically connected to wiring 121. The other of the source and drain of transistor 103 is electrically connected to wiring 121. The other of the source and drain of transistor 104 is electrically connected to wiring 122. The other of the source and drain of transistor 105 is electrically connected to wiring 122. The other of the source and drain of transistor 112 is electrically connected to wiring 121. The other of the source and drain of transistor 113 is electrically connected to wiring 122.

[0158] Here, the wiring connecting the other electrode of capacitor 106, one of the source and drain of transistor 112, one electrode of capacitor 114, and one of the source and drain of transistor 105 is designated as node E. Furthermore, the wiring connecting the other electrode of capacitor 114, one of the source and drain of transistor 103, and one of the source and drain of transistor 113 is designated as node F.

[0159] exist Figure 4In the circuit 13 shown, the gates of transistors 102 and 105, connected to wiring 124[n-2], are used as first input terminals. The gates of transistors 112 and 113, connected to wiring 124[n-1], are used as second input terminals. The gate of transistor 103, connected to wiring 124[n], is used as a third input terminal. The gate of transistor 104, connected to wiring 124[n+1], is used as a fourth input terminal.

[0160] <Working Example of Variation Example 3>

[0161] Basic workings of boosting voltage and Figure 2A The circuit shown is the same as 13. (Refer to...) Figure 5 Timing diagram explanation Figure 4 The circuit 13 shown is an example of how it works. Note that wiring 121 is supplied with "H", wiring 122 is supplied with "L", and wiring 124 is supplied with either "H" or "L".

[0162] At time T1, when the potential of wiring 124[n-2] becomes "H" (the potentials of wiring 124[n-1], wiring 124[n], and wiring 124[n+1] are "L"), transistor 102 is turned on, and the potential of node A becomes "H". Additionally, transistor 105 is turned on, and the potential of node E becomes "L".

[0163] At time T2, when the potential of wiring 124[n-2] becomes “L” (the potentials of wiring 124[n-1], wiring 124[n], and wiring 124[n+1] are all “L”), transistor 102 is not turned on, and the potential of node A remains “H”. Furthermore, transistor 105 is not turned on, and the potential of node E remains “L”.

[0164] At time T3, when the potential of wiring 124[n-1] becomes "H" (the potentials of wiring 124[n-2], wiring 124[n], and wiring 124[n+1] are "L"), transistor 112 turns on, and the potential of node E changes from "L" to "H". This change is based on the capacitance ratio of capacitor 106 to node A plus the potential of node A, so the potential of node A becomes "H+(HL)". That is, when "L" = 0, the potential of node A becomes "2H". Furthermore, transistor 113 turns on, and the potential of node F becomes "L".

[0165] At time T4, when the potential of wiring 124[n-1] becomes “L” (the potentials of wiring 124[n-2], wiring 124[n], and wiring 124[n+1] are all “L”), transistor 112 is not turned on, and the potential of node E remains “H”. Furthermore, transistor 113 is not turned on, and the potential of node F remains “L”.

[0166] At time T5, when the potential of wiring 124[n] becomes "H" (the potentials of wiring 124[n-2], wiring 124[n-1], and wiring 124[n+1] are "L"), transistor 103 is turned on, and the potential of node F changes from "L" to "H". This change is calculated by adding the potential of node A to the capacitance ratio of capacitor 114 to that of node E and node A, resulting in the potential of node A becoming "2H + (HL)". That is, when "L" = 0, the potential of node A becomes "3H".

[0167] At time T6, when the potential of wiring 124[n] becomes “L” (the potentials of wiring 124[n-2], wiring 124[n-1] and wiring 124[n+1] are “L”), transistor 103 is not turned on, and the potential of node A remains “3H”.

[0168] At time T7, when the potential of wiring 124[n+1] becomes “H” (the potentials of wiring 124[n-2], wiring 124[n-1], and wiring 124[n] are “L”), transistor 104 is turned on, and the potential of node A becomes “L”.

[0169] At time T8, when the potential of wiring 124[n+1] becomes “L” (the potentials of wiring 124[n-2], wiring 124[n-1], and wiring 124[n] become “L”), transistor 104 is not turned on, and the potential of node A remains “L”.

[0170] The writing operation to pixel 10 can be performed during the period when node A (wiring 125[n]) is supplied with a potential of "3H" (after time T5 and before time T7). Furthermore, since the potential of node A remains "L" after T7, the image signal written to pixel 10 can be maintained until the next frame (the next operation).

[0171] As mentioned above, by means of Figure 2A Adding two transistors and a capacitor to circuit 13 can improve the boost function. Further adding this structure can further enhance the boost function.

[0172] <Example 4 of a variation of a boost circuit>

[0173] Figure 6A Other variations of circuit 13 are shown. The circuit 13 shown in Figure 6 has a simplified structure, with features from... Figure 2AThe circuit 13 shown is the structure minus transistors 103 and 105. In this structure, the other electrode of capacitor 106 is electrically connected to wiring 124[n]. That is, the other electrode of capacitor 106 is used as a second input terminal.

[0174] <Working Example of Variation 4>

[0175] Basic workings of boosting voltage and Figure 2A The circuit shown is the same as 13. Since transistor 103 is omitted, the boost operation depends on the duration during which the signal voltage "H" is input to the second input terminal.

[0176] Reference Figure 6B Timing diagram explanation Figure 6A This is an example of the operation of circuit 13 shown. Note that in the following description or timing diagram, low potential is denoted as "L" and high potential is denoted as "H". Furthermore, wiring 121, wiring 122, and wiring 124 are supplied with conditions of "H", "L", "H", or "L", respectively.

[0177] At time T1, when the potential of wiring 124[n-1] becomes "H" (the potentials of wiring 124[n] and wiring 124[n+1] are "L"), transistor 102 is turned on, and the potential of node A becomes "H". At this time, the other electrode of capacitor 106 is supplied with potential "L".

[0178] At time T2, when the potential of wiring 124[n-1] becomes “L” (the potentials of wiring 124[n] and wiring 124[n+1] are “L”), transistor 102 is not turned on, and the potential of node A remains “H”. At this time, the other electrode of capacitor 106 is supplied with potential “L”.

[0179] At time T3, when the potential of wiring 124[n] becomes "H" (the potentials of wiring 124[n-1] and wiring 124[n+1] are "L"), the potential of the other electrode of capacitor 106 changes from "L" to "H". This change is based on the capacitance ratio of capacitor 106 to node A plus the potential of node A, so the potential of node A becomes "H+(HL)". That is, when "L" = 0, the potential of node A becomes "2H".

[0180] At time T4, when the potential of wiring 124[n] becomes "L" (the potentials of wiring 124[n-1] and wiring 124[n+1] are both "L"), the potential of the other electrode of capacitor 106 changes from "H" to "L". This change is based on the capacitance ratio of capacitor 106 to node A plus the potential of node A, resulting in the potential of node A being "2H + (LH)". That is, when "L" = 0, the potential of node A becomes "H".

[0181] At time T5, when the potential of wiring 124[n+1] becomes “H” (the potentials of wiring 124[n-1] and wiring 124[n] are “L”), transistor 104 is turned on, and the potential of node A becomes “L”.

[0182] At time T6, when the potential of wiring 124[n+1] becomes “L” (the potentials of wiring 124[n-1] and wiring 124[n] are “L”), transistor 104 is not turned on, and the potential of node A remains “L”.

[0183] As described above, the potential of node A becomes "2H" after time T3 and returns to "H" at time T4. That is, the period during which a high potential can be maintained is shorter compared to circuit 13 illustrated in Figures 2 to 6. Figure 6A The circuit 13 shown is preferably used in a display device that can adequately ensure the pixel write time even when performing this operation.

[0184] Note that the same structure can be applied to circuit 13 with a higher voltage. Figure 7 Showing the Figure 4 The circuit 13 shown also includes an input terminal, which can output a maximum potential "4H". Figure 7 and Figure 4 The difference in circuit 13 shown is that capacitor 115 is electrically connected to node F. Capacitor 115 can be electrically connected to the input terminal of the last stage that performs the boost operation.

[0185] <Other methods of boost circuits, other connection methods of boost circuits>

[0186] Figures 1 to 7 The structure of the connection between the output terminal of gate driver 12 and circuit 13 is described as follows: Figure 8A As shown, circuit 13 can also be a component of gate driver 12. In this structure, boost voltage is performed inside gate driver 12. Furthermore, circuitry such as shift registers included in gate driver 12 can be stacked with circuit 13. By stacking these layers, the display device can achieve a narrow bezel.

[0187] In addition, such as Figure 8B As shown, a selection circuit 16 can also be provided in circuit 13. The selection circuit 16 can output the boosted output potential in circuit 13 to the selected wiring 125. By adopting this structure, the number of circuits 13 provided in the display device can be reduced, thereby enabling the display device to have a narrow bezel. Note that the selection circuit 16 can also be provided outside of circuit 13, and the output terminals of circuit 13 can be electrically connected to the selection circuit 16.

[0188] In addition, such as Figure 8C As shown, a selection circuit 17 can also be provided between the gate driver 12 and the circuit 13. The selection circuit 17 can select either a first path for the signal voltage output from the gate driver 12 to the circuit 13 or a second path for the signal voltage output from the circuit 13 to the pixel 10. By adopting this structure, a signal voltage without boost can be supplied to the pixel, and low-power operation such as suppressing display brightness can be switched.

[0189] <Pixel Circuit>

[0190] In addition to the structure shown in Figure 2, pixel 10 can also adopt... Figure 9A The structure shown. Figure 9A The pixel 10 shown has the function of boosting the voltage of the input data. Figure 9A The pixel 10 shown includes transistors 116 and 117, capacitor 118, and circuit 21, and is electrically connected to two gate lines (wiring 125 and wiring 126) and two source lines (wiring 127 and wiring 128). Wiring 125 and wiring 126 are electrically connected to different circuits 13, respectively.

[0191] The gate of transistor 116 is electrically connected to wiring 126, one of its source and drain is electrically connected to wiring 127, and the other of its source and drain is electrically connected to one electrode of capacitor 118 and circuit 21. The gate of transistor 117 is electrically connected to wiring 125, one of its source and drain is electrically connected to wiring 128, and the other of its source and drain is electrically connected to the other electrode of capacitor 118.

[0192] Transistor 116 is controlled by a signal supplied to wiring 126, and transistor 117 is controlled by a signal supplied to wiring 125.

[0193] Figure 9A Pixel 10 shown is effective when supplying high voltage to the display devices included in circuit 21. The boost function of pixel 10 is explained below. Note that in... Figure 9A In pixel 10 shown, the wiring connecting the source and drain of transistor 116, one electrode of capacitor 118, and circuit 21 is designated as node NM.

[0194] First, node NM is supplied with a potential "D1" of wiring 127 via transistor 116. In a timing overlap with this, the other electrode of capacitor 118 is supplied with a reference potential "V" from wiring 128 via transistor 117. ref At this time, capacitor 118 maintains "D1-V". ref Next, node NM is floated, and the other electrode of capacitor 118 is supplied with the potential "D2" of wiring 128 through transistor 117. Here, potential "D2" is the additive potential.

[0195] At this point, the capacitance value of capacitor 118 is set to C. 118 And set the capacitance value of node NM to C. NM At that time, the potential of node NM becomes D1+(C 118 / (C 118 +C NM ))×(D2-V ref Here, let's assume C 118 The value of C NM When the value of C is sufficiently large, 118 / (C 118 +C NM The potential of node NM is approximately 1. Therefore, the potential of node NM can be said to be approximately "D1 + (D2 - V)". ref Furthermore, when D1 = D2 and V ref When = 0, it becomes "D1 + (D2 - V) ref ))” = “2D1”.

[0196] In other words, by properly designing the circuit, approximately twice the potential that can be input from wiring 125 or wiring 126 can be supplied to node NM.

[0197] This function allows high voltage to be supplied to the display device. Therefore, even when using a general-purpose driver IC, display devices with high threshold voltages can operate. Alternatively, the power consumption of the driver IC can be suppressed.

[0198] In addition, pixel 10 can also have Figure 9B The structure shown. Figure 9B The pixel 10 shown is Figure 9A The difference in pixel 10 shown is the inclusion of transistor 119. The gate of transistor 119 is electrically connected to wiring 126, one of its source and drain is electrically connected to the other of the source and drain of transistor 117 and the other electrode of capacitor 118, and the other of its source and drain is electrically connected to wiring 128. Additionally, one of the source and drain of transistor 117 is connected to wiring 127.

[0199] exist Figure 9A In pixel 10 shown, as described above, the reference potential and the calculation potential are supplied to the other electrode of capacitor 118 via transistor 117. At this time, since the two wirings 125 and 126 and wiring 128 need to alternately rewrite the reference potential and the calculation potential, there are sometimes problems with high-speed operation and power consumption.

[0200] exist Figure 9BIn pixel 10 shown, although transistor 119 is added, the gate of transistor 119 can be connected to wiring 126, so the number of wirings does not increase. Furthermore, wiring 128 can be a dedicated wiring for supplying a reference potential, eliminating the need for alternating between the reference and calculation potentials using a single wiring, thus making it suitable for high-speed operation and low power consumption. Additionally, since wiring 128 can utilize low-potential lines connected to circuit 21, the number of wirings can be substantially reduced.

[0201] Note that in Figure 9A , Figure 9B In the middle, as "V" ref Alternatively, the reverse potential "D1B" of "D1" can be used. In this case, approximately three times the potential input from wiring 125 or wiring 126 can be supplied to node NM. Note that a reverse potential is a potential that is the same (or approximately the same) in absolute value as a reference potential and different from the original potential. The original potential is set to "D1", the reverse potential to "D1B", and the reference potential to V. ref When V is satisfied ref The relationship can be expressed as (D1+D1B) / 2.

[0202] <Circuit 21>

[0203] Figures 10A to 10D This is a structural example of a display device, including a liquid crystal device, that can be used in circuit 21.

[0204] Figure 10A The structure shown includes a capacitor 141 and a liquid crystal device 142. One electrode of the liquid crystal device 142 is electrically connected to one electrode of the capacitor 141. One electrode of the capacitor 141 is electrically connected to node NM.

[0205] The other electrode of capacitor 141 is electrically connected to wiring 151. The other electrode of liquid crystal device 142 is electrically connected to wiring 152. Wiring 151 and 152 have the function of supplying power. For example, wiring 151 and 152 can supply reference potentials such as GND and 0V or any potential.

[0206] Note that, as Figure 10B As shown, a structure in which capacitor 141 is omitted can be used. As described above, an OS transistor can be used as the transistor connected to node NM. Since the leakage current of the OS transistor is extremely small, the display can be maintained for a long time even without omitting capacitor 141, which serves as a storage capacitor. Furthermore, the transistor structure is not limited; omitting capacitor 141 is also effective when shortening the display period using high-speed operation such as field-sequence driving. Omitting capacitor 141 increases the aperture ratio. Additionally, the pixel transmittance can be increased.

[0207] exist Figure 10A and Figure 10B In this structure, the liquid crystal device 142 begins operation when the potential of node NM is above the operating threshold of the liquid crystal device 142. Therefore, sometimes display operation begins before the potential of node NM is determined. Note that in the case of a transmissive liquid crystal display device, by also employing operations such as turning off the backlight until the potential of node NM is determined, unwanted display operation can be suppressed from being seen.

[0208] Figure 10C Yes Figure 10A The structure of the additional transistor 143 is shown. One of the source and drain of transistor 143 is electrically connected to one electrode of capacitor 141. The other of the source and drain of transistor 143 is electrically connected to node NM.

[0209] In this structure, the potential of node NM is applied to the liquid crystal device 142 simultaneously with the conduction of transistor 143. Therefore, operation of the liquid crystal device 142 can begin at any timing after the potential of node NM is determined.

[0210] Figure 10D Yes Figure 10C The structure includes an additional transistor 144. One of the source and drain of transistor 144 is electrically connected to one electrode of liquid crystal device 142. The other of the source and drain of transistor 144 is electrically connected to wiring 153.

[0211] The circuit 170, which is electrically connected to the wiring 153, can have the function of resetting the potential supplied to the capacitor 141 and the liquid crystal device 142.

[0212] Figures 11A to 11D This is a structural example of a display device, including a light-emitting device, that can be used in circuit 21.

[0213] Figure 11A The structure shown includes a transistor 145, a capacitor 146, and a light-emitting device 147. One of the source and drain terminals of transistor 145 is electrically connected to one electrode of the light-emitting device 147. One electrode of the light-emitting device 147 is electrically connected to one electrode of the capacitor 146. The other electrode of the capacitor 146 is electrically connected to the gate of transistor 145. The gate of transistor 145 is electrically connected to node NM.

[0214] One of the source and drain terminals of transistor 145 is electrically connected to wiring 154. The other electrode of light-emitting device 147 is electrically connected to wiring 155. Wiring 154 and 155 have the function of supplying power. For example, wiring 154 can supply a high-potential power supply. Furthermore, wiring 155 can supply a low-potential power supply.

[0215] exist Figure 11AIn the structure shown, current flows through the light-emitting device 147 when the potential of node NM is above the threshold voltage of transistor 145.

[0216] In addition, such as Figure 11B As shown, one electrode of the light-emitting device 147 can be electrically connected to the wiring 154, and the other electrode of the light-emitting device 147 can be electrically connected to another of the source and drain electrodes of the transistor 145. This structure can also be used in other circuits 21 that have the light-emitting device 147.

[0217] Figure 11C Yes Figure 15A The structure of the additional transistor 148 is described. One of the source and drain of transistor 148 is electrically connected to one of the source and drain of transistor 145. The other of the source and drain of transistor 148 is electrically connected to the light-emitting device 147.

[0218] In this structure, the potential of node NM is above the threshold voltage of transistor 145, and when transistor 148 is turned on, current flows through light-emitting device 147. Therefore, light emission from light-emitting device 147 can begin at any timing after the potential of node NM is determined.

[0219] Figure 11D Yes Figure 11A The structure of the additional transistor 149 is described. One of the source and drain of transistor 149 is electrically connected to one of the source and drain of transistor 145. The other of the source and drain of transistor 149 is electrically connected to wiring 156.

[0220] Wiring 156 can be electrically connected to a supply source with a specific potential, such as a reference potential. By supplying a specific potential to one of the source and drain of transistor 145 from wiring 156, the writing of image data can be stabilized. Furthermore, the emission timing of light-emitting device 147 can be controlled.

[0221] Furthermore, wiring 156 can be connected to circuit 171 and can function as a monitoring line. Circuit 171 can have one or more functions, such as supplying a power source for the specific potential mentioned above, acquiring the electrical characteristics of transistor 145, and generating correction data.

[0222] <Examples of transistor variations>

[0223] In addition, such as Figure 12 As shown in Figure A, in one embodiment of the circuit of the present invention, a transistor with a back gate can be used. Figure 12A shows a structure where the back gate and front gate are electrically connected, which improves the on-state current. Alternatively, a structure can be provided where the back gate is electrically connected to wiring capable of supplying a constant potential. By employing this structure, the threshold voltage of the transistor can be controlled. Note that the back gate can also be provided in the transistor included in circuit 21.

[0224] <Simulation Results>

[0225] Next, we will explain the simulation results regarding the operation of pixels. Figure 13 The structure of pixel 10 used in the simulation is shown. In the simulation, the following is used... Figure 6A The circuit structure shown is as follows: Figure 6B The timing diagram shown is for the operation of objects.

[0226] The parameters used for simulation are as follows. Transistor dimensions are L / W = 3μm / 1600μm (transistors Tr1 and Tr2), capacitor C1 has a capacitance of 149pF, and the capacitance and resistance of the load connected to node A are assumed to be 149pF and 1.9kΩ respectively for a vertical panel approximately 9 inches diagonally. The power supply voltages to circuit 13 are GVDD = +11V and GVSS = -21V. Furthermore, the input voltage (GOUT) from the gate driver is set as -21V as "L" and as +11V as "H". Note that the circuit simulation software used is SPICE.

[0227] Figure 14 This is the simulation result. The horizontal axis represents time (μ seconds), and the vertical axis represents the voltage (V) of node A of pixel 10. Note that GOUT[i-1] is the signal voltage input to the gate of transistor Tr1, GOUT[i] is the signal voltage input to capacitor C1, and GOUT[i+1] is the signal voltage input to the gate of transistor Tr2.

[0228] like Figure 14 As shown, the potential at node A rises from -21V in the initial state when input to GVSS to approximately 8.4V upon input to GOUT[i-1], to approximately 27.6V upon input to GOUT[i], and returns to 21V upon input to GOUT[i+1]. Based on the initial state, it can be confirmed that the output voltage at input to GOUT[i] can rise to approximately 1.65 times the output voltage at input to GOUT[i-1]. With further appropriate design, the boost characteristics can be further improved.

[0229] The effectiveness of one aspect of the present invention can be confirmed based on the simulation results above.

[0230] This embodiment can be implemented by appropriately combining the structures described in other embodiments, etc.

[0231] (Implementation Method 2)

[0232] This embodiment describes structural examples of a display device using a liquid crystal device and structural examples of a display device using a light-emitting device. Note that the constituent elements, operation, and functions of the display device described in Embodiment 1 are omitted in this embodiment.

[0233] The pixels described in Embodiment 1 can be used in the display device described in this embodiment. Note that the scan line driving circuit described below corresponds to the gate driver, while the signal line driving circuit corresponds to the source driver.

[0234] Figures 15A to 15C The structure of a display device in which one aspect of the present invention can be used is shown.

[0235] exist Figure 15A In this process, a sealant 4005 is provided around a display portion 215 disposed on a first substrate 4001, and the display portion 215 is sealed by the sealant 4005 and the second substrate 4006.

[0236] exist Figure 15A In this circuit, the scan line driving circuit 221a, signal line driving circuit 231a, signal line driving circuit 232a, and common line driving circuit 241a all include multiple integrated circuits 4042 disposed on the printed circuit board 4041. The integrated circuits 4042 are formed of single-crystal semiconductors or polycrystalline semiconductors. The common line driving circuit 241a has the function of supplying a specified potential to the wirings 151, 152, 154, 155, etc., shown in Embodiment 1.

[0237] Various signals and potentials are supplied to the scan line drive circuit 221a, common line drive circuit 241a, signal line drive circuit 231a and signal line drive circuit 232a through the FPC (Flexible printed circuit) 4018.

[0238] The integrated circuit 4042, included in the scan line driving circuit 221a and the common line driving circuit 241a, has the function of supplying selection signals to the display unit 215. The integrated circuit 4042, included in the signal line driving circuit 231a and the signal line driving circuit 232a, has the function of supplying image data to the display unit 215. The integrated circuit 4042 is mounted in a region different from the region surrounded by the sealant 4005 on the first substrate 4001.

[0239] Note that there are no particular restrictions on the connection method of the integrated circuit 4042. The wire bonding method, COF (Chip On Film) method, COG (Chip On Glass) method, and TCP (Tape Carrier Package) method can be used.

[0240] Figure 15B An example is shown of an integrated circuit 4042 included in signal line drive circuits 231a and 232a, mounted using the COG method. Furthermore, by forming a portion or all of the drive circuitry on a substrate on which the display section 215 is formed, a system-on-panel can be formed.

[0241] Figure 15B An example is shown in which the scan line driving circuit 221a and the common line driving circuit 241a are formed on a substrate on which the display section 215 is formed. By simultaneously forming the driving circuit and the pixel circuit within the display section 215, the number of components can be reduced. As a result, productivity can be improved.

[0242] In addition, Figure 15B In this configuration, a sealant 4005 is provided around the display portion 215, the scan line drive circuit 221a, and the common line drive circuit 241a disposed on the first substrate 4001. A second substrate 4006 is disposed on the display portion 215, the scan line drive circuit 221a, and the common line drive circuit 241a. Thus, the display portion 215, the scan line drive circuit 221a, and the common line drive circuit 241a are sealed together with the display device via the first substrate 4001, the sealant 4005, and the second substrate 4006.

[0243] Although Figure 15B The illustration shows an example of separately forming signal line driving circuits 231a and 232a and mounting them to the first substrate 4001. However, one aspect of the invention is not limited to this structure; a scan line driving circuit may also be separately formed and mounted, or a part of the signal line driving circuit or a part of the scan line driving circuit may be separately formed and mounted. Additionally, as... Figure 15C The signal line driving circuit 231a and signal line driving circuit 232a can also be formed on the substrate on which the display section 215 is formed.

[0244] In addition, display devices sometimes include a panel in which the display device is sealed and a module, including an IC and a controller, which is installed in the panel.

[0245] The display section and scan line driving circuit disposed on the first substrate include a plurality of transistors. The transistors can be Si transistors or OS transistors as shown in Embodiment 1.

[0246] The transistors included in the peripheral driving circuit and the transistors included in the pixel circuit of the display unit can have the same structure or different structures. The transistors included in the peripheral driving circuit can all have the same structure or combine two or more structures. Similarly, the transistors included in the pixel circuit can all have the same structure or combine two or more structures.

[0247] Alternatively, an input device 4200 may be provided on the second substrate 4006. Figures 15A to 15C The structure shown for setting an input device 4200 for a display device can be used as a touch screen.

[0248] There are no particular limitations on the sensing devices (also called sensing elements) included in the touchscreen of one embodiment of the present invention. Various sensors capable of detecting the proximity or contact of objects such as fingers or styluses can also be used as sensing devices.

[0249] For example, various methods can be used as sensors, such as electrostatic capacitive, resistive film, surface acoustic wave, infrared, optical, and pressure-sensitive types.

[0250] In this embodiment, a touchscreen including an electrostatic capacitive sensing device will be used as an example for explanation.

[0251] As electrostatic capacitive sensors, there are surface-type electrostatic capacitive sensors and projection-type electrostatic capacitive sensors. Furthermore, projection-type electrostatic capacitive sensors include self-capacitance type and mutual-capacitance type. Mutual-capacitance type is preferred because it allows for simultaneous multi-point sensing.

[0252] One aspect of the touchscreen of the present invention can adopt various structures such as a structure in which a display device and a sensing element are bonded together separately, or a structure in which electrodes constituting the sensing element are provided on one or both of a substrate supporting the display element and an opposing substrate.

[0253] Figure 16A and Figure 16B An example of a touchscreen is shown. Figure 16A This is a 3D view of the touchscreen 4210. Figure 16B This is a three-dimensional schematic diagram of the input device 4200. Note that, for clarity, only typical components are shown.

[0254] The touchscreen 4210 has a structure that integrates separately manufactured display devices and sensing devices.

[0255] The touchscreen 4210 includes an input device 4200 and a display device arranged in an overlapping manner.

[0256] Input device 4200 includes substrate 4263, electrode 4227, electrode 4228, multiple wirings 4237, multiple wirings 4238, and multiple wirings 4239. For example, electrode 4227 may be electrically connected to wiring 4237 or wiring 4239. Additionally, electrode 4228 may be electrically connected to wiring 4239. FPC 4272b may be electrically connected to each of the multiple wirings 4237 and multiple wirings 4238. FPC 4272b may be equipped with IC 4273b.

[0257] A touch sensor may be disposed between the first substrate 4001 and the second substrate 4006 of the display device. When a touch sensor is disposed between the first substrate 4001 and the second substrate 4006, an optical touch sensor utilizing a photoelectric conversion element may be used in addition to an electrostatic capacitive touch sensor.

[0258] Figure 17A and Figure 17B It is along Figure 15B The cross-sectional view of the dotted lines N1-N2 in the figure. Figure 17A and Figure 17B The display device shown includes an electrode 4015, which is electrically connected to the terminals of the FPC 4018 via an anisotropic conductive layer 4019. Additionally, in Figure 17A and Figure 17B In this process, electrode 4015 is electrically connected to wiring 4014 in the openings formed in insulating layer 4112, insulating layer 4111 and insulating layer 4110.

[0259] Electrode 4015 and first electrode layer 4030 are formed using the same conductive layer, and wiring 4014 and source and drain electrodes of transistors 4010 and 4011 are formed using the same conductive layer.

[0260] Additionally, the display section 215 and the scan line driving circuit 221a disposed on the first substrate 4001 include a plurality of transistors. Figure 17A and Figure 17B The image shows transistor 4010 in display unit 215 and transistor 4011 in scan line drive circuit 221a. Although Figure 17A and Figure 17B The transistors 4010 and 4011 are shown as bottom-gate transistors, but top-gate transistors can also be used.

[0261] exist Figure 17A and Figure 17B In this configuration, an insulating layer 4112 is provided on transistors 4010 and 4011. Additionally, in... Figure 17B In the middle, a partition wall 4510 is formed on the insulating layer 4112.

[0262] Additionally, transistors 4010 and 4011 are disposed on insulating layer 4102. Furthermore, transistors 4010 and 4011 include an electrode 4017 formed on insulating layer 4111. Electrode 4017 can be used as a back gate electrode.

[0263] Figure 17A , Figure 17B The display device shown includes a capacitor 4020. Figure 17A , Figure 17B The illustration shows an example of a capacitor 4020 including an electrode 4021 formed in the same process as the gate electrode of a transistor 4010, an insulating layer 4103, and an electrode formed in the same process as the source and drain electrodes. The structure of the capacitor 4020 is not limited to this and may also be formed from other conductive and insulating layers.

[0264] The transistor 4010 disposed in the display section 215 is electrically connected to the display device. Figure 17A This is an example of a liquid crystal display device that uses a liquid crystal device as a display device. Figure 17A In this embodiment, the liquid crystal device 4013, serving as a display device, includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. Note that insulating layers 4032 and 4033, used as alignment films, are disposed to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is disposed on one side of the second substrate 4006, and the first electrode layer 4030 and the second electrode layer 4031 overlap with the liquid crystal layer 4008.

[0265] As a liquid crystal device 4013, liquid crystal devices using various modes can be employed. For example, liquid crystal devices employing VA (Vertical Alignment) mode, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, ASM (Axially Symmetric Aligned Micro-cell) mode, OCB (Optically Compensated Bend) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Anti-Ferroelectric Liquid Crystal) mode, ECB (Electrically Controlled Birefringence) mode, VA-IPS (Vertical Alignment In-Plane-Switching) mode, guest-host mode, etc., can be used.

[0266] Alternatively, a normally black liquid crystal display device, such as a transmissive liquid crystal display device employing vertical alignment (VA) mode, can also be used for the liquid crystal display device shown in this embodiment. As the vertical alignment mode, MVA (Multi-Domain Vertical Alignment), PVA (Patterned Vertical Alignment), ASV (Advanced Super View), and other similar modes can be used.

[0267] Liquid crystal devices (LCDs) utilize the optical modulation properties of liquid crystals to control the transmission or blocking of light. The optical modulation of liquid crystals is controlled by an electric field (horizontal, vertical, or tilted) applied to the liquid crystal. Liquid crystals used in LCD devices can be thermotropic liquid crystals, low-molecular-weight liquid crystals, high-molecular-weight liquid crystals, polymer-dispersed liquid crystals (PDLCs), ferroelectric liquid crystals, and antiferroelectric liquid crystals. These liquid crystal materials exhibit cholesteric, smectic, cubic, chiral, and isotropic phases depending on the conditions.

[0268] Although Figure 17A An example of a liquid crystal display device with a vertical electric field is shown, but a liquid crystal display device with a horizontal electric field can also be applied to one aspect of the present invention. In the case of a horizontal electric field, a liquid crystal displaying a blue phase without an alignment film can also be used. The blue phase is a type of liquid crystal phase, referring to the phase that appears just before the cholesteric liquid crystal transitions to a homogeneous phase when the temperature is raised. Because the blue phase only appears within a narrow temperature range, a liquid crystal composition containing at least 5 wt% chiral reagent is used in the liquid crystal layer 4008 to broaden the temperature range. The liquid crystal composition containing the blue phase liquid crystal and the chiral reagent has a fast response speed and is optically isotropic. Furthermore, the liquid crystal composition containing the blue phase liquid crystal and the chiral reagent does not require alignment processing and has low viewing angle dependence. Additionally, since no alignment film is required and no rubbing process is needed, electrostatic damage caused by rubbing processing can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced.

[0269] The spacer 4035 is a columnar spacer obtained by selectively etching the insulating layer, and it is provided to control the spacing (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. Note that spherical spacers can also be used.

[0270] Furthermore, optical components (optical substrates) such as a black matrix (light-shielding layer), a color layer (color filter), polarizing components, phase difference components, and anti-reflection components can be appropriately provided as needed. For example, circular polarization utilizing polarizing substrates and phase difference substrates can also be used. Additionally, backlighting or sidelighting can be used as the light source. Micro-LEDs can also be used as the aforementioned backlighting or sidelighting.

[0271] exist Figure 17A In the display device shown, a light-shielding layer 4132, a coloring layer 4131 and an insulating layer 4133 are disposed between the second substrate 4006 and the second electrode layer 4031.

[0272] Examples of materials suitable for use in the light-shielding layer include carbon black, titanium black, metals, metal oxides, or composite oxides comprising solid solutions of multiple metal oxides. The light-shielding layer can also be a film containing a resin material or a thin film containing inorganic materials such as metals. Alternatively, a laminated film containing a material with a coloring layer can be used for the light-shielding layer. For example, a laminated structure can be used consisting of a film containing a material with a coloring layer for transmitting a certain color of light and a film containing a material with a coloring layer for transmitting other colors of light. By using the same material for the coloring layer and the light-shielding layer, the process can be simplified, allowing the use of the same equipment, which is therefore preferable.

[0273] Examples of materials that can be used for coloring layers include metallic materials, resin materials, and resin materials containing pigments or dyes. The light-shielding layer and coloring layer can be formed, for example, using inkjet printing.

[0274] in addition, Figure 17A and Figure 17B The display device shown includes an insulating layer 4111 and an insulating layer 4104. The insulating layers 4111 and 4104 are designed to prevent impurities from permeating. By sandwiching the semiconductor layer of the transistor between the insulating layers 4111 and 4104, the ingress of external impurities can be prevented.

[0275] Light-emitting devices can be used as display devices included in a display apparatus. For example, an electroluminescent (EL) device can be used. An EL device has a layer containing a light-emitting compound (also called an EL layer) between a pair of electrodes. When a potential difference higher than the threshold voltage of the EL device is created between the pair of electrodes, holes are injected into the EL layer from the anode side, while electrons are injected into the EL layer from the cathode side. The injected electrons and holes recombine in the EL layer, thereby causing the light-emitting compound contained in the EL layer to emit light.

[0276] As an EL device, organic or inorganic EL devices can be used, for example. Note that LEDs (including micro-LEDs) that include compound semiconductors can also be used in the light-emitting material.

[0277] In addition to light-emitting compounds, the EL layer can also include materials with high hole injection capacity, materials with high hole transport capacity, hole blocking materials, materials with high electron transport capacity, materials with high electron injection capacity, or bipolar materials (materials with high electron and hole transport capacity), etc.

[0278] EL layers can be formed by methods such as vapor deposition (including vacuum vapor deposition), transfer printing, printing, inkjet printing, and coating.

[0279] Inorganic EL devices are classified into distributed inorganic EL devices and thin-film inorganic EL devices based on their device structure. Distributed inorganic EL devices include a light-emitting layer in which luminescent material particles are dispersed in a binder, and their light-emitting mechanism utilizes donor-acceptor recombination luminescence. Thin-film inorganic EL devices have a structure in which the light-emitting layer is sandwiched between dielectric layers, and these dielectric layers are sandwiched between electrodes. Their light-emitting mechanism utilizes localized luminescence from the inner-shell electron transitions of metal ions. Note that organic EL devices are used here as the light-emitting device in this explanation.

[0280] To extract light, at least one of the pair of electrodes of the light-emitting device is made transparent. A transistor and a light-emitting device are formed on a substrate. The light-emitting device can be a top-emitting structure that extracts light from a surface opposite to the substrate; a bottom-emitting structure that extracts light from a surface on one side of the substrate; or a double-sided emitting structure that extracts light from both surfaces.

[0281] Figure 17B This is an example of a light-emitting display device (also called an "EL display device") that uses a light-emitting device as a display device. The light-emitting device 4513, which is used as a display device, is electrically connected to a transistor 4010 disposed in the display section 215. Although the light-emitting device 4513 has a stacked structure of a first electrode layer 4030, a light-emitting layer 4511, and a second electrode layer 4031, it is not limited to this structure. The structure of the light-emitting device 4513 can be appropriately modified according to the direction of light extracted from the light-emitting device 4513, etc.

[0282] The partition wall 4510 is formed using organic or inorganic insulating materials. It is particularly preferred to use a photosensitive resin material to form an opening in the first electrode layer 4030, and the side of the opening is formed as an inclined surface with a continuous curvature.

[0283] The light-emitting layer 4511 can be composed of a single layer or a stack of multiple layers.

[0284] The light-emitting color of the light-emitting device 4513 can be white, red, green, blue, cyan, magenta, or yellow, depending on the material constituting the light-emitting layer 4511.

[0285] Methods for achieving color display include: a method of combining a white-emitting light-emitting device 4513 and a coloring layer; and a method of setting a different light-emitting device 4513 for each pixel. The former method has higher productivity than the latter. On the other hand, in the latter method, a light-emitting layer 4511 needs to be formed for each pixel, so its productivity is lower than that of the former method. However, the latter method can obtain a emitted color with higher color purity than the former method. By giving the light-emitting device 4513 a microcavity structure in the latter method, the color purity can be further improved.

[0286] The luminescent layer 4511 may also contain inorganic compounds such as quantum dots. For example, by using quantum dots in the luminescent layer, they can also be used as luminescent materials.

[0287] To prevent oxygen, hydrogen, moisture, carbon dioxide, etc., from entering the light-emitting device 4513, a protective layer can be formed on the second electrode layer 4031 and the partition wall 4510. Silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum oxynitride, DLC (diamond-like carbon), etc., can be formed as the protective layer. Furthermore, a filler 4514 is provided and sealed within the space sealed by the first substrate 4001, the second substrate 4006, and the sealant 4005. Thus, to prevent exposure to external gases, it is preferable to use a protective film (adhesive film, UV-curable resin film, etc.) with high hermeticity and low degassing for encapsulation (sealing).

[0288] As filler 4514, in addition to inert gases such as nitrogen or argon, ultraviolet-curing resins or thermosetting resins can also be used, such as PVC (polyvinyl chloride), acrylic resins, polyimide, epoxy resins, silicone resins, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate). Filler 4514 may also contain a desiccant.

[0289] As a sealant 4005, glass materials such as glass powder or two-component mixed resins that cure at room temperature, such as light-curing resins or thermosetting resins, can be used. Sealant 4005 may also contain a desiccant.

[0290] Additionally, depending on the requirements, optical thin films such as polarizers or circular polarizers (including elliptical polarizers), phase retardation plates (λ / 4 plates, λ / 2 plates), and color filters can be appropriately placed on the light-emitting surface of the light-emitting device. Furthermore, anti-reflective films can be placed on the polarizers or circular polarizers. For example, anti-glare treatment can be performed, which reduces reflected glare by utilizing the surface's unevenness to diffuse reflected light.

[0291] By incorporating microcavity structures into light-emitting devices, it is possible to extract light with high color purity. Furthermore, by combining microcavity structures with color filters, reflected glare can be prevented, thereby improving image visibility.

[0292] Regarding the first electrode layer and the second electrode layer (also known as the pixel electrode layer, common electrode layer, counter electrode layer, etc.) that apply voltage to the display device, their light transmittance and reflectivity can be selected according to the direction of light extraction, the location of the electrode layer, and the pattern structure of the electrode layer.

[0293] As the first electrode layer 4030 and the second electrode layer 4031, transparent conductive materials such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon oxide can be used.

[0294] Furthermore, the first electrode layer 4030 and the second electrode layer 4031 may be formed from one or more of the following metals, alloys, and metal nitrides: tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag).

[0295] Furthermore, the first electrode layer 4030 and the second electrode layer 4031 can be formed using a conductive composition containing a conductive polymer (also known as a conductive polymer). As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. Examples include polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers or derivatives thereof composed of two or more of aniline, pyrrole, and thiophene.

[0296] Furthermore, since transistors are easily damaged by static electricity, it is preferable to include a protection circuit to protect the drive circuit. The protection circuit is preferably constructed using non-linear devices.

[0297] Note that, as Figure 18As shown, a stacked structure in which transistors and capacitors include overlapping regions in the height direction can also be used. For example, by arranging transistors 4011 and 4022, which form the driving circuit in an overlapping manner, a narrow bezel display device can be realized. Furthermore, by arranging transistors 4010, 4023, capacitors 4020, etc., that form the pixel circuit in a manner that partially includes overlapping regions, the aperture ratio and resolution can be improved. In addition, in Figure 18 The middle shows the Figure 17A The liquid crystal display device shown is an example of using a multilayer structure, but it can also be applied to... Figure 17B The EL display device shown.

[0298] Furthermore, in pixel circuits, using a light-transmitting conductive film with high visible light transmittance as electrodes and wiring can increase the light transmittance in the pixel, thus substantially increasing the aperture ratio. Additionally, since the semiconductor layer is also light-transmitting when using OS transistors, the aperture ratio is further increased. This is also effective when transistors and other components do not employ a multilayer structure.

[0299] In addition, a display device can be formed by combining a liquid crystal display device and a light-emitting device.

[0300] The light-emitting device is located on the opposite side of the display surface or at one end of the display surface. The light-emitting device has the function of supplying light to the display device. The light-emitting device is called a backlight.

[0301] Here, the light-emitting device may include a plate-shaped or film-shaped light guide (also called a light guide plate) and multiple light-emitting devices that emit light of different colors. By arranging the light-emitting devices near the side of the light guide, light can be emitted from the side of the light guide into the interior. The light guide includes a mechanism for changing the light path (also called a light extraction mechanism), thereby allowing the light-emitting device to uniformly illuminate the pixels of the display panel. Alternatively, a structure may be adopted in which the light-emitting device is arranged directly below the pixel without a light guide.

[0302] The light-emitting device preferably includes light-emitting devices of three colors: red (R), green (G), and blue (B). Alternatively, a white (W) light-emitting device may also be included. Light-emitting diodes (LEDs) are preferably used as these light-emitting devices.

[0303] Furthermore, the light-emitting device preferably has a full width at half maximum (FWHM) of its emission spectrum of less than 50 nm, more preferably less than 40 nm, more preferably less than 30 nm, and even more preferably less than 20 nm, indicating extremely high color purity. Note that the smaller the FWHM of the emission spectrum, the better; for example, it can be greater than 1 nm. This allows for vivid display with high color reproducibility during color display.

[0304] Furthermore, red light-emitting devices preferably use elements with a peak wavelength of emission spectrum in the range of 625 nm or higher and 650 nm or lower. Green light-emitting devices preferably use elements with a peak wavelength of emission spectrum in the range of 515 nm or higher and 540 nm or lower. Blue light-emitting devices preferably use elements with a peak wavelength of emission spectrum in the range of 445 nm or higher and 470 nm or lower.

[0305] The display device sequentially illuminates three different colored light-emitting devices while simultaneously driving the pixels, achieving color display through a time-sequential additive color mixing method. This driving method can also be called field-sequence driving.

[0306] Field-sequence driving can display vibrant color images. Furthermore, it can display smooth dynamic images. Moreover, by using the aforementioned driving method, since a pixel does not need to be composed of multiple sub-pixels of different colors, the effective reflective area (also known as effective display area or aperture ratio) of a pixel can be increased, resulting in brighter displays. Furthermore, since color filters are not required within pixels, pixel transmittance can be increased, leading to even brighter displays. Additionally, manufacturing processes can be simplified, thereby reducing manufacturing costs.

[0307] Figure 19A , Figure 19B This is an example of a cross-sectional schematic diagram of a display device capable of field-sequential driving. A backlight unit capable of emitting light of each of the RGB colors is disposed on one side of the first substrate 4001 of this display device. Note that in field-sequential driving, since the colors are displayed by time-dividing the RGB colors, color filters are not required.

[0308] Figure 19A The backlight unit 4340a shown has a structure in which multiple light-emitting devices 4342 are disposed directly below the pixels and separated by a diffuser plate 4352. The diffuser plate 4352 has the function of diffusing light emitted from the light-emitting devices 4342 to the side of the first substrate 4001, thereby making the brightness uniform within the display area. A polarizer may also be disposed between the light-emitting devices 4342 and the diffuser plate 4352 as needed. In addition, the diffuser plate 4352 may be omitted if not required. Furthermore, the light-shielding layer 4132 may also be omitted.

[0309] The backlight unit 4340a can accommodate a large number of light-emitting devices 4342, thus achieving a bright display. Furthermore, it eliminates the need for a light guide plate, minimizing the loss of light efficiency from the light-emitting devices 4342. Note that, if necessary, a light-diffusing lens 4344 can also be incorporated into the light-emitting device 4342.

[0310] Figure 19B The backlight unit 4340b shown has a structure in which a light guide plate 4341 is disposed directly below the pixel and separated from it by a diffuser plate 4352. Multiple light-emitting devices 4342 are disposed at the ends of the light guide plate 4341. The light guide plate 4341 has an uneven shape on the side opposite to the diffuser plate 4352, which allows the guided light to be scattered towards the diffuser plate 4352.

[0311] The light-emitting device 4342 can be fixed to the printed circuit board 4347. Note that in... Figure 19B The light-emitting devices 4342 of each of the RGB colors are shown overlapping each other, or the light-emitting devices 4342 of each of the RGB colors can be arranged in the depth direction. In addition, a reflective layer 4348 for reflecting visible light is provided on the side of the light guide plate 4341 opposite to the light-emitting devices 4342.

[0312] Because the number of light-emitting devices 4342 can be reduced, the backlight unit 4340b can achieve a low-cost and thin backlight unit.

[0313] Light-scattering liquid crystal devices can also be used as liquid crystal devices. Preferably, a component comprising a composite material containing liquid crystal and a polymer is used as a light-scattering liquid crystal device. For example, a polymer-dispersed liquid crystal device can be used. Alternatively, a polymer network liquid crystal (PNLC) element can also be used.

[0314] A light-scattering liquid crystal device has a structure in which a liquid crystal portion is disposed within a three-dimensional network structure of a resin portion sandwiched between a pair of electrodes. Nematic liquid crystals can be used as the material for the liquid crystal portion, for example. Furthermore, a photocurable resin can be used as the resin portion. The photocurable resin can be, for example, a monofunctional monomer such as acrylate or methacrylate; a polyfunctional monomer such as diacrylate, triacrylate, dimethacrylate, or trimethacrylate; or a polymeric compound of the above substances.

[0315] Light-scattering liquid crystal devices (LCDs) utilize the anisotropy of the refractive index of liquid crystal materials to display light by allowing light to pass through or scatter. Furthermore, the resin portion can also possess anisotropy of refractive index. When the liquid crystal molecules align in a specific direction according to the voltage applied to the light-scattering LCD, a direction arises where the difference in refractive index between the liquid crystal portion and the resin portion is minimized. Light incident along this direction passes through without being scattered by the liquid crystal portion. Therefore, the light-scattering LCD is viewed as transparent from this direction. On the other hand, when the liquid crystal molecules align randomly according to the applied voltage, the difference in refractive index between the liquid crystal portion and the resin portion does not change significantly, and thus incident light is scattered by the liquid crystal portion. Therefore, the light-scattering LCD remains opaque regardless of the viewing direction.

[0316] Figure 20A It is Figure 19A The liquid crystal device 4013 of the display device is replaced with a light-scattering type liquid crystal device 4016. The light-scattering type liquid crystal device 4016 includes a composite layer 4009 having a liquid crystal portion and a resin portion, a first electrode layer 4030, and a second electrode layer 4031. Regarding the components of field-sequence driving... Figure 19A Similarly, when using the light-scattering liquid crystal device 4016, an alignment film and polarizer are not required. Note that the spacer 4035 is spherical, but it can also be columnar.

[0317] Figure 20B Showing will Figure 19B The liquid crystal device 4013 of the display device is replaced with a light-scattering type liquid crystal device 4016. Figure 19B The structure shown is preferably one that operates in a mode where light is transmitted when no voltage is applied to the light-scattering liquid crystal device 4016, but scatters light when a voltage is applied. By adopting this structure, it can become a transparent display device in its normal state (non-display state). In this case, color display can be performed when the light is scattered.

[0318] Figures 21A to 21E Show Figure 20B The illustration shows a modified example of the display device. Note that in... Figures 21A to 21E In order to make it easier to understand, the following is shown: Figure 20B It omits some of the constituent elements while omitting other constituent elements.

[0319] Figure 21A The diagram shows a structure in which the first substrate 4001 is used as a light guide plate. The outer surface of the first substrate 4001 can also be provided with an uneven shape. This structure eliminates the need for a separate light guide plate, thus reducing manufacturing costs. Furthermore, since there is no light attenuation due to the light guide plate, the light emitted by the light-emitting device 4342 can be utilized efficiently.

[0320] Figure 21BThe structure of incident light near the end of composite layer 4009 is shown. By utilizing total internal reflection at the interfaces between composite layer 4009 and the second substrate 4006, and between composite layer 4009 and the first substrate 4001, light can be emitted from the light-scattering liquid crystal device to the outside. The resin portion of composite layer 4009 uses a material with a refractive index greater than that of the first substrate 4001 and the second substrate 4006.

[0321] Note that the light-emitting device 4342 is not only located on one side of the display device, but also, as... Figure 21C The light-emitting device 4342 can also be positioned on two opposite sides. Furthermore, it can be positioned on three or four sides. By placing the light-emitting device 4342 on multiple sides, light attenuation can be compensated for, and it can also be used for large-area display devices.

[0322] Figure 21D The diagram illustrates a structure in which light emitted from the light-emitting device 4342 is guided to the display device via a mirror 4345. This structure allows for efficient total internal reflection of light because light can be easily guided to the display device at a specific angle.

[0323] Figure 21E The structure of the composite layer 4009, including layers 4003 and 4004, is shown. One of layers 4003 and 4004 is a support such as a glass substrate, while the other can be formed from an inorganic film, an organic resin coating film, or a thin film. The resin portion of the composite layer 4009 uses a material with a higher refractive index than layer 4004. Similarly, layer 4004 uses a material with a higher refractive index than layer 4003.

[0324] A first interface is formed between composite layer 4009 and layer 4004, and a second interface is formed between layer 4004 and layer 4003. Through this structure, light that does not undergo total internal reflection at the first interface undergoes total internal reflection at the second interface and can return to composite layer 4009. Therefore, the light emitted by light-emitting device 4342 can be utilized efficiently.

[0325] Notice, Figure 20B and Figures 21A to 21E The structures can be combined with each other.

[0326] This embodiment can be implemented by appropriately combining the structures described in other embodiments, etc.

[0327] (Implementation Method 3)

[0328] In this embodiment, an example of a transistor that can be used instead of the transistors shown in the above embodiments will be described with reference to the accompanying drawings.

[0329] One embodiment of the display device of the present invention can be manufactured using transistors of various forms, such as bottom-gate transistors or top-gate transistors. Therefore, the semiconductor layer material or transistor structure used can be easily replaced to accommodate existing production lines.

[0330] Bottom-gate transistor

[0331] Figure 22A1 A cross-sectional view along the channel length of a channel-protected transistor 810, one of the bottom-gate transistors, is shown. Figure 22A1 In this embodiment, transistor 810 is formed on substrate 771. Furthermore, transistor 810 includes an electrode 746 on substrate 771, separated by an insulating layer 772. Additionally, a semiconductor layer 742 is included on electrode 746, separated by an insulating layer 726. Electrode 746 can be used as a gate electrode. Insulating layer 726 can be used as a gate insulating layer.

[0332] Additionally, an insulating layer 741 is included in the channel formation region of the semiconductor layer 742. Furthermore, electrodes 744a and 744b are included on the insulating layer 726 in contact with a portion of the semiconductor layer 742. Electrode 744a can be used as one of the source electrode and the drain electrode. Electrode 744b can be used as the other of the source electrode and the drain electrode. A portion of electrode 744a and a portion of electrode 744b are formed on the insulating layer 741.

[0333] The insulating layer 741 can be used as a channel protection layer. By providing the insulating layer 741 on the channel formation region, the semiconductor layer 742 can be prevented from being exposed during the formation of electrodes 744a and 744b. This prevents the channel formation region of the semiconductor layer 742 from being etched during the formation of electrodes 744a and 744b. According to one aspect of the present invention, a transistor with excellent electrical characteristics can be realized.

[0334] Additionally, transistor 810 includes an insulating layer 728 on electrodes 744a, 744b and insulating layer 741, and an insulating layer 729 on insulating layer 728.

[0335] When an oxide semiconductor is used in semiconductor layer 742, it is preferable to use a material capable of abstracting oxygen from a portion of semiconductor layer 742 to generate oxygen defects in at least the portions of electrodes 744a and 744b that are in contact with semiconductor layer 742. The carrier concentration in the region of semiconductor layer 742 where oxygen defects are generated increases, and this region becomes n-type, thus becoming an n-type region (n... + (Region). Therefore, this region can be used as a source region or a drain region. When an oxide semiconductor is used for the semiconductor layer 742, tungsten, titanium, etc. can be cited as examples of materials that can abstract oxygen from the semiconductor layer 742 to generate oxygen defects.

[0336] By forming source and drain regions in semiconductor layer 742, the contact resistance between electrodes 744a and 744b and semiconductor layer 742 can be reduced. Therefore, the electrical characteristics of the transistor, such as field-effect mobility and threshold voltage, can be optimized.

[0337] When a semiconductor such as silicon is used for semiconductor layer 742, it is preferable to provide layers that are used as n-type or p-type semiconductors between semiconductor layer 742 and electrode 744a and between semiconductor layer 742 and electrode 744b. The layers used as n-type or p-type semiconductors can be used as the source region or drain region of a transistor.

[0338] The insulating layer 729 is preferably formed of a material that prevents impurities from diffusing into the transistor from the outside or reduces the diffusion of impurities. Alternatively, the insulating layer 729 may be omitted if necessary.

[0339] Figure 22A2 The transistor 811 shown differs from the transistor 810 in that it includes an electrode 723 on the insulating layer 729, which can be used as a back gate electrode. The electrode 723 can be formed using the same material and method as the electrode 746.

[0340] Generally, the back gate electrode is formed using a conductive layer and is positioned such that a channel region of the semiconductor layer is sandwiched between the gate electrode and the back gate electrode. Therefore, the back gate electrode can have the same function as the gate electrode. The potential of the back gate electrode can be the same as the gate electrode, or it can be ground potential (GND potential) or any other potential. Furthermore, the threshold voltage of the transistor can be changed by independently altering the potential of the back gate electrode without being linked to the gate electrode.

[0341] Both electrode 746 and electrode 723 can be used as gate electrodes. Therefore, insulating layers 726, 728, and 729 can all be used as gate insulating layers. Alternatively, electrode 723 can be disposed between insulating layers 728 and 729.

[0342] Note that when one of electrodes 746 and 723 is referred to as the "gate electrode," the other is referred to as the "back gate electrode." For example, in transistor 811, when electrode 723 is referred to as the "gate electrode," electrode 746 is referred to as the "back gate electrode." Additionally, when electrode 723 is used as the "gate electrode," transistor 811 is a type of top-gate transistor. Furthermore, sometimes one of electrodes 746 and 723 is referred to as the "first gate electrode," and sometimes the other is referred to as the "second gate electrode."

[0343] By setting electrodes 746 and 723 with the semiconductor layer 742 in between and setting their potentials to be the same, the area through which charge carriers flow in the semiconductor layer 742 is expanded in the film thickness direction, thus increasing the amount of charge carrier movement. As a result, the on-state current of transistor 811 increases, and the field-effect mobility also increases.

[0344] Therefore, transistor 811 is a transistor with a large on-state current relative to its occupied area. That is, the occupied area of ​​transistor 811 can be reduced relative to the required on-state current. According to one aspect of the invention, the occupied area of ​​the transistor can be reduced. Therefore, according to one aspect of the invention, a highly integrated semiconductor device can be realized.

[0345] Furthermore, since the gate electrode and back gate electrode are formed using conductive layers, they have the function of preventing electric fields generated outside the transistor from affecting the semiconductor layer forming the channel (especially the electric field shielding function against static electricity, etc.). In addition, when the back gate electrode is formed to be larger than the semiconductor layer so as to cover the semiconductor layer with the back gate electrode, the electric field shielding function can be improved.

[0346] Furthermore, by using a conductive film with light-shielding properties to form the back gate electrode, light can be prevented from entering the semiconductor layer from the back gate electrode side. This prevents light degradation of the semiconductor layer and degradation of electrical characteristics such as threshold voltage drift in the transistor.

[0347] According to one aspect of the present invention, a transistor with high reliability can be realized. Furthermore, a semiconductor device with high reliability can be realized.

[0348] Figure 22B1 Showing with Figure 22A1 A cross-sectional view along the channel length of a channel-protected transistor 820 with a different structure. Transistor 820 has a structure substantially the same as transistor 810, except that insulating layer 741 covers the end of semiconductor layer 742. In an opening formed by selectively removing portions of insulating layer 741 overlapping semiconductor layer 742, semiconductor layer 742 is electrically connected to electrode 744a. Additionally, in other openings formed by selectively removing portions of insulating layer 741 overlapping semiconductor layer 742, semiconductor layer 742 is electrically connected to electrode 744b. The region of insulating layer 741 overlapping the channel formation region can be used as a channel protection layer.

[0349] Figure 22B2 The transistor 821 shown differs from the transistor 820 in that it includes an electrode 723 on the insulating layer 729, which can be used as a back gate electrode.

[0350] By providing the insulating layer 741, the exposure of the semiconductor layer 742 generated during the formation of electrodes 744a and 744b can be prevented. Therefore, the thinning of the semiconductor layer 742 during the formation of electrodes 744a and 744b can be prevented.

[0351] Furthermore, compared to transistors 810 and 811, the distances between electrodes 744a and 746, and between electrodes 744b and 746, are longer in transistors 820 and 821. Therefore, the parasitic capacitance generated between electrodes 744a and 746 can be reduced. Additionally, the parasitic capacitance generated between electrodes 744b and 746 can also be reduced. According to one aspect of the present invention, a transistor with excellent electrical characteristics can be provided.

[0352] Figure 22C1 A cross-sectional view along the channel length of a channel-etched transistor 825, one type of bottom-gate transistor, is shown. In transistor 825, electrodes 744a and 744b are formed without an insulating layer 741. Therefore, a portion of the semiconductor layer 742 exposed during the formation of electrodes 744a and 744b is sometimes etched. On the other hand, the absence of an insulating layer 741 improves transistor productivity.

[0353] Figure 22C2 The difference between transistor 826 and transistor 825 is that transistor 826 has an electrode 723 on insulating layer 729 that can be used as a back gate electrode.

[0354] Figures 23A1 to 23C2 Cross-sectional views of transistors 810, 811, 820, 821, 825, and 826 in the channel width direction are shown.

[0355] exist Figure 23B2 and Figure 23C2 In the structure shown, the gate electrode and the back gate electrode are connected to each other, so that the gate electrode and the back gate electrode have the same potential. In addition, the semiconductor layer 742 is sandwiched between the gate electrode and the back gate electrode.

[0356] In the channel width direction, the lengths of the gate electrode and the back gate electrode are greater than those of the semiconductor layer 742, and the semiconductor layer 742 is entirely covered by the gate electrode and the back gate electrode, sandwiching the insulating layers 726, 741, 728, and 729.

[0357] By employing this structure, the semiconductor layer 742 included in the transistor can be surrounded by the electric fields of the gate electrode and the back gate electrode.

[0358] The device structure of a transistor, such as transistor 821 or transistor 826, which uses the electric fields of the gate electrode and the back gate electrode to surround the semiconductor layer 742 forming the channel region, can be called a Surrounded channel (S-channel) structure.

[0359] By employing an S-channel structure, an electric field for inducing channel formation can be effectively applied to the semiconductor layer 742 using one or both of the gate and back gate electrodes. This improves the transistor's current drive capability, resulting in higher on-state current characteristics. Furthermore, the increased on-state current allows for transistor miniaturization. Additionally, the S-channel structure enhances the transistor's mechanical strength.

[0360] Top-gate transistor

[0361] Figure 24A1 The illustrated transistor 842 is one of the top-gate transistors. Electrodes 744a and 744b are electrically connected to the semiconductor layer 742 through openings formed in insulating layers 728 and 729.

[0362] Additionally, a portion of the insulating layer 726 that does not overlap with the electrode 746 is removed, and impurities are introduced into the semiconductor layer 742 using the electrode 746 and the remaining insulating layer 726 as a mask. This allows impurity regions to be formed in the semiconductor layer 742 in a self-aligned manner. The transistor 842 includes a region where the insulating layer 726 extends beyond the end of the electrode 746. The impurity concentration in the region of the semiconductor layer 742 where impurities are introduced through the insulating layer 726 is lower than in the region where impurities are introduced without the insulating layer 726. Therefore, an LDD (Lightly Doped Drain) region is formed in the region of the semiconductor layer 742 that overlaps with the insulating layer 726 but does not overlap with the electrode 746.

[0363] Figure 24A2 The transistor 843 shown differs from transistor 842 in that it includes an electrode 723. Transistor 843 includes an electrode 723 formed on a substrate 771. Electrode 723 includes a region that overlaps with semiconductor layer 742 across an insulating layer 772. Electrode 723 can be used as a back gate electrode.

[0364] In addition, such as Figure 24B1 The transistor 844 shown Figure 24B2 As shown in transistor 845, the insulating layer 726 in the area not overlapping with electrode 746 can also be completely removed. Additionally, as... Figure 24C1 The transistor 846 shown and Figure 24C2As with the transistor 847 shown, the insulating layer 726 can also be left unremoved.

[0365] In transistors 842 to 847, impurities can be introduced into semiconductor layer 742 after electrode 746 is formed, using electrode 746 as a mask, thereby self-aligning impurity regions in semiconductor layer 742. According to one aspect of the invention, transistors with excellent electrical characteristics can be realized. Furthermore, according to another aspect of the invention, highly integrated semiconductor devices can be realized.

[0366] Figures 25A1 to 25C2 Cross-sectional views of transistors 842, 843, 844, 845, 846, and 847 in the channel width direction are shown.

[0367] Transistors 843, 845, and 847 have the aforementioned S-channel structure. However, they are not limited to this; transistors 843, 845, and 847 may also not have an S-channel structure.

[0368] This embodiment can be implemented by appropriately combining the structures described in other embodiments, etc.

[0369] (Implementation Method 4)

[0370] Examples of electronic devices that can utilize a display device according to one aspect of the present invention include display devices, personal computers, image storage devices and image reproduction devices with recording media, mobile phones, game consoles including portable game consoles, portable data terminals, e-book readers, shooting devices such as video cameras or digital cameras, head-mounted displays, navigation systems, audio reproduction devices (car audio systems, digital audio players, etc.), photocopiers, fax machines, printers, multifunction printers, automatic teller machines (ATMs), and vending machines. Figure 26 shows specific examples of these electronic devices.

[0371] Figure 26A It is a digital camera, including a housing 961, a shutter button 962, a microphone 963, a speaker 967, a display unit 965, operation keys 966, a zoom button 968, a lens 969, etc. By using the display device of one aspect of the present invention in the display unit 965, various images can be displayed.

[0372] Figure 26B It is a portable data terminal, including a housing 911, a display unit 912, a speaker 913, operation buttons 914, a camera 919, etc. Data can be input or output using the touch screen function of the display unit 912. By using a display device according to one aspect of the present invention in the display unit 912, various images can be displayed.

[0373] Figure 26C This is a mobile phone, including a housing 951, a display unit 952, operation buttons 953, an external connection port 954, a speaker 955, a microphone 956, a camera 957, etc. The mobile phone includes a touch sensor in the display unit 952. All operations, such as making calls or inputting text, can be performed by touching the display unit 952 with a finger or stylus. Furthermore, the housing 901 and the display unit 952 are flexible and can be bent as shown in the figure. By using a display device according to one aspect of the present invention in the display unit 952, various images can be displayed.

[0374] Figure 26D It is a video camera, including a first housing 901, a second housing 902, a display unit 903, operation keys 904, a lens 905, a connecting part 906, a speaker 907, etc. The operation keys 904 and the lens 905 are disposed in the first housing 901, while the display unit 903 is disposed in the second housing 902. By using the display device of one aspect of the present invention in the display unit 903, various images can be displayed.

[0375] Figure 26E It is a television set, including a housing 971, a display unit 973, operation buttons 974, a speaker 975, a communication connection terminal 976, and a photoelectric sensor 977, etc. The display unit 973 is equipped with a touch sensor, which allows for input operations. By using the display device of one aspect of the present invention in the display unit 973, various images can be displayed.

[0376] Figure 26F It is a digital signage system, including a large display unit 922. For example, the large display unit 922 is mounted on the side of a pillar 921. By using a display device according to one aspect of the present invention in the display unit 922, a display of high quality can be achieved.

[0377] This embodiment can be implemented by appropriately combining the structures described in other embodiments.

[0378] [Symbol Explanation]

[0379] 10: Pixel, 11: Source Driver, 12: Gate Driver, 13: Circuit, 14: Circuit, 15: Circuit, 16: Select Circuit, 17: Select Circuit, 18: Pixel Array, 21: Circuit, 25a: Output Terminal, 25b: Output Terminal, 25c: Output Terminal, 101: Transistor, 102: Transistor, 103: Transistor, 104: Transistor, 105: Transistor, 106: Capacitor, 107: Transistor, 108: Capacitor, 109: Transistor, 110: Transistor, 111: Capacitor, 112: Transistor, 113: Transistor, 114: Capacitor, 115: Capacitor, 116: Transistor, 117: Transistor, 118: Capacitor, 119: Transistor 121: Wiring, 122: Wiring, 123: Wiring, 124: Wiring, 125: Wiring, 126: Wiring, 127: Wiring, 128: Wiring, 141: Capacitor, 142: Liquid Crystal Device, 143: Transistor, 144: Transistor, 145: Transistor, 146: Capacitor, 147: Light Emitting Device, 148: Transistor, 149: Transistor, 151: Wiring, 152: Wiring, 153: Wiring, 154: Wiring, 155: Wiring, 156: Wiring, 170: Circuit, 171: Circuit, 215: Display Unit, 221a: Scan Line Drive Circuit, 231a: Signal Line Drive Circuit, 232a: Signal Line Drive Circuit, 241a: Common Line Drive Circuit, 723 726: Electrode, 728: Insulating layer, 729: Insulating layer, 741: Insulating layer, 742: Semiconductor layer, 744a: Electrode, 744b: Electrode, 746: Electrode, 771: Substrate, 772: Insulating layer, 810: Transistor, 811: Transistor, 820: Transistor, 821: Transistor, 825: Transistor, 826: Transistor, 842: Transistor, 843: Transistor, 844: Transistor, 845: Transistor, 846: Transistor, 847: Transistor, 901: Housing, 902: Housing, 903: Display unit, 904: Operation key, 905: Lens, 906: Connector, 907: Speaker, 911: Housing, 912: Display unit, 913 914: Speaker; 919: Operation button; 921: Camera; 922: Column; 951: Display unit; 952: Housing; 953: Operation button; 954: External connection port; 955: Speaker; 956: Microphone; 957: Camera; 961: Housing; 962: Shutter button; 963: Microphone; 965: Display unit; 966: Operation key; 967: Speaker; 968: Zoom button; 969: Lens; 971: Housing; 973: Display unit; 974: Operation button; 975: Speaker; 976: Communication connection terminal; 977: Light sensor; 4001: Substrate; 4003: Layer; 4004: Layer; 4005: Sealant; 4006: Substrate.4008: Liquid crystal layer, 4009: Composite layer, 4010: Transistor, 4011: Transistor, 4013: Liquid crystal device, 4014: Wiring, 4015: Electrode, 4016: Light scattering liquid crystal device, 4017: Electrode, 4018: FPC, 4019: Anisotropic conductive layer, 4020: Capacitor, 4021: Electrode, 4022: Transistor, 4023: Transistor, 4030: Electrode layer, 4031: Electrode layer, 4032: Insulating layer, 4033: Insulating layer, 4035: Spacer, 4041: Printed circuit board, 4042: Integrated circuit, 4102: Insulating layer, 4103: Insulating layer, 4104: Insulating layer, 4110: Insulating layer, 4111: Insulating layer 4112: Insulating layer; 4131: Coloring layer; 4132: Light-shielding layer; 4133: Insulating layer; 4200: Input device; 4210: Touch screen; 4227: Electrode; 4228: Electrode; 4237: Wiring; 4238: Wiring; 4239: Wiring; 4263: Substrate; 4272b: FPC; 4273b: IC; 4340a: Backlight unit; 4340b: Backlight unit; 4341: Light guide plate; 4342: Light-emitting device; 4344: Lens; 4345: Mirror; 4347: Printed circuit board; 4348: Reflective layer; 4352: Diffuser plate; 4510: Partition wall; 4511: Light-emitting layer; 4513: Light-emitting device; 4514: Filler material.

Claims

1. A display device, comprising: Shift register; Boost circuit; as well as Pixels The shift register includes a first output terminal, a second output terminal, and a third output terminal. The boost circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor. The pixel includes a fifth transistor. One of the source and drain terminals of the first transistor is electrically connected to one electrode of the first capacitor. One electrode of the first capacitor is electrically connected to one of the source and drain electrodes of the third transistor. One of the source and drain of the third transistor is electrically connected to the gate of the fifth transistor. The other electrode of the first capacitor is directly connected to one of the source and drain of the second transistor and one of the source and drain of the fourth transistor. The gates of the first transistor and the fourth transistor are directly connected to the first output terminal. The gate of the second transistor is electrically connected to the second output terminal. The gate of the third transistor is electrically connected to the third output terminal. The other of the source and drain of the third transistor is electrically connected to the other of the source and drain of the fourth transistor. Furthermore, the shift register is configured to output signal voltages at different timings for each output terminal, in the order of the first output terminal, the second output terminal, and the third output terminal.

2. The display device according to claim 1, The boost circuit also includes a sixth transistor and a second capacitor. One of the source and drain terminals of the sixth transistor is electrically connected to the first output terminal. The other of the source and drain of the sixth transistor is electrically connected to one electrode of the second capacitor and the gate of the first transistor. Furthermore, the other electrode of the second capacitor is electrically connected to one of the source and drain electrodes of the first transistor.

3. The display device according to claim 1, The boost circuit further includes a seventh transistor, an eighth transistor, and a third capacitor. The gate of the seventh transistor is electrically connected to the third output terminal. One of the source and drain of the seventh transistor is electrically connected to one electrode of the third capacitor, the gate of the third transistor, and one of the source and drain of the eighth transistor. Furthermore, the gate of the eighth transistor is electrically connected to the first output terminal.

4. The display device according to claim 1, The pixels include display elements. Furthermore, the pixel is configured to generate third data based on the first data and the second data, and to perform display using the display element based on the third data.

5. The display device according to claim 4, The display element is a liquid crystal device.

6. The display device according to claim 1, The boost circuit and the first to fourth transistors included in the pixel all contain metal oxides in the channel forming region, the metal oxides including In, Zn and M, and M is Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd or Hf.

7. An electronic device comprising the display device and camera as described in claim 1.

Images