Camera device

Abstract

The plurality of pixels respectively include: a light receiving element (100) that generates an electric charge in response to received light; a pixel circuit (11) that outputs an analog signal corresponding to the electric charge generated by the light receiving element; and a conversion circuit (12) that converts the analog signal output from the pixel circuit into a digital signal based on a reference signal whose voltage changes in a step-like manner. A generation unit (5) generates a first reference signal to be provided to a first pixel of the plurality of pixels and a second reference signal to be provided to a second pixel of the plurality of pixels different from the first pixel as reference signals. The first reference signal is provided to a first pixel of the plurality of pixels via a first wiring (1031a), and the second reference signal is provided to a second pixel of the plurality of pixels different from the first pixel via a second wiring (1031b).

Description

Technical Field

[0001] The invention relates to a camera device. Background Art

[0002] A pixel array is known in which pixels are arranged in a matrix, each pixel including a light receiving element that converts received light into an analog signal by photoelectric conversion. For such a pixel array, a structure has been proposed in which an analog-to-digital (AD) converter that converts a pixel signal based on an analog signal read out from each pixel into a pixel signal based on a digital signal is incorporated into each pixel (referred to as an in-pixel ADC).

[0003] For the in-pixel ADC, a single-slope ADC is generally used, which uses a RAMP signal whose voltage value changes according to the color scale over time. In this single-slope ADC, a RAMP signal is generated for each pixel of the pixel array, and a counter is started at the same time as the RAMP signal is generated. The comparator compares the voltage of the RAMP signal with the voltage of the pixel signal read out from the pixel. When the high-low relationship between these voltages is reversed, the comparator reverses the output and stops the counter, and outputs time information. This time information is converted into a digital code to obtain a pixel signal converted into a digital signal.

[0004] [Citation list]

[0005] [Patent Document]

[0006] [Patent Document 1] JP 2013-055589A

[0007] [Patent Document 2] JP 2018-186478 A Summary of the invention

[0008] [Technical issues]

[0009] In a configuration in which AD conversion is performed with respect to a pixel signal read out from each pixel included in a pixel array using a single slope type in-pixel ADC, for example, when the in-plane luminance distribution is flat, the output of the comparator is inverted at the same time. Therefore, there is a concern that the instantaneous current in the entire pixel array increases.

[0010] An object of the present disclosure is to provide an image pickup device in which a transient current in a pixel array can be suppressed.

[0011] [Solution to the problem]

[0012] According to the present disclosure, an imaging device includes: a plurality of pixels, each of the plurality of pixels including a light receiving element that generates an electric charge through photoelectric conversion in response to received light; a pixel circuit that reads out the electric charge from the light receiving element and outputs an analog signal corresponding to the electric charge; and a conversion circuit that converts the analog signal into a digital signal based on a comparison result obtained by comparing the analog signal with a reference signal whose voltage changes in a step-like manner at a constant slope over time; a generation unit that generates a first reference signal to be provided to a first pixel of the plurality of pixels and a second reference signal to be provided to a second pixel of the plurality of pixels different from the first pixel as reference signals; a first wiring that connects the generation unit and the first pixel; and a second wiring that connects the generation unit and the second pixel, wherein the first reference signal is provided to the first pixel via the first wiring, and the second reference signal is provided to the second pixel via the second wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 : is a block diagram showing the configuration of an example of an imaging device to which each embodiment of the present disclosure is applicable.

[0014] Figure 2 : is a block diagram showing an example of the configuration of a pixel to which each embodiment is applicable.

[0015] Figure 3 1 is a diagram showing an example of the structure of an image pickup device to which each embodiment is applicable.

[0016] Figure 4A 1 is a diagram showing an example of arrangement of each unit in the first semiconductor chip.

[0017] Figure 4B 1 is a diagram showing an example of arrangement of each unit in the second semiconductor chip.

[0018] Figure 5A : is a circuit diagram showing a configuration example of a pixel circuit and an ADC to which each embodiment is applicable.

[0019] Figure 5B : is a circuit diagram showing a configuration example of a pixel circuit and an ADC to which each embodiment is applicable.

[0020] Figure 6 It is a diagram for explaining the operation of the ADC and the storage circuit to which each embodiment is applicable.

[0021] Figure 7 is a diagram showing an example of the relationship between the operation of a pixel circuit to which each embodiment is applicable and a reference signal.

[0022] Figure 8: is a diagram showing a configuration of an example of an imaging device according to the related art.

[0023] Fig. 9 is a diagram showing an example of a reference signal output by a DAC in the related art.

[0024] Fig.10 is a diagram showing a configuration of an example of an image pickup device according to the first embodiment.

[0025] Fig.11 is a diagram for explaining the first offset according to the first embodiment.

[0026] Fig.12 2 is a diagram for explaining the second offset according to the first embodiment.

[0027] Fig.13 is a diagram showing a configuration of an example of an image pickup device according to a first modification of the first embodiment.

[0028] Fig.14 is a diagram showing a first example of wiring according to a second modification of the first embodiment.

[0029] Fig.15 is a diagram showing a second example of wiring according to the second modification of the first embodiment.

[0030] Fig.16 is a diagram showing a third example of wiring according to the second modification example of the first embodiment.

[0031] Fig.17 is a diagram showing a configuration of an example of an image pickup device according to the second embodiment.

[0032] Fig.18 is a circuit diagram showing a first example of a circuit capable of generating and outputting first and second reference signals to which the second embodiment is applicable.

[0033] Fig.19 is a circuit diagram showing a second example of a circuit capable of generating and outputting first and second reference signals to which the second embodiment is applicable.

[0034] Fig. 20 is a circuit diagram showing a third example of a circuit capable of generating and outputting first and second reference signals to which the second embodiment is applicable.

[0035] Fig.21 is a block diagram showing the configuration of an example of an electronic device according to the third embodiment.

[0036] Fig. 22 This is a diagram for explaining a usage example of an imaging device to which the technology of the present disclosure is applied.

[0037] Fig.23is a block diagram showing an example of a schematic configuration of an in-vivo information acquisition system.

[0038] Fig.24 : is a diagram showing an example of a schematic configuration of an endoscopic surgery system.

[0039] Fig.25 : is a block diagram showing an example of the functional configuration of a camera and a CCU.

[0040] Fig.26 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0041] Fig. 27 2 is an explanatory diagram showing an example of installation positions of the vehicle exterior information detection unit and the imaging unit. DETAILED DESCRIPTION

[0042] Hereinafter, each embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. In addition, in each of the following embodiments, the same parts are denoted by the same reference numerals, and repeated descriptions thereof are omitted.

[0043] (Common Configuration of Each Embodiment)

[0044] Figure 1 1 is a block diagram showing the configuration of an example of an imaging device to which each embodiment of the present disclosure is applicable. Figure 1 In the embodiment, the imaging device 1000 includes a pixel array unit 1, a vertical scanning circuit 2, a horizontal scanning circuit 3, a timing control unit 4, a digital-to-analog converter (DAC) 5, a time code generating circuit 6, an overall control unit 7 and an image processing unit 8.

[0045] The pixel array unit 1 includes a plurality of pixels 10. In addition, the pixel 10 includes a light receiving element, a pixel circuit, a conversion circuit, and a storage unit. Although each detail will be described later, the light receiving element generates a charge in response to light received by photoelectric conversion. The pixel circuit reads out the charge generated by the light receiving element and outputs it as an analog signal. The conversion circuit converts the analog signal output from the pixel circuit into a pixel signal as a digital signal based on a reference signal. The storage unit stores the pixel signal converted by the conversion circuit. The pixel 10 may also include a signal processing circuit that performs correlated double sampling (CDS) processing on the pixel signal to reduce noise.

[0046] In the pixel array unit 1, a plurality of pixels 10 are arranged in a matrix array in the horizontal direction (row direction) and the vertical direction (column direction). In the pixel array unit 1, the arrangement of the pixels 10 in the row direction is called a row. A frame of image (image data) is formed by pixel signals read out from a predetermined number of rows in the pixel array unit 1. For example, in a case where a frame of image is formed by 3000 pixels×2000 rows, the pixel array unit 1 includes at least 2000 rows each including at least 3000 pixels 10.

[0047] The vertical scanning circuit 2 generates a control signal such as a drive pulse when reading out a pixel signal from each pixel 10 according to the control of the overall control unit 7 described later, and supplies the control signal to each row of the pixel array unit 1. The horizontal scanning circuit 3 performs a selection operation for selecting each column of the pixel array unit 1 in a predetermined order according to the control of the overall control unit 7, thereby sequentially outputting each pixel signal held in a storage unit of each pixel 10. For example, the horizontal scanning circuit 3 is constructed by using a shift register or an address decoder.

[0048] For example, the timing control unit 4 generates one or more types of clock signals for controlling the operation of each unit of the image pickup device 1000 according to the control of the overall control unit 7. The clock signal generated by the timing control unit 4 is supplied to the vertical scanning circuit 2 and the horizontal scanning circuit 3. In addition, although not shown, the clock signal generated by the timing control unit 4 is also supplied to the DAC 5 and the time code generation circuit 6.

[0049] The DAC 5 generates a reference signal used in a conversion circuit in each pixel 10. For example, the DAC 5 generates a reference signal (RAMP signal) whose voltage decreases (or increases) in a stepwise manner with a constant slope based on the clock signal supplied from the timing control unit 4 and the digital value whose value decreases (or increases) in response to the clock signal supplied from the overall control unit 7. The reference signal generated by the DAC 5 is supplied to the pixel array unit 1, and is transferred to each pixel 10 included in the pixel array unit 1.

[0050] In addition, hereinafter, unless otherwise specified, the fact that the ramp (voltage drop or rise) of the reference signal has started is described as “the reference signal has started.” Similarly, the fact that the ramp of the reference signal has ended is described as “the reference signal has ended.”

[0051] The time code generation circuit 6 generates a time code according to the slope of the voltage in the reference signal. For example, in the time code generation circuit 6, a clock signal is provided from the timing control unit 4, and a signal indicating the start of the reference signal is provided from the overall control unit 7. When the reference signal has started, the time code generation circuit 6 counts according to the clock signal, and generates a time code indicating the time for each counted time. The time code generated by the time code generation circuit 6 is provided to the pixel array unit 1, and is transmitted to each pixel 10.

[0052] For example, the overall control unit 7 includes a processor, and uses a predetermined program to control the overall operation of the imaging device 1000. In addition, the overall control unit 7 can also control the overall operation of the imaging device 1000 according to a control signal input from the outside.

[0053] For example, the image processing unit 8 includes a frame memory, and stores pixel signals of one frame output from the horizontal scanning circuit 3. The image processing unit 8 performs predetermined image processing on the pixel signals of one frame stored. As the image processing here, processing such as gain adjustment and white balance adjustment can be considered. Without being limited to this, the image processing unit 8 can also implement processing such as edge extraction and face determination.

[0054] Figure 2 is a block diagram showing an example of a pixel configuration to which each embodiment is applicable. Figure 2 In the embodiment, the pixel 10 includes a pixel circuit 11, an analog-to-digital converter (ADC) 12, a storage circuit 13 and a calculation circuit 14.

[0055] The pixel circuit 11 includes a light receiving element and a readout circuit. The readout circuit reads out the charge generated in response to the light received by the light receiving element from the light receiving element. The readout circuit outputs an analog signal having a voltage corresponding to the readout charge. The analog signal output from the readout circuit is provided to the ADC 12. In addition, a reference signal is provided to the ADC 12 from the DAC 5.

[0056] Although details will be described later, the DAC 5 generates a reference signal for detecting a reset level of the readout circuit in one reading process from the readout circuit, and then generates a reference signal for detecting a level of an analog signal read out from the readout circuit.

[0057] The ADC 12 includes a comparison circuit. The comparison circuit compares the analog signal supplied from the pixel circuit 11 with the reference signal supplied from the DAC 5, and inverts the output signal VCO when the high-low relationship of the voltage between the analog signal and the reference signal is inverted. The output signal VCO of the ADC 12 is supplied to the storage circuit 13.

[0058] On the other hand, for example, the time code generation circuit 6 generates a time code updated at clock time intervals based on the clock signal. The time code generated by the time code generation circuit 6 is supplied to the write transmission circuit 20. For example, a write transmission circuit 20 is provided for each column in the pixel array unit 1, and a plurality of pixels 10 aligned in a corresponding row are connected thereto. The write transmission circuit 20 supplies the time code supplied from the time code generation circuit 6 to each connected pixel 10.

[0059] The storage circuit 13 is, for example, a latch circuit, and holds the time code supplied from the write transmission circuit 20. For example, the storage circuit 13 updates the time code supplied and held immediately before it with the time code supplied from the write transmission circuit 20. When the output signal VCO supplied from the ADC 12 is inverted, the storage circuit 13 stops updating the time code.

[0060] In addition, the calculation circuit 14 performs noise removal processing on the analog signal read out from the readout circuit based on the time code held in the storage circuit 13. For example, the calculation circuit 14 performs an operation to obtain the difference between the time code held based on the reference signal for detecting the reset level of the readout circuit and the time code held based on the reference signal for detecting the level of the analog signal read out from the readout circuit. Pixel data can be obtained based on the difference. The pixel data is pixel data from which offset noise has been removed and returned to the storage circuit 13. The storage circuit 13 holds the pixel data returned from the calculation circuit 14.

[0061] At the end timing of the reference signal, for example, for each row, pixel data from which noise has been removed is read out from the storage circuits 13 of the pixels 10 aligned in the row, and the read pixel data is output via the readout transfer circuit 21 .

[0062] For example, the readout transfer circuit 21 reads out the time code from each pixel 10 specified by the vertical scanning circuit 2 and the horizontal scanning circuit 3, and outputs the time code as pixel data. The pixel data output from the readout transfer circuit 21 is supplied to the image processing unit 8, and is stored in the frame memory. For example, when one frame of pixel data is stored in the frame memory, the image processing unit 8 performs predetermined image processing on the pixel data stored in the frame memory, and outputs the pixel data to the outside of the image pickup device 1000, for example.

[0063] Figure 3 1 is a diagram showing an example of the structure of an image pickup device 1000 to which each embodiment is applicable. Figure 3 In the embodiment, the imaging device 1000 is formed as one imaging device 1000 by bringing a first semiconductor chip 1001 and a second semiconductor chip 1002 into electrical contact with each other via, for example, a conductive path 16 and bonding them.

[0064] The pixel region 1010 is arranged on the first semiconductor chip 1001. In the pixel region 1010, light receiving elements are arranged in a matrix. Figure 3 In the example of FIG. 1 , the pixel circuits 11 are arranged in a matrix with respect to the pixel region 1010. The pixel logic region 1011 is arranged on the second semiconductor chip 1002. In the pixel logic region 1011, for example, the processing circuits 15 corresponding to the pixel circuits 11 are arranged in a matrix to correspond to the arrangement of the pixel circuits 11 in the first semiconductor chip 1001. For example, the processing circuits 15 include Figure 2 The ADC 12, the storage circuit 13 and the calculation circuit 14 are shown. That is, the pixel 10 includes the pixel circuit 11 arranged on the first semiconductor chip 1001 and the processing circuit 15 arranged on the second semiconductor chip 1002 one-to-one with respect to the pixel circuit 11.

[0065] In the above description, among the elements included in the pixel 10, the pixel circuit 11 is arranged on the first semiconductor chip 1001, and the processing circuit 15 is arranged on the second semiconductor chip 1002, but the arrangement is not limited to this example. For example, the pixel circuit 11 and a portion of the processing circuit 15 corresponding to the pixel circuit 11 may be arranged on the first semiconductor chip 1001, and the other portion of the processing circuit 15 corresponding to the pixel circuit 11 may be arranged on the second semiconductor chip 1002. As an example, among the elements included in the processing circuit 15, a portion of the ADC 12 is arranged on the first semiconductor chip 1001 together with the corresponding pixel circuit 11, and the other portion of the ADC 12 is arranged on the second semiconductor chip 1002 together with the storage circuit 13 and the calculation circuit 14 included in the corresponding processing circuit 15.

[0066] Next, the arrangement of each portion in the first semiconductor chip 1001 and the second semiconductor chip 1002 will be schematically explained. Figure 4A 1 is a diagram showing an example of the arrangement of each part in the first semiconductor chip 1001. Figure 4A In the embodiment, the pixel region 1010 is arranged on the first semiconductor chip 1001, and a part of the vertical scanning circuit 2, a part of the horizontal scanning circuit 3, and the DAC 5 are also arranged. Figure 4A In the example of FIG. 1 , the vertical scanning circuits 2 are arranged on both sides of the pixel region 1010 in the row direction ( Figure 4A In addition, Figure 4A In the example of FIG. 1 , a portion of the horizontal scanning circuit 3 is arranged on one side of the pixel region 1010 in the column direction (eg, Figure 4A ), and the DAC 5 is arranged on the other side in the column direction.

[0067] Figure 4B 1 is a diagram showing an example of the arrangement of each part in the second semiconductor chip 1002. Figure 4B In the embodiment, the pixel logic region 1011 is arranged on the second semiconductor chip 1002, and a part of the vertical scanning circuit 2, a part of the horizontal scanning circuit 3 and a logic unit 1012 are also arranged thereon. For example, the logic unit 1012 includes Figure 1 The timing control unit 4, the time code generating circuit 6, the overall control unit 7 and the image processing unit 8 are shown.

[0068] In addition, Figure 4A and Figure 4B In the example of FIG. 1 , the vertical scanning circuit 2 and the horizontal scanning circuit 3 are separated and arranged on the first semiconductor chip 1001 and the second semiconductor chip 1002 .

[0069] Next, we will refer to Figure 5A and Figure 5B The configurations of the pixel circuit 11 and the ADC 12 to which each embodiment is applicable will be described. Figure 5A and Figure 5B 1 is a circuit diagram showing a configuration example of a pixel circuit 11 and an ADC 12 to which each embodiment is applicable. Figure 5A An example of a circuit of the pixel circuit 11 and the ADC 12 is shown in the case where a part of the ADC 12 and the pixel circuit 11 to which the embodiments are applicable are arranged on the first semiconductor chip 1001. The other part of the ADC 12 is arranged on the second semiconductor chip 1002.

[0070] exist Figure 5A , the pixel circuit 11 includes a reset transistor 104, a floating diffusion (FD) 101, a transfer transistor 103, a photodiode (PD) 100, and a drain transistor 102. For example, N-channel metal oxide semiconductor (MOS) transistors are used for the reset transistor 104, the transfer transistor 103, and the drain transistor 102.

[0071] The photodiode 100 generates electric charge by photoelectric conversion. The discharge transistor 102 discharges the electric charge accumulated in the photodiode 100 at the start of exposure according to the drive signal OFG supplied from the vertical scanning circuit 2. The transfer transistor 103 transfers the electric charge from the photodiode 100 to the FD 101 at the end of exposure according to the transfer signal TRG from the vertical scanning circuit 2. The FD 101 accumulates the transferred electric charge and generates a voltage corresponding to the amount of the accumulated electric charge. The reset transistor 104 initializes the FD 101 according to the reset signal RST supplied from the vertical scanning circuit 2.

[0072] The ADC 12 includes a comparator including transistors 108 , 109 , and 110 , which are P-channel MOS transistors, and transistors 106 , 107 , and 105 , which are N-channel MOS transistors.

[0073] The transistors 106 and 105 form a differential pair, and the sources of these transistors are commonly connected to the drain of the transistor 107. In addition, the drain of the transistor 106 is connected to the drain of the transistor 108 and the gates of the transistors 108 and 109. The drain of the transistor 105 is connected to the drain of the transistor 109, the gate of the transistor 110, and the drain of the reset transistor 104. In addition, the RAMP signal is input to the gate of the transistor 106 as a reference signal.

[0074] A predetermined bias voltage BIAS is applied to the gate of the transistor 107, and a predetermined ground voltage is applied to the source of the transistor 107. The gate of the transistor 105 is connected to the reset transistor 104, the FD 101, and the transfer transistor 103.

[0075] The transistors 108 and 109 form a current mirror circuit. A power supply voltage HV is applied to the sources of the transistors 108, 109, and 110. The power supply voltage HV is set higher than the power supply voltage LV. In addition, the drain of the transistor 110 is connected to the transistor 113 constituting the voltage conversion circuit.

[0076] Furthermore, the pixel circuit 11 and transistors 106, 107, and 105 are formed in the first semiconductor chip 1001. The transistors 105 and 106 are connected to transistors 108 and 109 forming a current mirror circuit formed on the second semiconductor chip via connection portions 120a and 120b, for example, by copper-copper connection (CCC).

[0077] The power supply voltage LV is applied to the gate of a transistor 113 constituting a voltage conversion circuit as part of the ADC 12. The voltage conversion circuit can convert the power supply voltage HV into a lower power supply voltage LV, and a circuit operating at a low voltage can be arranged in a subsequent stage. The drain of the transistor 113 is connected to the drain of the transistor 110, and its source is connected to a positive feedback circuit as part of the ADC 12.

[0078] exist Figure 5A In the example of , the positive feedback circuit is configured to include transistors 111 and 112 which are P-channel MOS transistors, a transistor 114 which is an N-channel MOS transistor, and a NOR circuit 115 .

[0079] In the positive feedback circuit, transistors 111 and 112 are connected in series with a power supply voltage LV. In addition, a drive signal INI supplied from the vertical scanning circuit 2 is input to the gate of the transistor 111. The drain of the transistor 112 is connected to the source of the transistor 113, the drain of the transistor 114, and one input terminal of the NOR circuit 115. The control signal VCO supplied from the vertical scanning circuit 2 FORCE The signal FB is input to the other input terminal of the NOR circuit 115. The output of the NOR circuit 115 is input to the gate of the transistor 112 as a positive feedback signal FB.

[0080] A ground voltage is applied to the source of the transistor 114, and a driving signal supplied from the vertical scanning circuit 2 is input to the gate.

[0081] The output of the NOR circuit 115 is also output as an output signal VCO via buffer circuits 116 and 117 .

[0082] In the above configuration, when the high-low relationship between the voltage generated by FD 101 input to the gate of transistor 105 and the voltage of the reference signal input to the gate of transistor 106 is reversed, the comparator reverses the signal output from the drain of transistor 109 from a high level to a low level. The signal is further reversed by transistor 110 and input to the voltage conversion circuit (transistor 113). At this time, since the signal input to the voltage conversion circuit is inert, the high-level voltage is an intermediate voltage. Therefore, the positive feedback circuit provided in the rear stage of the voltage conversion circuit causes the high-level voltage to rise and shapes the signal. The shaped signal is output as the output signal VCO of ADC 12.

[0083] Figure 5B A circuit example is shown in which the pixel circuit 11 to which each embodiment is applicable is arranged on the first semiconductor chip 1001 and the entire ADC 12 is arranged on the second semiconductor chip 1002. Figure 5B In the example of FIG. 1 , the output of the pixel circuit 11 and the gate of the transistor 105 constituting the comparator in the ADC 12 are connected via the connection portion 120c by CCC or the like. Here, unlike the usual CCC, the connection portion 120c uses a configuration in which parallel plates are formed and capacitive coupling is used.

[0084] At this time, in order to prevent the capacity of the connection portion 120 c from looking like the capacity of the FD 101 when viewed from the comparator side, a buffer formed of transistors 130 and 131 which are N-channel MOS transistors is provided between the connection portion 120 c and the FD 101 .

[0085] In addition, Figure 5BIn the configuration of , the drain of the transistor 118, which is an N-channel MOS transistor, is connected to the drain of the transistor 105, and the source thereof is connected to the gate of the transistor 105. For example, the auto-zero signal AZ is supplied from the vertical scanning circuit 2 to the gate of the transistor 118. For example, the transistor 118 is controlled so that it is turned on / off according to the auto-zero signal AZ, is connected between the drain and the gate of the transistor 105 in its on state, and initializes the capacity of the connection portion 120c when viewed from the transistor 105. In addition, the auto-zero signal AZ does not need to be synchronized with the reset signal RST.

[0086] In addition, Figure 5A The configuration shown is applicable to a case where the DAC 5 is arranged in Figure 4A and Figure 4B In the case of the example shown on the first semiconductor chip 1001, a signal line (RAMP line) and a driver for supplying a reference signal (RAMP signal) output from the DAC 5 to the transistor 106 are arranged on the first semiconductor chip 1001. Figure 5B The configuration shown is suitable for Figure 4A and Figure 4B In the case of the illustrated arrangement example, the RAMP line and the driver are arranged on the second semiconductor chip 1002. In the case where the DAC 5 includes the driver, the DAC 5 will be divided and arranged on the first semiconductor chip 1001 and the second semiconductor chip 1002.

[0087] In addition, the above Figure 4A and Figure 4B The arrangement shown in is not limited to this example. For example, the DAC 5 may also be arranged on the second semiconductor chip 1002. Figure 5A In the case where the configuration shown is applicable to this arrangement, the RAMP line and the driver are arranged on the first semiconductor chip 1001. In the case where the DAC 5 includes the driver, the DAC 5 will be divided and arranged on the first semiconductor chip 1001 and the second semiconductor chip 1002. On the other hand, in Figure 5B The illustrated configuration is applicable to the case of an example in which the DAC 5 is arranged on the second semiconductor chip 1002 , and the RAMP line and the driver are arranged on the second semiconductor chip 1002 .

[0088] Will refer to Figure 6 and Figure 7 The operations of the pixel circuit 11 , the ADC 12 , and the storage circuit 13 to which each embodiment is applicable are described. Figure 6 1 is a diagram for explaining the operation of the ADC 12 and the storage circuit 13 to which each embodiment is applicable. Figure 6In FIG. 1 , the reference signal (RAMP signal) is shown as a signal whose voltage decreases at a predetermined slope as time passes. Figure 6 , for convenience of explanation, the reference signal is shown as a ramp-shaped signal in which the voltage decreases linearly with respect to time, but actually, the DAC 5 generates a signal in which the voltage decreases stepwise in response to, for example, a color scale value.

[0089] The time when the voltage drop in the reference signal starts is set as the time when the ADC operation starts, and the time code generating circuit 6 generates a time code based on a predetermined clock. Figure 6 In the example of , in the high state of the signal displayed as the time code, the time code is updated. The storage circuit 13 holds the time code generated by the time code generating circuit 6. When the supplied time code is updated, the storage circuit 13 updates the held time code with the updated time code.

[0090] When the ADC operation starts, the voltage of the reference signal and the voltage of the FD 101 are compared in the comparator of the ADC 12. When the high-low relationship of these voltages is reversed, the comparator reverses the output voltage in the high state to put it in the low state, and the ADC operation is ended. The storage circuit 13 stops updating the retained time code in response to the inversion of the output of the comparator. As a result, the time code when the ADC operation is completed is retained in the storage circuit 13.

[0091] Figure 7 1 is a diagram showing an example of the relationship between the operation of the pixel circuit 11 to which each embodiment can be applied and the reference signal. For example, the reference signal is initially the voltage of the reset level of the FD 101 detected last time. At time t0 to t1, the reset signal RST is set to a high state, and the FD 101 is initialized. After the initialization of the FD 101, the DAC 5 causes the voltage of the reference signal to drop from a predetermined voltage. As a result, a first slope 1040 of the reference signal is formed. In response to the first slope 1040, a first ADC operation is performed in the ADC 12. Due to the first ADC operation, the voltage of the reset level of the FD 101 is detected based on the first slope 1040 of the reference signal. The DAC 5 stops the reduction of the reference signal at a predetermined timing (time t2), and sets the voltage of the reference signal to a predetermined voltage when the voltage drop starts.

[0092] Next, at time t3 to t4, the transfer signal TRG is set to a high state, charges are transferred from the photodiode 100 to the FD 101, and the FD 101 generates a voltage corresponding to the amount of the transferred charges. The DAC 5 causes the transfer signal TRG to cause the voltage of the reference signal to drop from a predetermined voltage at time t4. As a result, a second slope 1041 of the reference signal is formed. In response to the second slope 1041, a second ADC operation is started in the ADC 12. Due to the second ADC operation, a voltage corresponding to the amount of charge in the FD 101 is detected based on the second slope 1041 of the reference signal. When the reference signal reaches the lower limit (time t5), the DAC 5 stops the reduction of the reference signal.

[0093] By obtaining the difference between the voltage detected by the first ADC operation and the voltage detected by the second ADC operation, a pixel signal from which offset noise has been removed can be obtained. In this way, the ADC 12 performs two ADC operations when a pixel signal is read out once in the pixel circuit 11.

[0094] (Configuration example using conventional technology)

[0095] Next, before explaining the present disclosure, reference will be made to Figure 8 and Fig. 9 The invention describes the provision of a reference signal to a pixel array unit by an in-pixel ADC according to the prior art. Figure 8 FIG. 1 is a diagram showing an example of a configuration of an imaging device according to the prior art. Figure 8 For example, in Figure 1 In the configuration of the imaging device 1000 shown in FIG. 1 , the pixel array unit 1 and the DAC 5 are extracted and shown. Figure 8 A method of providing a reference signal to a pixel array unit in which each pixel has an in-pixel ADC is described. Figure 8 In similar figures thereafter, the first semiconductor chip 1001 is illustrated as an “upper chip”, and the second semiconductor chip 1002 is illustrated as a “lower chip”.

[0096] In the upper chip, pixels 10 having an in-pixel ADC configuration are arranged in a matrix in a pixel area 1010. In addition, a DAC 5 for generating and providing a reference signal is provided on the lower chip. The reference signal output from the DAC 5 is provided to each column in the pixel array unit 1 via each driver 1020 provided in each column. The reference signal is provided to each pixel 10 in the pixel array unit 1 via a grid-shaped wiring 1030 corresponding to the arrangement of the pixels 10.

[0097] For example, in the pixel array unit 1, a transparent insulating film is formed on each pixel 10. The wiring 1030 is formed on the transparent insulating film, and is connected to the circuit in each pixel 10 via a through hole 1021 provided in the transparent insulating film.

[0098] Fig. 9 is a diagram showing an example of a reference signal output by a DAC 5 in the prior art. Figure 7 As described above, the reference signal includes a first slope 1040 for detecting a voltage at a reset level of the FD 101 and a second slope 1041 for detecting a voltage corresponding to an amount of charge accumulated in the FD 101 .

[0099] According to the prior art, for example, when the brightness distribution of light received by the pixel array unit 1 in the plane of the pixel area 1010 is flat, the outputs of the comparators will be inverted all together in the ADC 12. Therefore, there is a concern that the instantaneous current in the entire pixel array unit 1 increases.

[0100] [First embodiment]

[0101] Next, the first embodiment will be described. In the first embodiment, a plurality of DACs for generating and providing reference signals are provided, and, for example, each of the plurality of DACs generates and outputs respective reference signals shifted in the voltage direction or the time direction. The respective reference signals are provided to different pixels 10 via different wirings. With this configuration, for example, in the case where the brightness distribution of light received by the pixel array unit 1 in the plane of the pixel region 1010 is flat, simultaneous inversion of the comparator in the ADC in each pixel can be avoided.

[0102] Fig.10 1 is a diagram showing the configuration of an example of an image pickup device according to the first embodiment. Fig.10 in Figure 1 In the configuration of the imaging device 1000 shown in FIG. 1 , the pixel array unit 1 and the DAC 5 ( Fig.10 DAC 5a and 5b) in the example, and the other parts are omitted.

[0103] exist Fig.10 In FIG. 1 , the imaging device 1000 a includes two DACs 5 a and 5 b that generate and output reference signals, respectively. Fig.10 In the example of , DACs 5a and 5b are provided together on one side of the pixel region 1010. The output from the DAC 5a is connected to the wiring 1031a provided on the pixel region 1010 via the driver 1020. On the other hand, the output of the DAC 5b is connected to the wiring 1031b provided on the pixel region 1010 via the driver 1020.

[0104] For example, the wirings 1031a and 1031b are formed in two layers via a transparent insulating film. The wirings 1031a and 1031b are connected to different pixels 10 via the through holes 1021, respectively. Fig.10 In the example of FIG. 1 , the wirings 1031 a and 1031 b are connected to pixels 10 which are not adjacent to each other.

[0105] Furthermore, in the first embodiment, the wirings 1031a and 1031b are arranged in a lattice shape so as to respectively correspond to the positions of the pixels 10 arranged in a matrix-like layout. Fig.10 In the example of FIG. 1 , each of the wirings 1031 a and 1031 b is configured as a lattice of every other column and every other row, respectively. Each of the wirings 1031 a and 1031 b is provided with a through hole 1021 at each lattice point, and is connected to the pixel 10 via the through hole 1021 .

[0106] The DAC 5a generates a first reference signal (referred to as RAMP(A)) and supplies it to the wiring 1031a via each driver 1020. The first reference signal is supplied to each pixel 10 connected to the wiring 1031a via the wiring 1031a. Similarly, the DAC 5b generates a second reference signal (referred to as RAMP(B)) and supplies it to the wiring 1031b via each driver 1020. The second reference signal is supplied to each pixel 10 connected to the wiring 1031b via the wiring 1031b.

[0107] In addition, in reference Figure 5A In the pixel 10, when a part of the pixel circuit 11 and the ADC 12 are arranged on the first semiconductor chip 1001 and the other parts are arranged on the second semiconductor chip 1002, the wirings 1031a and 1031b are preferably provided on the first semiconductor chip 1001. Figure 5B In the above-described pixel 10 , in the case where the pixel circuit 11 is arranged on the first semiconductor chip 1001 and the other parts are arranged on the second semiconductor chip 1002 , the wirings 1031 a and 1031 b are preferably provided on the second semiconductor chip 1002 .

[0108] (Regarding Reference Signal According to First Embodiment)

[0109] As described above, in the first embodiment, a plurality of reference signals are dispersed and provided to each pixel 10 included in the pixel region 1010. As a result, in the case where each pixel 10 included in the pixel region 1010 has an intra-pixel ADC configuration, the outputs of the comparators in each pixel 10 included in the pixel region 1010 can be prevented from being simultaneously inverted.

[0110] Next, the reference signal according to the first embodiment will be described. In the first embodiment, a signal obtained by applying an offset to the first reference signal generated by the DAC 5a is generated as a second reference signal by the DAC 5b. Fig.11 and Fig.12 Describes the offset applied to the reference signal.

[0111] Fig.11 is a diagram for explaining the first offset according to the first embodiment. The first offset offsets the voltage V ofst The reset level of the first reference signal (RAMP(A)) and the second reference signal (RAMP(B)) generated by the DACs 5a and 5b is provided. ofst For the same FD voltage, the FD voltage FD_A seen from the first reference signal and the FD voltage FD_B seen from the second reference signal can be made to differ from each other by the offset voltage V ofst The corresponding amount.

[0112] exist Fig.11 In the example of FIG. 1 , before detecting the reset level of the FD voltage, the reset level of the second reference signal is set to be equal to the value obtained by setting the offset voltage V ofst A voltage obtained by adding the reset level of the first reference signal.

[0113] exist Fig.11 In the example of , the first slope 1040a and the second slope 1041a of the first reference signal are the same as the first slope 1040b and the second slope 1041b of the second reference signal. On the other hand, as described above, the FD voltage FD_A seen from the first reference signal and the FD voltage FD_B seen from the second reference signal differ from each other by the offset voltage V ofst Therefore, if Fig.11 As shown in the enlarged lower left of FIG. 1 , an offset voltage V is generated between the inversion time of the comparator relative to the FD voltage FD_A in the first reference signal and the inversion time of the comparator relative to the FD voltage FD_B in the second reference signal. ofst The corresponding time difference Δt. Therefore, the simultaneous inversion of the outputs of the comparators in the pixel array unit 1 can be avoided.

[0114] In addition, in this case, the first reference signal generated by the DAC 5a can be regarded as a signal in which the offset voltage V ofst =0 signal applied to the first reference signal.

[0115] Fig.12 5a is a diagram for explaining the second offset according to the first embodiment. The second offset is an offset in the time direction relative to the first reference signal (RAMP(A)) generated by the DAC 5a. Fig.12As shown, DAC 5a generates a first reference signal (RAMP(A)) including a first slope 1040a and a second slope 1041a. On the other hand, DAC 5b generates a first reference signal (RAMP(A)) by applying an offset time t to the first reference signal. ofst The obtained signal is used as the second reference signal (RAMP(B)).

[0116] exist Fig.12 In the example of FIG. 1 , the timing of the first slope 1040b and the second slope 1041b of the second reference signal are respectively offset by an offset time t relative to the first slope 1040a and the second slope 1041a of the first reference signal. ofst Therefore, if Fig.12 As shown in the enlarged lower left of FIG. 1 , the first slope 1040b of the second reference signal is offset in the time direction relative to the first slope 1040a of the first reference signal, and therefore, the intersection of the first slopes 1040a and 1040b relative to the same voltage FD occurs at the offset time t ofst Therefore, even when the voltage FD of the FD 101 supplied from the pixel circuit 11 to the ADC 12 is equal in each pixel 10, an offset time t may occur in the inversion timing of the comparator between each pixel 10 supplied with the first reference signal and each pixel 10 supplied with the second reference signal. ofst Therefore, the simultaneous inversion of the outputs of the comparators in the pixel array unit 1 can be avoided.

[0117] In this case, the first reference signal generated by the DAC 5a can be regarded as an offset time t of the zero time. ofst signal applied to the first reference signal.

[0118] (First Modification of the First Embodiment)

[0119] Next, a first modification of the first embodiment will be described. Fig.10 As shown, DACs 5a and 5b are provided together on one side of the pixel region 1010, but the layout is not limited to this example. In the first modification of the first embodiment, DAC 5a is provided on one side of the opposite side of the pixel region 1010, and DAC 5b is provided on the other side.

[0120] Fig.13 1 is a diagram showing a configuration of an example of an image pickup device according to a first modification of the first embodiment. Fig.13 In the above Fig.10 Similar, in Figure 1 In the configuration of the imaging device 1000 shown in FIG. 1 , the pixel array unit 1 and the DAC 5 ( Fig.13DAC 5a and 5b) in the example, and the other parts are omitted.

[0121] exist Fig.13 In FIG. 1 , the imaging device 1000 b includes two DACs 5 a and 5 b that generate and output reference signals, respectively. Fig.13 In the example of , the DAC 5a is provided on one side of the pixel region 1010. On the other hand, the DAC 5b is provided on the opposite side to the DAC 5a with the pixel region 1010 sandwiched therebetween. The output of the DAC 5a is connected to the wiring 1031a provided on the pixel region 1010 via the driver 1020 from the side of the pixel region 1010 opposite to the side on which the DAC 5a is provided with the pixel region 1010 sandwiched therebetween, and is connected to the wiring 1031b provided on the pixel region 1010 via the driver 1020.

[0122] The first reference signal (RAMP(A)) generated by the DAC 5a and the second reference signal (RAMP(B)) generated by the DAC 5b may be applied with the first offset (offset voltage V ofst ) and the second offset (offset time t ofst )

[0123] In this first variant of the first embodiment, similar to the above-mentioned first embodiment, even when the voltage of FD 101 supplied from the corresponding pixel circuit 11 to ADC 12 is equal between the pixel 10 supplied with the first reference signal and the pixel 10 supplied with the second reference signal, the inversion timing of the comparator in each pixel 10 can be made different.

[0124] Furthermore, even if the layout on the semiconductor chip is limited, the Fig.10 The DACs 5a and 5b are arranged or according to Fig.13 In the case of the arrangement of DACs 5a and 5b, the same effect can be obtained.

[0125] (Second Modification of the First Embodiment)

[0126] Next, a second modification of the first embodiment will be described. The second modification of the first embodiment is an example in the case where a color filter is provided for each pixel 10 included in the pixel array unit 1 .

[0127] In the second modification of the first embodiment, in this case, one of the plurality of wirings providing different reference signals is commonly connected to each of the plurality of pixels 10 provided with a color filter that passes the same wavelength component. In this way, the reference signal is provided to each of the pixels 10 provided with a color filter that passes the same wavelength component via the common wiring, and thus the influence of the offset in the reference signal on the pixel signal having the same wavelength component can be avoided. In addition, hereinafter, unless otherwise specified, "the same wavelength component" is described as "the same color".

[0128] Fig.14 1 is a diagram showing a first example of wiring according to a second modification of the first embodiment. Fig.14 In the example of , for each pixel 10, color filters of red (R), green (G), and blue (B) are arranged in units of 2 pixels×2 pixels according to the Bayer arrangement. Fig.14 In the example of , one R color filter, one B color filter, and two G color filters are provided for four pixels 10 of 2 pixels×2 pixels so that color filters of the same color are not adjacent to each other. Fig.14 , the pixels 10 provided with color filters of R, G, and B colors are respectively illustrated as a pixel 10R, a pixel 10G, and a pixel 10B.

[0129] exist Fig.14 In the example of, for example, the wiring 1031a provided with the first reference signal (RAMP(A)) is connected to each pixel 10G. On the other hand, the wiring 1031b provided with the second reference signal (RAMP(B)) is connected to the pixels 10R and 10B, respectively. In this case, two types of reference signals are applicable to three color filters of R color, G color, and B color. Therefore, the first reference signal is provided to the pixel 10G provided with the color filter of G color which is more visually sensitive. In addition, the second reference signal is commonly provided to the pixels 10R and 10B provided with the color filters of R color and B color which are less sensitive than G color.

[0130] Fig.15 1 is a diagram showing a second example of wiring according to a second modification of the first embodiment. The second example is a wiring example in which color filters of R, G, and B colors are provided for each pixel 10 in an arrangement different from the Bayer arrangement. Fig.15 In the example of , in an arrangement where each pixel of the Bayer arrangement is divided into 4 pixels consisting of 2 pixels×2 pixels, each color filter of R color, G color, and B color is provided in each pixel 10. This color filter arrangement is called a 4-division Bayer type RGB arrangement.

[0131] In this 4-division Bayer type RGB arrangement, for example, as shown in FIG. Fig.14As in the case of the Bayer type arrangement described above, the wiring 1031a provided with the first reference signal (RAMP(A)) is also connected to each pixel 10G. On the other hand, the wiring 1031b provided with the second reference signal (RAMP(B)) is connected to the pixels 10R and 10B, respectively. In the 4-division Bayer type RGB arrangement, color filters of the same color are provided for four adjacent pixels 10 in an arrangement of 2 pixels×2 pixels. Therefore, the wirings 1031a and 1031b are connected in an arrangement of 2 pixels×2 pixels in units of four adjacent pixels 10.

[0132] Fig.16 is a diagram showing a third example of wiring according to the second modification example of the first embodiment. The third example is an example in which three or more reference signals are provided via different wirings. Fig.16 The example of is an example in which a white (W) color filter is provided as a color filter provided for each pixel 10 in addition to the color filters of R color, G color, and B color. Fig.16 , a pixel 10 provided with a W color filter is shown as a pixel 10W. For example, a white (W) color filter is a color filter that transmits all wavelengths in the visible light region at a transmittance of a predetermined value or higher. As a W color filter, a filter that transmits wavelengths outside the visible light region such as the near-infrared region in addition to all wavelengths in the visible light region at a transmittance of a predetermined value or higher can also be used. Without being limited to this, a W color pixel 10W can be constructed without a color filter. For each of the four pixels 10 of 2 pixels × 2 pixels, each of these color filters of R color, G color, B color, and W color is set one-to-one.

[0133] exist Fig.16 In the example of , four types of reference signals are provided to correspond to four color filters of, for example, R color, G color, B color, and W color. For example, in addition to DACs 5a and 5b that respectively generate the first and second reference signals, two DACs 5 are provided to generate third and fourth reference signals offset from the first reference signal. For example, the second, third, and fourth reference signals are signals to which different offsets are applied to the first reference signal.

[0134] exist Fig.16 , the wiring 1031a is connected to each pixel 10G. The wiring 1031b is connected to each pixel 10W, and the wiring 1031c is connected to each pixel 10B. Similarly, the wiring 1031d is connected to each pixel 10R. Here, the wirings 1031a and 1031b are connected to the pixel region 1010 on one side ( Fig.16 The outputs of the DACs 5a and 5b (not shown) that generate the third reference signal and the fourth reference signal are connected to the wirings 1031c and 1031d, respectively.

[0135] [Second embodiment]

[0136] Next, a second embodiment will be described. The second embodiment is an example in which a plurality of reference signals to which different offsets are applied are generated and output by one DAC 5 . Fig.17 is a diagram showing the configuration of an example of an image pickup device according to the second embodiment. Fig.17 In the figure, we extract and show Figure 1 The image pickup device 1000 shown in the figure includes a pixel array unit 1 and a DAC 5 ( Fig.17 DAC 5c) in the example, and the other parts are omitted.

[0137] exist Fig.17 In the embodiment, the image pickup device 1000c according to the second embodiment includes a DAC 5c that can generate a first reference signal (RAMP(A)) and a second reference signal (RAMP(B)) to which different offsets are applied and output them simultaneously. The output of the first reference signal of the DAC 5c is connected to the wiring 1031a via each driver 1020. In addition, the output of the second reference signal of the DAC 5c is connected to the wiring 1031b via each driver 1020 different from the first reference signal.

[0138] In addition, Fig.17 For example, since the wirings 1031a and 1031b are connected to each pixel 10 and the above Fig.10 The connections are the same as in , so their description will be omitted here.

[0139] (Example of a Circuit That Can Generate and Output First and Second Reference Signals)

[0140] Figures 18 to 20 : is a circuit diagram showing an example of a circuit capable of generating and outputting first and second reference signals to which the second embodiment is applicable. Figures 18 to 20 DACs 5c(a), 5c(b), and 5c(d) are shown showing the application of an offset voltage V to a reference signal. ofst Example of the situation.

[0141] Fig.18 is a circuit diagram showing a first example of a circuit capable of generating and outputting first and second reference signals to which the second embodiment is applicable. Fig.18 , DAC 5c(a) generally includes a reference current generating unit and two DACs connected in parallel to each other and outputting a first reference signal (RAMP(A)) and a second reference signal (RAMP(B)), respectively. Each DAC includes a RAMP generating unit and an offset generating unit, and includes an output unit at a subsequent stage of the offset generating unit.

[0142] The reference current generating unit includes a transistor 201 which is an N-channel MOS transistor, a differential amplifier 200, and a resistor 202. A constant voltage V is generated by a bandgap reference (BGR) circuit (not shown) as a constant voltage source. BGR The output of the differential amplifier 200 is input to the gate of the transistor 201. The source of the transistor 201 is connected to the ground potential via the resistor 202 and is connected to the negative input terminal of the differential amplifier 200.

[0143] In this configuration, due to negative feedback formed by connecting the source of the transistor 201 to the negative input terminal (-), the differential amplifier 200 controls the potentials of both ends of the resistor 202 to be equal to the voltage V output from the BGR circuit. BGR The current flowing through the resistor 202 is a constant current and is used as a reference current Iref.

[0144] The drain of transistor 201 is connected to the drain of transistor 210a which is a current copy source of a current mirror circuit in which transistor 210a which is a P-channel MOS transistor is the copy source and transistors 210b and 210c which are P-channel MOS transistors are the copy destinations. Reference current Iref is copied by the current mirror circuit. The drain of transistor 210b which is the copy destination of the current mirror circuit is connected to the drain of transistor 215a which is an N-channel MOS transistor.

[0145] A current mirror circuit is constructed in which the transistor 215a is a copy source, and the transistors 215b' and 215c' and the transistors 215b and 215c which are N-channel MOS transistors are copy destinations.

[0146] Here, the current copied from the reference current Iref by transistors 215b and 215c will be used to generate Fig.18 On the other hand, the current copied from the reference current Iref by transistors 215b' and 215c' will be used to generate the first reference signal (RAMP(A)) in the circuit shown on the upper side. Fig.18 The lower side shows the current used in the circuit of the second reference signal (RAMP(B)).

[0147] First, the instructions are used to generate Fig.18 The current copied from the reference current Iref by the transistor 215b is supplied to a current mirror circuit formed by transistors 211a and 211b which are P-channel MOS transistors included in the RAMP generation unit on the upper side.

[0148] Furthermore, the transistor 215 b includes a predetermined number of N-channel MOS transistors connected in parallel, and the current value of the replica current can be controlled according to the number of transistors to be turned on among the predetermined number of transistors.

[0149] Here, for example, the transistor 211b included in the RAMP generating unit in the configuration related to the first reference signal (RAMP(A)) includes a number of P-channel MOS transistors connected in parallel corresponding to the color scale compared by the reference signal (RAMP(A)). According to control from the outside, for example, the overall control unit 7, the number of transistors to be turned on among the transistors included in the transistor 211b is sequentially reduced or increased according to the clock signal, thereby generating a current that changes in a step-like manner over time. As described later, for example, the current is converted into a voltage through the resistor 218 and is output via the transistor 217 connected via a source follower, which is a P-channel MOS transistor, thereby generating a reference signal whose voltage changes in a step-like manner over time.

[0150] On the other hand, the drain of the transistor 210c is connected to the drain of the transistor 216a which is an N-channel MOS transistor. A current mirror circuit is constructed in which the transistor 216a is a copy source, and the transistors 216b and 216c which are N-channel MOS transistors are copy destinations.

[0151] The drain of transistor 216b is connected to the drain of transistor 212a which is a P-channel MOS transistor. A current mirror circuit is constructed in which transistor 212a is a copy source and transistors 212b and 212c which are P-channel MOS transistors are copy destinations. The offset generation unit in the configuration related to the first reference signal (RAMP(A)) is constructed to include a current mirror circuit formed by these transistors 212a and transistors 212b and 212c.

[0152] The drain of transistor 215c is connected to the drain of transistor 213a which is a P-channel MOS transistor. A current mirror circuit is constructed in which transistor 213a is a copy source and transistor 213b which is a P-channel MOS transistor is a copy destination. The drain of transistor 213b is connected to one end of resistor 218 which is a terminal resistor. The other end of resistor 218 is connected to the ground voltage.

[0153] The output of the RAMP generation unit in the configuration related to the first reference signal (RAMP (A)), that is, the drain of the transistor 211b is connected to the drains of the transistors 212b and 212c, which are included in the offset generation unit in the configuration related to the first reference signal (RAMP (A)) and are the copy destinations of the current mirror circuit. As a result, the offset can be applied to the output of the RAMP generation unit by the current in the configuration related to the first reference signal (RAMP (A)).

[0154] Here, for example, the transistors 212b and 212c include a predetermined number of P-channel MOS transistors connected in parallel, and the current value of the replica current can be controlled according to the number of transistors to be turned on among the predetermined number of transistors. By controlling the number of transistors to be turned on among the predetermined number of transistors included in the transistors 212b and 212c, the offset amount and the presence or absence of the offset can be controlled.

[0155] The drain of the transistor 211b is further connected to a connection point where the drain of the transistor 213b is connected to the resistor 218. This connection point is also connected to the gate of the transistor 217 which is a P-channel MOS transistor. That is, the current flowing through the resistor 218 is converted into a voltage by the resistor 218, and the converted voltage is input to the gate of the transistor 217.

[0156] On the other hand, the drain of transistor 216c is connected to the drain of transistor 214a which is a P-channel MOS transistor. A current mirror circuit is constructed in which transistor 214a is a copy source and transistor 214b which is a P-channel MOS transistor is a copy destination. The source of transistor 217 is connected to the drain of transistor 214b in the current mirror circuit, and a source follower using the current mirror circuit as a current source is constructed. An output voltage is taken out from the source of transistor 217. This output voltage becomes a first reference signal (RAMP(A)).

[0157] In addition, for example, the transistor 214b includes a predetermined number of P-channel MOS transistors connected in parallel, and the current value of the replica current can be controlled according to the number of transistors to be turned on among the predetermined number of transistors. As a result, the gain of the source follower due to the transistor 217 can be adjusted.

[0158] In addition, the above-mentioned configuration for generating the first reference signal (RAMP(A)) is basically the same as the configuration of a general-purpose DAC for generating a reference signal.

[0159] Next, the instructions for generating Fig.18 The circuit for generating the second reference signal (RAMP(B)) shown on the lower side of FIG. Fig.18The circuit of the first reference signal (RAMP(A)) shown on the upper side is basically the same in structure.

[0160] That is, the current copied from the reference current Iref by transistor 215b' is provided to a current mirror circuit formed by transistors 211a' and 211b' which are P-channel MOS transistors included in a RAMP generation unit in a configuration related to the second reference signal (RAMP(B)).

[0161] Furthermore, the transistor 215 b ′ includes a predetermined number of N-channel MOS transistors connected in parallel, and the current value of the replica current can be controlled according to the number of transistors to be turned on among the predetermined number of transistors.

[0162] Similar to the above-mentioned transistor 211b, for example, the transistor 211b' included in the RAMP generation unit in the configuration related to the second reference signal (RAMP(B)) includes a number of P-channel MOS transistors connected in parallel corresponding to the color scale compared by the reference signal (RAMP(A)). According to the control, the number of transistors to be turned on among the transistors included in the transistor 211b is sequentially reduced or increased according to the clock signal, thereby generating a current that changes in a step-like manner over time. As described later, for example, by converting the current into a voltage in the resistor 218' and outputting it via the transistor 217' connected via a source follower which is a P-channel MOS transistor, a second reference signal (RAMP(B)) whose voltage changes in a step-like manner over time can be generated.

[0163] On the other hand, the drain of the transistor 210c' is connected to the drain of the transistor 216a' which is an N-channel MOS transistor. A current mirror circuit is constructed in which the transistor 216a' is a copy source, and the transistors 216b' and 216c' which are N-channel MOS transistors are copy destinations.

[0164] The drain of the transistor 216b' is connected to the drain of the transistor 212a' which is a P-channel MOS transistor. A current mirror circuit is constructed in which the transistor 212a' is a copy source, and the transistors 212b' and 212c' which are P-channel MOS transistors are copy destinations.

[0165] The drain of transistor 215c' is connected to the drain of transistor 213a' which is a P-channel MOS transistor. A current mirror circuit is constructed in which transistor 213a' is a copy source and transistor 213b' which is a P-channel MOS transistor is a copy destination. The drain of transistor 213b' is connected to one end of resistor 218 which is a terminal resistor. The other end of resistor 218 is connected to the ground voltage.

[0166] The output of the RAMP generation unit in the configuration related to the second reference signal (RAMP (B)), that is, the drain of the transistor 211b is connected to the drains of the transistors 212b' and 212c' which are the copy destinations of the current mirror circuit and the current mirror circuit included in the offset generation unit in the configuration related to the second reference signal (RAMP (B)). As a result, the offset can be applied to the output of the RAMP generation unit by the current in the configuration related to the second reference signal (RAMP (B)).

[0167] Here, for example, the transistors 212b' and 212c' include a predetermined number of P-channel MOS transistors connected in parallel, and the current value of the replica current can be controlled according to the number of transistors to be turned on among the predetermined number of transistors. By controlling the number of transistors to be turned on among the predetermined number of transistors included in the transistors 212b' and 212c', the offset amount and the presence or absence of the offset can be controlled.

[0168] The drain of transistor 211b' is further connected to a connection point where the drain of transistor 213b' is connected to resistor 218'. This connection point is also connected to the gate of transistor 217' which is a P-channel MOS transistor. That is, the current flowing through resistor 218' is converted into a voltage by resistor 218', and the converted voltage is input to the gate of transistor 217'.

[0169] On the other hand, the drain of transistor 216c' is connected to the drain of transistor 214a' which is a P-channel MOS transistor. A current mirror circuit is constructed in which transistor 214a' is a copy source and transistor 214b' which is a P-channel MOS transistor is a copy destination. The source of transistor 217' is connected to the drain of transistor 214b' in the current mirror circuit, and a source follower using the current mirror circuit as a current source is constructed. An output voltage is taken out from the source of transistor 217'. This output voltage becomes a second reference signal (RAMP(B)).

[0170] In addition, for example, transistor 214b' includes a predetermined number of P-channel MOS transistors connected in parallel, and the current value of the replica current can be controlled according to the number of transistors to be turned on among the predetermined number of transistors. As a result, the gain of the source follower formed by transistor 217' can be adjusted.

[0171] Fig.18 The first example shown has a high degree of freedom in control because it has a configuration connected in parallel after the reference current generating unit.

[0172] Fig.195 is a circuit diagram showing a second example of a circuit capable of generating and outputting first and second reference signals to which the second embodiment is applicable. DAC 5c(b) in the second example is an example in which a reference current generating unit and a RAMP generating unit are shared compared to DAC 5c(a) in the first example described above. Fig.19 The reference current generating unit and the RAMP generating unit are constructed in the same manner as described above. Fig.18 The reference current generating unit and the RAMP generating unit have the same structure, so their description will be omitted here.

[0173] In the current mirror circuit formed by transistors 210a and 210b that copies the reference current Iref generated by the reference current generating unit, the drain of transistor 210b is connected to the drain of transistor 215a which is an N-channel MOS. A current mirror circuit is constructed in which transistor 215a is a copy source, and transistors 215b' and 215c' and transistors 215b and 215c which are N-channel MOS transistors are copy destinations.

[0174] The drain of transistor 210c, which is a P-channel MOS transistor, constituting a current mirror circuit whose copy source is transistor 210a in the reference current generating unit is connected to the drain of transistor 216a, which is an N-channel MOS transistor. A current mirror circuit is constructed in which transistor 216a is the copy source and transistors 216b and 216c, which are N-channel MOS transistors, are the copy destinations.

[0175] The drain of the transistor 216b is connected to the drain of the transistor 212a which is a P-channel MOS transistor. A current mirror circuit is constructed in which the transistor 212a is a copy source, and the transistors 212b and 212c which are P-channel MOS transistors are copy destinations.

[0176] The drain of transistor 215c is connected to the drain of transistor 213a which is a P-channel MOS transistor. A current mirror circuit is constructed in which transistor 213a is a copy source and transistor 213b which is a P-channel MOS transistor is a copy destination. The drain of transistor 213b is connected to one end of resistor 218 which is a terminal resistor. The other end of resistor 218 is connected to the ground voltage.

[0177] The output of the RAMP generation unit, that is, the drain of the transistor 211b is connected to the drains of the transistors 212b and 212c as the copy destination of the current mirror circuit. In addition, the drain of the transistor 211b is connected to the drains of the transistors 230a and 230a' which are N-channel MOS transistors.

[0178] A current mirror circuit is constructed in which transistor 230a is a copy source and transistor 230b, which is an N-channel MOS transistor, is a copy destination. A first reference signal (RAMP(A)) is generated based on the output of the RAMP generation unit copied by the current mirror circuit formed by transistors 230a' and 230b'.

[0179] Similarly, a current mirror circuit is constructed in which transistor 230a' is a copy source and transistor 230b', which is an N-channel MOS transistor, is a copy destination. Based on the output of the RAMP generation unit copied by the current mirror circuit formed by transistors 230a' and 230b', a second reference signal (RAMP(B)) is generated.

[0180] The drain of the transistor 230b is connected to the drain of the transistor 231a which is a P-channel MOS transistor. A current mirror circuit is constructed in which the transistor 231a is a copy source and the transistor 231b which is a P-channel MOS transistor is a copy destination.

[0181] Here, for example, the transistors 212 b and 212 c include a predetermined number of P-channel MOS transistors connected in parallel, and the current value of the replica current can be controlled according to the number of transistors to be turned on among the predetermined number of transistors.

[0182] The drain of transistor 231b is connected to a connection point where the drain of transistor 213b is connected to one end of resistor 218 as a terminal resistor. The other end of resistor 218 is connected to the ground potential. The connection point is also connected to the gate of transistor 217 which is a P-channel MOS transistor. That is, the current flowing through resistor 218 is converted into a voltage, and the converted voltage is provided to the gate of transistor 217.

[0183] On the other hand, the drain of transistor 216c is connected to the drain of transistor 214a which is a P-channel MOS transistor. A current mirror circuit is constructed in which transistor 214a is a copy source and transistors 214b and 214b' which are P-channel MOS transistors are copy destinations. The source of transistor 217 is connected to the drain of transistor 214b in the current mirror circuit, and a source follower using the current mirror circuit as a current source is constructed. For example, transistor 214b includes a predetermined number of P-channel MOS transistors connected in parallel, and the current value of the copy current can be controlled according to the number of transistors to be turned on among the predetermined number of transistors. As a result, the gain of the source follower through transistor 217 can be adjusted. The output voltage is taken out from the source of transistor 217. The output voltage becomes the first reference signal (RAMP(A)).

[0184] On the other hand, the drain of the transistor 230b' is connected to the drain of the transistor 231a' which is a P-channel MOS transistor. A current mirror circuit is constructed in which the transistor 231a' is a copy source and the transistor 231b' which is a P-channel MOS transistor is a copy destination.

[0185] The drain of transistor 231b' is connected to a connection point where the drain of transistor 213b' is connected to one end of resistor 218' as a terminal resistor. The other end of resistor 218' is connected to the ground potential. The connection point is also connected to the gate of transistor 217' which is a P-channel MOS transistor. That is, the current flowing through resistor 218' is converted into a voltage, and the converted voltage is provided to the gate of transistor 217'.

[0186] The transistor 217' is connected to the drain of the transistor 214b' as the copy destination in the current mirror circuit whose source uses the transistor 214a as the copy source, and constitutes a source follower using the current mirror circuit formed by the transistors 214a and 214b' as a current source. For example, the transistor 214b' includes a predetermined number of P-channel MOS transistors connected in parallel, and the current value of the copy current can be controlled according to the number of transistors to be turned on among the predetermined number of transistors. As a result, the gain of the source follower through the transistor 217' can be adjusted. The output voltage is taken out from the source of the transistor 217'. The output voltage becomes the second reference signal (RAMP(B)).

[0187] In the above configuration, for example, transistors 231b and 231b' provided with the output of the RAMP generation unit include a predetermined number of P-channel MOS transistors connected in parallel, and the current value of the replica current can be controlled according to the number of transistors to be turned on among the predetermined number of transistors.

[0188] The number of transistors to be turned on among the predetermined number of transistors included in the transistor 231b and the number of transistors to be turned on among the predetermined number of transistors included in the transistor 231b' can be independently controlled. As a result, the offset amount and the presence or absence of the offset of the first reference signal (RAMP(A)) and the second reference signal (RAMP(B)) can be independently controlled.

[0189] According to Fig.18 Compared with the configuration of the first example shown, Fig.19 The second example shown may be constructed with a smaller number of components.

[0190] Fig. 205 is a circuit diagram showing a third example of a circuit capable of generating and outputting first and second reference signals to which the second embodiment is applicable. The DAC 5c(c) in the third example divides the output of the RAMP generating unit into two branches in a conversion unit that converts the output into a voltage, and applies an offset voltage to each voltage converted from the output of the RAMP generating unit, thereby outputting a first reference signal (RAMP(A)) and a second reference signal (RAMP(B)).

[0191] In addition, Fig. 20 The reference current generating unit and the RAMP generating unit are constructed in the same manner as described above. Fig.18 The reference current generating unit and the RAMP generating unit have the same structure, so their description will be omitted here.

[0192] In the current mirror circuit formed by transistors 210a and 210b that copies the reference current Iref generated by the reference current generating unit, the drain of transistor 210b is connected to the drain of transistor 215a which is an N-channel MOS transistor. A current mirror circuit is constructed in which transistor 215a is a copy source and transistors 215b and 215c which are N-channel MOS transistors are copy destinations.

[0193] The drain of transistor 210c, which is a P-channel MOS transistor, constituting a current mirror circuit whose copy source is transistor 210a in the reference current generating unit is connected to the drain of transistor 216a, which is an N-channel MOS transistor. A current mirror circuit is constructed in which transistor 216a is the copy source and transistor 216b, which is an N-channel MOS transistor, is the copy destination.

[0194] The drain of transistor 216b is connected to the drain of transistor 214a which is a P-channel MOS transistor. A current mirror circuit is constructed in which transistor 214a is a copy source, and transistors 214b and 214b' which are P-channel MOS transistors are copy destinations. The drain of transistor 214b is connected to the source of transistor 217. In addition, the drain of transistor 214b' is connected to the source of transistor 217'.

[0195] In addition, for example, the transistors 214 b and 214 b ′ include a predetermined number of P-channel MOS transistors connected in parallel, and the current value of the replica current can be controlled according to the number of transistors to be turned on among the predetermined number of transistors.

[0196] The drain of transistor 215c is connected to the drain of transistor 212a which is a P-channel MOS transistor. A current mirror circuit is constructed in which transistor 212a is a copy source and transistors 212b, 212c and 212c' which are P-channel MOS transistors are copy destinations. The drain of transistor 212b is connected to one end of resistor 218 which is a terminal resistor. The other end of resistor 218 is connected to a ground voltage.

[0197] The output of the RAMP generation unit, that is, the drain of the transistor 211b is connected to the connection point where the transistor 212b and the resistor 218 are connected. In addition, one end of the capacitor 245 related to the first reference signal (RAMP(A)) and the drain of the transistor 244 which is a P-channel MOS transistor are connected to the connection point. The source of the transistor 244 is connected to the other end of the capacitor 245. In addition, one end of the capacitor 245' related to the second reference signal (RAMP(B)) and the drain of the transistor 244' which is a P-channel MOS transistor are connected to the connection point. The source of the transistor 244' is connected to the other end of the capacitor 245'.

[0198] The drain of the transistor 212c is connected to one end of the resistor 241, and the other end of the resistor 241 is connected to the ground voltage. One end of the capacitor 246 is connected to the connection point where the drain of the transistor 212c and the resistor 241 are connected. The other end of the capacitor 246 is connected to the connection point between the other end of the capacitor 245 and the source of the transistor 244. In addition, the gate of the transistor 217, which is a P-channel MOS transistor, is connected to the connection point.

[0199] Here, the capacitors 245 and 246 constitute an adder that adds (or subtracts) the voltages supplied to one end of each of the capacitors 245 and 246, and takes out the added voltage from the connection point to which the other end thereof is connected. A voltage obtained by adding a voltage obtained by converting the output of the RAMP generating unit using the resistor 218 and a voltage taken out from the connection point connecting the transistor 212c and the resistor 241 in the adder is input to the gate of the transistor 217. In addition, the capacitor 245 is updated by controlling the transistor 244 whose drain is connected to one end of the capacitor 245 and whose source is connected to the other end thereof in an on state.

[0200] The source of transistor 217 is connected to the drain of transistor 214b in a current mirror circuit in which transistor 214a is a copy source and transistor 214b is a copy destination. Transistor 217 constitutes a source follower using this current mirror circuit as a current source. For example, transistor 214b includes a predetermined number of P-channel MOS transistors connected in parallel, and the current value of the copy current can be controlled according to the number of transistors to be turned on among the predetermined number of transistors. As a result, the gain of the source follower through transistor 217 can be adjusted.

[0201] An output voltage according to a voltage obtained by adding a voltage obtained by converting the output of the RAMP generating unit using the resistor 218 and a voltage taken from a connection point connecting the transistor 212c and the resistor 241 is taken out from the gate of the transistor 217. The voltage taken out from the transistor 217 becomes a first reference signal (RAMP(A)).

[0202] The drain of transistor 212c' is connected to one end of resistor 241', and the other end of resistor 241' is connected to the ground voltage. One end of capacitor 246' is connected to the connection point where the drain of transistor 212c' and resistor 241' are connected. The other end of capacitor 246' is connected to the connection point between the other end of capacitor 245' and the source of transistor 244'. In addition, the gate of transistor 217', which is a P-channel MOS transistor, is connected to the connection point.

[0203] Similar to the above, the capacitors 245' and 246' constitute an adder that adds (or subtracts) the voltages supplied to one end of each of the capacitors 245' and 246', and takes out the added voltage from the connection point to which the other end thereof is connected. The voltage obtained by adding the voltage obtained by converting the output of the RAMP generation unit using the resistor 218' and the voltage taken out from the connection point to which the transistor 212c' and the resistor 241' are connected in the adder is input to the gate of the transistor 217'. In addition, the capacitor 245' is updated by controlling the transistor 244' whose drain is connected to one end of the capacitor 245' and whose source is connected to the other end thereof in the on state.

[0204] The source of transistor 217' is connected to the drain of transistor 214b' in a current mirror circuit (in which transistor 214a is a copy source and transistor 214b' is a copy destination). Transistor 217' constitutes a source follower using the current mirror circuit as a current source. For example, transistor 214b' includes a predetermined number of P-channel MOS transistors connected in parallel, and the current value of the copy current can be controlled according to the number of transistors to be turned on among the predetermined number of transistors. As a result, the gain of the source follower through transistor 217' can be adjusted.

[0205] An output voltage according to a voltage obtained by adding a voltage obtained by converting the output of the RAMP generating unit by using the resistor 218' to a voltage taken out from a connection point connecting the transistor 212c' and the resistor 241' is taken out from the source of the transistor 217'. The voltage taken out from the transistor 217' becomes a second reference signal (RAMP(B)).

[0206] In the above-described configuration, for example, the transistors 212c and 212c' provided with the output of the RAMP generation unit include a predetermined number of P-channel MOS transistors connected in parallel, and the current value of the repetitive current can be controlled according to the number of transistors to be turned on among the predetermined number of transistors. As a result, the voltage taken out from the connection point connecting the transistor 212c and the resistor 241 and the voltage taken out from the connection point connecting the transistor 212c' and the resistor 241' are also controlled.

[0207] The number of transistors to be turned on among the predetermined number of transistors included in the transistor 212c and the number of transistors to be turned on among the predetermined number of transistors included in the transistor 212c' can be independently controlled. As a result, the offset amount and the presence or absence of the offset of the first reference signal (RAMP(A)) and the second reference signal (RAMP(B)) can be independently controlled.

[0208] [Third embodiment]

[0209] Next, a third embodiment of the present disclosure will be described. In the third embodiment, a configuration example of an electronic device to which the techniques according to the first embodiment, its modification, and the second embodiment described above are applied will be described. Fig.21 is a block diagram showing the configuration of an example of an electronic device according to the third embodiment.

[0210] exist Fig.21 In the embodiment, the electronic device 300 includes an optical system 301, a camera 1000, a signal processing circuit 310, a storage medium 311, and a monitor 312. Fig. 22 In the present invention, a digital camera, a digital video camera, a mobile phone with an imaging function, a smart phone, etc. can be used as the electronic device 300.

[0211] The optical system 301 forms an image of image light (incident light) from a subject on an imaging surface of the image pickup device 1000. As a result, signal charge is accumulated in the image pickup device 1000 for a period of time. The signal processing circuit 310 performs various signal processing on the signal output from the image pickup device 1000. The video signal processed by the signal processing can be stored in a storage medium 311 such as a memory. In addition, the video signal can be output to a monitor 312.

[0212] [Fourth embodiment]

[0213] Next, an application example of the image pickup device 1000 according to the first embodiment, its modified example, and the second embodiment of the present disclosure will be described as a fourth embodiment. Fig. 22 1 and 2 are diagrams showing a usage example of the imaging device 1000 according to the above-described first embodiment, its modified example, and the second embodiment.

[0214] As described below, the above-described imaging device 1000 may be used in various situations to sense light such as visible light, infrared light, ultraviolet light, and X-rays.

[0215] · Devices for viewing captured images, such as digital cameras and portable devices with camera functions.

[0216] Equipment used for traffic, such as on-board sensors that photograph the front, rear, periphery, and interior of a car, surveillance cameras that monitor moving vehicles and roads, and distance-measuring sensors that measure the distance between vehicles, for safe driving purposes such as automatic stopping and driver status recognition.

[0217] Devices for home appliances, such as a TV, refrigerator, or air conditioner, etc., in order to capture a user's gesture and perform operations on the device according to the gesture.

[0218] Equipment used in medical care, such as endoscopes and equipment for angiography by receiving infrared light.

[0219] Equipment used for security, such as surveillance cameras for crime prevention and cameras for personal identity verification.

[0220] Equipment used for beauty treatments, such as skin measurement equipment that photographs the skin and microscopes that photograph the scalp.

[0221] Equipment for sports, such as action cameras and wearable cameras for sports use.

[0222] Equipment used in agriculture, such as cameras that monitor the status of fields and crops.

[0223] [Another application example of the technology disclosed herein]

[0224] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be applied to an endoscopic surgery system.

[0225] (Application example of in vivo information acquisition system)

[0226] Fig.23 : is a block diagram showing an example of a schematic configuration of a patient in vivo information acquisition system using a capsule endoscope to which the technology of the present disclosure (the present technology) can be applied.

[0227] The in-vivo information acquisition system 10001 is composed of a capsule endoscope 10100 and an external control device 10200 .

[0228] The capsule endoscope 10100 is swallowed by the patient during the examination. The capsule endoscope 10100 has an imaging function and a wireless communication function, and before being naturally discharged from the patient's body, it sequentially captures images of the inside of organs such as the stomach and intestines (hereinafter referred to as in-vivo images) at predetermined intervals while moving inside the organs by peristaltic motion, and sequentially wirelessly transmits information about the in-vivo images to the external control device 10200 outside the body.

[0229] The external control device 10200 comprehensively controls the operation of the in-vivo information acquisition system 10001. In addition, the external control device 10200 receives information about in-vivo images sent from the capsule endoscope 10100, and generates image data for displaying the in-vivo images on a display device (not shown) based on the received information about the in-vivo images.

[0230] In this manner, in the in-vivo information acquiring system 10001, in-vivo images of the patient's body can be obtained at any time from the time the capsule endoscope 10100 is swallowed to the time it is excreted.

[0231] The structure and function of the capsule endoscope 10100 and the external control device 10200 will be described in more detail.

[0232] The capsule endoscope 10100 has a capsule-shaped shell 10101, and the shell 10101 contains a light source unit 10111, a camera unit 10112, an image processing unit 10113, a wireless communication unit 10114, a power supply unit 10115, a power supply unit 10116 and a control unit 10117.

[0233] For example, the light source unit 10111 is composed of a light source such as a light emitting diode (LED), and irradiates light to the imaging field of the imaging unit 10112 .

[0234] The imaging unit 10112 is composed of an imaging element and an optical system including a plurality of lenses disposed in front of the imaging element. Reflected light (hereinafter referred to as observation light) of light applied to body tissue as an observation object is collected by the optical system and incident on the imaging element. In the imaging unit 10112, the observation light incident on the imaging element is photoelectrically converted, and an image signal corresponding to the observation light is generated. The image signal generated by the imaging unit 10112 is provided to the image processing unit 10113.

[0235] The image processing unit 10113 is composed of a processor such as a central processing unit (CPU) or a graphics processing unit (GPU), and performs various signal processing on the image signal generated by the imaging unit 10112. The image processing unit 10113 supplies the image signal subjected to the signal processing to the wireless communication unit 10114 as RAW data (raw data).

[0236] The wireless communication unit 10114 performs predetermined processing such as modulation processing on the image signal that has undergone the signal processing performed by the image processing unit 10113, and transmits the resulting image signal via the antenna 10114A to the external control device 10200. In addition, the wireless communication unit 10114 receives a control signal related to the drive control of the capsule endoscope 10100 from the external control device 10200 via the antenna 10114A. The wireless communication unit 10114 provides the control signal received from the external control device 10200 to the control unit 10117.

[0237] For example, the power supply unit 10115 is composed of a power receiving antenna coil, a power regeneration circuit that regenerates power from the current generated in the antenna coil, a booster circuit, etc. The power supply unit 10115 generates power using the so-called non-contact charging principle.

[0238] The power supply unit 10116 is composed of a secondary battery and stores the power generated by the power supply unit 10115. Fig. 27 In order to avoid complicating the drawings, the arrow indicating the destination of power supply from the power supply unit 10116 is omitted, but the power stored in the power supply unit 10116 can be provided to the light source unit 10111, the camera unit 10112, the image processing unit 10113, the wireless communication unit 10114 and the control unit 10117, and used to drive them.

[0239] The control unit 10117 is composed of a processor such as a CPU, and appropriately controls the driving of the light source unit 10111, the camera unit 10112, the image processing unit 10113, the wireless communication unit 10114 and the power supply unit 10115 according to the control signal sent from the external control device 10200.

[0240] The external control device 10200 is composed of a processor such as a CPU or a GPU, or a microcomputer, or a control board on which a processor and a storage element such as a memory are mounted. The external control device 10200 sends a control signal to the control unit 10117 of the capsule endoscope 10100 via the antenna 10200A to control the action of the capsule endoscope 10100. In the capsule endoscope 10100, for example, the light irradiation condition for the observation object in the light source unit 10111 can be changed according to the control signal from the external control device 10200. In addition, the imaging condition (for example, the frame rate, the exposure value, etc. in the imaging unit 10112) can be changed according to the control signal from the external control device 10200. In addition, the processing content in the image processing unit 10113 or the condition for sending the image signal by the wireless communication unit 10114 (for example, the sending interval, the number of images sent, etc.) can also be changed according to the control signal of the external control device 10200.

[0241] In addition, the external control device 10200 performs various image processing on the image signal sent from the capsule endoscope 10100, and generates image data for displaying the captured in-vivo image on the display device. As image processing, for example, various signal processing such as development processing (demosaic processing), high image quality processing (band enhancement processing, super-resolution processing, noise reduction processing, camera shake correction processing), and magnification processing (electronic zoom processing) can be performed independently or in combination. The external control device 10200 controls the drive of the display device to display the captured in-vivo image based on the generated image data. Alternatively, the external controller device 10200 can cause the generated image data to be recorded in a recording device (not shown), or can cause the image data to be printed and output by a printing device (not shown).

[0242] An example of an in vivo information acquisition system to which the technology of the present disclosure can be applied has been described above. For example, the technology of the present disclosure can be applied to the imaging unit 10112 in the above-mentioned configuration. By applying the technology of the present disclosure to the imaging unit 10112, it is possible to suppress transient current when the imaging unit 10112 captures a planar subject, which can reduce the size of the capsule endoscope 10100.

[0243] (Application example of endoscopic surgery system)

[0244] The technology according to the present disclosure may be further applicable to an endoscopic surgery system. Fig.24 : is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0245] Fig.24The figure shows a state where an operator (doctor) 11131 is using an endoscopic surgery system 11000 to perform surgery on a patient 11132 on a bed 11133. As shown in the figure, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy treatment instrument 11112, a support arm device 11120 supporting the endoscope 11100, and a cart 11200 equipped with various devices for endoscopic surgery.

[0246] The endoscope 11100 includes a lens barrel 11101 inserted into a body cavity of a patient 11132 at a predetermined length from a distal end, and a camera 11102 connected to a base end of the lens barrel 11101. Although the endoscope 11100 constructed as a so-called rigid scope having a rigid lens barrel 11101 is shown in the illustrated example, the endoscope 11100 may also be constructed as a so-called flexible scope having a flexible lens barrel.

[0247] An opening for mounting an objective lens is provided at the end of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the end of the lens barrel 11101 through a light guide extending into the interior of the lens barrel, and irradiated toward an observation target in the body cavity of the patient 11132 via the objective lens. The endoscope 11100 may be a direct-view endoscope, or may be a fluoroscopic endoscope or a side-view endoscope.

[0248] An optical system and an imaging element are provided inside the camera head 11102, and reflected light (observation light) from an observation object is focused on the imaging element through the optical system. The observation light is photoelectrically converted by the imaging element, and an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image, is generated. The image signal is sent to the camera control unit (CCU) 11201 as RAW data.

[0249] The CCU 11201 is composed of a CPU, a GPU, and the like, and comprehensively controls the operations of the endoscope 11100 and the display device 11202. In addition, for example, the CCU 11201 receives an image signal from the camera 11102, and performs various image processing such as development processing (demosaic processing) on ​​the image signal to display an image based on the image signal.

[0250] The display device 11202 displays an image signal based on image processing performed by the CCU 11201 under the control of the CCU 11201 .

[0251] The light source device 11203 includes a light source such as a light emitting diode (LED), and provides the endoscope 11100 with irradiation light for photographing a surgical site or the like.

[0252] The input device 11204 is an input interface for the endoscopic surgery system 11000. The user can input various types of information or instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0253] The treatment instrument control device 11205 controls the drive of the energy treatment instrument 11112 for cauterization, incision, sealing of blood vessels, etc. of tissues. The pneumoperitoneum device 11206 injects gas into the body cavity of the patient 11132 via the pneumoperitoneum tube 11111 to expand the body cavity of the patient 11132 to ensure the field of view of the endoscope 11100 and the working space of the operator. The recorder 11207 is a device capable of recording various types of information related to the operation. The printer 11208 is a device capable of printing various types of information related to the operation in various forms such as text, images, graphics, etc.

[0254] In addition, the light source device 11203 that provides the endoscope 11100 with irradiation light for photographing the surgical site can be composed of, for example, an LED, a laser light source, or a white light source composed of them. In the case where the white light source is composed of a combination of red, green, and blue (RGB) laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, and thus the light source device 11203 can adjust the white balance of the captured image. In addition, in this case, by irradiating the laser from each RGB laser light source onto the observed object in a time-division manner and controlling the drive of the imaging element of the camera 11102 in synchronization with the irradiation timing, it is also possible to photograph images corresponding to each RGB in a time-division manner. According to this method, a color image can also be obtained without providing a color filter in the imaging element.

[0255] In addition, the drive of the light source device 11203 can be controlled to change the intensity of the output light at a predetermined time interval. By controlling the drive of the imaging element of the camera 11102 in synchronization with the timing of the change in light intensity, images are acquired in a time-division manner, and the images are synthesized, so that a high dynamic range image without so-called blackout and overexposure can be generated.

[0256] In addition, the light source device 11203 may be configured to provide light of a predetermined wavelength band corresponding to special light observation. In special light observation, for example, by irradiating light of a narrower band than the irradiation light (i.e., white light) during ordinary observation using the wavelength dependence of light absorption in body tissue, a so-called narrowband light observation (narrowband imaging) is performed in which predetermined tissues such as blood vessels of the surface layer of the mucosa are photographed with high contrast. Alternatively, in special light observation, fluorescence observation in which an image is obtained by using fluorescence generated by irradiating excitation light may be performed. In fluorescence observation, for example, excitation light may be irradiated to body tissue and fluorescence from the body tissue may be observed (autofluorescence observation), or a reagent such as indocyanine green (ICG) may be locally injected into body tissue and the body tissue may be irradiated with excitation light corresponding to the fluorescence wavelength of the reagent to obtain a fluorescence image. The light source device 11203 may be configured to provide narrowband light and / or excitation light corresponding to such special light observation.

[0257] Fig.25 It is shown Fig.24 A block diagram showing an example of the functional configuration of the camera 11102 and the CCU 11201 shown.

[0258] The camera 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera 11102 is connected to the CCU 11201 via a transmission cable 11400 so as to be able to communicate with each other.

[0259] The lens unit 11401 is an optical system provided at a portion connected to the lens barrel 11101. Observation light introduced from the end of the lens barrel 11101 is guided to the camera 11102 and incident on the lens unit 11401. The lens unit 11401 is configured by combining a plurality of lenses including a zoom lens and a focus lens.

[0260] The imaging unit 11402 includes an imaging element. The number of imaging elements constituting the imaging unit 11402 may be one (so-called single-board type) or multiple (so-called multi-board type). In the case where the imaging unit 11402 is constructed as a multi-board type, for example, image signals corresponding to RGB are generated by each imaging element, and the image signals can be combined to obtain a color image. Alternatively, the imaging unit 11402 may be constructed to have a pair of imaging elements for respectively acquiring image signals for the right eye and the left eye corresponding to a three-dimensional (3D) display. By performing a 3D display, the operator 11131 can more accurately grasp the depth of biological tissue in the surgical site. In addition, in the case where the imaging unit 11402 is constructed as a multi-board type, a plurality of lens units 11401 corresponding to each imaging element may be provided.

[0261] In addition, the camera unit 11402 may not necessarily be disposed in the camera head 11102. For example, the camera unit 11402 may be disposed directly behind the objective lens inside the lens barrel 11101.

[0262] The driving unit 11403 is constituted by an actuator, and moves the zoom lens and the focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera control unit 11405. Therefore, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0263] The communication unit 11404 is configured by a communication device for transmitting and receiving various information to and from the CCU 11201. The communication unit 11404 transmits an image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0264] In addition, the communication unit 11404 receives a control signal for controlling the driving of the camera 11102 from the CCU 11201, and provides the control signal to the camera control unit 11405. For example, the control signal includes information related to imaging conditions, such as information specifying a frame rate of an image to be captured, information specifying an exposure value at the time of imaging, and / or information specifying a magnification and a focus of an image to be captured.

[0265] In addition, imaging conditions such as frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set based on the acquired image signal by the control unit 11413 of the CCU 11201. In the latter case, a so-called automatic exposure (AE) function, an automatic focus (AF) function, and an automatic white balance (AWB) function are incorporated in the endoscope 11100.

[0266] The camera control unit 11405 controls the driving of the camera 11102 based on the control signal received from the CCU 11201 via the communication unit 11404 .

[0267] The communication unit 11411 is constituted by a communication device for transmitting and receiving various information to and from the camera 11102. The communication unit 11411 receives an image signal transmitted from the camera 11102 via the transmission cable 11400.

[0268] Furthermore, the communication unit 11411 transmits a control signal for controlling the driving of the camera 11102 to the camera 11102. The image signal and the control signal may be transmitted via electrical communication, optical communication, or the like.

[0269] The image processing unit 11412 performs various image processing on the image signal which is RAW data transmitted from the camera 11102 .

[0270] The control unit 11413 performs various controls related to imaging of a surgical site, etc. using the endoscope 11100 and display of an imaged image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102 .

[0271] In addition, the control unit 11413 causes the display device 11202 to display a captured image obtained by photographing a surgical site, etc., based on an image signal subjected to image processing by the image processing unit 11412. In this case, the control unit 11413 can recognize various objects within the captured image by using various image recognition techniques. For example, the control unit 11413 can detect the shape, color, etc. of the edge of an object contained in the captured image, thereby recognizing surgical instruments such as forceps, specific living body parts, bleeding, mist when using the energy treatment instrument 11112, etc. When the captured image is displayed on the display device 11202, the control unit 11413 can use the recognition result to superimpose and display various surgical support information on the image of the surgical site. By superimposing and displaying the surgical support information and presenting it to the operator 11131, the burden on the operator 11131 can be reduced, and the operator 11131 can reliably perform surgery.

[0272] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for communication of electrical signals, an optical fiber for optical communication, or a composite cable thereof.

[0273] Here, in Fig.25In the example, wired communication is performed using the transmission cable 11400, but communication between the camera 11102 and the CCU 11201 can also be performed wirelessly.

[0274] An example of an endoscopic surgical system to which the technology of the present disclosure can be applied has been described above. In the above configuration, for example, the technology of the present disclosure can be applied to the imaging unit 11402 of the endoscope 11100 or the camera 11102. By applying the technology of the present disclosure to the imaging unit 11402, it is possible to suppress transient current when the imaging unit 11402 captures a planar subject.

[0275] Furthermore, although the description is given here by taking an endoscopic surgery system as an example, the technology according to the present disclosure can be applied to a microscope surgery system, for example.

[0276] [Application examples for mobile objects]

[0277] The technology according to the present disclosure can also be applied to devices mounted on various mobile bodies such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, unmanned aerial vehicles, ships, and robots.

[0278] Fig.26 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a vehicle control system to which the technology according to the present disclosure can be applied.

[0279] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.26 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a main body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound and image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown as the functional configuration of the integrated control unit 12050.

[0280] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device for a drive force generating device such as an internal combustion engine or a drive motor for generating a drive force of the vehicle, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0281] The main system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the main system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a taillight, a brake light, a turn signal light, and a fog light. In this case, a radio wave transmitted from a portable device used instead of a key or a signal of various switches may be input to the main system control unit 12020. The main system control unit 12020 receives the input of the radio wave or the signal, and controls the door lock device, the power window device, the light, etc. of the vehicle.

[0282] The vehicle exterior information detection unit 12030 detects information on the exterior of the vehicle on which the vehicle control system 12000 is installed. For example, the camera unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the exterior of the vehicle and receive the captured image. Based on the received image, the vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing of pedestrians, cars, obstacles, signs, text on the road, and the like. For example, the vehicle exterior information detection unit 12030 performs image processing on the received image, and performs object detection processing and distance detection processing based on the result of the image processing.

[0283] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or can also output the electrical signal as ranging information. In addition, the light received by the imaging unit 12031 can be visible light or invisible light such as infrared rays.

[0284] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. For example, the driver state detection unit 12041 includes a camera that images the driver, and based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or concentration, or can determine whether the driver is dozing off.

[0285] The microcomputer 12051 can calculate the control target value of the driving force generation device, the steering mechanism or the braking device based on the information related to the inside and outside of the vehicle obtained by the vehicle outside information detection unit 12030 or the vehicle inside information detection unit 12040, and can output a control instruction to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to realize advanced driver assistance system (ADAS) functions including collision avoidance, collision mitigation, tracking driving based on the distance between vehicles, vehicle speed maintenance driving, vehicle collision warning, lane departure warning of the vehicle, etc.

[0286] In addition, the microcomputer 12051 can perform coordinated control based on the information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040 by controlling the driving force generating device, steering mechanism, braking device, etc., so as to achieve automatic driving in which the vehicle drives autonomously without relying on the driver's operation.

[0287] In addition, the microcomputer 12051 can output a control instruction to the main system control unit 12020 based on the information about the outside of the vehicle obtained by the vehicle outside information detection unit 12030. For example, the microcomputer 12051 can perform coordinated control by controlling the headlights according to the position of the front vehicle or the oncoming vehicle detected by the vehicle outside information detection unit 12030, so as to achieve the purpose of preventing glare, such as switching the high beam to the low beam.

[0288] The sound and image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or auditorily notifying the vehicle occupants or the outside of the vehicle of information. Fig.26 In the example of FIG. 1 , an audio speaker 12061, a display unit 12062, and a dashboard 12063 are illustrated as output devices. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0289] Fig. 27 1 is a diagram showing an example of the installation position of the camera unit 12031. Fig. 27 In the figure, vehicle 12100 has camera units 12101 , 12102 , 12103 , 12104 , and 12105 as camera unit 12031 .

[0290] For example, the camera units 12101, 12102, 12103, 12104, and 12105 are arranged at positions such as the front nose, rearview mirror, rear bumper, rear door, upper side of the windshield in the vehicle 12100, etc. The camera unit 12101 arranged in the front nose and the camera unit 12105 arranged on the upper side of the windshield in the vehicle mainly obtain images of the front side of the vehicle 12100. The camera units 12102 and 12103 arranged in the rearview mirror mainly obtain images of the side of the vehicle 12100. The camera unit 12104 arranged in the rear bumper or the rear door mainly obtains images of the rear side of the vehicle 12100. The front side images acquired by the camera units 12101 and 12105 are mainly used to detect the front vehicle, pedestrians, obstacles, traffic signals, traffic signs, lanes, etc.

[0291] also, Fig. 27 An example of the imaging ranges of the imaging units 12101 to 12104 is shown. The imaging range 12111 is the imaging range of the imaging unit 12101 provided in the front nose, the imaging ranges 12112 and 12113 are the imaging ranges of the imaging units 12102 and 12103 provided in the rearview mirrors, and the imaging range 12114 is the imaging range of the imaging unit 12104 provided in the rear bumper or the rear door. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from the upper side can be obtained.

[0292] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0293] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 can obtain the distance to each solid object within each camera range 12111 to 12114 and the change in distance over time (relative speed relative to the vehicle 12100), thereby being able to extract, as the leading vehicle, a solid object located on the driving route of the vehicle 12100, especially the closest solid object and traveling at a predetermined speed (for example, 0 km / h or more) in the same direction as the vehicle 12100. In addition, the microcomputer 12051 can pre-set the inter-vehicle distance to be ensured in front of the leading vehicle, and can perform automatic braking control (also including follow-up stop control), automatic acceleration control (also including follow-up start control), etc. In this way, coordinated control such as automatic driving in which the vehicle travels autonomously without relying on the operation of the driver can be performed.

[0294] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 can classify the three-dimensional object data about the three-dimensional object into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and extract the three-dimensional object data, and can use them to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be identified by the driver of the vehicle 12100 and obstacles that are difficult to identify. Then, the microcomputer 12051 can determine the collision risk indicating the risk of collision with each obstacle, and in the case where the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 can cause the audio speaker 12061 or the display unit 12062 to output a warning to the driver or cause the drive system control unit 12010 to perform forced deceleration and evasive steering, thereby providing driving support for collision avoidance.

[0295] At least one of the camera units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether the pedestrian exists in an image captured by the camera units 12101 to 12104. For example, the identification of pedestrians is performed by extracting feature points in the captured images of the camera units 12101 to 12104 as a process of an infrared camera and by performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether the person is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the image captured by the camera units 12101 to 12104 and identifies the pedestrian, the sound and image output unit 12052 controls the display unit 12062 so that the identified pedestrian is superimposed and displayed with a quadrilateral outline for emphasis. In addition, the sound and image output unit 12052 may control the display unit 12062 so that it displays an icon indicating a pedestrian at a desired location, etc.

[0296] An example of a vehicle control system to which the technology of the present disclosure is applicable has been described above. The technology of the present disclosure can be applied to the camera unit 12031 and the like in the above-mentioned configuration. By applying the technology of the present disclosure to the camera unit 12031, it is possible to suppress the instantaneous current when the camera unit 12031 captures a planar subject and the like.

[0297] In addition, the beneficial effects described in this specification are merely exemplary and not restrictive, and other beneficial effects may be obtained.

[0298] Furthermore, the present technology can adopt the following configurations. (1)

[0300] A camera device, comprising:

[0301] a plurality of pixels, each of the plurality of pixels including a light receiving element that generates charge by photoelectric conversion in response to received light,

[0302] a pixel circuit that reads out the charge from the light receiving element and outputs an analog signal according to the charge, and

[0303] a conversion circuit that converts the analog signal into a digital signal based on a comparison result obtained by comparing the analog signal with a reference signal whose voltage changes in a step-like manner at a constant slope over time;

[0304] a generating unit that generates, as reference signals, a first reference signal to be provided to a first pixel among the plurality of pixels and a second reference signal to be provided to a second pixel among the plurality of pixels that is different from the first pixel;

[0305] a first wiring connecting the generating unit and the first pixel; and

[0306] a second wiring connecting the generating unit and the second pixel,

[0307] in,

[0308] The first reference signal is supplied to the first pixel via the first wiring, and

[0309] The second reference signal is supplied to the second pixel via the second wiring. (2)

[0311] According to the imaging device described in (1) above,

[0312] The generating unit generates the second reference signal obtained by applying an offset to the first reference signal. (3)

[0314] According to the imaging device described in (2) above,

[0315] The generating unit generates the second reference signal obtained by applying the offset to the first reference signal, wherein the offset causes a reference voltage serving as a reference of the slope to be offset. (4)

[0317] According to the imaging device described in (2) above,

[0318] The generating unit generates the second reference signal obtained by applying the offset to the first reference signal, wherein the offset causes the slope to be offset in a time direction. (5)

[0320] The imaging device according to any one of (1) to (4) above,

[0321] The plurality of pixels are arranged in a two-dimensional grid array.

[0322] The first wiring is arranged in a lattice pattern, and a plurality of the first pixels in the array are arranged in a one-to-one correspondence at each lattice point in the lattice pattern, and

[0323] The second wirings are arranged in a lattice pattern, and a plurality of the second pixels in the array are arranged in a one-to-one correspondence at each lattice point in the lattice pattern. (6)

[0325] The imaging device according to any one of (1) to (5) above,

[0326] wherein each of the plurality of pixels is provided with a color filter corresponding to the light receiving element, and

[0327] At least one of the first wiring and the second wiring is connected to each of the plurality of pixels provided with the color filter that transmits the same wavelength component. (7)

[0329] The imaging device according to any one of (1) to (6) above, further comprising a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip.

[0330] The light receiving element and the pixel circuit are arranged on the first semiconductor chip, and the conversion circuit and the generation unit are arranged on the second semiconductor chip. (8)

[0332] The image pickup device according to (7) above, wherein the first wiring and the second wiring are arranged on the second semiconductor chip. (9)

[0334] The imaging device according to any one of (1) to (6) above, further comprising a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip.

[0335] At least a portion of the conversion circuit, the light receiving element, and the pixel circuit are arranged on the first semiconductor chip, and a portion of the conversion circuit not provided on the first semiconductor chip and the generating unit are arranged on the second semiconductor chip. (10)

[0337] The image pickup device according to (9) above, wherein the first wiring and the second wiring are arranged on the first semiconductor chip. (11)

[0339] A camera device, comprising:

[0340] a plurality of pixels, each of the plurality of pixels including a light receiving element that generates charge by photoelectric conversion in response to received light,

[0341] a pixel circuit that reads out the charge from the light receiving element and outputs an analog signal corresponding to the charge, and

[0342] a conversion circuit that converts the analog signal into a digital signal based on a comparison result obtained by comparing the analog signal with a reference signal whose voltage changes in a step-like manner at a constant slope over time;

[0343] a first generating unit that generates a first reference signal to be provided to a first pixel among the plurality of pixels as the reference signal;

[0344] a second generating unit that generates a second reference signal to be provided to a second pixel among the plurality of pixels as the reference signal;

[0345] a first wiring connecting the first generating unit and the first pixel; and

[0346] a second wiring connecting the second generation unit and the second pixel,

[0347] in,

[0348] The first reference signal is supplied to the first pixel via the first wiring, and

[0349] The second reference signal is supplied to the second pixel via the second wiring. (12)

[0351] According to the imaging device described in (11) above,

[0352] The first generating unit and the second generating unit are arranged on the same side of a region in which the plurality of pixels are arranged. (13)

[0354] According to the imaging device described in (11) or (12),

[0355] wherein the first generating unit is arranged on one side of one end of a region in which the plurality of pixels are arranged, and

[0356] The second generating unit is arranged at the other end of the region opposite to the one end. (14)

[0358] The imaging device according to any one of (11) to (13) above,

[0359] The second generation unit generates the second reference signal obtained by applying an offset to the first reference signal. (15)

[0361] According to the imaging device described in (14) above,

[0362] The second generation unit generates the second reference signal obtained by applying the offset to the first reference signal, wherein the offset offsets a reference voltage serving as a reference of the slope. (16)

[0364] According to the imaging device described in (14) above,

[0365] The second generation unit generates the second reference signal obtained by applying the offset to the first reference signal, wherein the offset causes the slope to shift in a time direction. (17)

[0367] The imaging device according to any one of (11) to (16) above,

[0368] The plurality of pixels are arranged in a two-dimensional grid array.

[0369] The first wiring is arranged in a lattice pattern, and a plurality of the first pixels in the array are arranged in a one-to-one correspondence at each lattice point in the lattice pattern, and

[0370] The second wirings are arranged in a lattice pattern, and a plurality of the second pixels in the array are arranged in a one-to-one correspondence at each lattice point in the lattice pattern. (18)

[0372] The imaging device according to any one of (11) to (17) above,

[0373] wherein each of the plurality of pixels is provided with a color filter corresponding to the light receiving element, and

[0374] At least one of the first wiring and the second wiring is connected to each of the plurality of pixels provided with the color filter that transmits the same wavelength component. (19)

[0376] The imaging device according to any one of (11) to (18) above, further comprising a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip,

[0377] wherein the light receiving element and the pixel circuit are arranged on the first semiconductor chip, and the conversion circuit, the first generation unit and the second generation unit are arranged on the second semiconductor chip, and

[0378] The first wiring and the second wiring are arranged on the second semiconductor chip. (20)

[0380] The image pickup device according to (19) above, wherein the first wiring and the second wiring are arranged on the second semiconductor chip. (twenty one)

[0382] The imaging device according to any one of (11) to (18) above, further comprising a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip.

[0383] wherein at least a portion of the conversion circuit, the light receiving element, and the pixel circuit are arranged on the first semiconductor chip, and a portion of the conversion circuit not arranged on the first semiconductor chip, the first generating unit, and the second generating unit are arranged on the second semiconductor chip, and

[0384] The first wiring and the second wiring are arranged on the first semiconductor chip. (twenty two)

[0386] The image pickup device according to (21) above, wherein the first wiring and the second wiring are arranged on the first semiconductor chip.

[0387] [reference numerals list]

[0388] 1 Pixel array unit

[0389] 4 Timing control unit

[0390] 5, 5a, 5b, 5c, 5c(a), 5c(b), 5c(c) DAC

[0391] 6 Time code generation circuit

[0392] 7 Overall control unit

[0393] 10, 10R, 10G, 10B, 10W pixels

[0394] 11 Pixel Circuit

[0395] 12 ADC

[0396] 13 Storage Circuit

[0397] 14 Calculation Circuit

[0398] 16 Conductive Path

[0399] 20 Write transmission circuit

[0400] 21 Readout transmission circuit

[0401] 100 Photodiode

[0402] 101 FD

[0403] 120a, 120b, 120c connection part

[0404] 300 Electronic equipment

[0405] 1000 Camera Device

[0406] 1001 First Semiconductor Chip

[0407] 1002 second semiconductor chip

[0408] 1020 Driver

[0409] 1021 Through Hole

[0410] 1030, 1031a, 1031b wiring

[0411] 1040, 1040a, 1040b first slope

[0412] 1041, 1041a, 1041b second slope.

Claims

1. A camera device, comprising: a plurality of pixels, each of the plurality of pixels including a light receiving element that generates charge by photoelectric conversion in response to received light; a pixel circuit that reads out the charge from the light receiving element and outputs an analog signal corresponding to the charge; and a conversion circuit that converts the analog signal into a digital signal based on a comparison result obtained by comparing the analog signal with a reference signal whose voltage changes in a step-like manner at a constant slope over time; a generating unit that generates a first reference signal to be provided to a first pixel among the plurality of pixels and a second reference signal to be provided to a second pixel among the plurality of pixels that is different from the first pixel, the reference signal including the first reference signal and the second reference signal; a first wiring connecting the generating unit and the first pixel; and a second wiring connecting the generating unit and the second pixel, in, The first reference signal is supplied to the first pixel via the first wiring, and The second reference signal is supplied to the second pixel via the second wiring, The generating unit generates the second reference signal by applying an offset to the first reference signal.

2. The imaging device according to claim 1, in, The offset offsets a reference voltage used as a reference for the slope.

3. The imaging device according to claim 1, in, The offset shifts the slope in the time direction.

4. The imaging device according to claim 1, in, The plurality of pixels are arranged in a two-dimensional grid array, The first wiring is arranged in a lattice pattern, and a plurality of the first pixels in the array are arranged in a one-to-one correspondence at each lattice point in the lattice pattern of the first wiring, and The second wirings are arranged in a lattice pattern, and a plurality of the second pixels in the array are arranged in a one-to-one correspondence at respective lattice points in the lattice pattern of the second wirings.

5. The imaging device according to claim 1, in, The plurality of pixels are provided with color filters corresponding to the light receiving elements, and At least one of the first wiring and the second wiring is connected to each of the plurality of pixels provided with the color filter that transmits the same wavelength component.

6. The imaging device according to claim 1, comprising a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip, in, The light receiving element and the pixel circuit are arranged on the first semiconductor chip, and the conversion circuit and the generating unit are arranged on the second semiconductor chip.

7. The imaging device according to claim 6, wherein: The first wiring and the second wiring are arranged on the second semiconductor chip.

8. The imaging device according to claim 1, comprising a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip, in, At least a portion of the conversion circuit, the light receiving element, and the pixel circuit are arranged on the first semiconductor chip, and a portion of the conversion circuit not provided on the first semiconductor chip and the generating unit are arranged on the second semiconductor chip.

9. The imaging device according to claim 8, wherein: The first wiring and the second wiring are arranged on the first semiconductor chip.

10. A camera device, comprising: a plurality of pixels, each of the plurality of pixels including a light receiving element that generates charge by photoelectric conversion in response to received light; a pixel circuit that reads out the charge from the light receiving element and outputs an analog signal according to the charge; and a conversion circuit that converts the analog signal into a digital signal based on a comparison result obtained by comparing the analog signal with a reference signal whose voltage changes in a step-like manner at a constant slope over time; a first generating unit which generates a first reference signal to be provided to a first pixel among the plurality of pixels; a second generating unit which generates a second reference signal to be provided to a second pixel among the plurality of pixels; a first wiring connecting the first generation unit and the first pixel; and a second wiring connecting the second generation unit and the second pixel, in, The reference signal includes the first reference signal and the second reference signal, The first reference signal is supplied to the first pixel via the first wiring, and The second reference signal is supplied to the second pixel via the second wiring, The second generating unit generates the second reference signal by applying an offset to the first reference signal.

11. The imaging device according to claim 10, in, The first generation unit and the second generation unit are respectively arranged on the same side of a region where the plurality of pixels are arranged.

12. The imaging device according to claim 10, in, The first generation unit is arranged on one side of one end of a region where the plurality of pixels are arranged, and The second generating unit is arranged at the other end of the region opposite to the one end.

13. The imaging device according to claim 10, in, The offset offsets a reference voltage used as a reference for the slope.

14. The imaging device according to claim 10, in, The offset shifts the slope in the time direction.

15. The imaging device according to claim 10, in, The plurality of pixels are arranged in a two-dimensional grid array, The first wiring is arranged in a lattice pattern, and a plurality of the first pixels in the array are arranged in a one-to-one correspondence at each lattice point in the lattice pattern of the first wiring, and The second wirings are arranged in a lattice pattern, and a plurality of the second pixels in the array are arranged in a one-to-one correspondence at respective lattice points in the lattice pattern of the second wirings.

16. The imaging device according to claim 10, in, The plurality of pixels are provided with color filters corresponding to the light receiving elements, and At least one of the first wiring and the second wiring is connected to each of the plurality of pixels provided with the color filter that transmits the same wavelength component.

17. The imaging device according to claim 10, comprising a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip, in, The light receiving element and the pixel circuit are arranged on the first semiconductor chip, and the conversion circuit, the first generation unit, and the second generation unit are arranged on the second semiconductor chip, and The first wiring and the second wiring are arranged on the second semiconductor chip.

18. The imaging device according to claim 10, comprising a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip, in, At least a portion of the conversion circuit, the light receiving element, and the pixel circuit are arranged on the first semiconductor chip, and a portion of the conversion circuit not provided on the first semiconductor chip, the first generating unit, and the second generating unit are arranged on the second semiconductor chip, and The first wiring and the second wiring are arranged on the first semiconductor chip.

Images