Substrate comprising at least one patterned ground plane for shielding

Abstract

A substrate comprising at least one dielectric layer, a first inductor formed in the at least one dielectric layer, a second inductor formed in the at least one dielectric layer, and a patterned ground layer formed on a metal layer of the substrate. The patterned ground layer is configured to provide electromagnetic (EM) shielding. The patterned ground layer comprises a plurality of slots. The plurality of slots may be filled with the at least one dielectric layer. The plurality of slots may include slots having a rectangular shape, slots having a polygonal shape, slots having a circular shape, or a combination thereof. The patterned ground layer may include at least one slot having a spiral shape individually or as a whole.

Description

Background Art

[0001] Priority claim

[0002] This patent application claims priority to application No. 16 / 219,071, filed on December 13, 2018, entitled “SUBSTRATE COMPRISING ATLEAST ONE PATTERNED GROUND PLANE FOR SHIELDING,” which is assigned to the assignee of the present application and is hereby expressly incorporated herein by reference.

[0003] field

[0004] Various features relate to substrates, but more particularly to substrates including at least one patterned ground plane for shielding.

[0005] background

[0006] FIG. 1 illustrates an integrated device 100 including a substrate 102 and a die 104. The die 104 is coupled to the substrate 102 via a plurality of solder interconnects 140. The substrate 102 includes a plurality of dielectric layers 120 and a plurality of interconnects 122. Each layer in the dielectric layer 120 includes a patterned metal layer and a through hole. The substrate 102 includes a first solder resist layer 124, a second solder resist layer 126, and a plurality of solder interconnects 130. The substrate 102 may include several passive devices (such as inductors) embedded in the substrate 102. These passive devices may be defined by a plurality of interconnects 122 formed in the dielectric layer 120. These passive devices may be close to each other in the substrate 102, which may cause the passive devices to interfere with each other, thereby causing the passive devices to have lower inductance and Q factor.

[0007] Therefore, there is a need to provide a substrate that can isolate and / or shield passive devices that are close to each other. Ideally, such a substrate can isolate and / or shield the passive device from nearby passive devices while also minimizing the inductance reduction of the passive device.

[0008] Overview

[0009] Various features relate to substrates, but more particularly to substrates including at least one patterned ground plane for shielding.

[0010] One example provides a substrate having at least one dielectric layer, a first inductor formed in the at least one dielectric layer, a second inductor formed in the at least one dielectric layer, and a patterned ground layer formed on a metal layer of the substrate. The patterned ground layer is configured to provide electromagnetic (EM) shielding.

[0011] Another example provides a substrate having at least one dielectric layer, means for a first inductor formed in the at least one dielectric layer, means for a second inductor formed in the at least one dielectric layer, and means for electromagnetic (EM) shielding formed on a metal layer of the substrate.

[0012] Another example provides a method for manufacturing a substrate. The method forms at least one dielectric layer. The method forms a first inductor in the at least one dielectric layer. The method forms a second inductor in the at least one dielectric layer. The method forms a patterned ground layer on a metal layer of the substrate. The patterned ground layer is configured to provide electromagnetic (EM) shielding. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Various features, characteristics and advantages will become apparent when the detailed description set forth below is read in conjunction with the accompanying drawings in which like reference numerals designate corresponding features throughout.

[0015] FIG. 1 illustrates a cross-sectional view of a device including a die and a substrate.

[0016] Figure 2 An assembled view of a substrate including an inductor and a patterned ground layer for shielding the inductor is illustrated.

[0017] Figure 3 An assembled view of an inductor on several layers of a substrate is illustrated.

[0018] Figure 4 A cross-sectional view of a substrate including an inductor and a patterned ground layer for shielding the inductor is illustrated.

[0019] Figure 5 Illustrated assembly view of two patterned ground planes used for shielding.

[0020] Figure 6 Illustrated assembly view of two patterned ground planes used for shielding.

[0021] Figure 7 A plan view of a patterned ground layer with slots of varying lengths is illustrated.

[0022] Figure 8 A plan view of a patterned ground layer having grooves is illustrated.

[0023] Fig. 9 A plan view of a patterned ground layer having polygonal-shaped grooves is illustrated.

[0024] Fig.10 A plan view of a patterned ground layer having circular shaped grooves is illustrated.

[0025] Fig.11A plan view of a patterned ground layer having spiral-shaped grooves is illustrated.

[0026] Fig.12 A plan view of a patterned ground layer having spiral-shaped grooves is illustrated.

[0027] Figure 13 (including Figures 13A-13D ) illustrates an exemplary process for manufacturing a substrate including an inductor and a patterned ground layer for shielding the inductor.

[0028] Fig.14 An exemplary flow chart of a method for manufacturing a coreless substrate is illustrated.

[0029] Fig.15 Various electronic devices are illustrated into which the dies, integrated devices, integrated passive devices (IPDs), device packages, packages, integrated circuits, substrates, and / or PCBs described herein may be integrated.

[0030] Detailed Description

[0031] In the following description, specific details are given to provide a thorough understanding of various aspects of the present disclosure. However, it will be understood by those of ordinary skill in the art that these aspects can be practiced without these specific details. For example, circuits may be shown with block diagrams to avoid burying these aspects in unnecessary details. In other examples, well-known circuits, structures, and techniques may not be shown in detail to avoid burying these aspects of the present disclosure.

[0032] The present disclosure describes a substrate comprising at least one dielectric layer, a first inductor formed in the at least one dielectric layer, a second inductor formed in the at least one dielectric layer, and a patterned ground layer formed on a metal layer of the substrate. The patterned ground layer is configured to provide electromagnetic (EM) shielding. The first inductor may be an embedded inductor defined by one or more first interconnects. The second inductor may be an embedded inductor defined by one or more second interconnects. The patterned ground layer comprises a plurality of slots. The plurality of slots may be filled with the at least one dielectric layer. The plurality of slots may include slots having a rectangular shape, slots having a polygonal shape, slots having a circular shape, or a combination thereof. The patterned ground layer may include at least one slot having a spiral shape individually or as a whole. In some implementations, the substrate comprising the patterned ground layer is part of a device (e.g., an integrated device) comprising a die. The substrate may be implemented in a radio frequency front end (RFFE) device.

[0033] Exemplary substrate including a patterned ground layer for shielding

[0034] Figure 2An assembled view of a substrate 200 including a first inductor 202, a second inductor 204, a first patterned ground layer 206, and a second patterned ground layer 208 is illustrated. The substrate 200 may include dielectric layers. The first inductor 202 may be defined by one or more first interconnects in the substrate 200. The second inductor 204 may be defined by one or more second interconnects in the substrate 200. The first inductor 202 and the second inductor 204 are located between the first patterned ground layer 206 and the second patterned ground layer 208. The first patterned ground layer 206 is formed on a metal layer (M1) (e.g., a top metal layer) of the substrate 200, and the second patterned ground layer 208 is formed on another metal layer (M5) (e.g., a bottom metal layer) of the substrate 200. However, different implementations may have a substrate 200 including patterned ground layers (on different metal layers).

[0035] The first patterned ground layer 206 and the second patterned ground layer 208 may each be coupled to ground. The first patterned ground layer 206 and the second patterned ground layer 208 may include a conductive material, such as a metal (e.g., copper). The first patterned ground layer 206 and the second patterned ground layer 208 may provide shielding (e.g., electromagnetic (EM) shielding) and isolation for the first inductor 202 and the second inductor 204 individually or collectively. The first patterned ground layer 206 and / or the second patterned ground layer 208 may be designed to reduce and / or minimize eddy currents generated by nearby EM devices and / or inductors. This may in turn help the first inductor 202 and / or the second inductor 204 perform with better inductance and a higher Q factor. The first patterned ground layer 206 and / or the second patterned ground layer 208 may also help isolate the first inductor 202 from the second inductor 204, and vice versa.

[0036] The first patterned ground layer 206 may be a means for a first EM shield, and the second patterned ground layer 208 may be a means for a second EM shield. The first patterned ground layer 206 is shown on a top metal layer (e.g., M1) of the substrate, and the second patterned ground layer 208 is on a bottom metal layer (e.g., M5) of the substrate. However, the first patterned ground layer 206 may be on a bottom metal layer of the substrate, and the second patterned ground layer 208 may be on a top metal layer of the substrate.

[0037] The first patterned ground layer 206 includes a plurality of grooves 260 and the second patterned ground layer 208 includes a plurality of grooves 280. The plurality of grooves 260 and the plurality of grooves 280 may each have grooves of different sizes (e.g., lengths, widths) and shapes. The plurality of grooves 260 and 280 may operate as degassing openings. The first patterned ground layer 206 and / or the second patterned ground layer 208 may be configured to operate as a Faraday cage to improve EM shielding.

[0038] The configuration, dimensions, design, size, and / or shape of the patterned ground layer (e.g., 206, 208) can define how much shielding and / or isolation is provided by the first inductor 202 and the second inductor 204. Different implementations can provide patterned ground layers having different configurations, dimensions, designs, sizes, and / or shapes. These different configurations, dimensions, designs, sizes, and / or shapes can affect the shielding and isolation performance of the patterned ground layer differently. Examples of different configurations, dimensions, designs, sizes, and / or shapes of the patterned ground layer are further described below.

[0039] Similarly, the configuration, dimensions, design, size, and / or shape of the first inductor 202 and the second inductor 204 are exemplary. Different implementations may use inductors having different configurations, dimensions, designs, sizes, and / or shapes.

[0040] Figure 3 An assembled view of the first inductor 202 and the second inductor 204 is illustrated. The first inductor 202 can be an embedded inductor defined by a plurality of interconnects (e.g., a first interconnect). For example, the first inductor 202 can be defined as a plurality of interconnects 302 on metal layer M2, a plurality of interconnects 304 on metal layer M3, and a plurality of interconnects 306a on metal layer M4. The second inductor 204 can be an embedded inductor defined by a plurality of interconnects 306b formed on metal layer M4. The plurality of interconnects 306a (e.g., a first interconnect) and the plurality of interconnects 306b (e.g., a second interconnect) can be part of the plurality of interconnects 306 formed on metal layer M4.

[0041] Figure 2-3 Examples of inductor designs are explained. However, different implementations may use different inductor designs and / or combinations. For example, different inductors may have different numbers of turns. Different inductors may be implemented on different numbers of metal layers. Different inductors may have different shapes and / or sizes. Different implementations may implement different numbers of inductors (e.g., 3 or more inductors). Thus, Figure 2-3 The inductor designs are exemplary only.

[0042] Although not shown, the metal layer including the first patterned ground layer 206 and the second patterned ground layer 208 may also include interconnects (e.g., traces, pads) for providing electrical connections (e.g., connections for data signals, power, ground). Similarly, the metal layer between the first patterned ground layer 206 and the second patterned ground layer 208 may also include interconnects (e.g., traces, pads) for providing electrical connections (e.g., connections for data signals, power, ground).

[0043] Figure 4 An exemplary cross-sectional view of a substrate 400 including a patterned ground layer is illustrated. The substrate 400 may be representative of the substrate 200. The substrate 400 includes five metal layers (M1, M2, M3, M4, M5). The markings of the metal layers of the substrate are exemplary. Different implementations may specify the metal layers differently. For example, the metal layers may be designated as M1, M2, M3, M4, and M5 from bottom to top. In some implementations, the M1 and M5 metal layers are considered to be the top metal layer and the bottom metal layer of the substrate, respectively. In some implementations, the M1 and M5 metal layers may be considered to be the first metal layer and the last metal layer of the substrate, respectively. In some implementations, the substrate 400 may include less than 5 metal layers or more than 5 metal layers (e.g., 6 or more metal layers).

[0044] Figure 4 Substrate 400 is illustrated as including dielectric layer 420, dielectric layer 422, dielectric layer 424, and dielectric layer 426. In some implementations, dielectric layer 420, dielectric layer 422, dielectric layer 424, and dielectric layer 426 may be considered as one dielectric layer (e.g., a single dielectric layer). Substrate 400 includes multiple interconnects 402, multiple interconnects 404, and multiple interconnects 406. Multiple interconnects 406 may include multiple interconnects 410 and multiple interconnects 412.

[0045] A plurality of interconnects 402 may be formed on a metal layer (M1) (e.g., a first metal layer, a top metal layer) of substrate 400. The plurality of interconnects 402 may define a first patterned ground layer 206. A plurality of interconnects 404 may be formed on a metal layer (M5) (e.g., a last metal layer, a bottom metal layer) of substrate 400. The plurality of interconnects 404 may define a second patterned ground layer 208. Note that the positioning of the first patterned ground layer 206 and the second patterned ground layer 208 is exemplary. Different implementations may form the first patterned ground layer 206 and the second patterned ground layer 208 on different metal layers of substrate 400. In addition, substrate 400 may have a different number of metal layers. In some implementations, there may be only one patterned ground layer, or more than two patterned ground layers.

[0046] The plurality of interconnects 410 may define the first inductor 202, and the plurality of interconnects 412 may define the second inductor 204. The first inductor 202 may be a device for the second inductance, and the second inductor 204 may be a device for the second inductance. The first inductor 202 and the second inductor 204 are located between the first patterned ground layer 206 and the second patterned ground layer 208. The configuration, shape, size, positioning, and size of the first inductor 202 and the second inductor 204 are exemplary. In some implementations, the first inductor 202 and / or the second inductor 204 may be discrete inductors.

[0047] Figure 4 The substrate 400 is illustrated as a coreless substrate. In some implementations, the substrate 400 may include a core layer. The core layer may include different dielectric materials such as silicon, glass, quartz, epoxy, or a combination thereof.

[0048] Figure 2 The first patterned ground layer 206 and the second patterned ground layer 208 are illustrated as having substantially the same design. In some implementations, a substrate (eg, 200, 400) can include ground layers having different designs and / or combinations.

[0049] Figure 5 An assembled view illustrating the first patterned ground layer 206 as a top ground layer of the substrate and the second ground layer 508 as a bottom ground layer of the substrate. Figure 6 An assembly view illustrating the first ground layer 606 as the top ground layer of the substrate and the second patterned ground layer 208 as the bottom ground layer of the substrate. These two combinations are examples of different combinations of ground layers that can be implemented in the substrate. The positioning of the metal layers (M1, M5) is exemplary, and the ground layer can be formed on any metal layer of the substrate.

[0050] Exemplary Patterned Ground Layer

[0051] Figure 7-12 Examples of ground layers (eg, patterned ground layers) that may be implemented in a substrate are provided. Figure 7-12 The ground layers may be implemented in the substrate individually or in combination with each other. Figure 7-12 The ground layer may replace other ground layers described in this disclosure or be used in combination with other ground layers. Figure 5-12 The ground layer can be a means for EM shielding.

[0052] Figure 7 A first patterned ground layer 206 is illustrated that includes a plurality of slots 260. Each slot has a respective width (W) and length (L). Each slot is separated by a space (S). Figure 7It is explained that the slots can have different lengths and / or widths. In some implementations, the length of the slots can be a maximum of 50% of the X dimension of the shielded structure (e.g., 50% of the X dimension of the inductor). In some implementations, the combined width and spacing of the slots can be a maximum of 50% of the Y dimension of the shielded structure (e.g., 50% of the Y dimension of the inductor). In some implementations, the width of the slots is a minimum of 1 / 50 of the wavelength of the electromagnetic (EM) field generated by the inductor(s) (e.g., the first inductor 202, the second inductor 204). In some implementations, the spacing of the slots is a minimum of 1 / 50 of the wavelength of the EM field generated by the inductor(s) (e.g., the first inductor 202, the second inductor 204). Therefore, the width and / or spacing of the slots can be approximately 1 / 50 or more of the wavelength (e.g., the wavelength of the electromagnetic (EM) field generated by the inductor(s). Therefore, in some implementations, the width and / or spacing of the slots can be inversely proportional to the wavelength of the EM field generated by one or more inductors in the substrate.

[0053] The wavelength of the generated EM field is related to the frequency of the current flowing through and / or through the inductor(s) (e.g., the operating frequency). For example, wavelength multiplied by frequency can equal the speed of the EM field (wavelength*frequency=speed), where speed can be the speed of the EM field when passing through air or through a dielectric layer. The speed can be considered a constant. Therefore, higher frequencies result in lower wavelengths, and lower frequencies can result in higher wavelengths. Since the wavelength of the EM field is related to the frequency of the current, the width and / or spacing of the slots can also be related to the frequency of the current flowing through the inductor. When the width and / or spacing of the slots are related to the wavelength and / or frequency, this can mean that the width and / or spacing is directly proportional or inversely proportional to the wavelength and / or frequency.

[0054] In some implementations, the current flowing through one or more inductors (e.g., the first inductor 202, the second inductor 204) may have a frequency in the range of approximately 1-21 gigahertz (Ghz). However, different implementations may use currents with different frequencies. The size (e.g., width, length, diameter) of each slot and the spacing between adjacent slots can be designed based on the operating frequency of the one or more inductors located in the substrate to optimize shielding of the EM field to meet a minimum decibel (dB) isolation. However, too much decibel (dB) isolation may not be good because it will reduce the inductance and / or Q factor of the one or more inductors. Therefore, the slot size can be configured based on the operating frequency of the one or more inductors (e.g., the operating center frequency) to provide a minimum decibel (dB) isolation while also minimizing the loss of inductance and / or Q factor of the one or more inductors. In some implementations, the size, spacing, and / or shape of the slot is configured to provide at least negative 60 decibels (dB) of isolation. The above factors and considerations can be applied to other designs of the slots described in the present disclosure, such as Figure 8-12The design shown in .

[0055] Figure 8 The patterned ground layer 806 is illustrated. The patterned ground layer 806 is similar to the first patterned ground layer 206 and / or the second patterned ground layer 208. The patterned ground layer 806 includes a plurality of grooves 860. The plurality of grooves 860 have uniform grooves having the same length, width, and spacing.

[0056] Figure 2 and 5 -8 illustrates that the lengths of the slots (e.g., 260, 280, 860) are aligned along the X direction. However, note that the lengths of the slots may be aligned along the X direction, the Y direction, a diagonal (e.g., 45 degrees), or a combination thereof. For example, some slots may be aligned along a first direction (e.g., X direction, Y direction, diagonal) and some slots may be aligned along a second direction (e.g., Y direction, X direction, diagonal).

[0057] Fig. 9 A patterned ground layer 906 including a plurality of slots 910 is illustrated. The plurality of slots 910 have slots having a polygonal shape (e.g., an octagon). Each slot has a corresponding diameter (D). In some implementations, the diameter of the slot may be referred to as a width. Each slot is separated by a spacing (S). In some implementations, the combined length and spacing of the slots may be a maximum of 50% of the X dimension of the shielded structure (e.g., 50% of the X dimension of the inductor). In some implementations, the combined width and spacing of the slots may be a maximum of 50% of the Y dimension of the shielded structure (e.g., 50% of the Y dimension of the inductor). In some implementations, the width of the slots is a minimum of 1 / 50 of the wavelength. In some implementations, the spacing of the slots is a minimum of 1 / 50 of the wavelength. Thus, the width and / or spacing of the slots may be approximately 1 / 50 or more of a wavelength (e.g., a wavelength of an electromagnetic (EM) field generated by the inductor(s). An example of a width and / or spacing greater than 1 / 50 of a wavelength would be a width and / or spacing of 1 / 40 of a wavelength.

[0058] Fig.10 A patterned ground layer 1006 is illustrated that includes a plurality of grooves 1010. The plurality of grooves 1010 have grooves having a circular shape. Each groove has a corresponding diameter (D). Fig. 9 The dimensions described in can be applicable to multiple slots 1010. For example, for Figure 7-8 The minimum width of the slot can also be referred to as Figure 9-10 The minimum diameter of the groove.

[0059] Fig.11 A patterned ground layer 1106 including a groove 1110 and a groove 1120 is illustrated. The groove 1110 has a spiral shape. The groove 1120 has a spiral shape. The spiral of the groove 1120 is larger than the spiral of the groove 1110. Similarly, Fig. 9The overall dimensions described in may apply to grooves 1110 and 1120. The size and shape of the spirals are exemplary.

[0060] Fig.12 Illustrated is a patterned ground layer 1106 including a first plurality of grooves 1210 and a second plurality of grooves 1120. The first plurality of grooves 1210 has a spiral shape. The second plurality of grooves 1220 has a spiral shape. Fig.12 It is illustrated that the spiral shape may be defined as a number of grooves rather than a single groove. The spiral of plurality of grooves 1220 is greater than the spiral of plurality of grooves 1110 . Fig. 9 The overall dimensions described in may apply to multiple grooves 1210 and 1220. The size and shape of the spirals are exemplary.

[0061] Note that the 50% value described above is merely exemplary. Different implementations may provide slots with different coverage areas. In some implementations, the slots may collectively represent more or less than 50% of the surface area of ​​the inductor. In some implementations, a coverage area of ​​approximately 50% (e.g., 45% to 55%) of the surface area of ​​one or more inductors may provide an appropriate amount of shielding and isolation while also maximizing the inductance and Q of the inductor. The term "coverage area" may mean the area where the slot overlaps (e.g., vertically overlaps) the inductor when viewed from a plan view perspective. Note that the slot may be positioned in an area where there is no inductor below or above the slot. A coverage area of ​​approximately 50% may mean that the slot vertically overlaps approximately 50% of the inductor, but the slot may represent more than 50% of the area of ​​the metal layer on which the slot is formed. As mentioned above, the ground layer may provide EM shielding and / or isolation. In some implementations, Figure 5-12 The first patterned ground layer and the second patterned ground layer may individually or collectively provide negative 60-85 decibels (dB) of isolation between the first inductor and the second inductor.

[0062] Having described a substrate including a ground layer, a method for making the disclosed substrate will now be described below.

[0063] Exemplary Process for Making Coreless Substrates

[0064] In some implementations, manufacturing the substrate includes several processes. Figures 13A-13D ) illustrates an exemplary process for providing or manufacturing a substrate including a patterned ground layer. In some implementations, Figures 13A-13D The process can be used to provide or manufacture Figure 4 substrate 400.

[0065] It should be noted that Figures 13A-13DThe process of one or more stages can be combined to simplify and / or illustrate the process for providing or manufacturing a substrate. In some implementations, the order of these processes can be changed or modified. In some implementations, one or more processes can be replaced or substituted without departing from the spirit of the present disclosure.

[0066] like Fig.13A As shown in , stage 1 illustrates a state after providing a carrier 1300 and forming a metal layer over the carrier 1300. The metal layer may be patterned to form interconnects 402. A plating process may be used to form the metal layer and the interconnects.

[0067] Stage 2 illustrates a state after a dielectric layer 420 is formed on the carrier 1300 and the interconnects. The dielectric layer 420 may include polyimide.

[0068] Stage 3 illustrates a state after a plurality of cavities 1310 are formed in the dielectric layer 420. The plurality of cavities 1310 may be formed using an etching process or a laser process.

[0069] Stage 4 illustrates a state after interconnects 1312 are formed in and on dielectric layer 420. For example, vias, pads, and / or traces may be formed. These interconnects may be formed using a plating process.

[0070] Stage 5 illustrates the state after another dielectric layer 422 is formed over the dielectric layer 420 .

[0071] like Fig. 13B As shown in FIG. 4 , stage 6 illustrates the state after the cavity 1320 is formed in the dielectric layer 422 .

[0072] The cavity 1320 may be formed using an etching process or a laser process.

[0073] Stage 7 illustrates a state after interconnects 1322 are formed in and on dielectric layer 422. For example, vias, pads, and / or traces may be formed. These interconnects may be formed using a plating process.

[0074] Stage 8 illustrates the state after another dielectric layer 424 is formed over the dielectric layer 422 .

[0075] like Fig. 13C As shown in FIG. 1 , stage 9 illustrates the state after the cavity 1330 is formed in the dielectric layer 424 .

[0076] The cavity 1330 may be formed using an etching process or a laser process.

[0077] Stage 10 illustrates a state after interconnects 1332 are formed in and on dielectric layer 424. For example, vias, pads, and / or traces may be formed. These interconnects may be formed using a plating process.

[0078] Stage 11 illustrates the state after another dielectric layer 426 is formed over the dielectric layer 424 .

[0079] like Fig. 13C , stage 12 illustrates a state after a cavity 1340 is formed in the dielectric layer 426. The cavity 1340 may be formed using an etching process or a laser process.

[0080] Stage 13 illustrates a state after interconnects 1342 are formed in and on dielectric layer 426. For example, vias, pads, and / or traces may be formed. These interconnects may be formed using a plating process.

[0081] Stage 14 illustrates that after carrier 1300 is decoupled (e.g., removed, ground away) from dielectric layer 420, substrate 400 (e.g., a coreless substrate) is left. In some implementations, coreless substrate is an embedded trace substrate (ETS). Stage 14 illustrates substrate 400, which includes dielectric layer 420, dielectric layer 422, dielectric layer 424, and dielectric layer 426. In some implementations, dielectric layer 420, dielectric layer 422, dielectric layer 424, and dielectric layer 426 can be considered as one dielectric layer (e.g., a single dielectric layer). Substrate 400 includes multiple interconnects 402, multiple interconnects 404, and multiple interconnects 406. Multiple interconnects 406 can include multiple interconnects 410 and multiple interconnects 412.

[0082] Different implementations may use different processes to form the metal layer. In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process is used to form the metal layer(s). For example, a sputtering process, a spraying process, and / or a plating process may be used to form the metal layer.

[0083] Exemplary Flowchart of a Method for Manufacturing a Substrate Having a Patterned Ground Layer

[0084] In some implementations, manufacturing the substrate includes several processes. Fig.14 An exemplary flow chart of a method 1400 for providing or manufacturing a substrate having a patterned ground layer is illustrated. In some implementations, Fig.14 The method 1400 may be used to provide or manufacture Figure 2 and / or 4. For example, Fig.14 The method may be used to manufacture the substrate 400 .

[0085] It should be noted that Fig.14 The steps of the present invention may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a substrate. In some implementations, the order of these processes may be changed or modified.

[0086] The method provides (at 1405) a carrier 1300. The method forms (at 1410) a metal layer over the carrier 1300. The metal layer may be patterned to form interconnects. A plating process may be used to form the metal layer and the interconnects.

[0087] The method forms (at 1415) a dielectric layer 420 over the carrier 1300 and the interconnects. The dielectric layer 420 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (eg, 1310) in the dielectric layer 420. The plurality of cavities may be formed using an etching process or a laser process.

[0088] The method forms (at 1420) interconnects in and on the dielectric layer. For example, interconnects 1312 may be formed. These interconnects may be formed using a plating process. Forming the interconnects may include providing a patterned metal layer on and / or in the dielectric layer.

[0089] The method forms (at 1425) a dielectric layer 422 over the dielectric layer 420 and the interconnects. The dielectric layer 422 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (eg, 1320) in the dielectric layer 422. The plurality of cavities may be formed using an etching process or a laser process.

[0090] The method forms (at 1430) interconnects in and / or on the dielectric layer. For example, interconnects 1322 may be formed. These interconnects may be formed using a plating process. Forming the interconnects may include providing a patterned metal layer on and in the dielectric layer.

[0091] The method may form additional dielectric layers and additional interconnects, as described at 1425 and 1430 .

[0092] Once all dielectric layers and additional interconnects are formed, the method can decouple (eg, remove, grind away) the carrier (eg, 1300) from the dielectric layer 420, leaving the substrate. In some implementations, the coreless substrate is an embedded trace substrate (ETS).

[0093] Different implementations may use different processes to form the metal layer. In some implementations, a chemical vapor deposition (CVD) process and / or a physical vapor deposition (PVD) process is used to form the metal layer(s). For example, a sputtering process, a spraying process, and / or a plating process may be used to form the metal layer.

[0094] Exemplary Electronic Devices

[0095] Fig.15Various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, or packages-on-package (PoP) are illustrated. For example, a mobile phone device 1502, a laptop computer device 1504, a fixed location terminal device 1506, a wearable device 1508, or a motor vehicle 1510 may include a device 1500 as described herein. The device 1500 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. Fig.15 The devices 1502, 1504, 1506, and 1508, and the vehicle 1510 illustrated in the figure are merely exemplary. Other electronic devices can also feature the device 1500, including, but not limited to, the group of devices (e.g., electronic devices) including: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), devices enabled with a global positioning system (GPS), navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading equipment), communication devices, smart phones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0096] Figure 2-12 , 13A-13D and / or 14-15, one or more of the components, processes, features, and / or functions illustrated in the embodiments of the present invention may be rearranged and / or combined into a single component, process, feature, or function, or implemented in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that Figure 2-12 , 13A-13D and / or 14-15 and their corresponding descriptions in this disclosure are not limited to die and / or IC. In some implementations, Figure 2-12 , 13A-13D and / or 14-15 and their corresponding descriptions may be used to manufacture, create, provide, and / or produce equipment and / or integrated devices. In some implementations, the device may include a die, a substrate, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a semiconductor device, a package-on-package (PoP) device, and / or an interposer.

[0097] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as superior or superior to other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C may still be considered to be coupled to each other - even if they are not in direct physical contact with each other. Further note that the term "above", as used in the context of one component being above another component in this application, may be used to indicate that a component is on and / or in (e.g., on a surface of or embedded in) another component. Thus, for example, a first component being above a second component may mean: (1) the first component is above the second component, but not directly contacting the second component; (2) the first component is on (e.g., on a surface of) the second component; and / or (3) the first component is in (e.g., embedded in) the second component. As used in this disclosure, the term "about 'value X'" or "substantially" shall mean within ten percent of "value X." For example, a value of about 1 or a value of substantially 1 will mean a value in the range of 0.9-1.1.

[0098] In some implementations, interconnection is an element or component in a device that allows or facilitates electrical connection between two points, elements and / or components. In some implementations, interconnection may include traces, vias, pads, columns, metal layers (e.g., redistribution metal layers), and / or under bump metallization (UBM) layers. In some implementations, interconnection is a conductive material that can be configured to provide an electrical path for a signal (e.g., a data signal, grounding, or power). Interconnection can be part of a circuit. Interconnection may include more than one element or component.

[0099] In some implementations, the height of the device and / or package can be defined along the Z direction of the package, which is shown in the drawings of the present disclosure. In some implementations, the Z direction of the device and / or package can be defined along the axis between the top portion and the bottom portion of the device and / or package. The terms "top" and "bottom" can be assigned arbitrarily, however, as an example, the top portion of the device and / or package can be a portion including an encapsulation layer, while the bottom portion of the package can be a portion including a redistribution portion or a plurality of solder balls. In some implementations, the top portion of the package can be the back side of the package, while the bottom portion of the package can be the front side of the package. The front side of the package can be the active side of the package. The top portion can be a higher portion relative to the lower portion. The bottom portion can be a lower portion relative to the higher portion.

[0100] The XY direction or XY plane of a device and / or package may refer to the lateral direction and / or occupied area of ​​the device and / or package. Examples of the XY direction are shown in the drawings of the present disclosure. The width, length and / or diameter of an object may refer to the size(s) along the XY dimension and / or the XY plane. In many of the drawings of the present disclosure, devices and / or packages and their corresponding components are shown across an XZ cross section or an XZ plane. However, in some implementations, packages and their representative components may be represented across a YZ cross section or a YZ plane.

[0101] It is also noted that the various disclosures contained herein may be described as processes depicted as flow charts, flow diagrams, structure diagrams, or block diagrams. Although a flow chart may describe operations as sequential processes, many operations may be performed in parallel or simultaneously. In addition, the order of operations may be rearranged. A process terminates when its operations are completed.

[0102] The various features of the present disclosure described herein may be implemented in different systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the various aspects of the present disclosure is intended to be illustrative rather than limiting the scope of the appended claims. Thus, the teachings of the present invention may be readily applied to other types of devices, and many replacements, modifications, and variations will be apparent to those skilled in the art.

Claims

1. An electronic device comprising: A substrate, comprising: at least one dielectric layer; a first inductor formed in the at least one dielectric layer; a second inductor formed in the at least one dielectric layer; and a first patterned ground layer formed on the metal layer of the substrate, wherein the first patterned ground layer comprises a plurality of grooves, wherein each slot comprises a length in the X direction and a width in the Y direction and is separated by spaces, wherein the length of each slot is at most 50% of the X dimension of the first inductor, and Wherein the first patterned ground layer is configured to provide electromagnetic (EM) shielding.

2. The electronic equipment of claim 1, wherein a combined width and spacing of the slots is at most 50% of a Y dimension of the first inductor and the second inductor.

3. The electronic equipment of claim 1, wherein the width and / or spacing of the slots is at least 1 / 50 of a wavelength of an electromagnetic field generated by the first inductor and the second inductor. 4 . The electronic equipment of claim 1 , wherein an area where the slot overlaps the first inductor and the second inductor is 55% of a surface area of ​​the first inductor and the second inductor. 5 . The electronic equipment of claim 1 , wherein the plurality of grooves are filled with the at least one dielectric layer.

6. The electronic equipment of claim 1, wherein the first patterned ground layer provides at least negative 60 decibels (dB) of isolation between the first inductor and the second inductor. 7 . The electronic equipment of claim 1 , wherein the substrate further comprises a second patterned ground layer formed on another metal layer of the substrate.

8. The electronic equipment of claim 7, wherein the first patterned ground layer and the second patterned ground layer collectively provide negative 60-85 decibels (dB) of isolation between the first inductor and the second inductor.

9. The electronic equipment of claim 1, wherein the substrate is incorporated into at least one device selected from the group consisting of: a music player, a video player, an entertainment unit, a communication device, a mobile device, a fixed location terminal, a computer, and a wearable device.

10. An electronic device comprising: A substrate, comprising: a plurality of metal layers including a first metal layer and a second metal layer, the first metal layer including a pattern forming means for first electromagnetic (EM) shielding, the means for first EM shielding including a plurality of slots; at least one dielectric layer; means for a first inductance formed in the at least one dielectric layer, wherein the means for a first inductance is configured to generate a first electromagnetic field having a first wavelength; and means for a second inductance formed in said at least one dielectric layer, wherein each slot from the plurality of slots comprises a width that is at least 1 / 50 of the first wavelength of the first electromagnetic field generated by the means for a first inductance, and Wherein the means for a first inductance and the means for a second inductance are between the means for a first EM shield and the second metal layer.

11. The electronic equipment of claim 10, wherein the means for second inductance is configured to generate a second electromagnetic field having a second wavelength, and Wherein each slot from the plurality of slots comprises a width that is at least 1 / 50 of the second wavelength of the second electromagnetic field generated by the means for a second inductance.

12. The electronic device of claim 10, wherein the plurality of grooves are filled with the at least one dielectric layer, and wherein a spacing between at least two adjacent slots from said plurality of slots comprises a minimum width that is at least 1 / 50 of said first wavelength of said first electromagnetic field generated by said means for a first inductance, The area where the plurality of slots vertically overlap with the means for the first inductor is 55% of the surface area of ​​the means for the first inductor.

13. The electronic equipment of claim 10, wherein the means for a first EM shield provides at least negative 60 decibels (dB) of isolation between the means for a first inductor and the means for a second inductor.

14. The electronic equipment of claim 10, wherein the second metal layer includes a pattern forming means for a second EM shield, wherein the means for a first inductor and the means for a second inductor are between the means for a first EM shield and the means for a second EM shield.

15. The electronic equipment of claim 14, wherein the means for a first EM shield and the means for a second EM shield collectively provide a negative 60-85 decibel (dB) isolation between the means for a first inductor and the means for a second inductor.

16. The electronic equipment of claim 10, wherein the means for a first EM shield is coupled to ground.

17. The electronic equipment of claim 10, wherein the substrate is incorporated into at least one device selected from the group consisting of: a music player, a video player, an entertainment unit, a communication device, a mobile device, a fixed location terminal, a computer, and a wearable device.

18. A method for manufacturing a substrate, the method comprising: forming a plurality of metal layers including a first metal layer and a second metal layer; forming at least one dielectric layer; forming a first inductor in the at least one dielectric layer, wherein the first inductor is configured to generate an electromagnetic field having a wavelength; forming a second inductor in the at least one dielectric layer; as well as patterning the first metal layer so that the first metal layer includes a first patterned ground layer, the first patterned ground layer includes a plurality of grooves, wherein each slot from the plurality of slots comprises a minimum width that is at least 1 / 50 of the wavelength of the electromagnetic field generated by the first inductor, wherein the first patterned ground layer is configured to provide electromagnetic (EM) shielding, and Wherein forming the first inductor and the second inductor includes forming the first inductor and the second inductor between the first patterned ground layer and the second metal layer.

19. The method of claim 18, wherein a spacing between two adjacent slots from the plurality of slots comprises a minimum width that is at least 1 / 50 of the wavelength of the electromagnetic field generated by the first inductor.

20. The method of claim 18, wherein the plurality of trenches are filled with the at least one dielectric layer.

Images