Integrated Circuit Device, Method for Manufacturing the Same, and Integrated Circuit Manufacturing System

Abstract

An integrated circuit (IC) device includes: a substrate having opposite first and second faces; an active region located above the first face of the substrate; a first conductive pattern located above the active region; and a second conductive pattern located below the second face of the substrate. The active region includes a first portion and a second portion. The first conductive pattern is electrically connected to the first and second portions of the active region. The second conductive pattern is electrically connected to the first and second portions of the active region. The present invention also relates to the manufacture of integrated circuit devices and integrated circuit manufacturing systems.

Description

Technical Field

[0001] Embodiments of the present invention relate to integrated circuit devices, methods of manufacturing the same, and integrated circuit manufacturing systems. Background Art

[0002] Integrated circuit (IC) devices include a plurality of semiconductor devices represented by an IC layout. The IC layout is hierarchical and includes modules that perform higher-level functions according to semiconductor device design specifications. Modules are typically constructed from combinations of cells, each of which represents one or more semiconductor structures configured to implement a specific function. Cells with pre-designed layouts, sometimes referred to as standard cells, are stored in a standard cell library (hereinafter referred to as the "library" or "cell library" for simplicity) and can be accessed by various tools (such as electronic design automation (EDA) tools) to generate, optimize, and verify designs for ICs. Summary of the Invention

[0003] An embodiment of the present invention relates to an integrated circuit device, comprising: a substrate having opposite first and second surfaces; an active region located above the first surface of the substrate, the active region including a first part and a second part; a first conductive pattern located above the active region and electrically connected to the first part and the second part of the active region; and a second conductive pattern located below the second surface of the substrate and electrically connected to the first part and the second part of the active region.

[0004] Another embodiment of the present invention relates to an integrated circuit manufacturing system, comprising a processor configured to generate an integrated circuit (IC) layout that can be used to manufacture an IC device, the IC layout including: an active region; a plurality of gate regions extending over the active region, the plurality of gate regions including a first gate region and a second gate region; a first contact region located above the active region and adjacent to the first gate region; a second contact region located above the active region and adjacent to the second gate region; a first via located above the first contact region; a second via located above the second contact region; a first conductive pattern located above the first via and the second via; a first through-via located below the first contact region and the active region; a second through-via located below the second contact region and the active region; and a second conductive pattern located below the first through-via and the second through-via; wherein the first conductive pattern, the first via, the first contact region, the first through-via, and the second conductive pattern overlap each other, and the first conductive pattern, the second via, the second contact region, the second through-via, and the second conductive pattern overlap each other.

[0005] Another embodiment of the present invention relates to a method of manufacturing an integrated circuit device, comprising: forming a first transistor and a second transistor above a first surface of a substrate, the substrate having a second surface opposite to the first surface; forming a first conductive pattern in a first metal layer above the first surface of the substrate, the first conductive pattern electrically connecting a first source / drain of the first transistor to a second source / drain of the second transistor; and forming a second conductive pattern in a second metal layer below the second surface of the substrate, the second conductive pattern electrically connecting the first source / drain of the first transistor to the second source / drain of the second transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1A is a schematic IC layout diagram of an IC device according to some embodiments;

[0008] Figure 1B is a schematic cross-sectional view of a part of an IC device according to some embodiments;

[0009] Figure 1C is a schematic circuit diagram of a circuit in an IC device according to some embodiments;

[0010] Figures 2A - 2C is a schematic circuit diagram of a circuit in an IC device according to some embodiments;

[0011] Figure 3 is a schematic IC layout diagram of an IC device according to some embodiments;

[0012] Figures 4A - 4F is various schematic perspective views of an IC device in various layers according to some embodiments;

[0013] Figure 5 is a schematic perspective view of an IC device according to some embodiments;

[0014] Figures 6A - 6B is a schematic cross-sectional view of an IC device being manufactured at various stages of a manufacturing process according to some embodiments;

[0015] Figure 7 is a flowchart of a method according to some embodiments;

[0016] Figure 8 is a flowchart of a method of forming or manufacturing an integrated circuit according to some embodiments;

[0017] Figure 9 is a flowchart of a method for generating a layout design of an integrated circuit according to some embodiments;

[0018] Figure 10 is a block diagram of an EDA system according to some embodiments;

[0019] Figure 11 is a block diagram of an IC manufacturing system and an IC manufacturing process related thereto according to some embodiments. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first component and the second component are in direct contact, and may also include embodiments where additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. Additionally, the present invention may repeat reference numerals and / or letters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or structures discussed.

[0021] Moreover, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to easily describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientation shown in the figures, the spatially relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0022] Internal and parasitic parameters, such as resistance and capacitance, exist in and / or between various circuit elements and / or connections of an IC device. Under some operating conditions, such resistance and capacitance may affect the performance of the IC device. In some embodiments, various portions of the active region in the IC device are electrically connected to each other on both the front and back sides of the IC device. As a result, in one or more embodiments, the resistance of the connection between the electrically connected portions of the active region is reduced. In some embodiments, the gate between the electrically connected portions of the active region is a dummy gate that does not include a conductive material and / or is filled with a dielectric material. As a result, in one or more embodiments, the parasitic capacitance near the dummy gate is reduced. In at least one embodiment, at the reduced connection resistance and parasitic capacitance, it is possible to achieve an improved unity gain frequency in analog applications such as serializer / deserializer (SERDES) devices. Other applications and / or devices are within the scope of the various embodiments.

[0023] Figure 1A FIG. 100A is a schematic IC layout diagram (also referred to as a "layout design") of an IC device according to some embodiments. In at least one embodiment, the IC layout diagram 100A is stored on a non-transitory computer-readable medium.

[0024] The IC layout diagram 100A includes at least one active region, such as the active region OD1. The active region is sometimes referred to as an oxide-defined (OD) region and is schematically shown in the drawings with the label "OD". In some embodiments, the active region of the IC layout diagram 100A can be used to fabricate the corresponding active region OD1' of a transistor of one or more circuit elements or devices. In Figure 1AIn an exemplary configuration, the active region OD1 extends or elongates along a first axis or the X-axis. In the IC device 100B corresponding to the IC layout diagram 100A, the active region OD1 is configured to include P-type dopants or N-type dopants to form one or more circuit elements or devices. Examples of circuit elements include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, P-channel metal-oxide-semiconductor (PMOS), N-channel metal-oxide-semiconductor (NMOS), bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, P-channel and / or N-channel field-effect transistors (PFET / NFET), FinFETs, planar MOS transistors with raised source / drain, nanosheet FETs, nanowire FETs, etc. In some embodiments, the active region OD1 can be used to fabricate the source or drain of a transistor device. In some embodiments, the active region OD1 can be used to fabricate the anode or cathode of a diode device. The active region configured to form one or more PMOS devices is sometimes referred to as a "PMOS active region", while the active region configured to form one or more NMOS devices is sometimes referred to as an "NMOS active region". In connection with Figure 1A the exemplary configuration described, the active region OD1 includes an NMOS active region. Other configurations are within the scope of various embodiments.

[0025] The IC layout diagram 100A further includes a plurality of gate regions A, B, C, D, P1 extending over the active region OD1. The gate regions A, B, C, D, P1 are arranged side by side along the X-axis and extend or elongate along a second axis, i.e., the Y-axis transverse to the X-axis. In the IC device 100B corresponding to the IC layout diagram 100A, the gate regions A, B, C, D, also referred to as the gate regions of the functional transistors, can be used to form corresponding conductive gates including conductive materials. In some embodiments, the gate includes polysilicon. Polysilicon is sometimes referred to as "polycrystalline silicon", and the gate regions A, B, C, D are schematically shown in the drawings with the label "PO". Other conductive materials for the conductive gates, such as metals, are within the scope of various embodiments. The gate region P1 is a dummy gate region and is shown in the drawings with the label "dummy gate". In some embodiments, the dummy gate is the gate region of a dummy transistor. In some embodiments, the dummy transistor is a non-functional transistor. In the IC device 100B corresponding to the IC layout diagram 100A, the dummy gate region P1 corresponds to a dummy gate that does not include conductive materials and / or is filled with a dielectric material. In at least one embodiment, the dummy gate region P1 is a continuous polysilicon on oxide defined edge (CPODE) pattern or a polysilicon on oxide defined edge (PODE) pattern and corresponds to a dummy structure as described in U.S. Patent No. 10,157,856, the entire content of which is incorporated herein by reference. In Figure 1A an exemplary configuration, the gate regions A, B, C, D, P1 are arranged along the X-axis at a constant pitch specified by CPP (contact polysilicon pitch). The pitch CPP is the center-to-center distance along the X-axis between the centerlines of two adjacent gate regions (e.g., the gate regions A, B as shown in Figure 1A ). Two gate regions are adjacent along the X-axis when there are no other gate regions between the two gate regions and / or when the center-to-center distance along the X-axis between the two gate regions is CPP.

[0026] The gate regions A, B, C, D together with the active region OD1 constitute a plurality of transistors. For example, the gate region A, the source / drain region 101 in the active region OD1, and another source / drain region 102 in the active region OD1 together constitute a first transistor (not labeled). The gate region B, the source / drain region 102 in the active region OD1, and another source / drain region 103 in the active region OD1 together constitute a second transistor (not labeled), e.g., a transistor corresponding to the transistor T1 described with respect to Figures 1B - 1C . The first transistor having the gate region A and the second transistor having the gate region B share a common source / drain region 102. The gate region C, the source / drain region 104 in the active region OD1, and another source / drain region 105 in the active region OD1 together constitute a third transistor (not labeled), e.g., a transistor corresponding to the transistor described with respect to Figures 1B - 1CThe transistor of transistor T2 described. The gate region D, the source / drain region 105 in the active region OD1, and another source / drain region 106 in the active region OD1 together constitute a fourth transistor (not labeled). The third transistor with gate region C and the fourth transistor with gate region D share the common source / drain region 105. In some embodiments, the transistors with gate regions A, B, C, D are NMOS transistors with n-type active regions. Other configurations are within the scope of various embodiments. In some embodiments, the transistors with gate regions A, B, C, D are PMOS transistors with p-type active regions.

[0027] IC layout diagram 100A also includes contact regions MD1, MD2, MD3, MD4 located above corresponding portions of the active region OD1. In the IC device 100B corresponding to the IC layout diagram 100A, the contact regions can be used to form corresponding contact structures, which include conductive materials formed above the corresponding portions of the active region to define electrical connections from one or more devices formed in the active region to other internal circuits of the IC device or to external circuits. Exemplary conductive materials for the contact structures include metals. In some embodiments, the conductive materials or metals throughout this disclosure include copper, aluminum, titanium, nickel, tungsten, or other suitable conductive materials. Other configurations, materials, or layers are within the scope of various embodiments. The contact regions are schematically shown in the drawings with the label "MD" (metal in diffusion). In Figure 1A an exemplary configuration, IC layout diagram 100A includes contact regions MD1, MD2, MD3, MD4. Contact region MD1 is located above source / drain region 103, contact region MD2 is located above source / drain region 104, contact region MD3 is located above source / drain region 102, and contact region MD4 is located above source / drain region 105. Contact regions MD1, MD2, MD3, MD4 extend or elongate along the Y axis and are alternately arranged with gate regions A, B, C, D, P1 along the X axis. In Figure 1AIn an exemplary configuration, the contact pitch (not shown) between adjacent contact regions, i.e., the center-to-center distance along the X-axis between the centerlines of two adjacent contact regions, is the same as the CPP pitch between adjacent gate regions. When there are no other contact regions between two contact regions, and / or when the center-to-center distance along the X-axis between two contact regions is CPP, the two contact regions are adjacent along the X-axis. Along the X-axis, contact region MD1 is located between gate regions B and P1 and is adjacent to gate regions B and P1; contact region MD2 is located between gate regions C and P1 and is adjacent to gate regions C and P1; contact region MD3 is located between gate regions A and B and is adjacent to gate regions A and B; and contact region MD4 is located between gate regions C and D and is adjacent to gate regions C and D. When there are no other contact regions or gate regions between a contact region and a gate region, and / or when the center-to-center distance along the X-axis between the contact region and the gate region is CPP / 2, the contact region and the gate region are adjacent to each other.

[0028] IC layout diagram 100A also includes a plurality of vias VD1 to VD8 located above the contact regions and gate regions. In IC device 100B corresponding to IC layout diagram 100A, the vias can be used to form corresponding conductive via structures located above and in electrical contact with the corresponding gate and contact structures. Exemplary materials for the via structures include metals. Other configurations, materials, or layers are within the scope of various embodiments. The vias include via diffusion (VD) vias and via gate (VG) vias. For simplicity, both VD and VG vias are schematically shown with the label "VD" in the drawings. In Figure 1A an exemplary configuration, IC layout diagram 100A includes vias VD1 to VD4 located above corresponding contact regions MD1, MD2, MD3, MD4. In some embodiments, vias VD1 to VD4 are located in the VD layer of layout diagram 100A. In Figure 1A an exemplary configuration, IC layout diagram 100A also includes vias VD5 to VD8 located above corresponding gate regions A, B, C, D. In some embodiments, vias VD5 to VD8 are located in the VG layer of layout diagram 100A. In some embodiments, vias VD1 to VD8 belong to the same via layer, which is the lowest via layer above active region OD1 or the via layer closest to active region OD1. In some embodiments, one or more of vias VD1 to VD8 are located on other layers of layout design 100A or the corresponding IC device.

[0029] The IC layout diagram 100A further includes vias located below the active region OD1 and also below the corresponding contact regions. In the IC device 100B corresponding to the IC layout diagram 100A, as described herein, the vias can be used to fabricate corresponding conductive via structures that extend through the substrate of the IC device. Exemplary materials for the via structures include metals. Other configurations, materials, or layers are within the scope of various embodiments. The vias are sometimes referred to as back vias and are schematically shown in the figures with the label "VB". In Figure 1A an exemplary configuration, the IC layout diagram 100A includes a via VB1 located below the corresponding contact region MD1 and a via VB2 located below the corresponding contact region MD2. The vias VB1, VB2 extend or elongate along the Y-axis. The described elongated shape of the vias VB1, VB2 is an example, and other configurations are within the scope of various embodiments. In some embodiments, one or more of the vias VB1 to VB2 are located on other layers of the layout design 100A or the corresponding IC device.

[0030] In Figure 1A an exemplary configuration, at least one of the contact regions MD1, MD2 has a length or height along the Y-axis that is less than the length or height of the corresponding vias VB1, VB2 along the Y-axis. For example, as Figure 1A shown, the contact region MD1 has a length h MD along the Y-axis that is less than the length h VB of the corresponding via VB1 along the Y-axis. When the contact regions MD1, MD2 and the corresponding vias VB1, VB2 have the same width along the X-axis, since the length h MD along the Y-axis is less than the length h VB of the corresponding via VB1 along the Y-axis, the area of the contact regions MD1, MD2 is less than the area of the corresponding vias VB1, VB2. In at least one embodiment, the larger area of the vias VB1, VB2 compared to the corresponding contact regions MD1, MD2 results in a lower resistance for the vias VB1, VB2, which improves the performance as described herein. Other arrangements for configuring the area of the vias VB1, VB2 to be greater than the area of the corresponding contact regions MD1, MD2, and / or other arrangements for configuring the resistance of the vias VB1, VB2 to be less than the resistance of the corresponding contact regions MD1, MD2, are within the scope of various embodiments.

[0031] The IC layout diagram 100A further includes a first conductive pattern in the first metal layer above the vias VD1 to VD8. In the IC device 100B corresponding to the IC layout diagram 100A, the first conductive pattern can be used to fabricate a corresponding first conductive structure that is above and in electrical contact with the corresponding vias VD1 - VD8 of the IC device as described herein. Exemplary materials for the first conductive structure include metals. In Figure 1A the exemplary configuration, the first metal layer is the metal zero (M0) layer, which is the lowest metal layer above the active region OD1. In some embodiments, the M0 layer is located among other metal layers. The M0 layer is schematically shown in the drawings with the label "M0" and includes conductive patterns M01, M02, M03. The conductive pattern M01 is above the vias VD1, VD2. The conductive pattern M02 is above the vias VD3, VD4. The conductive pattern M03 is above the vias VD5, VD6, VD7, VD8. The conductive patterns M01, M02, M03 extend or elongate along the X-axis. Other numbers of metal traces in the conductive patterns are within the scope of the present invention.

[0032] The IC layout diagram 100A further includes a second conductive pattern in the second metal layer below the through vias VB1, VB2. In the IC device 100B corresponding to the IC layout diagram 100A, the second conductive pattern can be used to fabricate a corresponding second conductive structure that is below and in electrical contact with the corresponding vias VB1 - VB2 of the IC device as described herein. Exemplary materials for the second conductive structure include metals. In Figure 1A the exemplary configuration, the second metal layer is the back metal zero (BM0) layer, which is the topmost metal layer below the active region OD1. In some embodiments, the BM0 layer is located among other metal layers. The BM0 layer is schematically shown in the drawings with the label "BM0" and includes a conductive pattern BM01 below the through vias VB1, VB2. The conductive pattern BM01 extends or elongates along the X-axis.

[0033] In Figure 1A the exemplary configuration, at least one of the conductive patterns M01, M02, M03 has a width along the Y-axis that is less than the width of the conductive pattern BM01 along the Y-axis. For example, as Figure 1A shown, the width w M0 of the conductive pattern M01 along the Y-axis is less than the width w BM0 of the conductive pattern BM01 along the Y-axis. Also as Figure 1A shown, the length of the conductive pattern M01 along the X-axis ( Figure 1AThe one without a number (not numbered) is also smaller than the length of the conductive pattern BM01. As a result, the area of the conductive pattern M01 is smaller than the area of the conductive pattern BM01. In at least one embodiment, compared with the conductive pattern M01, the larger area of the conductive pattern BM01 results in a smaller resistance of the conductive pattern BM01, which improves the performance as described herein. Other arrangements for configuring the area of the conductive pattern BM01 to be larger than the area of the conductive pattern M01, and / or other arrangements for configuring the resistance of the conductive pattern BM01 to be smaller than the resistance of the conductive pattern M01, are within the scope of various embodiments.

[0034] In the IC layout diagram 100A, the first conductive pattern M01, the via VD1, the contact region MD1, the through via VB1, and the second conductive pattern BM01 overlap each other. Additionally, the first conductive pattern M01, the via VD2, the contact region MD2, the through via VB2, and the second conductive pattern BM01 overlap each other. In the IC device 100B corresponding to the IC layout diagram 100A, the described arrangement corresponds to the electrical connection between the source / drain regions 103 and 104 above both the front and back sides of the described IC device. Figure 1B The electrical connection between the source / drain regions 103 and 104 above both the front and back sides of the described IC device.

[0035] Figure 1B is a schematic cross-sectional view of a part of the IC device 100B. In at least one embodiment, Figure 1B The cross-sectional view in Figure 1A is taken along the line I-I' in Figure 1B and the part of the IC device 100B in Figure 1A corresponds to the part of the IC layout diagram 100A located between the source / drain region 102 and the source / drain region 105. The corresponding elements of the IC layout diagram 100A and the IC device 100B are denoted by similar reference numerals. Specifically, Figure 1B the gate regions A, B, C, D, P1 in Figure 1A correspond to the gates GA, GB, GC, GD, GP1 in Figure 1B and the source / drain regions 102, 103, 104, 105 in Figure 1A correspond to the source / drains 112, 113, 114, 115 in Figure 1B The other components in Figure 1A with corresponding components are denoted by the same reference numerals in Figure 1A with an added underscore (“_”) symbol. For example, Figure 1B the contact region MD1 in

[0036] In some embodiments, the layout diagram 100A can be used to fabricate the IC device 100B. The IC device 100B includes a substrate 120 having a first surface 121 and a second surface 122 that face each other along the Z-axis, where the Z-axis is aligned with the thickness direction of the substrate 120. In at least one embodiment, the first surface 121 is referred to as the "upper surface" or "front surface" or "device surface", while the second surface 122 is referred to as the "lower surface" or "back surface". In some embodiments, the substrate 120 is a semiconductor substrate or a dielectric substrate. Exemplary materials for the semiconductor substrate include, but are not limited to, silicon, silicon germanium (SiGe), gallium arsenide, or other suitable semiconductor materials. Exemplary materials for the dielectric substrate include, but are not limited to, SiO or other suitable dielectric materials. In some embodiments, N-type and P-type dopants are added to the doped regions of the substrate 120 and / or the isolation structures formed between adjacent doped regions. For simplicity, Figure 1B some components such as doped regions and / or isolation structures are omitted.

[0037] The IC device 100B includes an active region located above the first surface of the substrate, and the active region includes a first part and a second part, both of which are electrically connected to a first conductive pattern located above the active region and a second conductive pattern located below the second surface of the substrate. For example, as Figure 1B shown, the IC device 100B includes an active region OD_1 corresponding to Figure 1A the active region OD1 in, and the active region OD_1 includes portions 112 - 115 on the first surface 121 of the substrate 120. In the portions 112 - 115 of the active region OD_1, the first part 113 and the second part 114 are electrically connected to a first conductive pattern M0_1 located above the active region, and a second conductive pattern BM0_1 located below the second surface 122 of the substrate 120. The first part 113 is the source / drain of a transistor having a gate GB (e.g., the transistor corresponding to transistor T1 as described with respect to Figure 1C ). The second part 114 is the source / drain of another transistor having a gate GC (e.g., the transistor corresponding to transistor T2 as described with respect to Figure 1C ). The source / drain regions are schematically shown by the label "S / D" in the drawings. Other configurations where at least one of the first part 113 or the second part 114 of the active region is not configured as the source / drain of a transistor are within the scope of various embodiments.

[0038] Along the Z-axis, the source / drain 113 has opposing upper surface 131 and lower surface 132, while the source / drain 114 has opposing upper surface 141 and lower surface 142. The source / drain 113 is electrically connected to the contact structure MD_1 at the upper surface 131, and the contact structure MD_1 is in turn electrically connected to the conductive pattern M0_1 through the via structure VD_1. The source / drain 114 is electrically connected to the contact structure MD_2 at the upper surface 141, and the contact structure MD_2 is in turn electrically connected to the conductive pattern M0_1 through the via structure VD_2. As a result, the source / drain 113 and the source / drain 114 are electrically connected to each other through the conductive pattern M0_1 on the front side (e.g., the first side 121 of the substrate 120). In at least one embodiment, at least one of the upper surface 131 of the source / drain 113 or the upper surface 141 of the source / drain 114 is in direct contact with the corresponding contact structures MD_1, MD_2.

[0039] The source / drain 113 is also electrically connected to the conductive pattern BM0_1 through the through-via structure VB_1 at the lower surface 132. The source / drain 114 is also electrically connected to the conductive pattern BM0_1 through the through-via structure VB_2 at the lower surface 142. Each of the through-via structures VB_1, VB_2 extends along the thickness direction of the substrate 120 (i.e., along the Z-axis), from the second side 122 where the through-via structures VB_1, VB_2 are in electrical contact with the conductive pattern BM0_1, through the substrate 120, to the first side 121 in electrical contact with the corresponding lower surfaces 132, 142. As a result, the source / drain 113 and the source / drain 114 are electrically connected to each other through the conductive pattern BM0_1 on the back side (e.g., the second side 122 of the substrate 120). In at least one embodiment, at least one of the lower surface 132 of the source / drain 113 or the lower surface 142 of the source / drain 114 is in direct contact with the corresponding through-via structures VB_1, VB_2. In at least one embodiment, the described electrical connections between the source / drain 113 and the source / drain 114 on both the front and back sides result in a reduced connection resistance and improved performance, as described with respect to Figure 1C described.

[0040] In Figure 1BIn an exemplary configuration, the IC device 100B includes transistors or devices according to nanosheet FET technology. Other transistor or device technologies, such as planar transistor technology, FINFET technology, nanowire FET technology, etc., are within the scope of various embodiments. According to nanosheet FET technology, the gate GB includes a conductive gate stack 151 extending upward along the Z-axis from the first surface 121 of the substrate 120. A plurality of channels 152 extend along the X-axis through the conductive gate stack 151 and connect to corresponding source / drain 112, 113. The channels 152 are arranged one on top of the other along the Z-axis. A gate dielectric or gate oxide (not shown) is formed between the channels 152 and the conductive gate stack 151. A plurality of internal spacers 153 are arranged alternately with the channels 152 along the Z-axis. A top spacer 154 is arranged above the topmost channel 152 and surrounds the topmost of the conductive gate stack 151. In some embodiments, the source / drain 112, 113 are epitaxially grown above the first surface 121 of the substrate 120 on opposite sides of the gate structure including the conductive gate stack 151 and the channels 152. The conductive gate stack 151 and the corresponding source / drain 112, 113 together constitute the transistor T1. A via structure (not shown and corresponding to Figure 1A in VD6) electrically connects the topmost of the conductive gate stack 151 to a conductive pattern (not shown and corresponding to Figure 1A in M03) in the M0 layer. Another via structure (not shown and corresponding to Figure 1A in VD3) electrically connects the source / drain 112 to a conductive pattern (not shown and corresponding to Figure 1A in M02) in the M0 layer. Another via structure (not shown and corresponding to Figure 1A in VD5) electrically connects the topmost of the conductive gate stack (not shown and corresponding to Figure 1A in gate A) to a conductive pattern (not shown and corresponding to Figure 1A in M03) in the M0 layer. Exemplary materials for the conductive gate stack 151 include, but are not limited to, polysilicon, metal, Al, AlTi, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, MoN, and / or other suitable conductive materials. Exemplary materials for the channels 152 include, but are not limited to, silicon, silicon germanium, gallium arsenide, or other suitable semiconductor materials. Exemplary materials for the spacers 153, 154 include, but are not limited to, silicon nitride, oxynitride, silicon carbide, and other suitable materials. Exemplary materials for the gate dielectric include, but are not limited to, silicon oxide, silicon nitride, or high-k dielectric materials. Exemplary high-k dielectric materials include, but are not limited to, HfO2, HfSiO, HfSiON, HfTiO, HfTaO, HfZrO, titanium oxide, aluminum oxide, and zirconium oxide.

[0041] The gate GC includes a conductive gate stack 155 having a configuration similar to that of the conductive gate stack 151. The channel and spacers associated with the gate GC have configurations similar to the channel 152 and spacers 153, 154 described with respect to the gate GB, and the similar description is omitted. The conductive gate stack 155 and the corresponding source / drain 114, 115 together constitute the transistor T2.

[0042] The channel and spacers associated with the dummy gate GP1 have configurations similar to the channel 152 and spacers 153, 154 described with respect to the gate GB. However, the conductive material is removed from the gate stack 156 of the dummy gate GP1. In other words, the gate stack 156 does not contain conductive material. In one or more embodiments, the gate stack 156 is an empty space. In at least one embodiment, the gate stack 156 is filled with a dielectric material such as silicon oxide or other suitable dielectric material. In at least one embodiment, the absence of conductive material in the dummy gate GP1 can reduce the parasitic capacitance between the gates GB and GC, thereby having improved performance.

[0043] Although in Figure 1BAlthough not shown in the figure, the IC device 100B further includes a dielectric layer located between the M0 layer (such as the conductive pattern M0_1) and the active region (such as the source / drain 112-115). In at least one embodiment, the IC device 100B includes one or more additional via layers, dielectric layers, and metal layers (not shown) located above the M0 layer to form interconnections between the circuit elements of the IC device 100B and / or form electrical connections to external circuits. The via layers and metal layers from the M0 layer and above are sometimes referred to as front via layers and metal layers. The BM0 layer (such as the conductive pattern BM0_1) is located below the second surface 122 of the substrate 120. In at least one embodiment, the BM0 layer is in direct contact with the second surface 122 of the substrate 120, and / or the conductive pattern BM0_1 is in direct contact with the through-via structures VB_1, VB_2. In at least one embodiment, the IC device 100B includes one or more additional via layers, dielectric layers, and metal layers (not shown) located below the BM0 layer to form interconnections between the circuit elements of the IC device 100B and / or form electrical connections to external circuits. The via layers and metal layers from the BM0 layer and below are sometimes referred to as back via layers and metal layers. In at least one embodiment, the BM0 layer or one or more other metal layers (not shown) located below the BM0 layer include one or more power voltage rails for providing one or more power supply voltages to the circuit elements of the IC device 100B. For example, in at least one embodiment, the conductive pattern BM0_1 includes a power voltage rail for providing a positive power supply voltage VDD or a ground voltage VSS. In some embodiments, the conductive pattern BM0_1 includes a signal conductive pattern for data (rather than for providing a power supply voltage).

[0044] Figure 1C is a schematic circuit diagram of a circuit 100C in an IC device according to some embodiments. In at least one embodiment, the circuit 100C includes Figure 1B an equivalent circuit of a portion of the IC device 100B in. The corresponding elements of the circuit 100C and the IC device 100B are denoted by the same reference numerals.

[0045] The circuit 100C includes transistors T1 and T2, which are electrically connected to each other through a conductive pattern M0_1 on the front side (e.g., the first side 121 of the substrate 120) and a conductive pattern BM0_1 on the back side (e.g., the second side 122 of the substrate 120). Transistor T1 includes a gate GB, source / drain 112, and source / drain 113. Transistor T2 includes a gate GC, source / drain 114, and source / drain 115. Resistor R1 corresponds to the intrinsic resistance of a part of source / drain 113 between the contact structure MD_1 and the gate GB. Resistor R2 corresponds to the intrinsic resistance of another part of source / drain 113 between the contact structure MD_1 and the dummy gate P1. Resistors RVD_1, RMD_1, and RVB_1 are the corresponding intrinsic resistances of the via structure VD_1, the contact structure MD_1, and the through-via structure VB_1. Resistor R4 corresponds to the intrinsic resistance of a part of source / drain 114 between the contact structure MD_2 and the gate GC. Resistor R3 corresponds to the intrinsic resistance of another part of source / drain 114 between the contact structure MD_2 and the dummy gate P1. Resistors RVD_2, RMD_2, and RVB_2 are the corresponding intrinsic resistances of the via structure VD_2, the contact structure MD_2, and the through-via structure VB_2.

[0046] Capacitor C1 corresponds to the parasitic capacitance between the gate GB and the contact structure MD_1. Capacitor C2 corresponds to the parasitic capacitance between the dummy gate P1 and the contact structure MD_1. Capacitor C3 corresponds to the parasitic capacitance between the dummy gate P1 and the contact structure MD_2. Capacitor C4 corresponds to the parasitic capacitance between the gate GC and the contact structure MD_2. Region 156 in the circuit 100C corresponds to the gate stack 156 of the dummy gate P1. Since the gate stack 156 does not contain a conductive material and / or is filled with a dielectric material, the region 156 in the circuit 100C does not have associated electrical characteristics such as resistance or capacitance.

[0047] As Figure 1CAs shown, the source / drain 113 of transistor T1 and the source / drain 114 of transistor T2 are electrically connected to each other on both the front and back sides. On the front side, the source / drain 113 is electrically connected to the source / drain 114 through a first or front connection 161 including resistors RMD_1, RVD_1, RVD_2, RMD_2, and conductive pattern M0_1. On the back side, the source / drain 113 is electrically connected to the source / drain 114 through a second or back connection 162 including resistors RVB_1, RVB_2, and conductive pattern BM0_1. As a result, the source / drain 113 and the source / drain 114 are electrically connected through two parallel connections, namely the front connection 161 and the back connection 162. Therefore, compared with the case where the source / drain 113 and the source / drain 114 are electrically connected through one connection (e.g., through the front connection 161), the resulting connection resistance between the source / drain 113 and the source / drain 114 of transistors T1 and T2 becomes lower. In at least one embodiment, when the resistance of the front connection 161 is approximately the same as the resistance of the back connection 162, the resulting connection resistance between the source / drain 113 and the source / drain 114 is approximately half of the resistance of the front connection 161. In at least one embodiment, when the resistance of the back connection 162 is less than the resistance of the front connection 161, the resulting connection resistance between the source / drain 113 and the source / drain 114 is less than half of the resistance of the front connection 161. As described with respect to Figure 1A as described, there are several configurations for reducing the resistance of the back connection 162 compared to the front connection 161. In an exemplary configuration, the vias VB_1, VB_2 have a greater length or height along the Y-axis than the corresponding contact structures MD_1, MD_2. In another exemplary configuration, the conductive pattern BM0_1 has a greater width along the Y-axis than the corresponding conductive pattern M0_1. In yet another exemplary configuration, the material used for the vias VB_1, VB_2 has a higher conductivity than the material used for the corresponding contact structures MD_1, MD_2. In yet another exemplary configuration, the material used for the conductive pattern BM0_1 has a higher conductivity than the material used for the corresponding conductive pattern M0_1. Other configurations for providing a back connection 162 with a lower resistance than the front connection 161 are within the scope of various embodiments.

[0048] In Figures 1A - 1C the exemplary configuration, the source / drains 113, 114 that are electrically connected on both the front and back sides are adjacent to the source / drain. Other configurations where the source / drains that are electrically connected on both the front and back sides are not adjacent to the source / drain are within the scope of various embodiments.

[0049] In Figures 1A - 1CIn an exemplary configuration, source / drain electrodes 113 and 114 that are electrically connected on both the front and back sides are adjacent to the dummy gate P1. Other configurations in which at least one of the source / drain electrodes that are electrically connected on both the front and back sides is not adjacent to the dummy gate are within the scope of various embodiments.

[0050] In Figures 1A - 1C an exemplary configuration, source / drain electrodes 113 and 114 that are electrically connected on both the front and back sides are electrically connected through corresponding conductive patterns in the M0 layer and the BM0 layer. Other configurations in which at least one of the front connection 161 or the back connection 162 includes a conductive pattern in a front metal layer other than the M0 layer or a conductive pattern in a back metal layer other than the BM0 layer are within the scope of various embodiments.

[0051] In some embodiments, as the resulting connection resistance between the source / drain electrodes connected on both the front and back sides is reduced, the corresponding transconductance (Gm) of the IC device is improved, and in particular, the related performance improvement in high-frequency applications. In at least one embodiment, this effect can be achieved without increasing the pitch between the gate regions. This is contrary to other methods. According to other methods, in order to increase the Gm in high-frequency applications, the intrinsic resistance and / or capacitance on the wiring should be reduced by using wider wiring, which in turn leads to an increase in the gap or pitch between adjacent components to accommodate the wider wiring. The increased pitch reduces the device density and / or increases the chip area. This undesirable consequence can be avoided in at least one embodiment while still achieving an increased Gm and / or improved performance.

[0052] In some embodiments, increased Gm and / or improved performance can be obtained without complex changes to the IC layout. In at least one embodiment, such an effect can be achieved without additional masks in the manufacturing process. The reason is that it is possible to form the front-side connection 161 and / or the back-side connection 162 together with other contact structures, via structures, through-via structures, and metal layers of the IC device without additional masks. For example, in at least one embodiment, the BM0 layer and / or other back-side metal layers located below the BM0 layer include a back-side power supply voltage rail, i.e., a power supply voltage rail on the back side 122 of the substrate 120. Additional through-via structures (not shown) are also formed through the substrate 120 to supply power from the back-side power supply voltage rail to devices or circuit elements on the front side 121 of the substrate 120. In some embodiments, it is possible to form the BM0_1 conductive pattern for electrically connecting the source / drain 113, 114 to the back-side power supply voltage rail without additional masks. It is also possible to form the through-via structures VB_1, VB_2 together with additional through-via structures for power supply without additional masks. Since no additional masks are required in some embodiments, the manufacturing time, cost, or complexity is not significantly increased, while improved performance can still be achieved.

[0053] Figure 2A is a schematic circuit diagram of a circuit 200A in an IC device according to some embodiments. In some embodiments, the circuit 200A incorporates aspects of the IC device 100B or the circuit 100C.

[0054] In Figure 2A the exemplary configuration, the circuit 200A is a differential amplifier that includes a differential transistor pair Mn1, Mn2, load resistors R21, R22, and a current source in the form of a transistor Ms. The resistor R21 is electrically connected between VDD and at least one output node Vo.

[0055] The transistor Mnl has a source / drain electrically connected to at least the output node Vo, another source / drain electrically connected to at least the node Vx, and a gate electrically connected to the input node Vi.

[0056] The resistor R22 is electrically connected between VDD and at least one differential output node between. The transistor Mn2 has a source / drain electrically connected to at least the differential output node and another source / drain electrically connected to at least the node Vx, and a gate electrically connected to the differential input node and. The transistor Ms is electrically connected between the node Vx and the ground voltage VSS. The transistor Ms has a gate, electrically connected to at least the node a source / drain, and another source / drain electrically connected to a ground voltage VSS. In some embodiments, the source / drain of transistor Ms, the node each of the other source / drain of transistor Mn1, and the other source / drain of transistor Mn2 are electrically connected together.

[0057] Transistors Mn1, Mn2 have corresponding source / drains electrically connected to each other at node Vx. In some embodiments, circuit 200A incorporates aspects of IC device 100B or circuit 100C. For example, in some embodiments, transistors Mn1, Mn2 correspond to transistors T1, T2, and the connection between the source / drains of transistors Mn1, Mn2 corresponds to Figure 1C the connections 161, 162 between transistors T1, T2 in Figures 1A - 1C as described. In some embodiments, the source / drains of transistors Mn1, Mn2 are electrically connected on both the front and back sides of the IC device, for example, as described with respect to

[0058] Figure 2B and Figure 2C are schematic circuit diagrams of circuits 200B and 200C in an IC device according to some embodiments. In some embodiments, circuits 200A - 200B incorporate aspects of IC device 100B or circuit 100C.

[0059] In Figures 2B - 2C 's exemplary configuration, circuit 200B is a daisy chain arrangement of NMOS transistors, and circuit 200C is a corresponding daisy chain arrangement of PMOS transistors. In at least one embodiment, circuits 200B and 200C are part of a SERDES device. Circuit 200B includes NMOS transistors 206N(0), 206N(1), 206N(2), 206N(M - 2), and 206N(M - 1), and gate electrodes 208N(0), 208N(1), 208N(2), 208N(M - 2), and 208N(M - 1), where M is a positive integer. NMOS transistors 206N(0), 206N(1), 206N(2), 206N(M - 2), and 206N(M - 1) are electrically connected in a daisy chain, as Figure 2B shown.

[0060] The circuit 200C includes PMOS transistors 206P(0), 206P(1), 206P(2), 206P(M-2), and 206P(M-1), and gate electrodes 208P(0), 208P(1), 208P(2), 208P(M-2), and 208P(M-1). The PMOS transistors 206P(0), 206P(1), 206P(2), 206P(M-2), and 206P(M-1) are electrically connected in a daisy chain, as Figure 2C shown.

[0061] In circuits 200B and 200C, adjacent NMOS or PMOS transistors have source / drains that are electrically connected to each other and corresponding source / drains. In some embodiments, at least one of circuits 200B and 200C incorporates aspects of IC device 100B or circuit 100C. For example, in some embodiments, Figures 2B - 2C the adjacent NMOS or PMOS transistors correspond to transistors T1 and T2, and Figures 2B - 2C the connection between the source / drains of the adjacent NMOS or PMOS transistors corresponds to Figure 1C the connections 161 and 162 between transistors T1 and T2 in Figure 1C . In some embodiments, the source / drain connections between non-adjacent NMOS transistors (e.g., NMOS transistors 206N(0) and 206N(M-1)) or non-adjacent PMOS transistors (e.g., PMOS transistors 206P(0) and 206P(M-1)) are combined with (some of) the connections between the source / drains of adjacent NMOS or PMOS transistors and correspond to Figure 1C the connections 161 and 162 between transistors T1 and T2 in Figure 1C . In other words, in some embodiments, Figure 1C the connection 161 or 162 in

[0062] In some embodiments, Figures 2B - 2C the corresponding source / drains of at least one pair of adjacent NMOS or PMOS transistors are electrically connected on both the front and back sides of the IC device, e.g., as described with respect to Figures 1A - 1C . In some embodiments, the corresponding source / drains of each pair of adjacent NMOS or PMOS transistors are electrically connected on both the front and back sides of the IC device, e.g., as described with respect to Figures 1A - 1CAs described. In at least one embodiment, one or more advantages of the IC devices 100B - 100C described herein can be realized in a SERDES device including circuits 200B, 200C. In at least one embodiment, the SERDES device includes circuits 200B, 200C having a high Gm and also achieves a high unity gain frequency. Other circuit types or devices are within the scope of the present invention.

[0063] Figure 3 is a schematic IC layout diagram 300 of an IC device according to some embodiments.

[0064] The IC layout diagram 300 includes a region 301 corresponding to Figure 1A the IC layout diagram 100A in []. Compared with the IC layout diagram 100A, the IC layout diagram 300 further includes another active region OD2, gate regions E, F, and dummy gate regions P2 - P6. The gate regions E, F correspond to the gates for forming functional transistors. The dummy gate regions P2 - P6 correspond to dummy gates that do not include conductive materials and / or are filled with dielectric materials in at least one embodiment. In at least one embodiment, each of the gate regions E, F corresponds to two separated gate portions respectively located above the active region OD1 and the active region OD2, for example, as described with respect to Figures 4A - 4F as described.

[0065] The active region OD2 is spaced apart from the active region OD1 along the Y - axis. In at least one embodiment, the active region OD2 corresponds to a dopant type different from that of the active region OD1. For example, the active region OD1 is configured as an NMOS active region for forming an NMOS transistor, while the active region OD2 is configured as a PMOS active region for forming a PMOS transistor, and vice versa. In at least one embodiment, the NMOS transistors in the active region OD1 correspond to various NMOS transistors in the daisy - chain arrangement of the NMOS transistors of the circuit 200B, and the PMOS transistors in the active region OD2 correspond to various PMOS transistors in the daisy - chain arrangement of the PMOS transistors of the circuit 200C. In other words, in one or more embodiments, the IC layout diagram 300 includes the layout of the NMOS and PMOS daisy - chain arrangements in the SERDES device.

[0066] Above the active region OD1, the configuration and / or connection of various elements between the gate regions E and A are similar to the configuration and / or connection between the gate regions B and C described herein, and the similar detailed description is omitted. For example, the source / drain region adjacent to the gate region E is configured to be electrically connected to the source / drain region adjacent to the gate region A on both the front and back sides. The connection on the front side includes corresponding MD contact regions (not numbered), VD vias (not numbered), and a conductive pattern M01. The connection on the back side includes corresponding through vias VB3, VB4, and a conductive pattern BM01. Also above the active region OD1, the configuration and / or connection of various elements between the gate regions D and F are similar to the configuration and / or connection between the gate regions B and C described herein, and the similar detailed description is omitted. For example, the source / drain region adjacent to the gate region D is configured to be electrically connected to the source / drain region adjacent to the gate region F on both the front and back sides. The connection on the front side includes corresponding MD contact regions (not numbered), VD vias (not numbered), and a conductive pattern M01. The connection on the back side includes corresponding through vias VB5, VB6, and a conductive pattern BM01.

[0067] Above the active region OD2, the configuration and / or connection of various elements are similar to the configuration and / or connection described with respect to the active region OD1, and the similar detailed description is omitted. For example, the dummy gate regions P4 - P6 correspond to the dummy gate regions P1 - P3, the vias VB7 - VB12 correspond to the vias VB1 - VB6, and the conductive patterns M04, M05 correspond to the conductive patterns M02, M01. In some embodiments, the region (not marked) of the IC layout diagram 300 related to the active region OD1 is a mirror image about the X-axis of the region (not marked) of the IC layout diagram 300 related to the active region OD2. In at least one embodiment, the BM0 layer includes a conductive pattern BM01 located below the active region OD1 and another conductive pattern located below the active region OD2, for example, as described in reference Figures 4A - 4F described. Other configurations of the IC layout diagram 300 are within the scope of the present invention. For example, in some embodiments, at least the conductive patterns M01, M02, M04, or M05 are configured to be further connected to one or more of the gates A, B, C, D, E, or F.

[0068] In some embodiments, the IC layout diagram 300 or a part of the IC layout diagram 300 is stored as a standard cell in a standard cell library on a non-transitory computer-readable medium. For example, the IC layout diagram 300 includes a part 302, where the gate regions B, C, the dummy gate regions P1, and various corresponding MD contact regions, VD / VG vias, VB through vias, and conductive patterns in the M0 and BM0 layers are arranged as described with respect to Figure 1AAs described. In one or more embodiments, part 302 is stored as a standard analog cell. In at least one embodiment, multiple instances of the standard cell corresponding to IC layout 300 or a portion of IC layout 300 are placed side by side in a repeating manner along at least one of the X-axis or the Y-axis to obtain the IC layout of the IC device. In at least one embodiment, one or more of the advantages described herein can be realized in an IC device corresponding to IC layout 300.

[0069] Figures 4A - 4F Are various schematic perspective views of IC device 400 at various layers according to some embodiments. In at least one embodiment, IC device 400 corresponds to IC layout 300. In some embodiments, layout 300 can be used to fabricate IC device 400. Figures 4A - 4F The exemplary perspective views in are for illustrative purposes only and do not necessarily reflect the order used to fabricate IC device 400. Corresponding elements of IC layout 300 and IC device 400 are denoted by like reference numerals. Specifically, Figure 3 The gate regions A, B, C, D, E, F, P1, P2, P3, P4, P5, P6 in correspond to Figures 4A - 4F The gates GA, GB, GC, GD, GE, GF, GP1, GP2, GP3, GP4, GP5, GP6 in. In Figures 4A - 4F Other components in with corresponding components are Figure 3 Denoted by the same reference numeral of Figure 3 With an added underscore (“_”) symbol. For example, Figure 3 The active region OD2 in corresponds to Figures 4B - 4F The active region OD_2 in.

[0070] Figure 4A The schematic perspective view 400A in shows the BM0 layer of IC device 400. The BM0 layer includes conductive patterns BM0_1 and BM0_2 that extend along the X-axis and are spaced apart from each other along the Y-axis.

[0071] Figure 4BThe schematic perspective view 400B also shows various layers above the BM0 layer. Through-via structures VB_7 - VB_12 are located above the corresponding conductive patterns BM0_2. Other through-via structures VB_1 - VB_6 located above the corresponding conductive patterns BM0_1 are not visible in view 400B. For simplicity, the substrate through which the through-via structures extend is not shown. Active regions OD_1, OD_2 are located above the corresponding conductive patterns BM0_1, BM0_2. Gates GA - GF, GE’, and GF’ as well as dummy gates GP1 - GP6 extend through the corresponding active regions OD_1, OD_2. Gates GE’, GF’ are separated portions of the corresponding gates GE, GF and are located above the active region OD_2. Various channels (e.g., denoted as 452) are formed around the corresponding gate regions and correspond to the channels 152 described with respect to Figure 1B as described.

[0072] Figure 4C The schematic perspective view 400C also shows MD contact structures and VD / VG via structures located above the active and gate regions. For simplicity, only some rather than all of the MD contact structures and VD / VG via structures are numbered in Figure 4C this figure.

[0073] Figure 4D The schematic perspective view 400D also shows the M0 layer and the VIA0 layer located above the VD / VG via structures. For simplicity, only some rather than all of the VIA0 via structures in the VIA0 layer are numbered in Figure 4D this figure. For example, via structures VIA0_1, VIA0_2, VIA0_3 are located above the conductive pattern M0_1. Conductive patterns M0_1 - M0_5 extend along the X-axis and are spaced apart from each other along the Y-axis.

[0074] Figure 4E The schematic perspective view 400E also shows the metal 1 (M1) layer and the VIA1 layer located above the VIA0 layer. The M1 layer includes conductive patterns M1_1 - M1_9 that extend along the Y-axis and are spaced apart from each other along the X-axis. For simplicity, only some rather than all of the VIA1 via structures in the VIA1 layer are numbered in Figure 4E this figure. For example, conductive patterns M1_3, M1_6, M1_9 are located above the corresponding via structures VIA0_1, VIA0_2, VIA0_3 and are electrically connected to the conductive pattern M0_1 through the corresponding via structures VIA0_1, VIA0_2, VIA0_3. Via structure VIA1_1 is located above the conductive pattern M1_3, via structure VIA1_2 is located above the conductive pattern M1_6, and via structure VIA1_3 is located above the conductive pattern M1_9.

[0075] Figure 4F The schematic perspective view 400F in also shows a Metal 2 (M2) layer located above the VIA1 layer. The M2 layer includes conductive patterns M2_1, M2_2, M2_3 that extend along the X-axis and are spaced apart from each other along the Y-axis. For example, the conductive pattern M2_1 is located above the corresponding via structures VIA1_1, VIA1_2, VIA1_3, and is electrically connected to the conductive patterns M1_3, M1_6, M1_9 through the corresponding via structures VIA1_1, VIA1_2, VIA1_3. In at least one embodiment, one or more of the advantages described herein can be realized in the IC device 400.

[0076] Figure 5 is a schematic perspective view of an IC device 500 according to some embodiments. Figure 5 The perspective view in shows, in a manner similar to Figure 4D the perspective view in, various layers from the BM0 layer to the M0 layer. Figure 4D and Figure 5 the corresponding elements in are denoted by the same reference numerals.

[0077] The IC device 500 includes conductive patterns BM0_1, BM0_2, and through-via structures VB_51, VB_52, VB_53 located above the corresponding conductive pattern BM0_2. The IC device 500 also includes additional through-via structures (similar to the through-via structures VB_51, VB_52, VB_53) that are located above the corresponding conductive pattern BM0_1 but are not visible in the Figure 5 perspective view of. For simplicity, the substrate through which the through-via structures extend is not shown. The active regions OD_1, OD_2 are located above the corresponding conductive patterns BM0_1, BM0_2. The gates GA5 - GF5, and the dummy gates GP51, GP52 extend over the corresponding active region OD_2. The IC device 500 includes additional gates (similar to the gates GA5 - GF5) and dummy gates (similar to the dummy gates GP51, GP52) of functional transistors that extend over the corresponding active region OD_1 but are not visible in the Figure 5 perspective view of. The IC device 500 also includes various MD contact structures and VD via structures located above the corresponding active regions and gate regions. For simplicity, such MD contact structures are shown in Figure 5 but are not labeled (if labeled, they would be similar to those shown in FIG. 4). For simplicity, the VD via structures are not shown in Figure 5 but are similar to those shown in the IC device 400. For example, the MD contact structures are conductive patterns M0_1 - M0_5 in the M0 layer located above the corresponding VD via structures.

[0078] In Figure 5 an exemplary configuration, two or more of source / drain 511 between gates GA5 and GE5, source / drain 512 between gate GB5 and dummy gate GP51, and source / drain 513 between gates GD5 and GF5 are electrically connected to each other on both the front and back sides. On the front side, two or more of source / drains 511, 512, 513 are electrically connected through corresponding MD contact structures, VD via structures, and conductive pattern M0_5. On the back side, two or more of source / drains 511, 512, 513 are electrically connected through corresponding through-via structures VB_51, VB_52, VB_53 and conductive pattern BM0_2.

[0079] In some embodiments, active regions OD_1, OD_2, gates GA5 - GF5, dummy gates GP51, GP52, MD contact structures, VD vias, and various metal layers and via layers are formed above the front side of a semiconductor substrate. Next, the semiconductor substrate is removed and replaced with a dielectric layer or substrate, not shown for simplicity but schematically indicated by arrow 520 in Figure 5 . Through-via structures VB_51, VB_52, VB_53 are formed to pass through dielectric substrate 520, and conductive pattern BM0_2 is formed on the back side of dielectric substrate 520. Since the semiconductor substrate has been removed, there is no junction between source / drains 511, 512, 513 and the semiconductor material when source / drains 511, 512, 513 are electrically connected to conductive pattern BM0_2 through corresponding through-via structures VB_51, VB_52, VB_53. Additionally, in at least one embodiment, dummy gate GP51 does not include a conductive material or is filled with a dielectric material. Thus, there is no parasitic capacitance between dummy gate GP51 and adjacent through-via structure VB_52. In some embodiments, by removing the semiconductor substrate and / or removing the conductive material from the dummy gate, it is possible to reduce or at least maintain the parasitic capacitance at approximately the same level while reducing the parasitic resistance. As a result, in one or more embodiments, it is possible to increase the operating speed of IC device 500.

[0080] IC device 500 includes an exemplary configuration in which the source / drain electrically connected on both the front and back sides is not necessarily adjacent to the source / drain. For example, the source / drain 512, 513 electrically connected to each other on both the front and back sides are not adjacent to each other. IC device 500 also includes an exemplary configuration in which the pseudo gate is not necessarily adjacent to the source / drain electrically connected to another source / drain on both the front and back sides. For example, pseudo gate GP52 is not adjacent to any one of the source / drain 512, 513 electrically connected to each other on both the front and back sides. In at least one embodiment, one or more advantages described herein can be implemented in IC device 500.

[0081] Figures 6A - 6B is a schematic cross-sectional view of an IC device 600 being fabricated at various stages of a fabrication process according to some embodiments. In at least one embodiment, the IC device 600 corresponds to the IC device 100B. Figure 1B Elements corresponding to those in FIG. 6 are denoted by the same reference numerals.

[0082] exist Figure 6A In the present invention, the manufacturing process starts with a substrate 120. In at least one embodiment, the substrate 120 includes a silicon substrate. A stack of multiple alternating layers 651, 152 is grown on a first side 121 of the substrate 120. The stack corresponds to the gates GB, GC, GP1 (shown in FIG. 1 ) to be formed later. Figure 6B ), and are referred to herein as stacks GB', GC', GP1' (shown in Figure 6A ). In at least one embodiment, layer 152 includes Si and corresponds to the channel of a transistor to be formed later, and layer 651 includes SiGe. Other materials are within the scope of various embodiments. A dummy gate material 652 is deposited over the top of each of the stack members GB', GC', GP1'. In the example, the dummy gate material 652 is polysilicon. Other materials are within the scope of various embodiments. The sides of layer 651 are etched and filled with a dielectric material to form an internal spacer 153. A top spacer 154 is formed around the dummy gate material 652 at the top of each of the stack members GB', GC', GP1'. The source / drain 112, 113, 114, 115 is epitaxially grown over the first face 121 of the substrate 120 on opposite sides of each of the stack members GB', GC', GP1'. The resulting structure is obtained as Figure 6A shown.

[0083] exist Figure 6BIn this case, for example, the layers 651 and the dummy gate material 652 in each of the stacks GB′, GC′, and GP1′ are removed by etching. Thereafter, a gate dielectric material and then a conductive gate material such as metal are filled into the stacks GB′ and GC′ to form conductive gate stacks 151 and 155. The stack GP1′ is either left empty or filled with a dielectric material to form a gate stack 156 that does not contain a conductive material. The conductive gate stack 151 and the corresponding source / drain 112, 113 together constitute a transistor T1. The conductive gate stack 155 and the corresponding source / drain 114, 115 together constitute a transistor T2. The resulting structure is obtained as Figure 6B shown.

[0084] In a subsequent process, on the front side, corresponding MD contact structures are formed above the source / drains 112, 113, 114, 115 and the conductive gate stacks 151, 155, corresponding VD via structures are formed above the MD contact structures, and corresponding conductive patterns M0_1 are formed above the VD via structures. In some embodiments, a front-side metallization process is implemented to form various front-side metal layers connected by a plurality of front-side via layers to define various connections within the fabricated IC device and / or external connections to other devices external to the IC device.

[0085] On the back side, as described with respect to Figure 1B through-via structures VB_1 and VB_2 are formed to extend from the second side 122 through the substrate 120 to the first side 121 in electrical contact with the corresponding source / drains 113, 114. In some embodiments, after the metallization process described on the front side, the substrate 120 is flipped over and bonded to a carrier via an adhesive to expose the back side of the substrate 120. A thickness portion on the back side of the substrate is removed, for example, by an etching or mechanical grinding process. The VB via structures are formed to extend through the grounded substrate at various locations to form, for example, a power connection to a power rail to be formed later. The through-via structures VB_1 and VB_2 electrically connected to the source / drains 113, 114 are formed together with other VB via structures in this operation. Subsequently, a back-side metallization process is implemented. For example, a BM0 layer is formed above the second side 122 of the substrate 120 (which is in a flipped-over state) and patterned to form various BM0 conductive patterns, including a conductive pattern BM0_1 electrically connected to the through-via structures VB_1 and VB_2. Other BM0 conductive patterns include power rails for one or more power voltages. The resulting structure is obtained as Figure 1BAs shown. In at least one embodiment, the backside metallization process includes forming various backside metal layers connected through a plurality of backside via layers to define, for example, the connection of the IC device to an external circuit or a power supply. After completing the backside metallization process, the carrier is removed from the substrate 120, and subsequent processing such as singulation and / or packaging is then performed. In at least one embodiment, one or more of the advantages described herein can be realized in the IC device 600.

[0086] Figure 7 is a flowchart of a method 700 for manufacturing an IC device according to some embodiments. In at least one embodiment, the method 700 is used to manufacture an IC device with respect to Figures 1A - 1C , Figures 2A - 2C , Figure 3 , Figures 4A - 4F , Figure 5 , Figures 6A - 6B as described.

[0087] In operation 705, a first transistor and a second transistor are formed on a first surface of a substrate, which also has a second surface opposite to the first surface. For example, the first transistor T1 and the second transistor T2 are formed above the first surface 121 of the substrate 120, as described with respect to Figures 6A - 6B . The substrate 120 also has a second surface 122 opposite to the first surface 121.

[0088] In operation 715, in a first metal layer above the first surface of the substrate, a first conductive pattern is formed to electrically connect a first source / drain of the first transistor to a second source / drain of the second transistor. For example, in some embodiments, in the M0 layer above the first surface 121 of the substrate 120, the first conductive pattern M0_1 is formed to electrically connect the first source / drain 113 of the first transistor T1 to the second source / drain 114 of the second transistor T2 through corresponding contact structures MD_1, MD_2 and corresponding via structures VD_1, VD_2, as described with respect to Figure 1B .

[0089] In operation 725, in a second metal layer below the second surface of the substrate, a second conductive pattern is formed to electrically connect a first source / drain of the first transistor to a second source / drain of the second transistor. For example, in the BM0 layer below the second surface 122 of the substrate 120, the second conductive pattern BM0_1 is formed to electrically connect the first source / drain 113 of the first transistor T1 to the second source / drain 114 of the second transistor T2 through corresponding through-via structures VB_1, VB_2, as described with respect to Figure 1B .

[0090] In at least one embodiment, method 700 further includes forming a dummy gate. For example, dummy gate GP1 is formed without conductive material and / or filled with a dielectric material, as described with respect to Figures 6A - 6B described. In at least one embodiment, one or more of the advantages described herein may be realized in an IC device fabricated by method 700.

[0091] The methods described include exemplary operations, but need not be implemented in the order shown. Operations may be appropriately added, replaced, reordered, and / or cancelled in accordance with the spirit and scope of embodiments of the present disclosure. Embodiments that combine different features and / or different embodiments are within the scope of the present disclosure and will be apparent to those of ordinary skill in the art upon review of the present disclosure.

[0092] In some embodiments, at least one of the methods discussed above is implemented in whole or in part by at least one EDA system. In some embodiments, the EDA system may be used as part of a design house for an IC manufacturing system discussed below.

[0093] Figure 8 is a flow chart of a method 800 for forming or manufacturing an integrated circuit according to some embodiments. It should be understood that additional operations may be implemented before, during, and / or after the method 800 depicted, and only some other operations are briefly described herein. In some embodiments, method 800 may be used to form an integrated circuit, such as IC devices 100B - 100C, 400, 500, or 600. In some embodiments, method 800 may be used to form an integrated circuit having a structural relationship similar to one or more of layout designs 100A or 300. Figure 8 In operation 802 of method 800, a layout design of an integrated circuit is generated. Operation 802 is implemented by a processor device (e.g., processor 1002) configured to execute instructions for generating a layout design. In some embodiments, the layout design of method 800 includes at least one or more patterns of IC layout design 100A or 300, or components similar to at least IC devices 100B - 100C, 400, 500, or 600. In some embodiments, the layout design of the present application is in a Graphic Database System (GDSII) file format.

[0094] In operation 804 of method 800, an integrated circuit is fabricated based on the layout design. In some embodiments, operation 804 of method 800 includes: fabricating at least one mask based on the layout design, and fabricating an integrated circuit based on the at least one mask. In some embodiments, method 700 is an embodiment of operation 804.

[0095]

[0096] Figure 9 is a flowchart of a method 900 for generating a layout design of an integrated circuit according to some embodiments. It should be understood that additional operations may be performed before, during, and / or after the method 900 depicted, and only some other processes are briefly described herein. In some embodiments, the method 900 is an embodiment of operation 802 of the method 800. In some embodiments, the method 900 can be used to generate one or more layout patterns of at least the IC layout design 100A or 300, or patterns similar to one or more of at least the IC devices 100B - 100C, 400, 500, or 600. In some embodiments, the method 900 can be used to generate one or more layout patterns having structural relationships including alignment, length, and width, and configurations and layers of at least the layout design 100A or 300, or patterns similar to one or more of at least the IC devices 100B - 100C, 400, 500, or 600, and for the sake of brevity, similar detailed descriptions will not be described again in Figure 9 In operation 902 of the method 900, a first set of conductive patterns BM01, BM02 is generated or placed on the layout design. Figure 9 In operation 904 of the method 900, a first set of via patterns is generated or placed on the layout design. In some embodiments, the first set of via patterns of the method 900 includes at least a portion of one or more of the through vias VB1 - VB12.

[0097] In operation 906 of the method 900, a set of active region patterns is generated or placed on the layout design. In some embodiments, the set of active region patterns of the method 900 includes at least a portion of one or more of the active regions OD1 and OD2.

[0098] In operation 908 of the method 900, a set of gate patterns is generated or placed on the layout design. In some embodiments, the set of gate patterns of the method 900 includes at least a portion of one or more of the gate regions A - F and P1 - P6.

[0099] In operation 910 of the method 900, a set of contact patterns is generated or placed on the layout design. In some embodiments, the set of contact patterns of the method 900 includes at least a portion of one or more of the contacts MD1 - MD4.

[0100] In operation 912 of the method 900, a second set of conductive patterns BM03, BM04 is generated or placed on the layout design.

[0101] In operation 914 of the method 900, a second set of via patterns is generated or placed on the layout design. In some embodiments, the second set of via patterns of the method 900 includes at least a portion of one or more of the through vias VB13 - VB24.

[0102] In operation 912 of method 900, a second set of via patterns is generated or placed on the layout design. In some embodiments, the second set of via patterns of method 900 includes at least a portion of one or more of vias VD1 - VD8.

[0103] In operation 914 of method 900, a second set of conductive feature patterns is generated or placed on the layout design. In some embodiments, the second set of conductive feature patterns of method 900 includes at least a portion of one or more of conductive patterns M01 - M05.

[0104] Figure 10 FIG. 7 is a block diagram of an electronic design automation (EDA) system 1000 for designing an IC layout design and manufacturing an IC circuit according to some embodiments. In some embodiments, system 1000 generates or places one or more of the IC layout designs described herein. In some embodiments, system 1000 generates or places one or more of the IC layout designs described herein and then manufactures an IC circuit based on one or more of the IC layout designs.

[0105] In some embodiments, EDA system 1000 includes an APR system. According to one or more embodiments, the methods described herein for designing a layout represent routing path placement, for example, which can be implemented using EDA system 1000 according to some embodiments.

[0106] In some embodiments, EDA system 1000 is a computing device including a hardware processor 1002 and a non - transitory computer - readable storage medium 1004. The storage medium 1004 is encoded, among other things, with computer program code 1006 (i.e., a set of executable instructions), that is, stores the computer program code 1006. Execution of the instructions 1006 by the hardware processor 1002 represents (at least in part) an EDA tool that implements a part or all of the methods described herein according to one or more embodiments (the processes and / or methods mentioned hereinafter).

[0107] The processor 1002 is electrically connected to the computer-readable storage medium 1004 via the bus 1008. The processor 1002 is also electrically connected to the I / O interface 1010 via the bus 1008. The network interface 1012 is also electrically connected to the processor 1002 via the bus 1008. The network interface 1012 is connected to the network 1014, enabling the processor 1002 and the computer-readable storage medium 1004 to be connected to external components via the network 1014. The processor 1002 is configured to execute the computer program code 1006 encoded in the computer-readable storage medium 1004, such that the system 1000 can be used to implement part or all of the processes and / or methods mentioned. In one or more embodiments, the processor 1002 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0108] In one or more embodiments, the computer-readable storage medium 1004 is an electrical, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or component). For example, the computer-readable storage medium 1004 includes semiconductor or solid-state memory, magnetic tape, removable computer disks, random access memory (RAM), read-only memory (ROM), rigid disks, and / or optical disks. In one or more embodiments using optical disks, the computer-readable storage medium 1004 includes compact disk read-only memory (CD-ROM), compact disk read / write (CD-R / W), and / or digital video disk (DVD).

[0109] In one or more embodiments, the storage medium 1004 stores the computer program code 1006, which is configured such that the system 1000 (where such execution represents (at least in part) an EDA tool) can be used to implement part or all of the processes and / or methods mentioned. In one or more embodiments, the storage medium 1004 also stores information that helps implement part or all of the processes and / or methods mentioned. In one or more embodiments, the storage medium 1004 stores a standard cell library 1007 including such standard cells as disclosed herein.

[0110] The EDA system 1000 includes the I / O interface 1010. The I / O interface 1010 is connected to external circuitry. In one or more embodiments, the I / O interface 1010 includes a keyboard, keypad, mouse, trackball, touchpad, touchscreen, and / or cursor direction keys for communicating information and commands to the processor 1002.

[0111] The EDA system 1000 also includes a network interface 1012 connected to the processor 1002. The network interface 1012 allows the system 1000 to communicate with a network 1014 to which one or more other computer systems are connected. The network interface 1012 includes a wireless network interface such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA, or a wired network interface such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, part or all of the processes and / or methods mentioned are implemented in two or more systems 1000.

[0112] The system 1000 is configured to receive information through the I / O interface 1010. The information received through the I / O interface 1010 includes one or more of instructions, data, design rules, a standard cell library, and / or other parameters for processing by the processor 1002. The information is transmitted to the processor 1002 via the bus 1008. The EDA system 1000 is configured to receive UI-related information through the I / O interface 1010. This information is stored in the computer-readable medium 1004 as a user interface (UI) 1042.

[0113] In some embodiments, part or all of the processes and / or methods mentioned are implemented as a stand-alone software application for execution by a processor. In some embodiments, part or all of the processes and / or methods mentioned are implemented as a software application that is part of an additional software application. In some embodiments, part or all of the processes and / or methods mentioned are implemented as a plug-in to a software application. In some embodiments, at least one of the processes and / or methods mentioned is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the processes and / or methods mentioned are implemented as a software application used by the EDA system 1000. In some embodiments, the layout diagram of the standard cell is generated using tools such as obtained from CADENCE DESIGN SYSTEMS, Inc., or other suitable layout generation tools.

[0114] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable, and / or internal / built-in memories or memory units, such as one or more of an optical disc such as a DVD, a magnetic disk such as a hard disk, a semiconductor memory such as ROM, RAM, a memory card, and the like.

[0115] Figure 11FIG. 1100 is a block diagram of an integrated circuit (IC) manufacturing system 1100 and an IC manufacturing process associated therewith, according to some embodiments. In some embodiments, based on a layout, the manufacturing system 1100 is used to manufacture (A) one or more semiconductor masks, or (B) at least one component in a layer of a semiconductor integrated circuit.

[0116] In Figure 11 FIG. 1100, the IC manufacturing system 1100 includes entities that interact with each other in the design, development, and manufacturing cycle, and / or services related to manufacturing IC device 1160, such as design house 1120, mask house 1130, and IC manufacturer / fabricator ("fab") 1150. The entities in the system 1100 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design house 1120, mask house 1130, and IC fab 1150 are owned by a single larger company. In some embodiments, two or more of the design house 1120, mask house 1130, and IC fab 1150 coexist in a common facility and use common resources.

[0117] The design house (or design team) 1120 generates an IC design layout 1122. The IC design layout 1122 includes various geometric patterns designed for the IC device 1160. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers and constitute various components of the IC device 1160 to be manufactured. The individual layers are combined to form various IC features. For example, a portion of the IC design layout 1122 includes various IC features formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate, such as active regions, gate electrodes, source and drain electrodes, metal wires or vias for interlayer interconnects, and openings for bonding pads. The design house 1120 implements appropriate design procedures to form the IC design layout 1122. The design procedures include one or more of logic design, physical design, or layout and routing operations. The IC design layout 1122 is presented in one or more data files having geometric pattern information. For example, the IC design layout 1122 can be expressed in the GDSII file format or the DFII file format.

[0118] The mask chamber 1130 includes data preparation 1132 and mask fabrication 1144. The mask chamber 1130 uses the IC design layout 1122 to fabricate one or more masks 1145 for use in fabricating the various layers of the IC device 1160 according to the IC design layout 1122. The mask chamber 1130 implements mask data preparation 1132, in which the IC design layout 1122 is translated into a representative data file ("RDF"). The mask data preparation 1132 provides the RDF to the mask fabrication 1144. The mask fabrication 1144 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1145 or a semiconductor wafer 1153. The design layout 1122 is controlled by the mask data preparation 1132 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fab 1150. In Figure 11 it, the mask data preparation 1132 and the mask fabrication 1144 are shown as separate elements. In some embodiments, the mask data preparation 1132 and the mask fabrication 1144 may be collectively referred to as mask data preparation.

[0119] In some embodiments, the mask data preparation 1132 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. The OPC adjusts the IC design layout 1122. In some embodiments, the mask data preparation 1132 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0120] In some embodiments, the mask data preparation 1132 includes a mask rule checker (MRC), which uses a set of mask creation rules to check the IC design layout 1122 that has already been processed in the OPC. The mask creation rules include certain geometric and / or connectivity restrictions to ensure sufficient margins to address issues such as variability in semiconductor manufacturing processes. In some embodiments, the MRC modifies the IC design layout 1122 to compensate for the limitations during mask fabrication 1144, which may undo some of the modifications implemented by the OPC to meet the mask creation rules.

[0121] In some embodiments, mask data preparation 1132 includes lithography process check (LPC), which simulates the processes to be implemented by IC fab 1150 to fabricate IC device 1160. LPC simulates the processes based on IC design layout 1122 to create a simulated fabricated device, such as IC device 1160. The process parameters in the LPC simulation may include parameters related to various processes of the IC manufacturing cycle, parameters related to the tools used for manufacturing the IC, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc., or a combination thereof. In some embodiments, after a simulated fabricated device is created by LPC, if the simulated device is not close enough in shape to meet the design rules, OPC and / or MRC are repeated to further refine IC design layout 1122.

[0122] It should be understood that the above description of mask data preparation 1132 has been simplified for clarity purposes. In some embodiments, data preparation 1132 includes additional features such as logic operation (LOP) to modify IC design layout 1122 according to manufacturing rules. Additionally, the processes applied to IC design layout 1122 during data preparation 1132 may be performed in various different orders.

[0123] After mask data preparation 1132 and during mask manufacturing 1144, a mask 1145 or a set of masks 1145 can be manufactured based on the modified IC design layout 1122. In some embodiments, mask manufacturing 1144 includes performing one or more lithographic exposures based on the IC design layout 1122. In some embodiments, an electron beam (e-beam) or a mechanism of multiple electron beams is used to form a pattern on the mask (photomask or reticle) 1145 based on the modified IC design layout 1122. The mask 1145 can be formed using various techniques. In some embodiments, the mask 1145 is formed using binary technology. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam such as an ultraviolet (UV) beam, which is used to expose an image-sensitive material layer (e.g., photoresist) that has been coated on a wafer, is blocked by the opaque regions and transmitted through the transparent regions. In one example, the binary mask version of the mask 1145 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, the mask 1145 is formed using phase-shift technology. In the phase-shift mask (PSM) version of the mask 1145, various features in the pattern formed on the phase-shift mask are configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase-shift mask can be an attenuated PSM or an alternating PSM. (Some) masks generated by mask manufacturing 1144 are used in a variety of processes. For example, such (some) masks can be used in an ion implantation process to form various doped regions in the semiconductor wafer 1153; such (some) masks can be used in an etching process to form various etched regions in the semiconductor wafer 1153; and / or such (some) masks can be used in other suitable processes.

[0124] IC fab 1150 is an IC manufacturing enterprise that includes one or more manufacturing sites for manufacturing various different IC products. In some embodiments, IC Fab 1150 is a semiconductor foundry. For example, there may be one manufacturing site for front-end manufacturing (front-end-of-line (FEOL) manufacturing) of multiple IC products, while a second manufacturing site can provide back-end manufacturing (back-end-of-line (BEOL) manufacturing) for the interconnect and packaging of the IC products, and a third manufacturing site may provide other services for the foundry business.

[0125] IC fab 1150 includes manufacturing tools 1152 configured to perform various manufacturing operations on semiconductor wafer 1153 to fabricate IC device 1160 according to (some) masks (such as mask 1145). In various embodiments, manufacturing tools 1152 include one or more wafer steppers, ion implanters, photoresist coaters, process chambers (such as CVD chambers or LPCVD furnaces), CMP systems, plasma etch systems, wafer cleaning systems, or other manufacturing equipment capable of implementing one or more suitable manufacturing processes as discussed herein.

[0126] IC fab 1150 uses (some) masks 1145 fabricated by mask chamber 1130 to fabricate IC device 1160. Thus, IC fab 1150 uses IC design layout 1122 at least indirectly to fabricate IC device 1160. In some embodiments, semiconductor wafer 1153 is fabricated by IC fab 1150 using (some) masks 1145 to form IC device 1160. In some embodiments, IC fabrication includes performing at least one or more lithographic exposures indirectly based on IC design layout 1122. Semiconductor wafer 1153 includes a silicon substrate or other suitable substrate with material layers formed thereon. Semiconductor wafer 1153 also includes one or more of various doped regions, dielectric components, multi-level interconnections, etc. (formed in subsequent manufacturing steps).

[0127] Regarding an integrated circuit (IC) manufacturing system (such as Figure 11The system 1100) and details of the associated IC manufacturing process can be found, for example, in U.S. Patent No. 9,256,709, authorized on February 9, 2016 (A method of transforming a first IC pattern, where the first IC pattern includes a shape that is not one of a plurality of user-defined shapes, the method comprising the steps of: using a computer to derive a second IC pattern approximating the first IC pattern, where the second IC pattern includes a shape that is one of a plurality of user-defined shapes; calculating a pattern proximity error between the first IC pattern and the second IC pattern; and, under the condition that the pattern proximity error is greater than a user-defined threshold, performing the following steps: dividing the first IC pattern into a plurality of sub-patterns; and recursively transforming each of the plurality of sub-patterns), U.S. Pre-Grant Publication No. 20150278429, published on October 1, 2015 (A method comprising: receiving a design layout of an IC, the design layout having primary features; performing process correction on the primary features to generate modified primary features; using a computer to generate a simulated profile of the modified primary features, the simulated profile having a plurality of points; generating a plurality of auxiliary data, where each auxiliary data includes at least one process performance factor associated with one of the points; storing the simulated profile and the auxiliary data in a tangible computer-readable medium for use in other IC processing stages including a mask inspection process or a wafer inspection process; forming a mask using the design layout having the modified primary features; and inspecting the mask using the simulated profile and the plurality of auxiliary data, where at least one process performance factor includes a mask error enhancement factor (MEEF), and where the inspection of the mask includes: identifying one of the points associated with a higher MEEF data than another MEEF data; identifying a point associated with a higher MEEF data compared to another point; and inspecting the mask feature corresponding to one of the points more thoroughly than another mask feature corresponding to the other point), U.S. Pre-Grant Publication No. 20140040838, published on February 6, 2014 (A method of manufacturing a mask, comprising: receiving an IC design layout; performing a target feature surrounding (TFS) inspection operation to identify target feature surrounding locations (TFSLs) in the IC design layout; inserting phase lines (PBs) on the TFSLs; performing optical proximity correction (OPC) on the IC design layout having the PBs to form a modified IC design layout; and fabricating a mask according to the modified IC design layout), and U.S. Patent No. 7,260,442, authorized on August 21, 2007 (A mask manufacturing method, which includes: providing material data and mask data; determining first process parameters based on the material data and the mask data; performing a first mask process based on the first process parameters to process a first mask; collecting first process data corresponding to the first mask process; determining feedback correction data based on the material data, the mask data, and the first process data;Calibrate the first process parameter according to the feedback calibration data to obtain a second process parameter; and perform a second mask process on a second mask according to the second process parameter), the entire content of each item is incorporated herein by reference.;

[0128] In some embodiments, an integrated circuit (IC) device includes: a substrate having opposite first and second faces; an active region located above the first face of the substrate; a first conductive pattern located above the active region; and a second conductive pattern located below the second face of the substrate. The active region includes a first portion and a second portion. The first conductive pattern is electrically connected to the first portion and the second portion of the active region. The second conductive pattern is electrically connected to the first portion and the second portion of the active region.

[0129] In some embodiments, a system includes: a processor configured to generate an integrated circuit (IC) layout usable for manufacturing an IC device; an active region; a plurality of gate regions; a first contact region and a second contact region; a first via and a second via; a first conductive pattern and a second conductive pattern; and a first through-via and a second through-via. The plurality of gate regions extend over the active region and include a first gate region and a second gate region. The first contact region is located above the active region and adjacent to the first gate region. The second contact region is located above the active region and adjacent to the second gate region. The first via is located above the first contact region. The second via is located above the second contact region. The first conductive pattern is located above the first via and the second via. The first through-via is located below the first contact region and the active region. The second through-via is located below the second contact region and the active region. The second conductive pattern is located below the first through-via and the second through-via. The first conductive pattern, the first via, the first contact region, the first through-via, and the second conductive pattern overlap with each other. The first conductive pattern, the second via, the second contact region, the second through-via, and the second conductive pattern overlap with each other.

[0130] In some embodiments, a method includes: forming a first transistor and a second transistor above a first face of a substrate. The substrate has a second face opposite the first face. The method further includes: forming a first conductive pattern in a first metal layer above the first face of the substrate, the first conductive pattern electrically connecting a first source / drain of the first transistor to a second source / drain of the second transistor. The method further includes: forming a second conductive pattern in a second metal layer below the second face of the substrate, the second conductive pattern electrically connecting the first source / drain of the first transistor to the second source / drain of the second transistor.

[0131] One aspect of the present invention provides an integrated circuit device, comprising: a substrate having opposite first and second surfaces; an active region located above the first surface of the substrate, the active region including a first portion and a second portion; a first conductive pattern located above the active region and electrically connected to the first portion and the second portion of the active region; and a second conductive pattern located below the second surface of the substrate and electrically connected to the first portion and the second portion of the active region. In some embodiments, the integrated circuit device further comprises: a first through-via structure extending from the second surface through the substrate to the first surface in electrical contact with the first portion of the active region; and a second through-via structure extending from the second surface through the substrate to the first surface in electrical contact with the second portion of the active region; wherein the second conductive pattern is electrically connected to the first through-via structure and the second through-via structure. In some embodiments, the integrated circuit device further comprises: a first contact structure located above the first portion of the active region and in electrical contact with the first portion of the active region, the first contact structure being electrically connected to the first conductive pattern; and a second contact structure located above the second portion of the active region and in electrical contact with the second portion of the active region, the second contact structure being electrically connected to the first conductive pattern. In some embodiments of the integrated circuit device, at least one of the following: the first contact structure and the first through-via structure are in direct contact with corresponding opposing surfaces of the first portion of the active region, or the second contact structure and the second through-via structure are in direct contact with corresponding opposing surfaces of the second portion of the active region. In some embodiments, along the thickness direction of the substrate from the first surface to the second surface: the first conductive pattern, the first contact structure, the first portion of the active region, the first through-via structure, and the second conductive pattern overlap each other, and the first conductive pattern, the second contact structure, the second portion of the active region, the second through-via structure, and the second conductive pattern overlap each other. In some embodiments, the first conductive pattern is located in a metal zero layer, and the second conductive pattern is located in a backside metal zero layer. In some embodiments, the integrated circuit device further comprises: a dummy gate located between the first portion and the second portion of the active region. In some embodiments, the dummy gate comprises a dielectric material.In some embodiments, the integrated circuit device further includes: a plurality of gates that extend over the active region and together with the active region form a plurality of transistors, wherein the plurality of transistors includes: a first transistor and a second transistor, a source / drain of the first transistor is the first portion of the active region, a source / drain of the second transistor is the second portion of the active region, and the first transistor and the second transistor form a differential transistor pair. In some embodiments, the integrated circuit device further includes a plurality of gates that extend over the active region and together with the active region form a plurality of transistors, wherein the plurality of transistors includes: a first transistor, a source / drain of the first transistor is the first portion of the active region, and a second transistor, a source / drain of the second transistor is the second portion of the active region, and the plurality of transistors are connected in a daisy-chain arrangement to a serializer / deserializer device.

[0132] Another aspect of the present invention provides an integrated circuit manufacturing system, including a processor configured to generate an integrated circuit layout that can be used to manufacture integrated circuit devices. The integrated circuit layout includes: an active region; a plurality of gate regions extending over the active region, the plurality of gate regions including a first gate region and a second gate region; a first contact region located above the active region and adjacent to the first gate region; a second contact region located above the active region and adjacent to the second gate region; a first via hole located above the first contact region; a second via hole located above the second contact region; a first conductive pattern located above the first via hole and the second via hole; a first through via hole located below the first contact region and the active region; a second through via hole located below the second contact region and the active region; and a second conductive pattern located below the first through via hole and the second through via hole; wherein the first conductive pattern, the first via hole, the first contact region, the first through via hole, and the second conductive pattern overlap with each other, and the first conductive pattern, the second via hole, the second contact region, the second through via hole, and the second conductive pattern overlap with each other. In some embodiments, the processor is configured to generate or place on the integrated circuit layout, the first conductive pattern is located in metal layer zero, and the second conductive pattern is located in the back metal zero layer. In some embodiments, the processor is configured to generate or place on the integrated circuit layout, the second conductive pattern includes a power supply voltage rail. In some embodiments, the processor is configured to generate or place on the integrated circuit layout, the width of the first conductive pattern is less than the width of the second conductive pattern. In some embodiments, the processor is configured to generate or place on the integrated circuit layout, at least one of the following: the area of the first contact region is less than the area of the first through via hole, or the area of the second contact region is less than the area of the second through via hole. In some embodiments, the processor is configured to generate or place on the integrated circuit layout, the plurality of gate regions further includes a dummy gate region disposed between the first gate region and the second gate region, and between the first contact region and the second contact region. In some embodiments, the processor is configured to generate or place on the integrated circuit layout, the dummy gate region is adjacent to the first gate region and the second gate region.

[0133] In another aspect, the present invention provides a method of manufacturing an integrated circuit device, comprising: forming a first transistor and a second transistor above a first surface of a substrate, the substrate having a second surface opposite to the first surface; forming a first conductive pattern in a first metal layer above the first surface of the substrate, the first conductive pattern electrically connecting a first source / drain of the first transistor to a second source / drain of the second transistor; and forming a second conductive pattern in a second metal layer below the second surface of the substrate, the second conductive pattern electrically connecting the first source / drain of the first transistor to the second source / drain of the second transistor. In some embodiments, the method of manufacturing an integrated circuit device further comprises: removing a conductive material from a third gate disposed between the first gate and the second gate. In some embodiments, the method of manufacturing an integrated circuit device further comprises: after the removing, filling a dielectric material into the third gate.

[0134] The features of several embodiments are outlined above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same or similar purposes and / or achieving the same or similar advantages. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit device, comprising: A substrate having opposite first and second surfaces; An active region located above the first surface of the substrate, the active region including a first portion and a second portion; A first conductive pattern located above the active region and electrically connected to the first portion and the second portion of the active region; And A second conductive pattern located below the second surface of the substrate and electrically connected to the first portion and the second portion of the active region; A dummy gate located between the first portion and the second portion of the active region, wherein the dummy gate does not include a conductive material.

2. The integrated circuit device according to claim 1, further comprising: A first through-via structure extending from the second surface through the substrate to the first surface in electrical contact with the first portion of the active region; And A second through-via structure extending from the second surface through the substrate to the first surface in electrical contact with the second portion of the active region; Wherein the second conductive pattern is electrically connected to the first through-via structure and the second through-via structure.

3. The integrated circuit device according to claim 2, further comprising: A first contact structure located above the first portion of the active region and in electrical contact with the first portion of the active region, the first contact structure being electrically connected to the first conductive pattern; And A second contact structure located above the second portion of the active region and in electrical contact with the second portion of the active region, the second contact structure being electrically connected to the first conductive pattern.

4. The integrated circuit device according to claim 3, wherein the following At least one of: The first contact structure and the first through-via structure are in direct contact with corresponding opposing surfaces of the first portion of the active region, and The second contact structure and the second through-via structure are in direct contact with corresponding opposing surfaces of the second portion of the active region.

5. The integrated circuit device according to claim 3, wherein, Along the thickness direction of the substrate from the first surface to the second surface, The first conductive pattern, the first contact structure, the first portion of the active region, the first through-via structure, and the second conductive pattern overlap each other, and The first conductive pattern, the second contact structure, the second portion of the active region, the second through-via structure, and the second conductive pattern overlap each other.

6. The integrated circuit device according to claim 1, wherein, The first conductive pattern is located in a metal zero layer, and The second conductive pattern is located in a backside metal zero layer.

7. The integrated circuit device according to claim 1, wherein: The resistance of the second conductive pattern is less than the resistance of the first conductive pattern.

8. The integrated circuit device according to claim 7, wherein, The dummy gate includes a dielectric material.

9. The integrated circuit device according to claim 1, further comprising: A plurality of gates extending over the active region and together with the active region forming a plurality of transistors, Wherein, The plurality of transistors include: A first transistor, wherein source / drain of the first transistor is the first part of the active region, and A second transistor, wherein source / drain of the second transistor is the second part of the active region, and The first transistor and the second transistor form a differential transistor pair.

10. The integrated circuit device according to claim 1, further comprising: A plurality of gates extending over the active region and together with the active region forming a plurality of transistors, Wherein, The plurality of transistors includes: A first transistor, having source / drain that is the first part of the active region, and A second transistor, having source / drain that is the second part of the active region, and The plurality of transistors are connected in a daisy chain arrangement to a serializer / deserializer (SERDES) device.

11. An integrated circuit manufacturing system, comprising: A processor configured to generate an integrated circuit layout for use in manufacturing an integrated circuit device, the integrated circuit layout including: An active region; A plurality of gate regions extending over the active region, the plurality of gate regions including a first gate region, a second gate region, and a dummy gate region; A first contact region located above the active region and adjacent to the first gate region; A second contact region located above the active region and adjacent to the second gate region; A first via located above the first contact region; A second via located above the second contact region; A first conductive pattern located above the first via and the second via; A first through-via located below the first contact region and the active region; A second through-via located below the second contact region and the active region; and A second conductive pattern located below the first through-via and the second through-via; Wherein, The first conductive pattern, the first via, the first contact region, the first through-via, and the second conductive pattern overlap each other, and The first conductive pattern, the second via, the second contact region, the second through-via, and the second conductive pattern overlap each other, The dummy gate region is disposed between the first gate region and the second gate region, and between the first contact region and the second contact region, and the dummy gate region includes a dummy gate that does not include a conductive material.

12. The integrated circuit manufacturing system according to claim 11, wherein, The processor is configured to generate or place on the integrated circuit layout, The first conductive pattern is located in metal layer zero, The second conductive pattern is located in back metal zero layer.

13. The integrated circuit manufacturing system according to claim 11, wherein, The processor is configured to generate or place on the integrated circuit layout, The second conductive pattern includes a power supply voltage rail.

14. The integrated circuit manufacturing system according to claim 11, wherein, The processor is configured to generate or place on the integrated circuit layout, The width of the first conductive pattern is less than the width of the second conductive pattern.

15. The integrated circuit manufacturing system according to claim 11, wherein the processor is configured to generate or place on the integrated circuit layout at least one of the following: the area of the first contact region is smaller than the area of the first through via, and the area of the second contact region is smaller than the area of the second through via.

16. The integrated circuit manufacturing system according to claim 11, wherein the resistance of the second conductive pattern is less than the resistance of the first conductive pattern.

17. The integrated circuit manufacturing system according to claim 16, wherein the processor is configured to generate or place on the integrated circuit layout the dummy gate region is adjacent to the first gate region and the second gate region.

18. A method of manufacturing an integrated circuit device, comprising: forming a first transistor and a second transistor above a first surface of a substrate, the substrate having a second surface opposite to the first surface; forming a first conductive pattern in a first metal layer above the first surface of the substrate, the first conductive pattern electrically connecting a first source / drain of the first transistor to a second source / drain of the second transistor; and forming a second conductive pattern in a second metal layer below the second surface of the substrate, the second conductive pattern electrically connecting the first source / drain of the first transistor to the second source / drain of the second transistor removing conductive material from a third gate disposed between a first gate of the first transistor and a second gate of the second transistor; after the removing, filling a dielectric material into the third gate, the third gate not including conductive material.

19. The method according to claim 18, wherein: the resistance of the second conductive pattern is less than the resistance of the first conductive pattern.

20. The method according to claim 19, wherein: the dielectric material includes silicon oxide.

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