Level shifter device and method for converting signal voltage

Abstract

A level shifter apparatus and a method for converting signal voltage are disclosed. The level shifter apparatus includes a first stage level shifter configured to convert an input signal into a first output signal having a voltage between a VPS control voltage and ground, or between a VDD power supply voltage and a VNS control voltage. The level shifter apparatus includes a second stage level shifter arranged after the first stage level shifter and configured to convert the first output signal into a second output signal having a voltage between ground and the VDD power supply voltage.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of level shifters and sense amplifiers. BACKGROUND

[0002] One type of device that can be utilized in a circuit is a level shifter, such as a voltage translator, that can be used to convert a voltage from one voltage domain to a different voltage domain. For example, a first circuit, such as a processor, can operate at a 3.3V voltage, while a second circuit, such as a sensor, can operate at a 5V voltage. Since the first circuit and the second circuit operate at different voltage domains, the first circuit and the second circuit can not be compatible. Thus, a level shifter can be used to shift the 5V voltage used by the sensor to the 3.3V voltage used by the processor so that the processor can receive sensor data from the sensor at the 3.3V voltage operating domain of the processor. A simple level shifter can utilize transistors and resistors, such as NMOS transistors and pull-up resistors or PMOS transistors and pull-down resistors, to shift the voltage.

[0003] Another type of device that can be utilized in a circuit is a sense amplifier used to read data from a cell of a memory device. The sense amplifier is used to distinguish between states that a cell can store. In an example, the state of a cell can be represented by a modulation of current flowing through the cell so that the sense amplifier detects a difference in current through a bit line that connects the sense amplifier to a row that includes the cell. In this way, the state of the cell corresponds to the modulation of the current.

[0004] Due to manufacturing variability and external effects, such as external induced noise, the current state of a cell detected by a sense amplifier can not perfectly match the possible states of the cell. Additionally, a memory device can include far more than one sense amplifier and, thus, to accurately determine the state of a cell, manufacturing variability of the sense amplifier itself must be considered, not only for one sense amplifier, but for all sense amplifiers over the product use cycle. A read window is a range of values between two cell states. The sense amplifier operates within the read window, which unfortunately becomes smaller as variability increases. Thus, the ability of the sense amplifier to correctly determine the state of a cell is diminished when all sources of variability cannot be considered.

[0005] Some sense amplifiers that operate under a current detection principle can employ current mirrors to improve the accuracy of the sense amplifier to detect the state of a cell. However, due to transistor mismatch, each current mirror contributes significantly to circuit variability. Offset cancellation can be employed to reduce such circuit variability, but offset cancellation adds complexity, area, and increased power consumption. Furthermore, in many use cases, the use of current mirrors can make current consumption too high. SUMMARY

[0006] This Summary is provided to introduce some concepts in a simplified form that are further described below in the DETAILED DESCRIPTION. This Summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0007] In implementations of the technology presented herein, a level shifter apparatus is provided. The level shifter apparatus includes a first stage level shifter configured to convert an input signal from a bit line connected to at least one memory cell of a memory apparatus into a first output signal, the first output signal having a voltage between a VPS control voltage and ground or between a VDD power supply voltage and a VNS control voltage. The level shifter apparatus includes a second stage level shifter arranged after the first stage level shifter and configured to convert the first output signal into a second output signal, the second signal having a voltage between ground and the VDD power supply voltage.

[0008] In implementations of the technology presented herein, a level shifter apparatus is provided. The level shifter apparatus includes a first stage level shifter configured to convert an input signal into a first output signal, the first output signal having a voltage between a VPS control voltage and ground or between a VDD power supply voltage and a VNS control voltage. The level shifter apparatus includes a second stage level shifter arranged after the first stage level shifter and configured to convert the first output signal into a second output signal, the second output signal having a voltage between ground and the VDD power supply voltage. At least one of the VPS control voltage or the VNS control voltage is variably adjusted.

[0009] In implementations of the technology presented herein, a method is provided. The method includes controlling a first stage level shifter to convert an input signal to output a first output signal, the first output signal having a voltage between a VPS control voltage and ground or between a VDD power supply voltage and a VNS control voltage. The method includes controlling a second stage level shifter arranged after the first stage level shifter to convert the first output signal into a second output signal, the second output signal having a voltage between ground and the VDD power supply voltage.

[0010] In embodiments of the technology described herein, an apparatus is provided. The apparatus includes means for controlling a first-stage level shifter to convert an input signal to output a first output signal having a voltage between a VPS control voltage and ground, or a voltage between a VDD power supply voltage and a VNS control voltage. The apparatus includes means for controlling a second-stage level shifter disposed after the first-stage level shifter to convert the first output signal into a second output signal having a voltage between ground and the VDD power supply voltage.

[0011] To achieve the foregoing and related objectives, the following description and accompanying drawings illustrate certain exemplary aspects and implementations. These are merely indications of a number of ways in which one or more aspects may be employed. Other aspects, advantages, and novel features of this disclosure will become apparent when considered in conjunction with the accompanying drawings, based on the following detailed description. Attached Figure Description

[0012] Figure 1 This is a diagram illustrating an example method of operating a level shifter according to the techniques described in this article.

[0013] Figure 2 This is a component block diagram illustrating a level shifter according to the technology described herein.

[0014] Figure 3 This is a component block diagram illustrating a level shifter according to the technology described herein.

[0015] Figure 4 This is a component block diagram illustrating a level shifter according to the technology described herein, and a timing diagram illustrating the operation of the level shifter.

[0016] Figure 5 This is a component block diagram illustrating a level shifter according to the technology described herein, and a timing diagram illustrating the operation of the level shifter.

[0017] Figure 6 Examples of computer-readable media in which at least a portion of the techniques described herein may be utilized.

[0018] Figure 7 This is an example computing environment in which at least a portion of the techniques described herein can be utilized. Detailed Implementation

[0019] The claimed subject matter will now be described with reference to the accompanying drawings, wherein similar reference numerals are used throughout to refer to similar elements. In the following description, several specific details are set forth for illustrative purposes to provide a thorough understanding of the claimed subject matter. However, it will be apparent that the claimed subject matter can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form to facilitate the description of the claimed subject matter.

[0020] In the field of electronics, various types of devices can be used to perform a variety of functions. One example is a level shifter. A level shifter can be used to shift / convert a signal from one voltage domain to another different voltage domain. This allows two components, such as a processor and a sensor, that are otherwise incompatible due to operating in different voltage domains to exchange signals shifted to the appropriate voltage domain by the level shifter.

[0021] Another type of device is a sensing device, such as a sensing amplifier, for determining the state of cells within a storage device. This state can represent one or more states, such as logic "1", logic "0", or any other state. The sensing device can be implemented for any type of storage device, such as non-volatile memory, random access memory (RAM), etc.

[0022] One type of sensing device is a sense amplifier that operates on the principle of current sensing. This type of sense amplifier determines the state of a cell in a memory device by detecting the current difference through bit lines connected to the row containing the cell. In this way, the state of a cell is represented as a modulation of the current flowing through it. Unfortunately, manufacturing variability, external effects such as external induced noise, and other factors reduce the size of the read window within which the sense amplifier operates to detect the current state of the cell. The read window is a range of values ​​between two cell states and decreases with increasing variability. Current techniques cannot handle all variability and external effects, which reduces the ability of such a sense amplifier to accurately determine the cell state. A sense amplifier can use a current mirror to determine the cell state, but the current mirror can contribute significantly to circuit variability due to transistor mismatch. Offset cancellation can be used to reduce such circuit variability, but offset cancellation increases complexity, area, and power consumption. Furthermore, in many use cases, the use of a current mirror can result in excessive current consumption.

[0023] As provided herein, the level shifter device is configured with a first-stage level shifter and a second-stage level shifter. The first-stage level shifter is configured to convert an input signal (e.g., an input signal from any type of circuit / device such as a processor, sensor, memory cell bit line, or any other type of logic or circuitry) into a first output signal. If the first-stage level shifter utilizes a PMOS transistor, the first output signal will have a voltage between the VPS control voltage and ground. If the first-stage level shifter utilizes an NMOS transistor, the first output signal will have a voltage between the VDD supply voltage and the VNS control voltage.

[0024] The level shifter device includes a second level shifter disposed after the first level shifter. The second level shifter is configured to convert the first output signal into a second output signal having a voltage between ground and the VDD power supply voltage.

[0025] In implementations, the level shifter device can be configured to variably control its control voltage, such as the VPS control voltage and / or the VNS control voltage. The control voltage can be variably controlled during real-time operation based on environmental factors, such as the temperature of the circuit / device using the level shifter device, process variations, or manufacturing tolerances of wafer parameters. Variable control of the control voltage will take into account the impact of environmental factors on transistor behavior.

[0026] In this implementation, a level shifter device can be connected to the bit line of the memory device and function as a sense amplifier. The bit line can be connected to the memory cell from which its value is to be read. The level shifter device can be used to shift the voltage of the memory cell from a first voltage domain (e.g., a relatively low voltage, such as a voltage below 0.5*VDD) to a second voltage domain (e.g., a relatively high VDD voltage domain, such as 1V) for determining the value stored in the memory cell. In this way, the level shifter device is used to amplify the voltage from the memory cell during a read operation.

[0027] In implementations, a level shifter device can be used as a sensing device comprising one or more sense amplifiers operating in the time domain to determine the state of cells within a memory device (e.g., a level shifter can be connected to the memory device to operate as a sense amplifier). The operation of the sensing device includes a pre-charge phase, an integration phase, and a latching phase. During the pre-charge phase, certain components (e.g., nodes, transistor gates, bit lines, etc.) are pre-charged to a defined voltage. During the integration phase, one or more switches are toggled such that the pre-charged bit line connected to the cell to be read is discharged through the bit line to generate a sense amplifier output to the latch. The time required to discharge the bit line is related to the state of the cell attached to the bit line. During a latching event, the latch closes, and the final value of the latch depends on the sense amplifier output prior to the latching event, which in turn depends on the bit line discharge current. If the latch receives the sense amplifier output before the latch closes, the latch switches from one voltage value to another; otherwise, the voltage value remains within the latch. The state of the cell is determined based on whether the value of the latch changes. It is understandable that various numbers of sensing amplifiers and / or configurations of sensing amplifiers can be used.

[0028] In this implementation, the sensing device offers lower mismatch and improved operation at lower supply voltages due to the absence of a current mirror. The sensing device reduces the number of critical transistors that could introduce mismatch, as even a single transistor can be a potential mismatch factor. The sensing amplifier consumes relatively little power during sensing and avoids interruptions in cell state reads, even at low bit line / cell voltages. The sensing amplifier is able to track and compensate for variability, such as processing and temperature changes. Furthermore, the sensing amplifier enables faster read speeds, which are almost entirely determined by the time constant of the memory device.

[0029] One embodiment of the level shifter device is as follows: Figure 1 An exemplary method 100 is shown, and in combination with Figures 2 to 5 Further description is provided. The level shifter device can be configured, for example, to convert an input signal from a first voltage domain to an output signal in a second voltage domain by amplifying the voltage of the input signal. The level shifter device includes a first-stage level shifter and a second-stage level shifter. Figure 2 A level shifter device 200 according to a first configuration is shown, and Figure 3 A level shifter device 300 according to a second configuration is shown.

[0030] With the first configuration Figure 2The level shifter device 200 includes a first-stage level shifter 208 and a second-stage level shifter 206. At 102, the first-stage level shifter 208 is configured to convert an input signal from input 210 (e.g., a bit line connected to a memory cell of a memory device, a connection to any other type of circuit / device / logic such as a processor, etc.) into a first output signal 222 having a voltage between VPS control voltage 218 and ground 214 (VSS ground). In an embodiment, the first-stage level shifter 208 includes a first transistor, such as a PMOS transistor, and a first device, such as an NMOS transistor, a register, or other device.

[0031] A second-stage level shifter 206 is positioned after the first-stage level shifter 208, such that the first output signal 222 is input to the second-stage level shifter 206. At 104, the second-stage level shifter 206 is configured to convert the first output signal 222 into a second output signal 212 having a voltage between ground 214 and the VDD power supply voltage 220. The second-stage level shifter 206 includes a second transistor, such as an NMOS transistor, and second devices, such as a PMOS transistor, a register, or other devices.

[0032] Figure 5 A first configuration is shown. Figure 2 The level shifter device 500 is an embodiment of the level shifter device 200. The level shifter device 500 includes a first-stage level shifter, which includes a first transistor 508 (e.g., a PMOS transistor) and a first device 512 (e.g., an NMOS transistor depicted in a box with a dashed line X to indicate that the first device 512 may be different from...). Figure 5 The gate of the first transistor 508 is connected to the input signal 504. The source of the first transistor 508 is connected to the VPS control voltage 506. The drain of the first transistor 508 is connected to a first node between the first transistor 508 and the first device 512. The first device 512 is connected to a first signal that, when the first signal is set to a first value (e.g., set to high), allows the first output signal 516 to be precharged to ground 526 (VSS ground). The series connection of the first transistor 508 and the first device 512 is connected between the VPS control voltage 506 and ground 526. When the threshold voltage 502 (Vth, P) of the first transistor 508 is reached, the first transistor 508 outputs the first output signal 516 to the first node connected to the second-stage level shifter. The second-stage level shifter includes a second transistor 520 (e.g., an NMOS transistor) and a second device 510 (e.g., a PMOS transistor depicted in a box with a dashed line X to indicate that the second device 510 may be different). Figure 5(The transistor shown). In the embodiment, the VPS control voltage 506 is a positive voltage relative to ground 526.

[0033] In this implementation, the second transistor 520 of the second-stage level shifter includes an NMOS transistor, and the second device 510 includes a PMOS transistor, a register, or other devices. The gate of the second transistor 520 is connected to a first output signal 516. The second device 510 is connected to a second signal that, when the second signal is set to a second value (e.g., set low), allows the second output signal 518 to be pre-charged to the VDD supply voltage 514. For example, when a threshold voltage 524 (Vth, N) is reached, a second node between the second transistor 520 and the second device 510 supplies the second output signal 518. The series connection between the second transistor 520 and the second device 510 is connected between the VDD supply voltage 514 and ground 526.

[0034] Figure 5 Timing diagram 550 depicts an x-axis representing time and a y-axis representing voltage. At a first time point 552, the input signal 504 (e.g., the VBL voltage corresponding to the bit line voltage) is between the VDD supply voltage 514 and ground 526, and the VPS control voltage 506 is the sum of the input signal 504 (e.g., the VBL voltage) and the threshold voltage 502 (Vth, P) of the first transistor 508. At a second time point 554, the input signal 504 begins to discharge to ground 526. At a third time point 556 (e.g., when the threshold voltage 502 (Vth, P) is reached), the first output signal 516 flows from ground 526 to the VPS control voltage 506. At a fourth time point 558 (e.g., when the threshold voltage 524 (Vth, N) is reached), the second output signal 518 flows from the VDD supply voltage 514 to ground 526.

[0035] In this implementation, the VPS control voltage 506 (or VPS control voltage 218) is variably adjusted during operation based on various factors. For example, the VPS control voltage 506 may be variably adjusted based on environmental factors such as the temperature of the level shifter device 500 or the circuitry surrounding the level shifter device 500, process variations, or manufacturing tolerances of wafer parameters. The VPS control voltage 506 is variably adjusted to account for how temperature affects the operation of the transistors within the level shifter device 500. In this implementation, the VPS control voltage 506 is adjusted to track the threshold voltage of the transistors within the level shifter device 500, such as threshold voltage 502 (Vth, P). In this example, threshold voltage 502 (Vth, P) is added to the voltage of the input signal 504 to obtain the VPS control voltage 506.

[0036] In one embodiment, the input of the level shifter device 500 is connected to the storage device. In another embodiment, the level shifter device 500 is connected to the storage device such that it can be used as a sense amplifier for the storage device. For example, the input of the level shifter device 500 can be connected to a bit line of the storage device. The bit line is connected to the storage cell to be read. Therefore, the level shifter device 500 functions as a sense amplifier to shift the voltage of the input signal 504 from the storage cell's voltage domain (e.g., a relatively low voltage) to another voltage domain (e.g., a relatively high voltage) as a second output signal 518. The second output signal is output to a latch controlled by a reference sense amplifier to determine whether the storage cell stores a specific value in the time domain. If the reference signal from the reference sense amplifier decreases faster than the second output signal 518 corresponding to the actual data read from the storage cell, the latch will close before the second output signal 518 can pass through the latch. If the reference signal decreases slower than the second output signal 518, the second output signal 518 passes through the latch. In this way, the value stored in the memory cell can be detected based on whether the second output signal 518 passes through the latch.

[0037] With a second configuration Figure 3 The level shifter device 300 includes a first-stage level shifter 308 and a second-stage level shifter 306. At 102, the first-stage level shifter 308 is configured to convert an input signal from input 310 (e.g., a bit line connected to a memory cell of a memory device, a connection to any other type of circuit / device / logic such as a processor, etc.) into a first output signal 322 having a voltage between the VDD supply voltage 318 and the VNS control voltage 314. In an embodiment, the first-stage level shifter 308 includes a first transistor, such as an NMOS transistor, and a first device, such as a PMOS transistor, a register, or other device.

[0038] A second-stage level shifter 306 is positioned after the first-stage level shifter 308, such that the first output signal 322 is input to the second-stage level shifter 306. At 104, the second-stage level shifter 306 is configured to convert the first output signal 322 into a second output signal 312 having a voltage between ground 316 and the VDD power supply voltage 318. The second-stage level shifter 306 includes a second transistor, such as a PMOS transistor, and second devices, such as an NMOS transistor, a register, or other devices.

[0039] Figure 4 A first configuration is shown. Figure 3The level shifter device 400 is an embodiment of the level shifter device 300. The level shifter device 400 includes a first-stage level shifter, which includes a first transistor 404 (e.g., an NMOS transistor) and a first device 402 (e.g., a PMOS transistor depicted in a box with a dashed line X to indicate that the first device 402 may be different from...). Figure 4 (The transistor shown). The gate of the first transistor 404 is connected to the input signal 410. The first transistor 404 is connected to a first node between the first transistor 404 and the first device 402. The first transistor 404 is connected to the VNS control voltage 422. The first device 402 is connected to a first signal that, when the first signal is set to a first value, allows the first output signal 412 to be pre-charged to the VDD supply voltage 418. The series connection of the first transistor 404 and the first device 402 is connected between the VDD supply voltage 418 and the VNS control voltage 422. When the threshold voltage 414 (Vth, N) of the first transistor 404 is reached, the first transistor 404 outputs the first output signal 412 to the first node connected to the second-stage level shifter. The second-stage level shifter includes a second transistor 406 (e.g., a PMOS transistor) and a second device 408 (e.g., an NMOS transistor depicted in a box with a dashed line X to indicate that the second device 408 may be different). Figure 4 (The transistor shown).

[0040] In this implementation, the second transistor 406 of the second-stage level shifter includes a PMOS transistor, and the second device 408 includes an NMOS transistor, a register, or other devices. The gate of the second transistor 406 is connected to a first output signal 412. The second device 408 is connected to a second signal that, when the second signal is set to a second value, allows the second output signal 416 to be pre-charged to ground 420. For example, when a threshold voltage 424 (Vth, P) is reached, a second node between the second transistor 406 and the second device 408 supplies the second output signal 416. The series connection between the second transistor 406 and the second device 408 is connected between the VDD power supply voltage 418 and ground 420.

[0041] Figure 4Timing diagram 450 depicts an x-axis representing time and a y-axis representing voltage. At a first time point 452, the input signal 410 (e.g., the VBL voltage corresponding to the bit line voltage) is between the VDD supply voltage 418 and the VNS control voltage 422, and the VNS control voltage 422 is the difference between the input signal 410 (e.g., the VBL voltage) and the threshold voltage 414 (Vth, N) of the first transistor 404. At a second time point 454, the input signal 410 begins to transition to the VDD supply voltage 418. At a third time point 456 (e.g., when the threshold voltage 414 (Vth, N) is reached), the first output signal 412 transitions from the VDD supply voltage 418 to the VNS control voltage 422. At a fourth time point 458 (e.g., when the threshold voltage 424 (Vth, P) is reached), the second output signal 416 transitions from ground 420 to the VDD supply voltage 418.

[0042] In implementations, the VNS control voltage 422 (or VNS control voltage 314) is variably adjusted during operation based on various factors. For example, the VNS control voltage 422 is variably adjusted based on environmental factors such as the temperature of the level shifter device 400 or the circuitry surrounding the level shifter device 400, process variations, or manufacturing tolerances of wafer parameters. The VNS control voltage 422 is variably adjusted to account for how temperature affects the operation of the transistors within the level shifter device 400. In implementations, the VNS control voltage 422 is adjusted to track the threshold voltage (e.g., threshold voltage 414(Vth, N)) of the transistors within the level shifter device 400. In an example where the transistor is an NMOS transistor and the VNS control voltage 422 is less than the VDD supply voltage 418, the VNS control voltage 422 is obtained by subtracting the threshold voltage 414(Vth, N) from the voltage of the input signal 410.

[0043] In one embodiment, the input of the level shifter device 400 is connected to the storage device. In another embodiment, the level shifter device 400 is connected to the storage device such that it can function as a sense amplifier for the storage device. For example, the input of the level shifter device 400 can be connected to a bit line of the storage device. The bit line is connected to the memory cell to be read. Therefore, the level shifter device 400 functions as a sense amplifier to shift the voltage of the input signal 410 from the storage cell's voltage domain (e.g., a relatively low voltage) to another voltage domain (e.g., a relatively high voltage) as a second output signal 416. This second output signal is output to a latch controlled by a reference sense amplifier to determine whether the memory cell stores a specific value in the time domain. If the reference signal from the reference sense amplifier drops faster than the second output signal 416 corresponding to the actual data being read from the memory cell, the latch will close before the second output signal 416 can pass through the latch. If the reference signal drops slower than the second output signal 416, the second output signal 416 passes through the latch. In this way, the value stored in the memory cell can be detected based on whether the second output signal 416 passes through the latch.

[0044] Another embodiment relates to a computer-readable medium including processor-executable instructions configured to apply the techniques described herein. Such a computer-readable medium may include various types of communication media, such as signals that can propagate through various physical phenomena (e.g., electromagnetic signals, acoustic signals, or optical signals) and signals propagating in various wired scenarios (e.g., via Ethernet or fiber optic cables) and / or wireless scenarios (e.g., wireless local area networks (WLANs) such as WiFi, personal area networks (PANs) such as Bluetooth, or cellular or radio networks), and such a computer-readable medium encodes a set of computer-readable instructions that, when executed by a processor of a device, cause the device to implement the techniques described herein. Such computer-readable media may also include (as a class of technologies excluding communication media) computer-readable storage devices, such as storage semiconductors (e.g., semiconductors utilizing static random access memory (SRAM), dynamic random access memory (DRAM) and / or synchronous dynamic random access memory (SDRAM) technologies), hard disk platters, flash memory devices, or magnetic disks or optical disks (e.g., CD-R, DVD-R, or floppy disks). Such computer-readable media encodes a set of computer-readable instructions that, when executed by the processor of a device, enable the device to implement the techniques described herein.

[0045] Figure 6Example computer-readable media that can be designed in these ways are shown, wherein implementation 600 includes a computer-readable storage device 602 (e.g., a CD-R, DVD-R, or hard disk disk) on which computer-readable data 604 is encoded. The computer-readable data 604 further includes a computer instruction set 606 that, when executed on a processor 612 of device 610, provides implementations that enable device 610 to operate according to the techniques presented herein. Many such computer-readable media can be designed by those skilled in the art and configured to operate according to the techniques described herein. In some embodiments, the processor-executable computer instructions 606 are configured to perform method 608, for example, such as... Figure 1 At least some of the exemplary methods 100. In some embodiments, processor-executable computer instructions 604 are configured to implement the system, for example, Figure 2 At least some of the exemplary level shifter devices 200 Figure 3 At least some of the exemplary level shifters 300 Figure 4 At least some and / or of the exemplary level shifter devices 400 Figure 5 At least some of the exemplary level shifter devices 500. Many such computer-readable media are intended to operate according to the techniques described herein.

[0046] Figure 7 The following discussion provides a brief, general description of a suitable computing environment for implementing one or more of the implementation methods set forth herein. Figure 7 The operating environment described is merely an example of a suitable working environment and is not intended to impose any limitations on the scope or functionality of the working environment. Example computing devices include, but are not limited to, personal computers, server computers, handheld or laptop devices, mobile devices (e.g., mobile phones, personal digital assistants (PDAs), media players, etc.), multiprocessor systems, consumer electronics, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices.

[0047] Although not strictly required, the various implementations are described in the general context of computer-readable instructions executed by one or more computing devices. Computer-readable instructions may be distributed via computer-readable media (discussed below). Computer-readable instructions may be implemented as program modules that perform specific tasks or implement specific abstract data types, such as functions, objects, application programming interfaces (APIs), data structures, etc. Typically, the functionality of computer-readable instructions can be combined or distributed as needed in various environments.

[0048] Figure 7Example 700 of a system including a computing device 702 configured to implement one or more embodiments provided herein is shown. In one configuration, the computing device 702 includes a processing unit 706 and a memory 708. Depending on the exact configuration and type of the computing device, the memory 708 may be volatile (e.g., RAM), non-volatile (e.g., ROM, flash memory, etc.), or some combination of both. This configuration in Figure 7 It is indicated by the dashed line 704.

[0049] As provided herein, a sensing device may be used in memory 708 and / or storage device 710 to improve the accuracy of reading cells within memory 708 and / or storage device 710.

[0050] In some embodiments, device 702 may include additional features and / or functions. For example, device 702 may also include additional storage devices (e.g., removable and / or non-removable storage devices), including but not limited to magnetic storage devices, optical storage devices, etc. Such additional storage devices... Figure 7 The image is shown in storage device 710. In one embodiment, computer-readable instructions for implementing one or more embodiments provided herein may be stored in storage device 710. Storage device 710 may also store computer-readable instructions for implementing operating systems, applications, etc. Computer-readable instructions may be loaded into memory 708 for execution, for example, by processing unit 706.

[0051] As used herein, the term "computer-readable medium" includes computer storage media. Computer storage media includes volatile and non-volatile, removable and non-removable media implemented using any method or technology for storing information such as computer-readable instructions or other data. Memory 708 and storage device 710 are examples of computer storage media. Computer storage media include, but are not limited to: RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage devices, magnetic tape, magnetic tape, disk storage devices or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by computer device 702. Any such computer storage medium may be part of device 702.

[0052] Device 702 may also include a communication connection 716 that allows device 702 to communicate with other devices. Communication connection 716 may include, but is not limited to, a modem, network interface card (NIC), integrated network interface, radio frequency transmitter / receiver, infrared port, USB connection, or other interface for connecting device 702 to other computing devices. Communication connection 716 may include a wired connection or a wireless connection. Communication connection 716 can send and / or receive communication media.

[0053] The term "computer-readable medium" can include communication media. Communication media typically embody computer-readable instructions or other data as "modulated data signals" using mechanisms such as carrier waves or other transmission mechanisms, and include any information transmission medium. The term "modulated data signal" can include a signal having one or more characteristics that are set or altered in a manner that encodes information in the signal.

[0054] Device 702 may include input devices 714, such as a keyboard, mouse, pen, voice input device, touch input device, infrared camera, video input device, and / or any other input device. Device 702 may also include output devices 712, such as one or more displays, speakers, printers, and / or any other output devices. Input devices 714 and output devices 712 may be connected to device 702 via wired connections, wireless connections, or any combination thereof. In one embodiment, an input device or output device from another computing device may be used as input device 714 or output device 712 of computing device 702.

[0055] The components of device 702 can be connected via various interconnects such as buses. Such interconnects may include peripheral component interconnects (PCI), such as PCI Express, Universal Serial Bus (USB), FireWire (IEEE 794), optical bus architectures, etc. In some embodiments, the components of device 702 may be interconnected via a network. For example, memory 708 may include multiple physical memory cells located at different physical locations interconnected via a network.

[0056] Those skilled in the art will recognize that storage devices for storing computer-readable instructions can be distributed across a network. For example, computing device 720, accessible via network 718, can store computer-readable instructions to implement one or more of the embodiments provided herein. Computing device 702 can access computing device 720 and download some or all of the computer-readable instructions for execution. Alternatively, computing device 702 may download fragments of computer-readable instructions as needed, or some instructions may be executable at computing device 702 while others may be executable at computing device 720.

[0057] The currently disclosed technology includes a level shifter device. The level shifter device includes: a first-stage level shifter configured to convert an input signal from a bit line connected to at least one memory cell of a memory device into a first output signal having a voltage between a VPS control voltage and ground, or between a VDD power supply voltage and a VNS control voltage; and a second-stage level shifter disposed after the first-stage level shifter and configured to convert the first output signal into a second output signal having a voltage between ground and the VDD power supply voltage.

[0058] According to some implementations, a level shifter device is part of a sensing amplifier configured to determine the state of a storage cell in a storage device.

[0059] According to some embodiments, a first-stage level shifter includes a first transistor and a first device, wherein the gate of the first transistor is connected to an input signal, wherein the first device is connected to a first signal that, when set to a first value, allows a first output signal to be pre-charged to ground, wherein a first node between the first transistor and the first device supplies the first output signal, and wherein a series connection between the first transistor and the first device is connected between a VPS control voltage and ground.

[0060] According to some implementations, the first transistor includes a PMOS transistor and the first device includes an NMOS transistor.

[0061] According to some embodiments, the second-stage level shifter includes a second transistor and a second device, wherein the gate of the second transistor is connected to a first output signal and the second device is connected to a second signal, the second signal allowing the second output signal to be pre-charged to a VDD power supply voltage when set to a second value, wherein a second node between the second transistor and the second device supplies the second output signal, and wherein the series connection between the second transistor and the second device is connected between the VDD power supply voltage and ground.

[0062] According to some implementations, the second transistor includes an NMOS transistor and the second device includes a PMOS transistor.

[0063] According to some embodiments, a first-stage level shifter includes a first transistor and a first device, wherein the gate of the first transistor is connected to an input signal, wherein the first device is connected to a first signal, wherein the first signal, when set to a first value, allows a first output signal to be pre-charged to a VDD power supply voltage, wherein a first node between the first transistor and the first device supplies the first output signal, and wherein the series connection between the first transistor and the first device is connected between the VDD power supply voltage and the VNS control voltage.

[0064] According to some implementations, the first transistor includes an NMOS transistor and the first device includes a PMOS transistor.

[0065] According to some embodiments, the second-stage level shifter includes a second transistor and a second device, wherein the gate of the second transistor is connected to a first output signal and the second device is connected to a second signal, the second signal allowing the second output signal to be pre-charged to a VDD power supply voltage when set to a second value, wherein a second node between the second transistor and the second device supplies the second output signal, and wherein the series connection between the second transistor and the second device is connected between the VDD power supply voltage and ground.

[0066] According to some implementations, the second transistor includes a PMOS transistor and the second device includes an NMOS transistor.

[0067] According to some implementations, the storage device includes a random access memory (RAM) device.

[0068] The currently disclosed technology includes a level shifter device. The level shifter device includes: a first-stage level shifter configured to convert an input signal into a first output signal having a voltage between a VPS control voltage and ground, or between a VDD power supply voltage and a VNS control voltage; and a second-stage level shifter disposed after the first-stage level shifter and configured to convert the first output signal into a second output signal having a voltage between ground and the VDD power supply voltage, wherein at least one of the VPS control voltage or the VNS control voltage is variably adjusted.

[0069] According to some implementations, at least one of the VPS control voltage or VNS control voltage is variably adjusted based on at least one of environmental factors, process variations, or manufacturing tolerances of wafer parameters.

[0070] According to some implementations, at least one of the VPS control voltage or VNS control voltage is variably adjusted based on temperature.

[0071] According to some implementations, the first-stage level shifter includes at least one transistor, and wherein at least one memory cell of the VPS control voltage or the VNS control voltage tracks the threshold voltage of the at least one transistor.

[0072] According to some implementations, a threshold voltage is added to or subtracted from the input signal to obtain at least one of the VPS control voltage or the VNS control voltage.

[0073] According to some implementations, the first-stage level shifter includes a PMOS transistor and the second-stage level shifter includes an NMOS transistor, wherein the VPS control voltage is positive relative to ground.

[0074] According to some implementations, the first-stage level shifter includes an NMOS transistor and the second-stage level shifter includes a PMOS transistor.

[0075] Embodiments of this disclosure include a method. The method includes controlling a first-stage level shifter to convert an input signal to output a first output signal having a voltage between a VPS control voltage and ground, or between a VDD power supply voltage and a VNS control voltage; and controlling a second-stage level shifter disposed after the first-stage level shifter to convert the first output signal into a second output signal having a voltage between ground and the VDD power supply voltage.

[0076] According to some implementations, the input signal is received from a bit line connected to at least one memory cell of the storage device.

[0077] According to some implementations, the method includes variably adjusting at least one of the VPS control voltage or VNS control voltage based on at least one of environmental factors, process variations, or manufacturing tolerances of wafer parameters.

[0078] According to some embodiments, a first-stage level shifter includes a first transistor and a first device, wherein the gate of the first transistor is connected to an input signal, wherein the first device is connected to a first signal that, when set to a first value, allows a first output signal to be pre-charged to ground, wherein a first node between the first transistor and the first device supplies the first output signal, and wherein a series connection between the first transistor and the first device is connected between a VPS control voltage and ground.

[0079] According to some embodiments, the second-stage level shifter includes a second transistor and a second device, wherein the gate of the second transistor is connected to a first output signal and the second device is connected to a second signal, the second signal allowing the second output signal to be pre-charged to a VDD power supply voltage when set to a second value, wherein a second node between the second transistor and the second device supplies the second output signal, and wherein the series connection between the second transistor and the second device is connected between the VDD power supply voltage and ground.

[0080] According to some embodiments, a first-stage level shifter includes a first transistor and a first device, wherein the gate of the first transistor is connected to an input signal, wherein the first device is connected to a first signal, wherein the first signal, when set to a first value, allows a first output signal to be pre-charged to a VDD power supply voltage, wherein a first node between the first transistor and the first device supplies the first output signal, and wherein the series connection between the first transistor and the first device is connected between the VDD power supply voltage and the VNS control voltage.

[0081] According to some embodiments, the second-stage level shifter includes a second transistor and a second device, wherein the gate of the second transistor is connected to a first output signal and the second device is connected to a second signal, the second signal allowing the second output signal to be pre-charged to a VDD power supply voltage when set to a second value, wherein a second node between the second transistor and the second device supplies the second output signal, and wherein the series connection between the second transistor and the second device is connected between the VDD power supply voltage and ground.

[0082] Embodiments of the present disclosure include an apparatus comprising: means for controlling a first-stage level shifter to convert an input signal to output a first output signal, the first output signal having a voltage between a VPS control voltage and ground, or between a VDD power supply voltage and a VNS control voltage; and means for controlling a second-stage level shifter disposed after the first-stage level shifter to convert the first output signal into a second output signal, the second output signal having a voltage between ground and the VDD power supply voltage.

[0083] Although the subject matter has been described in language specific to structural features and / or methodological actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as exemplary forms of implementing the claims.

[0084] As used in this application, the terms “component,” “module,” “system,” “interface,” etc., are generally intended to refer to a computer-related entity, hardware, a combination of hardware and software, software, or software in execution. One or more components may be located on a single computer and / or distributed between two or more computers.

[0085] Furthermore, the claimed subject matter can be implemented as a method, apparatus, or article of manufacture using standard programming and / or engineering techniques to produce software, firmware, hardware, or any combination thereof to control a computer to implement the disclosed subject matter. As used herein, the term "article of manufacture" is intended to include computer programs accessible from any computer-readable device, carrier, or medium. Of course, those skilled in the art will recognize that many modifications can be made to this configuration without departing from the scope or spirit of the claimed subject matter.

[0086] This document provides various operations for each implementation. In one implementation, one or more of the described operations may constitute computer-readable instructions stored on one or more computer-readable media, which, if executed by a computing device, would cause the computing device to perform the described operations. The order in which some or all of the operations are described should not be construed as implying that these operations must depend on a specific order. Alternative orderings will be understood by those skilled in the art who benefit from this specification. Furthermore, it will be understood that not all operations must be present in every implementation provided herein.

[0087] Any aspect or design described herein as an “example” is not necessarily to be construed as advantageous over other aspects or designs. Rather, the use of the word “example” is intended to present one possible aspect and / or implementation that may be relevant to the technology presented herein. Such examples are not necessary for such technology or are intended to be limiting. Various implementations of such technology may include such examples alone or in combination with other features, and / or the examples shown may be modified and / or omitted.

[0088] As used in this application, the term "or" means inclusive "or," not exclusive "or." That is, unless otherwise specified or clear from the context, "X adopts A or B" means any natural inclusive arrangement. That is, if X adopts A, X adopts B, or X adopts both A and B, then "X adopts A or B" is satisfied in any of the foregoing cases. Additionally, unless otherwise specified or clearly addressed to the singular form from the context, the articles "a" and "an" as used in this application and the appended claims can generally be interpreted as meaning "one or more." Furthermore, unless otherwise specified, "first," "second," etc., are not intended to imply temporal, spatial, or sequential aspects. Rather, such terms are used only as identifiers, names, etc., of features, elements, items, etc. For example, a first element and a second element generally correspond to element A and element B, or two different or two identical elements, or the same element.

[0089] Furthermore, while this disclosure has been shown and described with respect to one or more implementations, equivalent changes and modifications will occur to those skilled in the art based on a reading and understanding of this specification and drawings. This disclosure includes all such modifications and changes and is limited only by the scope of the following claims. In particular, with respect to the various functions performed by the foregoing components (e.g., elements, resources, etc.), unless otherwise indicated, the terminology used to describe such components is intended to correspond to any component that performs the specified function of the described component (e.g., functionally equivalent), even where the function performed in the example implementations shown herein is not structurally equivalent to the disclosed structure. Additionally, although a particular feature of this disclosure may be disclosed only with respect to one of several implementations, such features may be combined as desired and advantageously for any given or particular application with one or more other features of other implementations. Furthermore, with regard to the terms “includes,” “having,” “has,” “with,” or variations thereof used in the detailed description and claims, such terms are intended to be included in a manner similar to the term “comprising.”

Claims

1. A level shifter device, comprising: A first-stage level shifter is configured to convert an input signal from a bit line connected to at least one memory cell of a storage device into a first output signal, the first output signal having a voltage between the VPS control voltage and ground, or between the VDD power supply voltage and the VNS control voltage. as well as A second-stage level shifter, disposed after the first-stage level shifter and configured to convert the first output signal into a second output signal having a voltage between ground and the VDD power supply voltage, is also present. The first-stage level shifter includes a first transistor and a first device, wherein the gate of the first transistor is connected to the input signal, and the first device is connected to a first signal different from the input signal.

2. The level shifter device according to claim 1, wherein, The level shifter device is part of a sensing amplifier configured to determine the state of the memory cells in the memory device.

3. The level shifter device according to claim 1, wherein, When the first signal is set to a first value, it allows the first output signal to be precharged to ground, wherein a first node between the first transistor and the first device supplies the first output signal, and wherein the series connection between the first transistor and the first device is connected between the VPS control voltage and ground.

4. The level shifter device according to claim 3, wherein, The first transistor includes a PMOS transistor, and the first device includes an NMOS transistor.

5. The level shifter device according to claim 3, wherein, The second-stage level shifter includes a second transistor and a second device, wherein the gate of the second transistor is connected to the first output signal, and the second device is connected to a second signal different from the first output signal, the second signal allowing the second output signal to be precharged to the VDD power supply voltage when set to a second value, wherein a second node between the second transistor and the second device supplies the second output signal, and wherein the series connection between the second transistor and the second device is connected between the VDD power supply voltage and ground.

6. The level shifter device according to claim 5, wherein, The second transistor includes an NMOS transistor, and the second device includes a PMOS transistor.

7. The level shifter device according to claim 1, wherein, When the first signal is set to a first value, it allows the first output signal to be precharged to the VDD power supply voltage, wherein the first node between the first transistor and the first device supplies the first output signal, and wherein the series connection between the first transistor and the first device is connected between the VDD power supply voltage and the VNS control voltage.

8. The level shifter device according to claim 7, wherein, The first transistor includes an NMOS transistor, and the first device includes a PMOS transistor.

9. The level shifter device according to claim 7, wherein, The second-stage level shifter includes a second transistor and a second device, wherein the gate of the second transistor is connected to the first output signal, and the second device is connected to a second signal different from the first output signal, the second signal allowing the second output signal to be precharged to the VDD power supply voltage when set to a second value, wherein a second node between the second transistor and the second device supplies the second output signal, and wherein the series connection between the second transistor and the second device is connected between the VDD power supply voltage and ground.

10. The level shifter device according to claim 9, wherein, The second transistor includes a PMOS transistor, and the second device includes an NMOS transistor.

11. The level shifter device according to claim 1, wherein, The storage device includes a random access memory device.

12. A level shifter device, comprising: A first-stage level shifter is configured to convert an input signal into a first output signal, the first output signal having a voltage between the VPS control voltage and ground, or between the VDD power supply voltage and the VNS control voltage. as well as A second-stage level shifter, arranged after the first-stage level shifter and configured to convert the first output signal into a second output signal having a voltage between ground and the VDD power supply voltage, wherein at least one of the VPS control voltage and the VNS control voltage is variably adjustable. The first-stage level shifter includes a first transistor and a first device, wherein the gate of the first transistor is connected to the input signal, and the first device is connected to a first signal different from the input signal.

13. The level shifter device according to claim 12, wherein, At least one of the VPS control voltage and the VNS control voltage is variably adjustable based on at least one of environmental factors, process variations, and manufacturing tolerances of wafer parameters.

14. The level shifter device according to claim 12, wherein, At least one of the VPS control voltage and the VNS control voltage is variably adjusted based on temperature.

15. The level shifter device according to claim 12, wherein, The first-stage level shifter includes at least one transistor, and wherein at least one of the VPS control voltage and the VNS control voltage tracks the threshold voltage of the at least one transistor.

16. The level shifter device according to claim 15, wherein, The threshold voltage is added to or subtracted from the input signal to obtain the VPS control voltage or the VNS control voltage.

17. The level shifter device according to claim 12, wherein, The first-stage level shifter includes a PMOS transistor, and the second-stage level shifter includes an NMOS transistor, wherein the VPS control voltage is positive relative to ground.

18. The level shifter device according to claim 12, wherein, The first-stage level shifter includes an NMOS transistor, and the second-stage level shifter includes a PMOS transistor.

19. A method for converting signal voltage, comprising: The first-stage level shifter is controlled to convert the input signal to output a first output signal, the first output signal having a voltage between the VPS control voltage and ground, or between the VDD power supply voltage and the VNS control voltage; as well as A second-stage level shifter, arranged after the first-stage level shifter, is controlled to convert the first output signal into a second output signal having a voltage between ground and the VDD power supply voltage. The first-stage level shifter includes a first transistor and a first device, wherein the gate of the first transistor is connected to the input signal, and the first device is connected to a first signal different from the input signal.

20. The method according to claim 19, wherein, The input signal is received from a bit line connected to at least one memory cell of the storage device.

21. The method of claim 19, comprising: At least one of the VPS control voltage and the VNS control voltage can be variably adjusted based on at least one of environmental factors, process variations, and manufacturing tolerances of wafer parameters.

22. The method according to claim 19, wherein, When the first signal is set to a first value, it allows the first output signal to be precharged to ground, wherein a first node between the first transistor and the first device supplies the first output signal, and wherein the series connection between the first transistor and the first device is connected between the VPS control voltage and ground.

23. The method according to claim 22, wherein, The second-stage level shifter includes a second transistor and a second device, wherein the gate of the second transistor is connected to the first output signal and the second device is connected to a second signal different from the first output signal, the second signal allowing the second output signal to be precharged to the VDD power supply voltage when set to a second value, wherein a second node between the second transistor and the second device supplies the second output signal, and wherein the series connection between the second transistor and the second device is connected between the VDD power supply voltage and ground.

24. The method according to claim 19, wherein, When the first signal is set to a first value, it allows the first output signal to be precharged to the VDD power supply voltage, wherein the first node between the first transistor and the first device supplies the first output signal, and wherein the series connection between the first transistor and the first device is connected between the VDD power supply voltage and the VNS control voltage.

25. The method according to claim 24, wherein, The second-stage level shifter includes a second transistor and a second device, wherein the gate of the second transistor is connected to the first output signal and the second device is connected to a second signal different from the first output signal, the second signal allowing the second output signal to be precharged to the VDD power supply voltage when set to a second value, wherein a second node between the second transistor and the second device supplies the second output signal, and wherein the series connection between the second transistor and the second device is connected between the VDD power supply voltage and ground.

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