A detection circuit and detection method of a DRED controller and an energy storage inverter

Abstract

The present invention discloses a detection circuit, a detection method and an energy storage inverter of a DRED controller. A detection circuit of a DRED controller includes a controller, and the detection circuit also includes: a first communication line, a second communication line, a third communication line, a fourth communication line and a fifth communication line; a first detection resistor, a second detection resistor, a third detection resistor, a fourth detection resistor and a fifth detection resistor. The detection circuit uses its own five AD ports to judge the switch state of each controlled switch S0 to S9, uses a small number of electronic components, has a simple circuit structure, simple and clear logic, is easy to operate and easy to implement; the energy storage inverter using the detection circuit and the detection method can respond to the state of the controlled switch in time, can perform corresponding operations according to the state of the controlled switch, uses a small number of electronic components, can reduce costs, reduce occupied space, and optimize product volume.

Description

Technical Field

[0001] The invention belongs to the field of inverters and relates to a detection circuit and a detection method of a DRED controller and an energy storage inverter. Background Art

[0002] In 2016, the Australian Power Grid Company released the latest safety standard "AS NZS 4777.2-2015" for photovoltaic grid-connected inverters and photovoltaic energy storage inverters in Australia and New Zealand. It also requires that all photovoltaic inverters sold to Australia and New Zealand after mid-July 2016 must comply with the latest safety standards. DRMs (Demand Response Modes) were newly added to the "AS NZS 4777.2-2015" safety standard: using an external control box---DRED (Demand Response Enabling Device) interface to transmit instructions to control the input and output of the energy storage inverter.

[0003] The existing DRED detection circuit is usually mainly composed of 8-3 encoder, MCU, operational amplifier, detection resistor and other devices, and uses six or eight communication lines to detect the closed state of ten controlled switches. However, DRED has many controlled switch states and cannot accurately detect the specific state of each controlled switch. At the same time, the circuit is complex, occupies a large volume and has a high cost. Summary of the invention

[0004] In order to solve the above technical problems, an object of the present invention is to provide a detection circuit of a DRED controller, which can realize accurate detection of a controlled switch of the DRED controller by using fewer devices and simpler logic.

[0005] Another object of the present invention is to provide a detection method for a DRED controller, which can realize accurate detection of a controlled switch of the DRED controller by using fewer devices and relatively simple logic.

[0006] Another object of the present invention is to provide an energy storage inverter that can accurately detect the controlled switches of a DRED controller with fewer devices and simpler logic.

[0007] In order to achieve the above object, a technical solution adopted by the present invention is:

[0008] A detection circuit of a DRED controller, comprising a controller, wherein the detection circuit further comprises:

[0009] A first communication line, one end of which is connected to the first input port of the controller, and the other end is used to connect the intermediate node of the controlled switches S1 and S5 of the DRED controller;

[0010] A second communication line, one end of which is connected to the second input port of the controller, and the other end is used to connect the intermediate node of the controlled switches S2 and S6 of the DRED controller;

[0011] A third communication line, one end of which is connected to the third input port of the controller, and the other end is used to connect the intermediate node of the controlled switches S3 and S7 of the DRED controller;

[0012] a fourth communication line, one end of which is connected to the fourth input port of the controller, and the other end of which is used to connect the intermediate node of the controlled switches S4 and S8 of the DRED controller;

[0013] a fifth communication line, one end of which is connected to the fifth input port of the controller, and the other end of which is used to be grounded through the controlled switches S9 and S0 of the DRED circuit;

[0014] A first detection resistor, one end of which is connected to a power supply, and the other end of which is connected to the first communication line;

[0015] A second detection resistor, one end of which is connected to the power supply, and the other end of which is connected to the second communication line;

[0016] A third detection resistor, one end of which is connected to the power supply, and the other end of which is connected to the third communication line;

[0017] a fourth detection resistor, one end of which is connected to the power supply, and the other end of which is connected to the fourth communication line; and

[0018] A fifth detection resistor, one end of which is connected to the power supply, and the other end of which is connected to the fifth communication line.

[0019] In a preferred embodiment, the controller is an MCU chip, and the first input port, the second input port, the third input port, the fourth input port and the fifth input port are AD ports of the MCU chip respectively.

[0020] In a preferred embodiment, the controller is used to identify the levels of voltage sampling signals input by the first input port, the second input port, the third input port, the fourth input port and the fifth input port, and determine the switching state of the controlled switches S0 to S9 of the DRED controller according to the levels of each voltage sampling signal.

[0021] In a preferred embodiment, the voltage sampling signal has three levels: Vcc, Vm and 0V, and Vcc>Vm>0.

[0022] In a preferred embodiment, the detection circuit further includes:

[0023] a signal sampling terminal DRM1 / 5, connected to the first input port and to the first communication line;

[0024] a signal sampling terminal DRM2 / 6, connected to the second input port and to the second communication line;

[0025] a signal sampling terminal DRM3 / 7, connected to the third input port and to the third communication line;

[0026] a signal sampling terminal DRM4 / 8, connected to the fourth input port and to the fourth communication line;

[0027] a signal sampling terminal COM LOAD, connected to the fifth input port and to the fifth communication line;

[0028] The signal sampling terminal DRM1 / 5, the signal sampling terminal DRM2 / 6, the signal sampling terminal DRM3 / 7, the signal sampling terminal DRM4 / 8 and the signal sampling terminal COM LOAD are respectively used to sample the voltage signal, and output the sampled signal to the first input port, the second input port, the third input port, the fourth input port and the fifth input port respectively.

[0029] The present invention also adopts the following technical solution:

[0030] A detection method for a DRED controller, using the detection circuit as described above, the detection method includes identifying the levels of voltage sampling signals input by the first input port, the second input port, the third input port, the fourth input port and the fifth input port, and judging the switching state of the controlled switches S0 to S9 of the DRED controller according to the levels of each voltage sampling signal.

[0031] In a preferred embodiment, the voltage sampling signal has three levels of Vcc, Vm and 0V, Vcc>Vm>0. More preferably, Vm is a value range between Vcc and 0, and the difference between its upper and lower endpoints is not greater than 0.5V. In a specific and preferred embodiment, Vcc is 3.3V, and Vm is 1.9-2.13V.

[0032] In a preferred and specific embodiment, the level of the first input port corresponds to the controlled switches S1 and S5, the level of the second input port corresponds to the controlled switches S2 and S6, the level of the third input port corresponds to the controlled switches S3 and S7, and the level of the fourth input port corresponds to the controlled switches S4 and S8;

[0033] When the levels of the first and fifth input ports are Vcc and Vm respectively, if the level of one or more ports among the second to third input ports is Vm, the controlled switch S9 and the controlled switches S2 / S3 / S4 corresponding to the one or more ports are turned on, and the other controlled switches are turned off; if the level of the other input ports is 0, the controlled switch S9 and the controlled switches S6 / S7 / S8 corresponding to the one or more ports are turned on, and the other controlled switches are turned off; if the levels of the other input ports are all Vcc, only the controlled switch S9 is turned on, and the other controlled switches are turned off;

[0034] When the levels of the first and fifth input ports are both Vm, if the level of one or more ports among the second to third input ports is Vm, the controlled switches S1, S9 and the controlled switches S2 / S3 / S4 corresponding to the one or more ports are turned on, and the other controlled switches are turned off; if the levels of the other input ports are all Vcc, only the controlled switches S1 and S9 are turned on, and the other controlled switches are turned off;

[0035] When the levels of the first and fifth input ports are 0 and Vm respectively, and the level of one or more ports among the second to third input ports is 0, the controlled switches S5, S9 and the controlled switches S6 / S7 / S8 corresponding to the one or more ports are turned on, and the other controlled switches are turned off; if the levels of the other input ports are all Vcc, only the controlled switches S5 and S9 are turned on, and the other controlled switches are turned off.

[0036] In a preferred embodiment, the detection method further comprises determining the abnormal state of the controlled switches S0 to S9 of the DRED controller according to each voltage sampling signal.

[0037] The present invention also adopts the following technical solution:

[0038] An energy storage inverter includes an inverter circuit. The energy storage inverter also includes the detection circuit as described above. The controller is used to control the input and output of the inverter circuit according to the detection result.

[0039] The present invention adopts the above solution, which has the following advantages compared with the prior art:

[0040] The present invention provides a detection circuit and a detection method of a DRED controller. The detection circuit comprises a controller. The controller itself has five input ports. A controlled switch can be connected to the five input ports by five communication lines respectively, so that each AD port can identify the level of an input voltage sampling signal, and judge the switch state of each controlled switch S0 to S9 according to the identification result. The detection circuit uses a small number of electronic components and has a simple circuit structure, so it occupies a small volume and is suitable for household energy storage inverters. It can accurately and quickly judge the closing status of each controlled switch, has simple and clear logic, is easy to operate, and is easy to implement. The energy storage inverter using the detection circuit and the detection method can respond to the state of the controlled switch in time, and can perform corresponding operations according to the state of the controlled switch. At the same time, the energy storage inverter uses a small number of electronic components, which can reduce costs, reduce the space occupied by the system, and optimize the product volume. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solution of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0042] Figure 1 A detection circuit diagram of a DRED controller of an embodiment;

[0043] Figure 2 A circuit diagram of an energy storage inverter according to an embodiment;

[0044] Figure 3 A schematic diagram of the corresponding relationship between the detection value and the state of the controlled switch;

[0045] Figure 4 Schematic diagram of the corresponding relationship between the detection value and the fault condition of the controlled switch.

[0046] 1. First input port; 2. Second input port; 3. Third input port; 4. Fourth input port; 5. Fifth input port; 6. First communication line; 7. Second communication line; 8. Third communication line; 9. Fourth communication line; 10. Fifth communication line; 11. MCU chip; 12. Inverter circuit. DETAILED DESCRIPTION

[0047] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings so that the advantages and features of the present invention can be more easily understood by those skilled in the art. It should be noted that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation of the present invention.

[0048] The circuit structure of the DRED controller can be found in Figure 1 As shown, the DRED circuit of the DRED controller includes ten controlled switches S0 to S9, wherein the controlled switches S1 and S5 are connected in series to form a first branch, S2 and S6 are connected in series to form a second branch, S3 and S7 are connected in series to form a third branch, S4 and S8 are connected in series to form a fourth branch, and the resistor R0 forms a fifth branch, and the five branches are connected in parallel. Specifically, one end of S1, S2, S3 and S4 is connected in parallel, and one end of S5, S6, S7 and S8 is connected in parallel and the parallel end is grounded. One end of the controlled switch S9 is connected to the parallel end of S1, S2, S3 and S4. One end of the controlled switch S0 is grounded, and the other end is connected to the middle node of the controlled switch S9 and the parallel end of the controlled switches S1, S2, S3 and S4.

[0049] This embodiment provides a detection circuit for the DRED controller. Figure 1 As shown, the detection circuit includes a controller. Specifically in this embodiment, the controller specifically includes an MCU chip 11, and the MCU chip 11 has at least five AD ports, which are: a first input port 1, a second input port 2, a third input port 3, a fourth input port 4, and a fifth input port 5. The detection circuit also includes a first communication line 6, a second communication line 7, a third communication line 8, a fourth communication line 9, and a fifth communication line 10. Among them, one end of the first communication line 6 is connected to the first input port 1 of the MCU chip 11, and the other end is connected to the intermediate node of the controlled switches S1 and S5 of the DRED circuit; one end of the second communication line 7 is connected to the second input port 2 of the MCU chip 11, and the other end is connected to the intermediate node of the controlled switches S2 and S6 of the DRED circuit; one end of the third communication line 8 is connected to the third input port 3 of the MCU chip 11, and the other end is connected to the intermediate node of the controlled switches S3 and S7 of the DRED circuit; one end of the fourth communication line 9 is connected to the fourth input port 4 of the MCU chip 11, and the other end is connected to the intermediate node of the controlled switches S4 and S8 of the DRED circuit; one end of the fifth communication line 10 is connected to the fifth input port 5 of the MCU chip 11, and the other end is connected to the controlled switch S9 of the DRED circuit, and the other end of the controlled switch S9 is connected to the parallel ends of the controlled switches S1 to S4, which can be grounded through the controlled switch S0.

[0050] The control circuit also includes a first detection resistor R1, a second detection resistor R2, a third detection resistor R3, a fourth detection resistor R4 and a fifth detection resistor R5. One end of the first detection resistor R1 is connected to the first communication line 6, one end of the second detection resistor R2 is connected to the second communication line 7, one end of the third detection resistor R3 is connected to the third communication line 8, one end of the fourth detection resistor R4 is connected to the fourth communication line 9, and one end of the fifth detection resistor R5 is connected to the fifth communication line 10. The other ends of the first detection resistor R1, the second detection resistor R2, the third detection resistor R3, the fourth detection resistor R4 and the fifth detection resistor R5 are respectively connected to the power supply Vcc.

[0051] The detection circuit also includes: a signal sampling terminal DRM1 / 5, which is connected to the first input port 1 and to the first communication line 6; a signal sampling terminal DRM2 / 6, which is connected to the second input port 2 and to the second communication line 7; a signal sampling terminal DRM3 / 7, which is connected to the third input port 3 and to the third communication line 8; a signal sampling terminal DRM4 / 8, which is connected to the fourth input port 4 and to the fourth communication line 9; a signal sampling terminal COM LOAD, which is connected to the fifth input port 5 and to the fifth communication line 10; the above-mentioned sampling signal terminals are respectively used to sample the voltage signal, and output the sampling signal to the first input port 1, the second input port 2, the third input port 3, the fourth input port 4 and the fifth input port 5, respectively.

[0052] The MCU chip 11 can identify the levels of the voltage sampling signals inputted from the first input port 1, the second input port 2, the third input port 3, the fourth input port 4 and the fifth input port 5, and judge the switch states of the controlled switches S0 to S9 of the DRED controller according to the levels of each voltage sampling signal. Three levels of voltage sampling signals can be obtained at the above five AD ports respectively: Vcc, 0V and Vm, where Vm is a range voltage value with a large degree of distinction from Vcc and 0V and a small interval. It can be understood that the magnitude relationship between Vcc, 0V and Vm is: Vcc>Vm>0. Specifically in this embodiment, the voltage provided by the power supply Vcc is 3.3V, and Vm is 1.9~2.13V.

[0053] This embodiment also provides a detection method for a DRED controller, using the detection circuit as described above, using the first input port 1, the second input port 2, the third input port 3, the fourth input port 4 and the fifth input port 5 of the MCU chip 11 to identify the level of the voltage sampling signal input to each port, and judging the switch state of the controlled switches S0 to S9 of the DRED controller according to the level of each voltage sampling signal. The above-mentioned input ports are AD ports of the MCU chip 11 itself. Three levels of voltage sampling signals can be obtained at the above-mentioned five AD ports: Vcc, 0V and Vm.

[0054] The level of the first input port 1 corresponds to the controlled switches S1 and S5, the level of the second input port 2 corresponds to the controlled switches S2 and S6, the level of the third input port 3 corresponds to the controlled switches S3 and S7, and the level of the fourth input port 4 corresponds to the controlled switches S4 and S8;

[0055] like Figure 3 and Figure 4 As shown, by identifying the levels of the voltage sampling signals of the five AD ports, the normal working state and the abnormal working state of the controlled switch can be detected; and the specific conditions of each controlled switch when the controlled switch is in the normal working state can be detected; and the specific conditions of each controlled switch when the controlled switch is in the abnormal working state can be detected. Figure 3 Specifically, it is the correspondence between the input value of each AD port and the state of the controlled switch when each controlled switch is in normal working state, wherein "1" in the controlled switch column indicates that the switch is turned on, and "0" indicates that the switch is turned off; "2" in the AD port column indicates that the level signal received by the port is Vcc, "1" indicates that the level signal received by the port is Vm, and "0" indicates that the level signal received by the port is 0V. Figure 4 Specifically, it is the corresponding relationship between the input value of each AD port and the fault situation of the controlled switch when the controlled switch is in an abnormal working state, wherein "1" in the controlled switch column indicates that the switch is turned on, "0" indicates that the switch is turned off, and " / " indicates that the switch connection is abnormal; "2" in the AD port column indicates that the level signal received by the port is Vcc, "1" indicates that the level signal received by the port is Vm, "0" indicates that the level signal received by the port is 0V, and " / " indicates that the signal received by the port is an arbitrary level signal.

[0056] Reference Figure 3 As shown, the implementation steps of the detection method for detecting the normal working state of the controlled switch are as follows:

[0057] When the levels of the first to fifth input ports are Vcc, Vcc, Vcc, Vcc and Vm respectively, it is determined that the controlled switch S9 is turned on and the other controlled switches are turned off;

[0058] When the levels of the first to fifth input ports are Vcc, Vcc, Vcc, Vm and Vm respectively, it is determined that the controlled switches S4 and S9 are turned on, and the other controlled switches are turned off;

[0059] When the levels of the first to fifth input ports are Vcc, Vcc, Vm, Vcc and Vm respectively, it is determined that the controlled switches S3 and S9 are turned on, and the other controlled switches are turned off;

[0060] When the levels of the first to fifth input ports are Vcc, Vcc, Vm, Vm and Vm respectively, it is determined that the controlled switches S3, S4 and S9 are turned on, and the other controlled switches are turned off;

[0061] When the levels of the first to fifth input ports are Vcc, Vm, Vcc, Vcc and Vm respectively, it is determined that the controlled switches S2 and S9 are turned on, and the other controlled switches are turned off;

[0062] When the levels of the first to fifth input ports are Vcc, Vm, Vcc, Vm and Vm respectively, it is determined that the controlled switches S2, S4 and S9 are turned on, and the other controlled switches are turned off;

[0063] When the levels of the first to fifth input ports are Vcc, Vm, Vm, Vcc and Vm respectively, it is determined that the controlled switches S2, S3 and S9 are turned on, and the other controlled switches are turned off;

[0064] When the levels of the first to fifth input ports are Vcc, Vm, Vm, Vm and Vm respectively, it is determined that the controlled switches S2, S3, S4 and S9 are turned on, and the other controlled switches are turned off;

[0065] When the levels of the first to fifth input ports are Vm, Vcc, Vcc, Vcc and Vm respectively, it is determined that the controlled switches S1 and S9 are turned on, and the other controlled switches are turned off;

[0066] When the levels of the first to fifth input ports are Vm, Vcc, Vcc, Vm and Vm respectively, it is determined that the controlled switches S1, S4 and S9 are turned on, and the other controlled switches are turned off;

[0067] When the levels of the first to fifth input ports are Vm, Vcc, Vm, Vcc and Vm respectively, it is determined that the controlled switches S1, S3 and S9 are turned on, and the other controlled switches are turned off;

[0068] When the levels of the first to fifth input ports are Vm, Vcc, Vm, Vm and Vm respectively, it is determined that the controlled switches S1, S3, S4 and S9 are turned on, and the other controlled switches are turned off;

[0069] When the levels of the first to fifth input ports are Vm, Vm, Vcc, Vcc and Vm respectively, it is determined that the controlled switches S1, S2 and S9 are turned on, and the other controlled switches are turned off;

[0070] When the levels of the first to fifth input ports are Vm, Vm, Vcc, Vm and Vm respectively, it is determined that the controlled switches S1, S2, S4 and S9 are turned on, and the other controlled switches are turned off;

[0071] When the levels of the first to fifth input ports are Vm, Vm, Vm, Vcc and Vm respectively, it is determined that the controlled switches S1, S2, S3 and S9 are turned on, and the other controlled switches are turned off;

[0072] When the levels of the first to fifth input ports are Vm, Vm, Vm, Vm and Vm respectively, it is determined that the controlled switches S1, S2, S3, S4 and S9 are turned on, and the other controlled switches are turned off;

[0073] When the levels of the first to fifth input ports are Vcc, Vcc, Vcc, 0V and Vm respectively, it is determined that the controlled switches S8 and S9 are turned on, and the other controlled switches are turned off;

[0074] When the levels of the first to fifth input ports are Vcc, Vcc, Vcc, 0V and Vm respectively, it is determined that the controlled switches S8 and S9 are turned on, and the other controlled switches are turned off;

[0075] When the levels of the first to fifth input ports are Vcc, Vcc, 0V, Vcc and Vm respectively, it is determined that the controlled switches S7 and S9 are turned on, and the other controlled switches are turned off;

[0076] When the levels of the first to fifth input ports are Vcc, Vcc, 0V, 0V and Vm respectively, it is determined that the controlled switches S7, S8 and S9 are turned on, and the other controlled switches are turned off;

[0077] When the levels of the first to fifth input ports are Vcc, 0V, Vcc, Vcc and Vm respectively, it is determined that the controlled switches S6 and S9 are turned on, and the other controlled switches are turned off;

[0078] When the levels of the first to fifth input ports are Vcc, 0V, Vcc, 0V and Vm respectively, it is determined that the controlled switches S6, S8 and S9 are turned on, and the other controlled switches are turned off;

[0079] When the levels of the first to fifth input ports are Vcc, 0V, 0V, Vcc and Vm respectively, it is determined that the controlled switches S6, S7 and S9 are turned on, and the other controlled switches are turned off;

[0080] When the levels of the first to fifth input ports are Vcc, 0V, 0V, 0V and Vm respectively, it is determined that the controlled switches S6, S7, S8 and S9 are turned on, and the other controlled switches are turned off;

[0081] When the levels of the first to fifth input ports are 0V, Vcc, Vcc, Vcc and Vm respectively, it is determined that the controlled switches S5 and S9 are turned on, and the other controlled switches are turned off;

[0082] When the levels of the first to fifth input ports are 0V, Vcc, Vcc, 0V and Vm respectively, it is determined that the controlled switches S5, S8 and S9 are turned on, and the other controlled switches are turned off;

[0083] When the levels of the first to fifth input ports are 0V, Vcc, 0V, Vcc and Vm respectively, it is determined that the controlled switches S5, S7 and S9 are turned on, and the other controlled switches are turned off;

[0084] When the levels of the first to fifth input ports are 0V, Vcc, 0V, 0V and Vm respectively, it is determined that the controlled switches S5, S7, S8 and S9 are turned on, and the other controlled switches are turned off;

[0085] When the levels of the first to fifth input ports are 0V, 0V, Vcc, Vcc and Vm respectively, it is determined that the controlled switches S5, S6 and S9 are turned on, and the other controlled switches are turned off;

[0086] When the levels of the first to fifth input ports are 0V, 0V, Vcc, 0V and Vm respectively, it is determined that the controlled switches S5, S6, S8 and S9 are turned on, and the other controlled switches are turned off;

[0087] When the levels of the first to fifth input ports are 0V, 0V, 0V, Vcc and Vm respectively, it is determined that the controlled switches S5, S6, S7 and S9 are turned on, and the other controlled switches are turned off;

[0088] When the levels of the first to fifth input ports are 0V, 0V, 0V, 0V and Vm respectively, it is determined that the controlled switches S5, S6, S7, S8 and S9 are turned on, and the other controlled switches are turned off;

[0089] Reference Figure 4 As shown, the implementation steps of the detection method for detecting the abnormal working state of the controlled switch are as follows:

[0090] When the levels of the first to fifth input ports are any level signal, any level signal, any level signal, any level signal and Vcc in sequence, it is determined that the controlled switch S9 is disconnected and the connections of other controlled switches are abnormal;

[0091] When the levels of the first to fifth input ports are any level signal, any level signal, any level signal, any level signal and 0V in sequence, it is determined that the controlled switches S9 and S0 are disconnected, and the other controlled switches are abnormally connected; or it is determined that the controlled switches S1, S5 and S9 are turned on, the controlled switch S0 is disconnected, and the other controlled switches are abnormally connected; or it is determined that the controlled switches S2, S6 and S9 are turned on, the controlled switch S0 is disconnected, and the other controlled switches are abnormally connected; or it is determined that the controlled switches S3, S7 and S9 are turned on, the controlled switch S0 is disconnected, and the other controlled switches are abnormally connected; or it is determined that the controlled switches S4, S8 and S9 are turned on, the controlled switch S0 is disconnected, and the other controlled switches are abnormally connected;

[0092] When the levels of the first to fifth input ports are Vm, 0V, any level signal, any level signal and Vm respectively, it is determined that the controlled switches S1, S6 and S9 are turned on, the controlled switch S0 is turned off, and the connections of other controlled switches are abnormal;

[0093] When the levels of the first to fifth input ports are Vm, any level signal, 0V, any level signal and Vm in sequence, it is determined that the controlled switches S1, S7 and S9 are turned on, the controlled switch S0 is turned off, and the connections of other controlled switches are abnormal;

[0094] When the levels of the first to fifth input ports are Vm, 0V, any level signal, any level signal and Vm respectively, it is determined that the controlled switches S1, S8 and S9 are turned on, the controlled switch S0 is turned off, and the connections of other controlled switches are abnormal;

[0095] When the levels of the first to fifth input ports are 0V, Vm, any level signal, any level signal and Vm respectively, it is determined that the controlled switches S2, S5 and S9 are turned on, the controlled switch S0 is turned off, and the connections of other controlled switches are abnormal;

[0096] When the levels of the first to fifth input ports are any level signal, Vm, 0V, any level signal and Vm in sequence, it is determined that the controlled switches S2, S7 and S9 are turned on, the controlled switch S0 is turned off, and the connections of other controlled switches are abnormal;

[0097] When the levels of the first to fifth input ports are any level signal, Vm, 0V, any level signal and Vm in sequence, it is determined that the controlled switches S2, S8 and S9 are turned on, the controlled switch S0 is turned off, and the connections of other controlled switches are abnormal;

[0098] When the levels of the first to fifth input ports are 0V, any level signal, Vm, any level signal and Vm respectively, it is determined that the controlled switches S3, S5 and S9 are turned on, the controlled switch S0 is turned off, and the connections of other controlled switches are abnormal;

[0099] When the levels of the first to fifth input ports are any level signal, 0V, Vm, any level signal and Vm in sequence, it is determined that the controlled switches S3, S6 and S9 are turned on, the controlled switch S0 is turned off, and the connections of other controlled switches are abnormal;

[0100] When the levels of the first to fifth input ports are any level signal, any level signal, Vm, 0V and Vm respectively, it is determined that the controlled switches S3, S8 and S9 are turned on, the controlled switch S0 is turned off, and the connections of other controlled switches are abnormal;

[0101] When the levels of the first to fifth input ports are 0V, any level signal, any level signal, Vm and Vm respectively, it is determined that the controlled switches S4, S5 and S9 are turned on, the controlled switch S0 is turned off, and the connections of other controlled switches are abnormal;

[0102] When the levels of the first to fifth input ports are any level signal, 0V, any level signal, Vm and Vm respectively, it is determined that the controlled switches S4, S6 and S9 are turned on, the controlled switch S0 is turned off, and the connections of other controlled switches are abnormal;

[0103] When the levels of the first to fifth input ports are any level signal, any level signal, 0V, Vm and Vm respectively, it is determined that the controlled switches S4, S7 and S9 are turned on, the controlled switch S0 is turned off, and the connections of other controlled switches are abnormal;

[0104] It can be understood that the above detection method is completed based on the AD port of the MCU chip 11 itself. The MCU port resource selection is highly flexible. At the same time, the MCU chip 11 has an analog-to-digital converter (ADC), which can convert the input voltage analog electrical signal into a level digital signal. The ADC can detect a wide range of voltage values. Therefore, the reference values ​​Vcc, Vm and 0V used in this embodiment are only a preferred example and do not represent a limitation on specific reference values. In this detection method, other reference values ​​can also be used to better complete the detection, and the accuracy of the detection should not be limited to the reference values ​​given in this embodiment.

[0105] This embodiment also provides an energy storage inverter, including an inverter circuit 12, which uses the detection circuit as described above to detect the state of the controlled switch and controls the input and output of the inverter circuit 12 according to the detection result.

[0106] The detection circuit of a DRED controller provided in this embodiment includes an MCU chip 11. The MCU chip 11 itself has five AD ports. Five communication lines are used to connect the controlled switches to the five AD ports respectively, so that the AD ports correspond to the corresponding controlled switches, so that each AD port can identify the level of the input voltage sampling signal, and judge the switch state of each controlled switch S0 to S9 according to the result of the identification. The detection circuit can complete the detection based on the port of the MCU chip 11, has a simple structure, uses a small number of electronic components, and can reduce costs; the detection method provided in this embodiment can judge the switch state of the controlled switches S0 to S9 according to the level of the voltage sampling signal input to each AD port of the MCU chip 11. The detection method can not only detect the specific closing status of each controlled switch under normal working conditions, but also detect the conduction, disconnection or abnormal connection of each controlled switch under abnormal working conditions, which is conducive to accurately and quickly judging the closing status of each controlled switch. If the working state is abnormal, fault detection and troubleshooting can also be performed. The operation is simple and easy to implement. The energy storage inverter provided in this embodiment can detect the state of the controlled switch and change the input and output of the inverter circuit 12 according to the state of the controlled switch. The energy storage inverter can respond to the state of the controlled switch in time, and can perform corresponding operations according to the state of the controlled switch, so as to better meet the requirements of safety regulations. At the same time, the energy storage inverter only uses the AD port, communication line and resistor of the MCU chip 11 to form a detection circuit, and the number of electronic components is small, which can reduce costs, reduce the space occupied by the system, and optimize the product volume.

[0107] The above embodiment is only for illustrating the technical concept and features of the present invention, and is a preferred embodiment. Its purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and it cannot be used to limit the protection scope of the present invention. Any equivalent transformation or modification made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A detection circuit of a DRED controller, comprising a controller, characterized in that: The detection circuit also includes: A first communication line, one end of which is connected to the first input port of the controller, and the other end of which is used to connect the intermediate node of the controlled switches S1 and S5 of the DRED circuit; A second communication line, one end of which is connected to the second input port of the controller, and the other end is used to connect the intermediate node of the controlled switches S2 and S6 of the DRED circuit; A third communication line, one end of which is connected to the third input port of the controller, and the other end of which is used to connect the intermediate node of the controlled switches S3 and S7 of the DRED circuit; a fourth communication line, one end of which is connected to the fourth input port of the controller, and the other end of which is used to connect the intermediate node of the controlled switches S4 and S8 of the DRED circuit; a fifth communication line, one end of which is connected to the fifth input port of the controller, and the other end of which is used to be grounded through the controlled switches S9 and S0 of the DRED circuit; A first detection resistor, one end of which is connected to a power supply, and the other end of which is connected to the first communication line; A second detection resistor, one end of which is connected to the power supply, and the other end of which is connected to the second communication line; A third detection resistor, one end of which is connected to the power supply, and the other end of which is connected to the third communication line; a fourth detection resistor, one end of which is connected to the power supply, and the other end of which is connected to the fourth communication line; and a fifth detection resistor, one end of which is connected to the power supply, and the other end of which is connected to the fifth communication line; Among them, the controlled switches S1 and S5 are connected in series to form a first branch, S2 and S6 are connected in series to form a second branch, S3 and S7 are connected in series to form a third branch, S4 and S8 are connected in series to form a fourth branch, and the resistor R0 forms a fifth branch, and the five branches are connected in parallel; one end of S1, S2, S3 and S4 is connected in parallel, and one end of S5, S6, S7 and S8 is connected in parallel and the parallel end is grounded; one end of the controlled switch S9 is connected to the parallel end of S1, S2, S3 and S4; one end of the controlled switch S0 is grounded, and the other end is connected to the middle node of the controlled switch S9 and the parallel end of the controlled switches S1, S2, S3 and S4; The controller is used to identify the levels of voltage sampling signals input from the first input port, the second input port, the third input port, the fourth input port and the fifth input port, and determine the switching state of the controlled switches S0 to S9 of the DRED controller according to the levels of each voltage sampling signal.

2. The detection circuit according to claim 1, characterized in that: The controller is an MCU chip, and the first input port, the second input port, the third input port, the fourth input port and the fifth input port are AD ports of the MCU chip respectively.

3. The detection circuit according to claim 1, characterized in that: The voltage sampling signal has three levels: Vcc, Vm and 0V, and Vcc>Vm>0.

4. The detection circuit according to claim 1, characterized in that: The controller is also used to identify the five voltage sampling signals and determine the abnormal state of the DRED controller.

5. A detection method for a DRED controller, characterized in that: Using the detection circuit as described in claim 1 or 2, the detection method includes identifying the levels of voltage sampling signals input by the first input port, the second input port, the third input port, the fourth input port and the fifth input port, and judging the switching state of the controlled switches S0 to S9 of the DRED controller according to the levels of each voltage sampling signal.

6. The detection method according to claim 5, characterized in that: The voltage sampling signal has three levels: Vcc, Vm and 0V, and Vcc>Vm>0.

7. The detection method according to claim 6, characterized in that: The level of the first input port corresponds to the controlled switches S1 and S5, the level of the second input port corresponds to the controlled switches S2 and S6, the level of the third input port corresponds to the controlled switches S3 and S7, and the level of the fourth input port corresponds to the controlled switches S4 and S8; When the levels of the first and fifth input ports are Vcc and Vm respectively, if the level of one or more ports among the second to third input ports is Vm, the controlled switch S9 and the controlled switches S2, S3 or S4 corresponding to the one or more ports are turned on, and the other controlled switches are turned off; if the level of the other input ports is 0, the controlled switch S9 and the controlled switches S6, S7 or S8 corresponding to the one or more ports are turned on, and the other controlled switches are turned off; if the levels of the other input ports are all Vcc, only the controlled switch S9 is turned on, and the other controlled switches are turned off; When the levels of the first and fifth input ports are both Vm, if the level of one or more ports among the second to third input ports is Vm, the controlled switches S1, S9 and the controlled switches S2, S3 or S4 corresponding to the one or more ports are turned on, and the other controlled switches are turned off; if the levels of the other input ports are all Vcc, only the controlled switches S1 and S9 are turned on, and the other controlled switches are turned off; When the levels of the first and fifth input ports are 0 and Vm respectively, and the level of one or more ports among the second to third input ports is 0, the controlled switches S5, S9 and the controlled switches S6, S7 or S8 corresponding to the one or more ports are turned on, and the other controlled switches are turned off; if the levels of the other input ports are all Vcc, only the controlled switches S5 and S9 are turned on, and the other controlled switches are turned off.

8. The detection method according to claim 5, characterized in that: The detection method further includes determining the abnormal state of the controlled switches S0 to S9 of the DRED controller according to each voltage sampling signal.

9. An energy storage inverter, comprising an inverter circuit, characterized in that: The energy storage inverter further includes a detection circuit as described in any one of claims 1 to 4, and the controller is used to control the input and output of the inverter circuit according to the detection result.

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