Recording medium, calculation method and calculation device

Abstract

The embodiment relates to a recording medium for recording simulation data, a calculation method, and a calculation device. The recording medium of the embodiment records simulation data input to a calculation device, the calculation device performs a simulation of a semiconductor device, the simulation data includes component shape information describing the shape of a component included in a simulation target circuit, model information describing the operation and connection information of the simulation target circuit, and symbol information of the component included in the simulation target circuit, and the calculation device performs the simulation of the semiconductor device by associating the component shape information, the model information, and the symbol information.

Description

[0001] Related Applications

[0002] This application claims priority based on Japanese Patent Application No. 2020-51733 (filing date: March 23, 2020), and this application refers to and incorporates all the contents of the basic application. Technical Field

[0003] One embodiment of the present invention relates to a recording medium, a calculation method, and a calculation device for recording simulation data. Background Art

[0004] When designing a system with electrical components such as motors, it is not possible to perform simulations based on circuit diagrams and block diagrams that take into account the configuration and size of components within the system. Currently, the configuration and size of components within the system are often studied manually by operators on CAD (Computer Aided Design), which takes a lot of time to determine the configuration and size of components. Summary of the invention

[0005] One embodiment of the present invention is to provide a recording medium, a calculation method, and a calculation device that record simulation data and enable efficient consideration of component arrangement and component size in a short time.

[0006] A recording medium according to one embodiment records simulation data input to a computing device that performs simulation of a semiconductor device.

[0007] The simulation data includes component shape information that describes the shape of components included in the simulation object circuit, model information that describes the operation and connection information of the simulation object circuit, and symbol information of the components included in the simulation object circuit. The computing device associates the component shape information, the model information, and the symbol information to perform the simulation of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a diagram showing simulation data according to one embodiment.

[0009] Figure 2A This is a plan view showing an example of a component.

[0010] Figure 2B is a diagram showing an example of a symbol indicating Figure 2A NMOS transistor.

[0011] Figure 3 Yes means Figure 1 FIG. 1 is a graph of a specific example of simulation data.

[0012] Figure 4 This is a diagram showing an example of an external file.

[0013] Figure 5 This is a block diagram showing an example of the internal structure of a computing device.

[0014] Figure 6 This is a flowchart showing an example of the processing operation of the computing device.

[0015] Figure 7 Yes means Figure 6 A circuit diagram of an example of the simulation target circuit generated in step S2.

[0016] Figure 8 This is a diagram schematically showing an example of a layout arrangement result.

[0017] Fig. 9 This is a conceptual diagram of redesigning the simulation target circuit and reconfiguring the layout.

[0018] Fig. 10A This is a signal waveform diagram showing the results of wiring circuit simulation.

[0019] Fig. 10B This is a diagram showing a signal waveform when a simulation target circuit is generated using only model information and circuit simulation is performed.

[0020] Fig.11 A diagram showing the waveform of a signal causing overradiation. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments of a recording medium, a calculation method, and a calculation device for recording simulation data will be described with reference to the accompanying drawings. Hereinafter, the description will be centered on the main components of the recording medium, the calculation method, and the calculation device, but the recording medium, the calculation method, and the calculation device may have components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0022] Figure 1 This is a diagram showing simulation data 1 according to one embodiment. Figure 1 The simulation data 1 includes component shape information I1, model information I2, and symbol information I3. Figure 1 The simulation data 1 can be recorded in a recording medium. The type of the recording medium is not particularly specified. For example, the recording medium may be a semiconductor memory, a magnetic recording device, an optical disk, or a magneto-optical disk.

[0023] The component shape information I1 is information describing the shape of the components included in the simulation target circuit. Here, the information describing the shape is information indicating the outer shape of the semiconductor device, such as the size of the semiconductor device, the position information of the corners, etc. The simulation target circuit is not limited, and can be an analog circuit, a digital circuit, or a mixture of analog circuits and digital circuits. The type of component is not specifically specified. The component can be an integrated circuit (IC) or a discrete component.

[0024] Figure 2A It is a plan view showing an example of the component 2. Figure 2A The component 2 is, for example, an NMOS transistor, and has three terminals T1 to T3 . The component shape information I1 includes information that specifies the outer shape of the component 2 . Figure 2A In the example of FIG. 1 , the component shape information I1 includes the corners of component 2 ( Figure 2A In addition, the component shape information I1 may also include the position information of the terminal of component 2. Figure 2A As shown, the component shape information I1 may also include coordinate information of three terminals.

[0025] Figure 1 The model information I2 is information describing the action and connection information of the simulation object circuit. Here, the action information is information describing what action the simulation object circuit performs. The connection information is information indicating the connection relationship between a certain component and other components. A more specific example is information indicating which terminal of another component each terminal of a certain component is connected to, information indicating which input terminal or output terminal in a semiconductor device each terminal of a certain component is connected to, etc. Based on the description of the model information I2, a circuit can be automatically generated in a simulator, etc. The model information I2 includes connection information of component 2 contained in the simulation object circuit, and action information of component 2. The model information I2 includes information related to the terminals of component 2. The information related to the terminals of component 2 includes information indicating the correspondence relationship with the terminals of component 2 contained in the component shape information I1. More specifically, the information related to the terminals of component 2 includes the connection information of the terminals of component 2. The model information I2 may also include the file name of a file describing the action of the simulation object circuit, and information for referencing the file.

[0026] Figure 1 The symbol information I3 is an index indicating the component 2 included in the simulation target circuit. The symbol information I3 may be an index that makes the component 2 easy to identify, and does not necessarily need to be an index of a uniform form. Figure 2B This is a diagram showing an example of symbol 3, which indicates Figure 2A NMOS transistor. Figure 2B In symbol 3, Figure 2A The three terminals T1 to T3 are provided in correspondence with the terminals T1 to T3 of the component 2. In addition, in the symbol information I3, the terminal name in the symbol 3 is recorded in correspondence with the terminal name in the component shape information I1, so the terminal name in the component shape information I1 and the terminal name in the symbol 3 do not necessarily have to be the same. The symbol information I3 is different for each type of component 2, and includes the position information of the terminal of the component 2. The symbol information I3 is recorded in correspondence with the position information of the terminal of the component 2 contained in the component shape information I1.

[0027] Figure 1 The simulation data 1 can be saved in a file (hereinafter sometimes referred to as an integrated file). The file is generated in a form that can be interpreted and executed by a computer. In addition, for example, the file can be downloaded from a specific website. The downloaded file can be interpreted and executed by the computer at the download location. The computer can generate a circuit and verify (simulate) the operation of the generated circuit by executing the simulation data in the integrated file. Instead of a computer, the integrated file can also be input into a dedicated simulator for simulation. In this specification, computers that interpret and execute integrated files are collectively referred to as computing devices.

[0028] Figure 3 Yes means Figure 1 A diagram showing a specific example of simulation data 1 is the content of the above-mentioned integrated file. Figure 3 The simulation is represented by data 1 and as Figure 2A as well as Figure 2B An example of description related to the NMOS transistor of component 2. Figure 3 The simulation data 1 is text information composed of ASCII codes, and includes component shape information I1, model information I2, and symbol information I3. Figure 3 In the example of , the component shape information I1, the model information I2, and the symbol information I3 are described in this order, but the order in which each piece of information is described is arbitrary.

[0029] Figure 3 The component shape information I1 includes a row group Ln1 describing the coordinates of the outer shape of the component 2, and a row group Ln2 describing the identification information and coordinates of the terminals T1 to T3 of the component 2. Figure 2A As shown, the terminals T1 to T3 of the component 2 each have a predetermined length and width, and the center coordinates of the regions of the terminals T1 to T3 are described in the row group Ln2.

[0030] Figure 3 The first line in the line Ln3 describing the model information I2 refers to the external file "NMOS.Lib." This external file is a file describing the operation and connection information of the simulation target circuit. Figure 4This is a diagram showing an example of an external file. Figure 4 In the external file, record that there is Figure 2A as well as Figure 2B The terminal information, characteristics, operation, and connection information of the NMOS transistor of the component 2 are provided. The characteristics are, for example, the gate width, gate length, film thickness of the gate insulating film, and voltage range supplied to the gate of the NMOS transistor.

[0031] exist Figure 3 The correspondence between each terminal of the NMOS transistor in the component shape information I1 and each terminal of the NMOS transistor in the model information I2 is described in the second row and below in the row group Ln3 of the description model information I2. For example, the identification IDs corresponding to the terminals T1 to T3 of the NMOS transistor in the component shape information I1 are set to "1" to "3", and the NMOS transistor in the model information I2 has the identification IDs "A", "B", and "C" corresponding to the terminals T1 to T3, so it is described that "1" is associated with "A", "2" is associated with "B", and "3" is associated with "C".

[0032] Figure 3 The symbol information I3 includes a row group Ln4 describing the outer shape of the symbol, and a row group Ln5 describing the correspondence between the terminals A, B, and C of the symbol and the terminals T1 to T3 of the NMOS transistor in the component shape information I1. Figure 3 This is an example of the model information I2, and the format of the model information I2 is arbitrary.

[0033] Figure 3 The integrated file including the simulation data 1 shown may be stored in a storage unit (not shown) as needed. Figure 3 The simulation data 1 shown interprets the contents of the integrated file and executes the simulation.

[0034] Figure 5 It is a block diagram showing an example of the internal structure of the computing device 10. Figure 5 The computing device 10 includes an input unit 11 , a component information storage unit 12 , a symbol information storage unit 13 , an external file storage unit 14 , an execution unit 15 , an output unit 16 , and a verification unit 17 . Figure 5 The computing device 10 performs a simulation of the semiconductor device. The computing device 10 associates the component shape information I1, the model information I2, and the symbol information I3, and uses the simulation data 1 to perform the simulation of the semiconductor device.

[0035] Input unit 11 inputs Figure 3 The operator can also enter the Figure 3Alternatively, the integrated file may be electronically acquired from an electrical device having a communication function via the input unit 11.

[0036] The component information storage unit 12 stores various component information. Figure 2A Shown is information such as the outer shape, size, number of terminals, and terminal positions of component 2.

[0037] The symbol information storage unit 13 stores symbol information I3 of various components 2. The symbol information I3 is as follows: Figure 2B Shown are symbols of the components 2 and terminal information included in the symbols.

[0038] The external file storage unit 14 stores the external file described in the model information I2. When the operation and connection information of the simulation target circuit are directly described in the model information I2 without referring to the external file, the external file storage unit 14 may not be provided.

[0039] The execution unit 15 reads and interprets the component shape information I1 , model information I2 , and symbol information I3 described in the input integrated file, generates a simulation target circuit based on the component shape information I1 , model information I2 , and symbol information I3 , and executes simulation based on the generated circuit.

[0040] As described later, the simulations performed by the execution unit 15 include circuit simulation, electromagnetic field simulation, temperature simulation, etc. In this specification, an example is shown in which the same execution unit 15 performs multiple simulations, but multiple computing devices 10 (simulators) may perform different simulations.

[0041] The output unit 16 outputs the simulation result executed by the execution unit 15. The output format of the simulation result is arbitrary.

[0042] The verification unit 17 verifies whether the circuit or layout arrangement generated based on the integrated file is appropriate based on the simulation result output from the output unit 16, and changes the circuit or layout arrangement if it is not appropriate.

[0043] Figure 6 1 is a flowchart showing an example of the processing operation of the computing device 10. First, the integrated file is inputted via the input unit 11 (step S1). Next, the execution unit 15 reads and interprets the integrated file, and generates a simulation object circuit based on the component shape information I1, the model information I2, and the symbol information I3 (step S2). The generated simulation object circuit is outputted from the output unit 16.

[0044] Figure 7 Yes means Figure 6 In step S2, a circuit diagram of an example of the simulation target circuit is generated. Figure 7The simulation object circuit includes a motor 21 , a plurality of transistors 22 for controlling the driving of the motor 21 , and a control unit 23 for controlling the gate voltages of the transistors 22 as a main component 2 . Figure 7 The symbols of the components 2 included in the simulation target circuit are the symbols included in the symbol information I3.

[0045] Next, the execution unit 15 and the verification unit 17 use the circuit simulator to verify the operation of the simulation object circuit (step S3). Next, it is determined whether there is a problem with the operation of the simulation object circuit based on the simulation result of the circuit simulator (step S4). If there is a problem with the operation, the processing after step S2 is repeated. In addition, depending on the situation, when it is determined that there is a problem in step S4, a new integrated file can be re-input. In this case, the processing after step S1 is repeated.

[0046] If it is determined in step S4 that the operation is OK, layout configuration is performed based on the simulation target circuit whose operation verification has been completed (step S5). Although the computing device 10 of this embodiment can also perform layout configuration, the processing after step S5 can also be performed by other computing devices 10. Alternatively, the computing device 10 of this embodiment can also rely on the layout configuration processing of other devices that perform layout configuration, and receive the layout configuration result to perform the processing after step S5.

[0047] Figure 8 is a schematic diagram showing an example of the layout configuration result. Figure 8 In the example, it means that Figure 7 The motor 21 is arranged in the arrangement region r1, the plurality of transistors 22 are arranged in the arrangement region r2, and the control unit 23 is arranged in the arrangement region r3.

[0048] exist Figure 6 After the layout is configured in step S5, the computing device 10 performs an electromagnetic field simulation based on the layout configuration result (step S6). Next, it is determined whether there is a problem in the result of the electromagnetic field simulation (step S7). For example, if it is determined through the electromagnetic field simulation that the electromagnetic interference (EMI: ElectroMagnetic Interference) noise generated from a part of the layout area of ​​the semiconductor device exceeds a predetermined threshold, it is determined that there is a problem.

[0049] If it is determined that there is no problem in step S7, it is determined whether to change the layout (step S8). If it is determined that the layout is changed, the processing after step S5 is repeated. On the other hand, for example, if it is determined that the problem in step S7 is not solved by the layout change, the processing after step S2 is repeated.

[0050] If it is determined in step S7 that there is no problem, the layout result of step S5 is outputted via the output unit 16 (step S9).

[0051] The simulation data 1 of the present embodiment includes not only the model information I2 but also the component shape information I1 and the symbol information I3, so that the symbol of the component 2 used in the simulation object circuit can be easily and automatically selected, and the simulation object circuit can be quickly generated. In addition, when performing layout configuration, the layout configuration taking into account the shape and size of the component 2 can also be performed based on the component shape information I1, and the estimation of the wiring length and wiring capacity between each component 2 becomes easy. In addition, when performing circuit simulation, the wiring length and wiring capacity between each component 2 estimated by the layout configuration can be considered, and the operation verification of the simulation object circuit can be performed on the basis of making each wiring have a wiring delay close to the actual wiring delay.

[0052] Fig. 9 The simulation object circuit ( Fig. 9 The simulation results of 24, the layout configuration ( Fig. 9 A conceptual diagram showing that the results of (below) 25 are mutually utilized to redesign the simulation object circuit and reconfigure the layout.

[0053] For example, Fig. 9 As shown in the layout configuration 25 of FIG. 2 , a case where the wiring lengths L1 and L2 from the control unit 23 to the gate of the transistor 22 are different depending on the transistor 22 will be described.

[0054] The simulation data 1 of this embodiment includes component shape information I1, so when performing layout configuration, each component 2 can be configured taking component shape and size into consideration, and wiring connections can be made between each component 2. For example, Fig. 9 In the layout configuration of , the wiring L1 is longer than L2. The longer the wiring length, the larger the wiring capacity and the easier it is to cause wiring delay. Therefore, by reflecting the results of the layout configuration to the user Fig. 9 In the circuit simulation of the simulation target circuit on the left side of , the circuit simulation can be performed based on the information that the wiring delay of the additional wiring L1 is larger than that of the wiring L2.

[0055] Fig. 10AThis is a signal waveform diagram showing the circuit simulation results of wirings L1 and L2. Wiring L1 is longer and has a larger wiring capacity than wiring L2, so the rising timing of the waveform is delayed compared to wiring L2, and the waveform is also slowed down. If the rising timing of the signal is delayed, the circuit may not operate normally. However, in the circuit simulation of this embodiment, the difference in wiring length can be taken into account based on the layout configuration results. Therefore, the deviation of the rising timing caused by the difference in wiring length can be predicted, and the operation verification of the simulated object circuit can be performed.

[0056] Fig. 10B This is a signal waveform diagram when a simulation target circuit is generated and a circuit simulation is performed using only the model information I2 without using the component shape information I1 and the symbol information I3. Fig. 10B In this case, the difference in wiring length cannot be taken into account, so Fig. 9 The rising timings of the wirings L1 and L2 are considered to be the same, and the accuracy of the operation verification of the circuit simulation is reduced.

[0057] Fig. 9 In the figure, an example is shown in which the result of layout configuration based on component shape information I1 is reflected in circuit simulation. However, by calculating the loss information of each component 2 from the result of circuit simulation and making the calculated loss information a condition for thermal simulation in physical shape, thermal simulation can be performed under conditions close to actual operation.

[0058] For example, focusing on Fig. 9 Assume that the wiring L1 and L2 are used. Fig. 9 As a result of the circuit simulation of the simulation target circuit, the signal waveforms of the wiring L1 and the wiring L2 are as follows Fig.11 As shown. Wiring L1 has greater overradiation than wiring L2, and it can be expected that the heat generated by transistor 22 connected to wiring L1 will increase. In other words, it can be predicted that wiring L1 has greater heat loss than wiring L2. Therefore, by assigning the heat loss information obtained by the circuit simulation to the thermal simulation, the transistor 22 arranged in the layout can be treated as a transistor with greater heat generation than transistor 22 in the thermal simulation.

[0059] Thus, in this embodiment, simulation data 1 is generated that includes not only model information I2 but also component shape information I1 and symbol information I3. Therefore, simulation can be performed in a state close to the actual component 2 configuration and wiring configuration, and the accuracy of simulation can be improved.

[0060] Furthermore, the symbol of the component 2 used in the simulation object circuit can be quickly selected, and the simulation object circuit can be quickly generated according to the designer's intention. Furthermore, by using the component shape information I1, the shape and size of the component 2 arranged in the layout area can be made close to the shape and size of the actual component.

[0061] Furthermore, according to the present embodiment, by performing layout configuration based on the component shape information I1, the difference in wiring length can be understood from the layout configuration result, and by reflecting the difference in wiring length in circuit simulation, circuit simulation taking wiring delay into consideration can be performed.

[0062] Furthermore, according to the present embodiment, loss information of each component 2 can be estimated from the results of circuit simulation, and by reflecting the loss information in thermal simulation, the temperature distribution in the layout area can be predicted with high accuracy.

[0063] The above Figure 1 The simulation data 1 may be data in the form of a program executable by the computing device 10. That is, Figure 1 The simulation data 1 may be described in the form of a program in which the component shape information I1, the model information I2, and the symbol information I3 are respectively different parameters. More specifically, one or more functions executable by the computing device 10 may be described in the program, and the component shape information I1, the model information I2, and the symbol information I3 may be given as independent variables of the function.

[0064] At least a part of the computing device 10 described in the above embodiment may be constituted by hardware or software. In the case of being constituted by software, a program for realizing at least a part of the functions of the computing device 10 may be stored in a recording medium such as a floppy disk or a CD-ROM, and read and executed by a computer. The recording medium is not limited to a removable recording medium such as a magnetic disk or an optical disk, but may also be a fixed recording medium such as a hard disk device or a memory.

[0065] In addition, the program that realizes at least a part of the functions of the computing device 10 may be distributed via a communication line (including wireless communication) such as the Internet. Furthermore, the same program may be encrypted, modulated, or distributed in a compressed state via a wired line such as the Internet, a wireless line, or stored in a recording medium.

Claims

1. A recording medium recording simulation data input to a computing device that performs simulation of a semiconductor device, wherein: The computing device comprises: An input unit inputs an integrated file, the integrated file including: component shape information describing the shape of a component included in a simulation target circuit; model information describing the operation and connection information of the simulation target circuit; and symbol information of the component included in the simulation target circuit; and An execution unit associates the component shape information, the model information, and the symbol information to execute a simulation of the simulation target circuit.

2. The recording medium according to claim 1, wherein The component shape information includes information defining the outer shape of the component.

3. The recording medium according to claim 2, wherein The component shape information includes position information of corners of the component.

4. The recording medium according to claim 1, wherein The component shape information includes position information of terminals of the component.

5. The recording medium according to claim 1, wherein The model information includes connection information of the components included in the simulation target circuit and operation information of the components.

6. The recording medium according to claim 1, wherein The model information includes information related to the terminals of the component, The information on the terminals of the component includes information indicating a correspondence relationship with the terminals of the component included in the component shape information.

7. The recording medium according to claim 6, wherein The information on the terminals of the component includes connection information of the terminals of the component.

8. The recording medium according to claim 1, wherein The model information includes a file name of a file describing the operation of the simulation target circuit and information for referring to the file.

9. The recording medium according to claim 1, wherein The symbol information varies according to the type of the component, and includes position information of terminals of the component.

10. The recording medium according to claim 9, wherein The symbol information includes position information of the terminal of the component described in association with the position information of the terminal of the component included in the component shape information.

11. The recording medium according to claim 1, wherein The component shape information, the model information, and the symbol information are described in a format that is interpreted and executed by a computing device that performs a simulation of the simulation target circuit.

12. A method of operation, wherein: inputting simulation data recorded in an integrated file, the integrated file including component shape information recording the shape of a component included in a simulation target circuit, model information recording the operation of the simulation target circuit, and symbol information of the component included in the simulation target circuit, The component shape information, the model information, and the symbol information included in the integrated file are associated with each other to execute a simulation of the simulation target circuit.

13. The operation method according to claim 12, wherein: generating the simulation target circuit based on the model information and the symbol information, verifying the generated simulation object circuit, Layout and arrange components based on the verified simulation target circuit, the component shape information, and the model information; The layout configuration of the components is verified.

14. The operation method according to claim 13, wherein: In the verification of the layout arrangement of the components, the arrangement locations of the components are verified based on the component shape information and the connection information of the components included in the model information.

15. A computing device comprising: an input unit that inputs an integrated file, the integrated file including component shape information describing the shape of a component included in a simulation target circuit, model information describing the operation of the simulation target circuit, and symbol information of the component included in the simulation target circuit; and An execution unit associates the component shape information, the model information, and the symbol information to execute a simulation of the simulation target circuit.

16. The computing device according to claim 15, comprising: A circuit generating unit that generates the simulation target circuit based on the model information and the symbol information; A first verification unit verifies the generated simulation target circuit; a layout configuration unit that performs layout configuration of components based on the verified simulation target circuit, the component shape information, and the model information; as well as The second verification unit verifies the layout of the components.

17. The computing device according to claim 16, wherein: The second verification unit verifies the arrangement position of the component based on the component shape information and the connection information of the component included in the model information during verification of the layout arrangement of the component.

18. The computing device according to claim 15, wherein: The component shape information includes information defining the outer shape of the component.

19. The computing device according to claim 18, wherein: The component shape information includes position information of corners of the component.

20. The computing device according to claim 15, wherein: The component shape information includes position information of terminals of the component.

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