Method for forming a blocking structure and semiconductor structure

Abstract

Embodiments of the present disclosure describe a method for forming a barrier structure between a linerless conductive structure and a conductive structure below. The method includes forming an opening in a dielectric layer arranged on a contact layer, wherein the opening exposes a conductive structure in the contact layer. A first metal layer is deposited in the opening and grows thicker on the top surface of the conductive structure and grows thinner on the sidewall surface of the opening. The method also includes exposing the first metal layer to ammonia to form a double layer having a first metal layer and a nitride of the first metal layer, and then exposing the nitride to oxygen plasma to convert a portion of the nitride of the first metal layer into an oxide layer. The method also includes removing the oxide layer and forming a semiconductor-containing layer on the nitride of the first metal layer. According to other embodiments of the present application, a semiconductor structure is also provided.

Description

Technical Field

[0001] Embodiments of the present application relate to methods of forming a barrier structure and a semiconductor structure. Background Art

[0002] In an integrated circuit, a conductive structure (e.g., a metal contact) is electrically coupled to transistor regions, such as gate electrodes and source / drain regions, and is configured to propagate electrical signals from and to the transistors. Depending on the complexity of the integrated circuit, the conductive structure may form one or more layers of metal wiring. Summary of the invention

[0003] According to an embodiment of the present application, a method for forming a blocking structure is provided, comprising: receiving a substrate, on which a contact layer is formed, wherein the contact layer includes a conductive structure; forming a through-hole opening in a dielectric layer arranged on the contact layer, wherein the through-hole opening exposes a top surface of the conductive structure; depositing a first metal layer in the through-hole opening, wherein the first metal layer is deposited thicker on the top surface of the conductive structure than on the sidewall surface of the through-hole opening; exposing the first metal layer to ammonia to form a bilayer on the top surface of the conductive structure, wherein the bilayer includes the first metal layer and a nitride of the first metal layer; exposing the nitride of the first metal layer to oxygen plasma to convert a portion of the nitride of the first metal layer into an oxide layer of the first metal layer; removing the oxide layer of the first metal layer; and forming a semiconductor-containing layer on the nitride of the first metal layer in the bilayer.

[0004] According to another embodiment of the present application, a semiconductor structure is provided, including: a substrate; a first dielectric layer on the substrate; a first conductive structure formed in the first dielectric layer; an etch stop layer formed on the first dielectric layer; a second dielectric layer formed on a first portion of the etch stop layer and coplanar with a second portion of the etch stop layer, wherein the second portion of the etch stop layer is thicker than the first portion of the etch stop layer; a second conductive structure arranged on the first conductive structure and formed in the second dielectric layer; and a blocking structure including a metal layer, a nitride of the metal layer, and a silicon-containing or germanium-containing layer, wherein the blocking structure is inserted between a top surface of the first conductive structure and a bottom surface of the second conductive structure.

[0005] According to another embodiment of the present application, a semiconductor structure is provided, including: a semiconductor substrate having a source / drain (S / D) structure and a gate structure on the semiconductor substrate; a first conductive structure on the S / D structure and the gate structure; a second conductive structure on the first conductive structure; a resistor structure adjacent to the second conductive structure, having a resistor contact on the resistor structure; and a blocking structure inserted between the first conductive structure and the second conductive structure and between the resistor structure and the resistor contact, wherein the blocking structure includes a metal layer, a metal nitride layer, and a semiconductor-containing layer.

[0006] Embodiments of the present application provide metal loss prevention in conductive structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 A method for forming a barrier structure between a linerless via and a contact layer according to some embodiments.

[0009] Figure 2-Figure 8 is a cross-sectional view of an intermediate structure during fabrication of a barrier structure formed between a linerless via and a contact layer, according to some embodiments.

[0010] Figure 9-10 is a cross-sectional view of a barrier structure formed between a linerless via and a contact layer according to some embodiments. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0013] As used herein, the term "nominal" refers to an expected or target value for a characteristic or parameter of a component or process operation set during the design phase of a product or process, as well as a range of values ​​above and / or below the expected value. This range of values ​​may be due to slight variations in manufacturing processes and / or tolerances.

[0014] In some embodiments, the terms "about" and "substantially" may represent a value of a given amount that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are merely examples and are not limiting. It should be understood that the terms "about" and "substantially" may refer to a percentage of a value as interpreted by a person skilled in the relevant art based on the teachings herein.

[0015] Active and passive devices in an integrated circuit (IC) are partially and entirely interconnected with conductive structures, such as metal contacts, metal vias, and metal lines. These conductive structures are formed in metallization layers stacked on top of each other. The manufacture of each metallization layer requires several operations, including but not limited to the deposition of dielectric and conductive materials, photolithography and etching (e.g., patterning), removal of contaminants (e.g., wet cleaning), polishing, and planarization. These manufacturing operations need to be compatible with the materials used in the underlying metallization layers to avoid defects and other integration issues.

[0016] Conductive structures characterized by no barrier or liner between the metal filler and the surrounding material (also referred to herein as "linerless conductive structures") have become attractive because they have lower resistance characteristics than conductive structures with barrier or liner layers. Challenges arise in the manufacture of linerless conductive structures because such structures require filler metals that can be grown using a bottom-up approach. In a bottom-up approach, metal growth begins from a nucleation site at the bottom of the conductive structure. As an example and not limitation, metals that can be grown using a bottom-up process include molybdenum (Mo), tungsten (W), ruthenium (Ru), iridium (Ir), cobalt (Co), etc. However, when the metal grows from the bottom and fills the contact opening or via opening, gaps can be formed between the sidewall surface of the contact opening or via opening and the metal. For example, these gaps can be formed because the metal grains are not aligned with the sidewall surface of the contact opening or via opening. These gaps can extend vertically along the sidewall surface of the conductive structure and provide a path for chemicals used in subsequent processes to reach and erode the underlying conductive structure. These chemicals may include, but are not limited to, wet etch chemicals, wet cleaning solutions, slurries from a chemical mechanical planarization (CMP) process, and the like.

[0017] In order to solve the above shortcomings, the present invention relates to a method for forming a barrier structure between a padless conductive structure (e.g., a padless metal via) and a conductive structure below (e.g., a metal contact) to prevent slurry or other chemicals from a process used in the padless conductive structure from reaching and corroding the metal filler of the conductive structure below. In some embodiments, the barrier structure includes a titanium / titanium nitride (Ti / TiN) double layer having a silicide or germanide layer thereon. In some embodiments, the silicon (Si) or germanium (Ge) included in the barrier structure acts as a seed for the subsequent bottom-up growth of the metal filler in the padless conductive structure. In some embodiments, the formation of the barrier structure includes but is not limited to depositing, nitriding and oxidizing a titanium (Ti) layer on the sidewalls and bottom surfaces of the through hole opening or the contact opening, and subsequently depositing an amorphous Si or Ge layer. In some embodiments, the method is not limited to the Ti layer. For example, other metals such as tantalum (Ta) or nickel (Ni) can be used.

[0018] Figure 1 1 is a flow chart of a manufacturing method 100 describing a process for forming a barrier structure between a linerless conductive structure and an underlying conductive structure. In some embodiments, the manufacturing method 100 forms the barrier structure in the bottom surface of a via opening or a contact opening that is subsequently filled with a linerless conductive material. Other manufacturing operations may be performed between the various operations of the method 100 and may be omitted solely for clarity and ease of description. These various operations are within the spirit and scope of the present invention. In addition, not all operations are necessary to perform the inventive content provided herein. Some operations may be performed simultaneously or in parallel. Figure 1 In some embodiments, one or more other operations may be performed in addition to or in place of the operations currently described. Figure 2-9 Describing the method 100, these figures are for illustrative purposes only and are not drawn to scale. For illustrative purposes, some structures, films, or geometric shapes may have been intentionally enlarged or omitted.

[0019] By way of example and not limitation, Figure 2 is a cross-sectional view of a precursor structure 200 used as a starting point for method 100. In some embodiments, precursor structure 200 includes gate structures 205 / 210 and source / drain (S / D) epitaxial stack 215 formed on semiconductor substrate 220. In the example of precursor structure 200, gate contact 225 and S / D contact 230 are disposed on gate structure 205 and S / D epitaxial stack 215, respectively, as shown in FIG. Figure 2 As shown. In some embodiments, another gate contact (not shown) can be formed on the gate structure 210. The gate structures (e.g., gate structures 205 and 210) and the contacts (e.g., gate contact 225 and S / D contact 230) are electrically isolated by dielectric layers 235 and 240. In some embodiments, the gate contact 225 and S / D contact 230 together with the dielectric layers 235 and 240 form a contact layer 245, such as a first metallization layer. Figure 2 , the contacts (e.g., gate contact 225 and S / D contact 230) are shown as having a "curved" bottom surface, rather than a flat bottom surface. In some embodiments, this can be attributed to the etching process used in the contact opening formation process, which recesses the underlying structure (e.g., over-etches) to increase the surface area between the contact and the underlying structure.

[0020] like Figure 2 As shown, via openings 250 and 255 are formed in dielectric layer 260, which is disposed on dielectric layer 240 of contact layer 245. Via openings 250 and 255 expose the top surfaces of gate contact 225 and S / D contact 230, and the via openings can be formed using photolithography and etching operations and have an aspect ratio between about 5:1 and about 8:1. In some embodiments, via openings 250 and 255 will be filled with metal (e.g., Mo, Ru, or W) to form linerless vias connected to corresponding contacts of underlying contact layer 245. Figure 2 As shown, via openings 250 and 255 may have a “curved” bottom surface with gate contact 225 and S / D contacts 230 as described above.

[0021] Figure 2A resistor structure 272 is also included. A resistor structure (e.g., similar to resistor structure 272) is a passive component that is used, for example, to reduce current, adjust signal levels, divide voltages, etc. In some embodiments, resistor structure 272 includes TiN or another resistive material such as tungsten nitride (WN). A via opening 277 is formed in dielectric layer 260, similar to via openings 250 and 255, to expose a portion of resistor structure 272. In some embodiments, resistor structure 272 is embedded in etch stop layer 282, which helps form via openings 250, 255, and 277. Similar to via openings 250 and 255, opening 277 will be filled with a metal (e.g., Mo, Ru, or W) to form a linerless via to connect resistor structure 272 to the metallization layer above.

[0022] In some embodiments, the semiconductor substrate 220 is a bulk semiconductor wafer (e.g., a silicon bulk wafer), a top semiconductor layer of a semiconductor on insulator (SOI) wafer, or a semiconductor fin structure formed on a bulk wafer or an SOI wafer. By way of example and not limitation, the S / D epitaxial stack 215 forms the S / D regions of the gate structures 205 and 210 and includes one or more epitaxially grown layers—for example, boron-doped silicon germanium (B: SiGe) or phosphorus-doped silicon carbide (P: SiC). In some embodiments, the gate structures 205 and 210 include a plurality of layers that are not shown in the figure for simplicity. Figure 2 . As an example and not limitation, these layers may include a gate dielectric stack, one or more work function layers, and a metal filler. Gate structures 205 and 210 are isolated from epitaxial stack 215 by spacer structures 265, which may include one or more dielectric layers, such as silicon nitride (Si3N4). In some embodiments, dielectric layers 235, 240, and 260 are silicon oxide-based interlayer dielectric layers (ILD layers) that may include carbon, hydrogen, and nitrogen. Dielectric layers 235, 240, and 260 may be deposited using a chemical vapor deposition (CVD) process, a plasma assisted CVD (PECVD) process, or any other suitable deposition process.

[0023] According to some embodiments, the gate contact 225 and the S / D contact 230 are filled with a metal 270 surrounded by a liner layer 275. As an example and not a limitation, the metal 270 includes Co, and the liner layer 275 includes a Ti / TiN stack. Referring to the S / D contact 230, the Ti layer from the liner layer 275 reacts with the silicon atoms in the S / D epitaxial stack 215 to form a silicide layer 280 (e.g., titanium silicide (TiSi x ) layer), the silicide layer reduces the contact resistance between the S / D contact 230 and the S / D epitaxial stack 215. In some embodiments, the silicide layer 280 is not limited to TiSi xFor example, the silicide layer 280 may be nickel silicide (NiSi) or cobalt silicide (CoSi).

[0024] refer to Figure 1 The method 100 begins with operation 105 and a process of depositing a Ti layer on the sidewalls and bottom surface of a via opening such as Figure 2 The through hole openings 250, 255 and 277 of the precursor structure 200 are shown in FIG. By way of example and not limitation, Figure 3 The precursor structure 200 is shown after forming the Ti layer 300 according to operation 105 of the method 100. In some embodiments, the deposition method for forming the Ti layer 300 is configured to deposit a thicker Ti layer on horizontal surfaces (e.g., the bottom surface of the via openings 250 / 255 / 277 and the top surface of the dielectric layer 260) and a thinner Ti layer on vertical surfaces (e.g., the sidewall surfaces of the via openings 250, 255, and 277). For example, the thickness 310 of the Ti layer 300 on the bottom of the via openings 250 / 255 and 277 is greater than the thickness 320 of the Ti layer 300 on the sidewall surfaces of the via openings 250 / 255 and 277. Therefore, the bottom coverage of the Ti layer 300 is greater than the sidewall coverage. Deposition methods that can achieve such a non-conformal deposition profile include, but are not limited to, physical vapor deposition (PVD) methods, such as ionized metal plasma (IMP) deposition.

[0025] In some embodiments, the thickness 310 of the Ti layer 300 in the via openings 250 and 255 is in a range between about 5 nm and about 13 nm (e.g., about 10 nm), while the thickness 320 is in a range between 0 nm and less than about 5 nm (e.g., about 2 nm). Thicker (e.g., greater than about 13 nm) or thinner (e.g., less than about 5 nm) Ti layers are possible; however, thinner Ti layers (e.g., less than about 5 nm) may not form a barrier structure with sufficient barrier properties, and thicker Ti layers (e.g., greater than about 13 nm) may unnecessarily increase via resistance. In some embodiments, the process conditions for Ti layer deposition may be adjusted based on the aspect ratio of the via openings 250 and 255 to achieve Figure 3 . By way of example and not limitation, the top width W of the via openings 250 and 255 can range between about 12 nm and about 20 nm. In addition, the aspect ratio (e.g., the ratio of the height H to the top width W) of the via openings 250 and 255 can range between about 6 and about 8. In some embodiments, the deposition of the Ti layer 300 is a "blanket deposition." This means that the Ti layer 300 is deposited entirely on the outside of the via openings 250 and 255; for example, on the top surface of the dielectric layer 260 and in the via opening 277, as shown in FIG. Figure 3In some embodiments, via opening 277 has a lower aspect ratio than via openings 250 and 255 , for example, between about 1 and about 3.

[0026] In an alternative, a Ta layer or a Ni layer may be deposited instead of the Ti layer 300. In addition, the Ta or Ni layer may be deposited to have Figure 3 The Ti layer 300 in FIG. 3 shows a similar bottom and sidewall coverage as shown in FIG. For example, a Ta or Ni layer may be deposited using a similar deposition method as that used for the Ti layer 300. For purposes of illustration, the Ti layer will be used to describe Figure 1 The method 100 shown in FIG. However, based on the teachings herein, other metal layers, such as Ta or Ni, may be used. These metal layers are within the spirit and scope of the present invention.

[0027] refer to Figure 1 , the method 100 continues with operation 110 and a process of treating the Ti layer 300 with ammonia (NH3) to form TiN. In some embodiments, the NH3 treatment described in operation 110 is performed in situ relative to the deposition of the Ti layer 300. In other words, after the Ti layer 300 is deposited, the NH3 treatment of operation 110 is performed without a vacuum interruption. This is to avoid oxidation of the deposited Ti layer due to a vacuum interruption.

[0028] In some embodiments, the NH3 treatment described in operation 110 is a thermal treatment performed at a temperature between about 400° C. and about 450° C. for a duration of about 5 minutes. Processing temperatures below about 400° C. require longer processing times, which increases the overall processing time and manufacturing costs. On the other hand, higher processing temperatures above about 450° C. may be detrimental to the stability of the layers included in the gate structures 205 and 210.

[0029] In some embodiments, nitridation of the Ti layer 300 (e.g., formation of TiN) begins from the exposed top surface of the Ti layer 300 and proceeds inwardly toward the bottom surface of the Ti layer 300. In other words, during the NH3 treatment described in operation 110, the Ti layer 300 is "converted" to TiN from the top surface inwardly. Therefore, the treatment of operation 110 can be timed so that the thinner portions of the Ti layer 300 on the sidewall surfaces of the via openings 250 and 255 are completely converted to TiN, while the thicker portions of the Ti layer 300 are partially converted to TiN. Therefore, a TiN layer can be formed on the sidewalls of the via openings 250, 255, and 277, where the Ti layer 300 is thinnest, and a Ti / TiN bi-layer can be formed on the top surface of the dielectric layer 260 and on the bottom surfaces of the via openings 250, 255, and 277, where the Ti layer 300 is thickest. By way of example and not limitation, Figure 4The precursor structure 200 and the Ti layer 300 are shown after forming a TiN layer 400 on the sidewall surfaces of the via openings 250, 255, and 277 and a Ti / TiN bi-layer 410 on the bottom of the via openings 250 / 255 / 277 and on the top surface of the dielectric layer 260. In some embodiments, the thickness of the TiN layer 400 in the Ti / TiN bi-layer 410 is between about 3 nm and about 9 nm, and the thickness of the Ti layer 300 is between about 2 nm and 4 nm. In other words, the thickness of the Ti / TiN bi-layer 410 ranges between about 5 nm and about 13 nm. If the NH3 treatment of operation 110 is extended (e.g., for more than about 5 minutes), the Ti layer 300 on the bottom of the via openings 250, 255, and 277 may be completely converted to the TiN layer 400, which is undesirable because TiN is more resistive than Ti, and a thicker TiN layer will increase the via resistance. Therefore, the duration of the NH3 treatment needs to be adjusted so that the TiN layer 400 has sufficient thickness (e.g., barrier properties) without affecting the through-hole resistance. In some embodiments, the duration of the thermal treatment can be adjusted based on the sidewall and bottom coverage of the Ti layer 300 and the desired thickness of the TiN in the Ti / TiN bi-layer 410. In other words, a shorter treatment (e.g., shorter than about 5 minutes) will produce a thinner TiN layer 400 in the Ti / TiN bi-layer 410 than a longer treatment time (e.g., longer than about 5 minutes).

[0030] If Ta or Ni is used instead of Ti, operation 110 will form a tantalum nitride (TaN) or nickel nitride (Ni3N) layer instead of the TiN layer 400. In addition, aspects of the TaN layer or the Ni3N layer will be similar to the above-described TiN layer 400, including, for example, the thickness distribution of the TaN or Ni3N layer and the formation of a Ta / TaN or Ni / Ni3N bilayer at the bottom of the via openings 250, 255, and 277.

[0031] refer to Figure 1 , the method 100 continues with operation 115 and a process of exposing the TiN layer 400 to oxygen plasma. In some embodiments, the oxygen plasma oxidizes the TiN layer 400 and may continue to oxidize the Ti layer 300 as long as the duration of the oxidation process is long enough.

[0032] In some embodiments, the reaction rate between the ions in the oxygen plasma and the TiN layer (e.g., the oxidation rate of the TiN layer) is "mass transport" limited. In other words, the oxidation rate of the TiN layer increases as the number of available oxygen ions increases, and decreases as the number of available oxygen ions decreases. Therefore, if the process conditions of the oxygen plasma process are configured such that the distribution (e.g., density) of oxygen ions is higher at the top of the via opening and lower at the bottom of the via opening, a greater number of oxygen ions will be available to oxidize the TiN layer 400 on the top of the via opening than at the bottom. This in turn means that the oxidation rate of the TiN layer 400 can increase at the top of the via opening and decrease at the bottom of the via opening.

[0033] In some embodiments, the oxidation process of operation 115 is configured to form a density gradient of oxygen ions across the thickness of dielectric layer 260. By way of example and not limitation, Figure 5 The curve 510 shown represents the Gaussian ion density distribution in the oxygen plasma as a function of depth during operation 115. In this exemplary representation, the x-axis corresponds to the number of oxygen ions per unit area (e.g., the density of oxygen ions), and the z-axis corresponds to the vertical distance measured from the top surface of the TiN layer 400 on the dielectric layer 260. As shown in the ion density distribution of curve 510, the oxygen ion density is higher at the top of the via openings 250 / 255 / 277 and decreases toward the bottom of the via openings 250, 255 and 277. In some embodiments, Figure 5 The ion density distribution shown in and represented by curve 510 is not limited to this representation, and alternative ion density distributions are possible, such as exponential distributions or linear distributions. These alternative ion density distributions are within the spirit and scope of the present invention. By way of example and not limitation, by removing any bias applied to substrate 220 during operation 115, a density gradient of oxygen ions can be formed across the thickness of dielectric layer 260.

[0034] Thus, the TiN layer 400 disposed on the sidewall surfaces of the via opening and the top surface of the dielectric layer 260 may be fully oxidized, and the TiN layer 400 in the Ti / TiN bi-layer 410 at the bottom surface of the via openings 250, 255, and 277 may be partially oxidized primarily due to the oxidation rate difference provided by the density gradient of the oxygen ions in the plasma. It should also be noted that the thickness of the Ti / TiN bi-layer 410 is reduced by an amount approximately equal to the thickness of the TiN oxidized by operation 115. In some embodiments, between about 62% and about 68% of the TiN layer 400 is oxidized during operation 115. By way of example and not limitation, Figure 5 The resulting TiO2 layer 500 is shown formed on the Ti / TiN bi-layer 410', which is larger than that described above. Figure 4The Ti / TiN bilayer 410 shown in FIG. 4 is thinner. In some embodiments, the thickness of the TiO2 layer 500 on the Ti / TiN bilayer 410' is between about 2 nm and 6 nm, the thickness of the TiN layer 400 is between about 1 nm and 3 nm, and the thickness of the Ti layer 300 is between about 2 nm and 4 nm.

[0035] In some embodiments, operation 115 is performed at a temperature between about 160° C. and 250° C. In some embodiments, temperatures below about 160° C. may slow down or even stop the oxidation reaction. On the other hand, temperatures above 250° C. may increase the oxidation rate out of control or compromise the stability of the layers included in the gate structures 205 and 210. In some embodiments, if an oxygen plasma process is not desired due to plasma damage issues, the oxygen plasma process of operation 115 may be replaced with a thermal process. For example, the TiN layer 400 may be exposed to an annealing process in oxygen in a temperature range between about 350° C. and about 550° C. In some embodiments, the temperature range of the annealing process may be increased compared to the temperature range used in the oxygen plasma process.

[0036] In the case of using Ta or Ni, operation 115 will form a tantalum oxide TaO5 or nickel oxide (NiO) layer, respectively, instead of the TiO2 layer 500. In addition, aspects of the TaO5 or NiO layer will be similar to the TiO2 layer 500 described above, including, for example, the thickness distribution of the TaO5 or NiO layer inside and outside the via openings 250 and 255.

[0037] refer to Figure 1, method 100 continues with operation 120 and a process of removing the TiO2 layer formed during operation 115 with a chlorine-based etching chemistry. In some embodiments, the chlorine-based etching chemistry includes a metal, such as tungsten (e.g., WCl5), tantalum (TaCl5), molybdenum (MoCl5), or niobium (NbCl5). In some embodiments, the etching chemistry is selective to the metal oxide layer to be removed, such as TiO2, Ta2O5, or NiO. For example, the selectivity between the metal oxide and other layers (e.g., dielectric layer 260 and Ti layer 300) can be about 100:1 or greater. In some embodiments, when the underlying layer of the metal oxide is a metal nitride (e.g., TiO2 and TiN; Ta2O5 and TaN; or NiO and Ni3N) or a dielectric layer, such as dielectric layer 260, the etching process is self-limiting. According to some embodiments, the etching process is performed at a temperature range between about 400° C. and about 550° C. (e.g., between about 400° C. and 500° C.) to ensure that sufficient thermal energy is available for the etching reaction to occur and to produce gaseous byproducts so that the byproducts can be removed from the etched surface. In some embodiments, temperatures above about 550° C. may not be desirable because, as described above, they may affect the stability of the layers in the gate structures 205 and 210.

[0038] According to some embodiments, Figure 6 The precursor structure 200 is shown after the etching process described in operation 120. Figure 6 In the embodiment, the TiN layer 400 is limited to the bottom of the via openings 250, 255 and 277 in the TiN bi-layer 410'. In addition, as described above, the TiN layer 400 in the Ti / TiN bi-layer 410' is smaller than Figure 4 The TiN layer 400 in the Ti / TiN bi-layer 410 shown in FIG. 4 is thinner. In some embodiments, the thickness of the Ti / TiN bi-layer 410′ is about Figure 3 , for example, between about 3 nm and about 7 nm. According to some embodiments, Ti layer 300 and TiN layer 400 in Ti / TiN bilayer 410 ′ form a barrier structure that protects underlying metal 270 in gate contact 225 and S / D contact 230 .

[0039] In some embodiments, if the resistor structure 272 includes, for example, TiN or a material that is not susceptible to corrosion, the Ti / TiN bi-layer 410′ formed in the via opening 277 may not be as critical as in the via openings 250 and 255. However, in embodiments where the resistor structure 272 includes a material or layer that is susceptible to corrosion, the Ti / TiN bi-layer 410′ may be used to protect the resistor structure 272.

[0040] refer to Figure 1 , method 100 continues with operation 125 and a process of depositing amorphous silicon ("a-Si" or "Si") on the Ti / TiN bi-layer 410' to form a silicon-containing layer, which serves as a nucleation layer (e.g., a seed layer) for bottom-up deposition of metal in the via openings 250, 255, and 277. In some embodiments, the formed silicon-containing layer may also include titanium and nitrogen originating from the underlying Ti / TiN bi-layer 410'. According to some embodiments, Si is deposited using a CVD process that includes pre-treatment with titanium chloride (TiCl4) at a temperature between about 400°C and about 550°C, followed by an in-situ silane (SiH4) soak at a substantially similar temperature range (e.g., between about 400°C and about 550°C). Other suitable deposition methods for the silicon-containing layer may also be used. As described above, temperatures above 550°C should be avoided to protect the layers in the gate structures 205 and 210. In addition, temperatures below 400°C may not be sufficient to decompose the SiH4 precursor or form the silicon-containing layer.

[0041] In some embodiments, an amorphous germanium ("a-Ge" or "Ge") layer may be deposited in place of Si using a similar deposition method. For example, the Ge layer deposition may include pretreatment with titanium chloride (TiCl4) at a temperature between about 400°C and about 550°C, followed by in-situ deposition of Ge using a germanium (GeH4) precursor at a substantially similar temperature range (e.g., between about 400°C and about 550°C). As an example and not limitation, Ge may be deposited by CVD or any other suitable deposition method. As described above, temperatures above 550°C should be avoided to protect the layers in the gate structures 205 and 210. In addition, temperatures below 400°C may not be sufficient to decompose the GeH4 precursor or form a germanium-containing layer. In some embodiments, as in the silicon-containing layer, the germanium-containing layer formed includes titanium and nitrogen derived from the underlying Ti / TiN bilayer 410'.

[0042] refer to Figure 7 During the aforementioned Si deposition process (or Ge deposition process), a silicon-containing layer (or germanium-containing layer) 700 is formed on the Ti / TiN double layer 410'. In some embodiments, the silicon-containing barrier layer (or germanium-containing layer) 700 has a thickness of about to about According to some embodiments, the above deposition temperature (e.g., between about 400° C. and about 550° C.) is sufficient to induce diffusion of silicon atoms in the underlying TiN to form a silicon-containing layer (or germanium-containing layer) 700, such as TiSiN (or TiGeN). In some embodiments, the resulting silicon-containing layer (or germanium-containing layer) also includes silicon-hydrogen (or germanium-hydrogen) bonds. By way of example and not limitation, a layer having a thickness greater than about The silicon-containing (or germanium-containing) layer 700 of less than about 100 mm / s may unnecessarily increase the via resistance without providing any additional benefit. The thickness of the silicon-containing (or germanium-containing) layer 700 may be detrimental to the bottom-up growth of metal in the via openings 250, 255, and 277. In some embodiments, the thickness of the silicon-containing (or germanium-containing) layer 700 may be controlled by process conditions (eg, deposition time).

[0043] In some embodiments, the silicon-containing (or germanium-containing) layer 700 is selectively formed on the exposed surface of the TiN layer 400 instead of the dielectric layer 260. This is because, in contrast to the dielectric surface, the TiN surface can provide electrons to break up silicon-hydrogen or germanium-hydrogen and allow silicon or germanium to bond to the TiN surface.

[0044] As described above, other metals may be used instead of Ti, such as Ta or Ni. If Ta or Ni is used, the silicon-containing (or germanium-containing) layer 700 may include Ta, Si (or Ge) and nitrogen, or include Ni, Si (or Ge) and nitrogen. In some embodiments, and depending on the thickness of the Ti layer 300, the silicon-containing (or germanium-containing) layer 700 may also include Co. For example, if the Ti layer 300 is very thin (e.g., about 5 nm), the silicon-containing (or germanium-containing) layer 700 may include Ti, Co, nitrogen and Si (or Ge). If Ta or Ni is used, the silicon-containing (or germanium-containing) layer 700 may include Ta, Co, nitrogen and Si (or Ge) or include Ni, Co, nitrogen and Si (or Ge).

[0045] refer to Figure 1 , method 100 continues with operation 130 and a process of growing a linerless metal directly on the silicon-containing (or germanium-containing) layer 700 to fill the via openings 250, 255, and 277. As described above, the silicon-containing (or germanium-containing) layer 700 serves as a nucleation layer for subsequent metal deposition in the via openings 250, 255, and 277. For example, the silicon-hydrogen (or germanium-hydrogen) bonds in the silicon-containing (or germanium-containing) layer 700 may promote bottom-up growth of the via metal. For example, in the case of Mo, Mo may be deposited using CVD using molybdenum hexafluoride (MoF6) and hydrogen in a temperature range between about 175°C and about 275°C and a pressure between about 1 Torr and about 3 Torr. In some embodiments, the thickness of the deposited metal ranges from about 50 nm to about 150 nm. According to some embodiments, Figure 8The precursor structure 200 is shown after bottom-up deposition of via metal 800 (e.g., Mo) and a subsequent CMP process, during which the via metal 800 extending outside the via has been polished so that the top surface of the via metal 800 and the top surface of the dielectric layer 260 are substantially coplanar. In some embodiments, a combination of temperature and pressure promotes bottom-up growth of Mo metal. For example, at higher temperatures (e.g., above about 275° C.) and / or higher pressures (e.g., above about 3 Torr), Mo metal may not selectively grow on the silicon-containing (or germanium-containing) layer 700 and begin to grow on the dielectric layer 260. Under these conditions, bottom-up metal growth may not be possible, and voids may be formed in the linerless vias 810A and 810B.

[0046] In some embodiments, if a metal other than Mo is used (eg, Ru, Ir, W, or Co), then no silicon- or germanium-containing layer may be needed and the metal may be deposited directly on the TiN layer 400 of the Ti / TiN bi-layer 410 ′.

[0047] In some embodiments, the via metal 800 is heat treated to increase its grain size and improve its conductivity. For example, the Mo via metal can be heat treated in hydrogen to increase its grain size by more than about 75%. In some embodiments, during the treatment or during the above-mentioned "grain growth" heat treatment, a silicide (or germanide) is formed between the via metal and the silicon-containing (or germanium-containing) layer 700. In other words, silicon (or germanium) atoms diffuse into the via metal 800, or metal atoms from the via metal 800 diffuse into the silicon-containing (or germanium-containing) layer 700 to form a silicide (or germanide) having a thickness between about 0.2nm and 3nm. In some embodiments, the silicide (or germanide) formed includes MoSi or MoGe (if Ge is used). In some embodiments, additional silicides or germanides can be formed, including but not limited to TiCoSi (or TiCoGe), TaCoSi (or TaCoGe), NiCoSi (or NiCoGe) or binary silicide (or germanide) CoSi (or CoGe). In some embodiments, the silicides or germanides may include nitrogen.

[0048] In some embodiments, the via metal 800 in the dielectric layer 260 forms a metallization layer 805, wherein the linerless vias 810A and 810B are arranged on the contact layer 245. In some embodiments, additional metallization layers can be formed on the metallization layer 805. For example, referring to Fig. 9, a metallization layer 900 may be formed on the metallization layer 805. The metallization layer 900 may include a dual damascene conductive structure 905A and / or a single damascene conductive structure 905B embedded in the dielectric layer 910. As an example and not a limitation, the dual damascene conductive structure 905A and / or the single damascene conductive structure 905B may include a metal 915 different from the through-hole metal 800. For example, the metal 915 may be copper (Cu), a copper alloy (e.g., copper-ruthenium (Cu-Ru), copper-aluminum (Cu-Al), copper-manganese (Cu-Mn), etc.), or any other suitable metal or alloy. In some embodiments, a barrier layer or barrier stack 920 surrounds the sidewalls and bottom surface of the metal 915 in the metallization layer 900. As an example and not a limitation, the barrier layer or barrier stack 920 may include Ta and TaN or other suitable layers.

[0049] In some embodiments, for ease of description, Fig. 9 . These layers or features include etch stop layers between dielectric layers 240, 260, and 910; etch stop layers on gate structures 205 and 210; additional gate structures; additional S / D epitaxial stacks, additional contacts, doped regions in semiconductor substrate 220, etc. These layers and features are within the spirit and scope of the present invention. In addition, in Fig. 9 , the layout of the contact layer 245 and the metallization layers 805 and 900 is not limiting, and different layouts are possible with additional conductive structures and / or sub-layers.

[0050] For example, Fig.10 A structure 200' is shown, which is characterized by Fig. 9 The precursor structure 200 shown in FIG. Fig.10 As shown, structure 200′ includes a gate structure 1000 having a gate contact 225 thereon and a gate structure 1005 having a hard mask (HM) layer 1010 thereon. In some embodiments, the gate contact of gate structure 1005 is formed on the gate structure 1005 from Fig.10 The cross-section view is not visible. Fig.10 Also included is an intermediate contact 1015 formed on the S / D contact 230 (eg, Fig. 9 By way of example and not limitation, something like Fig. 9 The gate contact 225 and S / D contact 230 shown in FIG. 1 , the intermediate contact 1015 is filled with metal 270 and liner layer 275. This means that Fig. 9 The S / D contacts 230 are Fig.10 In some embodiments, the additional intermediate contact 1015 may be connected to the Fig.10 The S / D contacts 230 not shown in the figure, and one or more S / D contacts 230 may be connected to Fig.10 The intermediate contact 1015 is not shown.

[0051] also, Fig.10 The linerless vias 810A may have different heights. For example, a taller linerless via 810A may be formed on the gate contact 225 and a shorter linerless via 810A may be formed on the intermediate contact 1015. In some embodiments, Fig.10 As shown, the padless via 810A connects the gate contact 225 and the intermediate contact 1015 to the dual damascene conductive structure 905A and / or the single damascene conductive structure 905B of the upper metallization layer. In some embodiments, the padless via 810A can be connected to the gate contact 225 and the intermediate contact 1015. Fig.10 The single damascene conductive structure 905B is shown, or connected to the dual damascene conductive structure 905A.

[0052] The method 100 can be applied to structures having different metallization schemes to form a barrier structure having a silicide (or germanide) and a Ti / TiN bilayer or a silicide (or germanide) and a Ta / TaN bilayer or a silicide (or germanide) and a Ni / NiN bilayer in a linerless conductive structure. In some embodiments, the barrier structure can protect the underlying conductive structure or layer from corrosion caused by subsequent processes such as chemical cleaning or CMP processes. Therefore, the application of the method 100 is not limited to the embodiments described herein, and can be implemented using any metallization scheme featuring a linerless conductive structure.

[0053] Methods for forming a barrier structure between a linerless conductive structure (e.g., a linerless metal via) and an underlying conductive structure (e.g., a metal contact) are described according to various embodiments of the present invention to prevent slurries or other chemicals from a process used in the linerless conductive structure from reaching and corroding the metal fill of the underlying conductive structure. In some embodiments, the barrier structure may include a double layer of Ti / TiN, Ta / TaN, or Ni / NiN. In some embodiments, the barrier structure also includes silicon or germanium, which serves as a nucleation site for bottom-up growth of the metal fill in the linerless conductive structure. In some embodiments, the underlying metal includes Co and the linerless metal includes Mo, W, or Ru. In some embodiments, the formation of the barrier structure includes, but is not limited to, deposition, nitridation, and oxidation of a Ti layer, a Ta layer, or a Ni layer on the sidewalls and bottom surfaces of the via opening or the contact opening.

[0054] In some embodiments, a method includes receiving a substrate having a contact layer formed thereon, wherein the contact layer includes a conductive structure; forming a via opening in a dielectric layer disposed on the contact layer, wherein the via opening exposes a top surface of the conductive structure. The method also includes depositing a first metal layer in the via opening, wherein the first metal layer is deposited thicker on the top surface of the conductive structure than on the sidewall surface of the via opening; exposing the first metal layer to ammonia to form a bilayer on the top surface of the conductive structure, wherein the bilayer includes the first metal layer and a nitride of the first metal layer. The method also includes exposing the nitride of the first metal layer to an oxygen plasma to convert a portion of the nitride of the first metal layer into an oxide layer of the first metal layer; removing the oxide layer of the first metal layer; and forming a semiconductor-containing layer on the nitride of the first metal layer in the bilayer.

[0055] In some embodiments, a structure includes a substrate, a first dielectric layer on the substrate, a first conductive structure formed in the first dielectric layer, and an etch stop layer formed on the first dielectric layer. The structure also includes a second dielectric layer formed on a first portion of the etch stop layer and coplanar with a second portion of the etch stop layer, wherein the second portion of the etch stop layer is thicker than the first portion of the etch stop layer. The structure also includes a second conductive structure disposed on the first conductive structure and formed in the second dielectric layer, and a barrier structure including a metal layer, a nitride of the metal layer, and a silicon-containing or germanium-containing layer, wherein the barrier structure is interposed between a top surface of the first conductive structure and a bottom surface of the second conductive structure.

[0056] In some embodiments, a structure includes a semiconductor substrate having a source / drain (S / D) structure and a gate structure on the semiconductor substrate. The structure also includes a first conductive structure on the S / D and gate structures, a second conductive structure on the first conductive structure, and a resistor structure adjacent to the second conductive structure, having a resistor contact on the resistor structure. In addition, the structure includes a barrier structure inserted between the first and second conductive structures and between the resistor structure and the resistor contact, wherein the barrier structure includes a metal layer, a metal nitride layer, and a semiconductor-containing layer.

[0057] According to an embodiment of the present application, a method for forming a blocking structure is provided, comprising: receiving a substrate, a contact layer is formed on the substrate, wherein the contact layer includes a conductive structure; forming a through hole opening in a dielectric layer arranged on the contact layer, wherein the through hole opening exposes the top surface of the conductive structure; depositing a first metal layer in the through hole opening, wherein the first metal layer is deposited thicker on the top surface of the conductive structure than on the sidewall surface of the through hole opening; exposing the first metal layer to ammonia to form a double layer on the top surface of the conductive structure, wherein the double layer includes the first metal layer and a nitride of the first metal layer; exposing the nitride of the first metal layer to oxygen plasma to convert a portion of the nitride of the first metal layer into an oxide layer of the first metal layer; removing the oxide layer of the first metal layer; and forming a semiconductor-containing layer on the nitride of the first metal layer in the double layer. In some embodiments, the method for forming the blocking structure further comprises: selectively growing a second metal layer on the semiconductor-containing layer to fill the through hole opening; and subjecting the second metal layer to an annealing process, wherein the annealing process converts the semiconductor-containing layer into a silicide layer or a germanide layer. In some embodiments, wherein selectively growing the second metal layer comprises growing molybdenum. In some embodiments, wherein depositing the first metal layer comprises depositing titanium, nickel, or tantalum. In some embodiments, wherein exposing the first metal layer to ammonia comprises converting the first metal layer on the sidewall surface of the through-hole opening into a nitride of the first metal layer. In some embodiments, wherein exposing the nitride of the first metal layer to oxygen plasma comprises oxidizing the nitride of the first metal layer on the sidewall surface of the through-hole opening to convert the nitride of the first metal layer into an oxide layer of the first metal layer. In some embodiments, wherein removing the oxide layer of the first metal layer comprises removing the oxide layer of the first metal layer using a chlorine-based chemical. In some embodiments, wherein removing the oxide layer of the first metal layer comprises removing the oxide layer of the first metal layer from the sidewall surface of the through-hole opening. In some embodiments, wherein forming the semiconductor-containing layer comprises depositing an amorphous silicon layer or an amorphous germanium layer. In some embodiments, wherein depositing a thicker first metal layer comprises depositing the first metal layer on a conductive structure, the conductive structure comprising one or more of a gate contact, a source / drain contact, and a resistor structure.

[0058] According to another embodiment of the present application, a semiconductor structure is provided, comprising: a substrate; a first dielectric layer on the substrate; a first conductive structure formed in the first dielectric layer; an etch stop layer formed on the first dielectric layer; a second dielectric layer formed on a first portion of the etch stop layer and coplanar with a second portion of the etch stop layer, wherein the second portion of the etch stop layer is thicker than the first portion of the etch stop layer; a second conductive structure arranged on the first conductive structure and formed in the second dielectric layer; and a blocking structure comprising a metal layer, a nitride of the metal layer, and a silicon- or germanium-containing layer, wherein the blocking structure is inserted between a top surface of the first conductive structure and a bottom surface of the second conductive structure. In some embodiments, the semiconductor structure further comprises: a resistor layer formed in a second portion of the etch stop layer; and a third conductive structure formed in a second portion of the etch stop layer and arranged on the resistor layer, wherein the blocking structure is inserted between a top surface of the resistor layer and a bottom surface of the third conductive structure. In some embodiments, the second and third conductive structures are linerless conductive structures, and the linerless conductive structures include molybdenum. In some embodiments, the first conductive structure includes a source / drain contact or a gate contact containing cobalt. In some embodiments, the silicon-containing or germanium-containing layer includes molybdenum (Mo), titanium (Ti), cobalt (Co), tantalum (Ta), nickel (Ni), or a combination thereof. In some embodiments, the metal layer includes titanium, tantalum, or nickel. In some embodiments, the metal layer has a thickness between about 2 nm and about 4 nm.

[0059] According to another embodiment of the present application, a semiconductor structure is provided, comprising: a semiconductor substrate having a source / drain (S / D) structure and a gate structure on the semiconductor substrate; a first conductive structure on the S / D structure and the gate structure; a second conductive structure on the first conductive structure; a resistor structure adjacent to the second conductive structure, having a resistor contact on the resistor structure; and a barrier structure inserted between the first conductive structure and the second conductive structure and between the resistor structure and the resistor contact, wherein the barrier structure comprises a metal layer, a metal nitride layer, and a semiconductor-containing layer. In some embodiments, wherein the metal layer comprises titanium, tantalum, or nickel; the metal nitride comprises titanium nitride, tantalum nitride, or nickel nitride; and the semiconductor-containing layer comprises a silicide layer or a germanide layer, wherein the silicide layer and the germanium layer comprise titanium, tantalum, nickel, cobalt, molybdenum, or a combination thereof. In some embodiments, the metal layer has a thickness between about 2 nm and about 4 nm, and the metal nitride layer has a thickness between about 1 nm and about 3 nm.

[0060] It should be understood that the Detailed Description section, rather than the Abstract of the present invention, is intended to be used to interpret the claims. The Abstract section of the present invention may set forth one or more but not all exemplary embodiments, and thus is not intended to limit the appended claims.

[0061] The above summary of the invention discusses the components of several embodiments so that those of ordinary skill in the art can better understand the various aspects of the present invention. Those of ordinary skill in the art will appreciate that the present invention can be easily used as a basis to design or modify other processes and structures for achieving the same purpose and / or achieving the same advantages as the embodiments described herein. Those of ordinary skill in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications may be made without departing from the spirit and scope of the appended claims.

Claims

1. A method for forming a barrier structure, comprising: receiving a substrate on which a contact layer is formed, wherein the contact layer includes a conductive structure; forming a via opening in a dielectric layer disposed on the contact layer, wherein the via opening exposes a top surface of the conductive structure; depositing a first metal layer in the via opening, wherein the first metal layer is deposited thicker on a top surface of the conductive structure than on a sidewall surface of the via opening; exposing the first metal layer to ammonia to form a bilayer on the top surface of the conductive structure, wherein the bilayer includes the first metal layer and a nitride of the first metal layer; exposing the nitride of the first metal layer to oxygen plasma to convert a portion of the nitride of the first metal layer into an oxide layer of the first metal layer; removing the oxide layer of the first metal layer; and A semiconductor-containing layer is formed on the nitride of the first metal layer in the bi-layer.

2. The method according to claim 1, further comprising: selectively growing a second metal layer on the semiconductor containing layer to fill the via opening; and The second metal layer is subjected to an annealing process that converts the semiconductor-containing layer into a silicide layer or a germanide layer.

3. The method according to claim 2, wherein: Selectively growing the second metal layer includes growing molybdenum.

4. The method according to claim 1, wherein: Depositing the first metal layer includes depositing titanium, nickel, or tantalum.

5. The method according to claim 1, wherein: Exposing the first metal layer to ammonia includes converting the first metal layer on sidewall surfaces of the via opening to a nitride of the first metal layer.

6. The method according to claim 1, wherein: Exposing the nitride of the first metal layer to oxygen plasma includes oxidizing the nitride of the first metal layer on sidewall surfaces of the via opening to convert the nitride of the first metal layer into an oxide layer of the first metal layer.

7. The method according to claim 1, wherein: Removing the oxide layer of the first metal layer includes removing the oxide layer of the first metal layer using a chlorine-based chemical.

8. The method according to claim 1, wherein: Removing the oxide layer of the first metal layer includes removing the oxide layer of the first metal layer from sidewall surfaces of the via opening.

9. The method according to claim 1, wherein: Forming the semiconductor-containing layer includes depositing an amorphous silicon layer or an amorphous germanium layer.

10. The method according to claim 1, wherein: The conductive structures include one or more of a gate contact, a source / drain contact, and a resistor structure.

11. A semiconductor structure comprising: substrate; a first dielectric layer on the substrate; a first conductive structure formed in the first dielectric layer; an etch stop layer formed on the first dielectric layer; a second dielectric layer formed on the first portion of the etch stop layer and coplanar with a second portion of the etch stop layer, wherein the second portion of the etch stop layer is thicker than the first portion of the etch stop layer; a second conductive structure disposed on the first conductive structure and formed in the second dielectric layer; and a barrier structure comprising a metal layer, a nitride of the metal layer, and a silicon-containing or germanium-containing layer, wherein the barrier structure is interposed between a top surface of the first conductive structure and a bottom surface of the second conductive structure; a resistor layer formed in the second portion of the etch stop layer; and A third conductive structure is formed in the second portion of the etch stop layer and is disposed on the resistor layer, wherein the barrier structure is interposed between a top surface of the resistor layer and a bottom surface of the third conductive structure.

12. The semiconductor structure according to claim 11, wherein: The second conductive structure and the third conductive structure are linerless conductive structures.

13. The semiconductor structure according to claim 12, wherein: The linerless conductive structure includes molybdenum.

14. The semiconductor structure according to claim 11, wherein: The first conductive structure includes a source / drain contact or a gate contact comprising cobalt.

15. The semiconductor structure according to claim 11, wherein: The silicon-containing or germanium-containing layer includes molybdenum (Mo), titanium (Ti), cobalt (Co), tantalum (Ta), nickel (Ni), or a combination thereof.

16. The semiconductor structure according to claim 11, wherein: The metal layer includes titanium, tantalum or nickel.

17. The semiconductor structure according to claim 11, wherein: The metal layer has a thickness between 2 nm and 4 nm.

18. A semiconductor structure comprising: A semiconductor substrate having a source / drain structure and a gate structure thereon; a first conductive structure, on the source / drain structure and the gate structure; a second conductive structure on the first conductive structure, wherein the second conductive structure is a liner-less conductive structure; a resistor structure adjacent to the second conductive structure, having a resistor contact on the resistor structure; and A blocking structure is inserted between the first conductive structure and the second conductive structure and between the resistor structure and the resistor contact, wherein the blocking structure includes a metal layer contacting the first conductive structure, a semiconductor-containing layer contacting the second conductive structure, and a metal nitride layer between the metal layer and the semiconductor-containing layer.

19. The semiconductor structure according to claim 18, wherein: The metal layer includes titanium, tantalum or nickel; The metal nitride comprises titanium nitride, tantalum nitride or nickel nitride; and The semiconductor-containing layer includes a silicide layer or a germanide layer, wherein the silicide layer and the germanium layer include titanium, tantalum, nickel, cobalt, molybdenum or a combination thereof.

20. The semiconductor structure of claim 18, wherein: The metal layer has a thickness between 2 nm and 4 nm, and the metal nitride layer has a thickness between 1 nm and 3 nm.

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